201124564 六、發明說明： 【發明所屬之技術頜城1 本發明關於，種於Co種晶層上藉由電解電锻而形 成Cu膜之成膜方法及記憶媒體。 L圯刖技術】 近年來’ Ik著半導體元件的高迷化、導線圖樣的微 細化等，較A1的導紐要高且抗％子遷料亦良好之 來作為-種導線便受_目。自過找，Cu導線廣 t由電解電賴形成，而藉由電解電鍍所形成之Cu 導^種晶層則係使用CU1而，隨著導線圖樣的更 =細化’被要求埋讀毅加提^因此，便評估從 ^的CU轉換為埋讀良好的CG。CG亦有電阻低且 與Cu的密接性高之優點。 j而’藉㈣解電料形成Cu麟，料雖係使 2 =來作為電鍍液，但由於c。會溶於硫酸，故當 VU難晶層使料，。。便會料至電鏟液。 達到Lt/以下線圖樣的更加微細化，電鑛種晶層 嶸q ：>nm以下而更加溥膜化。當 電鐘種晶層使料，因電鍍處理途_ Cqm。膜作為 液’便會有導致Co膜消失而產生未 ^容出至電鍍 部分或Cu膜的密接性降低之問題。1有Cu電鑛的 因此’本發明之目的在於提供— 種晶層並藉由電解電鑛來形成c C〇作為電鍍 、$，能夠抑制C〇 4 201124564 的溶出並於Co種晶展^ 臈之成膜方法。_·形成質地均勻且密接性高的Cu 又，本發明之其 行上述成膜方法的;的在於提供—種記憶有用以執 手王式之記憶媒體。 【發明内容】 本發明之第1 驟：準備表面形成有作為種成膜方法，係具有以下步 施加使Co的表面電日日s，Co膜之基板；對該基板 衣卸电位較C〇的氣化雷 後，在持續對該基板施力 =要低之負電塵；之 在以硫酸銅溶液為主體的電·，2二:夕膜浸潰 板的Co膜上形成C竭。 胃由电解電鍍而於該基 本發明之第2觀點提供一種成膜 步驟：藉由CVD而於基板上形為法曰，^具有以下 對該基板施加使C。的表面電位較 之負電壓；之後，在持續對該基板施 ^位要低 下’將該C。膜浸潰在以硫酸銅溶液為主狀態 並藉由電解電鍍而於該基板的c〇獏上形電鍍液， 本發明之第3觀點提供—種記憶媒體，技腦 動作，並記憶有用以控制成膜裝置的程式，盆:電細上 係使電腦控制該成膜裝置以於執行時4彳_^^該程式 驟的成膜方法：準備表面形成有作為種晶的以:步 基板；對該基板施加使Co的表面電位:二’ C〇艇之 位要低之負電壓;之後，在持續對該心 201124564 狀態下，將該Co膜浸潰在以硫酸銅溶液為主體的電鍍 液，並藉由電解電鍍而於該基板的Co膜上形成Cu膜。 【實施方式】 以下參照添附圖式，針對本發明之實施形態加以說 明。 <用以實施本發明成膜方法之成膜裝置的一例> 圖1為顯示實施本發明成膜方法之成膜裝置的一 例之概略剖面圖，係作為一種藉由電解電鍍來形成Cu 膜之含浸式電解電鍍裝置所構成。 此成膜裝置100具有支承組件1，係支承表面形成 有作為種晶層的Co膜之被處理基板(半導體晶圓（以下 簡稱為晶圓）W)。支承組件1係藉由迴轉機構(未圖示) 而可迴轉，並藉由迴轉支承組件1，來使晶圓W的面内 迴轉。晶圓W上表面的被處理面係沿著邊緣而相對於 晶圓W呈液密地設置有圓筒狀邊緣密封組件2。然後， 電鍍液L係被儲存在晶圓W表面與邊緣密封組件2所 形成之容器，而該等則構成了下部處理室（chamber)。 又，晶圓W表面之邊緣密封組件2的外侧部分係設置 有電極接點4。 支承組件1所支承之晶圓W的上方係配置有藉由 昇降機構17而可上下移動之圓筒狀電鍍頭10。電鍍頭 10具有：容納有電鍍液L之上部處理室11 ;於上部處 理室11内與晶圓W互相對向地設置之陽極電極12;及 6 201124564 構成上部處理室u 組件13。上部處理二：：質陶瓷所構成的含浸 給口14。然後，電處設置有電鍵液供 電鑛液供給口 14 、 ’、攸電鍍液供給機構16經由 極12上下貫穿地訊上部處理室11内。陽極電 通過孔15 置有供麵液L通過◎個電鑛液 直流㈣極12之間連接有 源5的負極，陽極電接點4而連接於直流電 直汽f*、7f 5係連接於直流電源5的正極。 直仙·窀源5係輪出可變式電壓。 、、：行電鍍處理時，使電鍍頭10接近晶圓w表面， ^攸電，液供給口 14來將電锻液L供給至上部處理室 π二，，係經由含浸組件13而被儲存在構成下 ^至之晶圓W表面與邊緣密封組件2所形成的容 崙，更進—步地而被儲存在上部處理室11内。此時電 鑛液L的液面為能夠讓陽極電極12浸潰其中的程度。 此外，所供給之電鍍液可藉由排液機構(未圖示）而被排 除0 ^成膜凌置1〇〇具有控制部20，而藉由該控制部2〇 來進行各構成部(例如直流電源5、昇降機構17、電鍍 液供給機構16、晶圓支承組件1的驅動機構等 2。該控制部2 〇係具有具備微處理器（電腦）之程序控制 器21、使用者介面22及記憶部23。程序控制器21係 %連接於成膜裝置1 〇〇的各構成部，而可向該等傳送控 201124564 制訊號。使用者介面22連接於程序控制 業員為了管理成膜裝置刚的各構係由作 輸入操作等之鍵盤，或可視化地顯示成膜 了指令的 構成部的稼働狀況之顯示器等所構成^吃鯈00之各 接於程序控制器2!，該記憶部23係容納有：23亦迷 程控制器21的控制來實現成膜裝置刚所執」用製 嫌呈式、配合處理條件來使成膜農置：〇 2 構成.行特定處理之控制程式（亦即處理=各 各種數據資訊等）。處理製程配㈣記憶在記憶部Μ中 =記:：體丄未圖示)。記憶媒體可固定地設置 久，亦可為咖OM、_、快閃記憶體等可移動性 傳逆制^亦可攸其他裝置，例如透過專用線路來適當地 傳送製程配方。 …然後’依需要，藉由利用來自使用者介面Μ的指 不寺’來將特定處理製程配方從記億部23呼叫出並於 制器21執行，以在程序控制器21的控制下於成 Μ裝置100進行所欲處理。 <本發明一實施形態之成臈方法> 接下來，針對利用上述方式構成的成膜裝置來進行 本發明一實施形態之成膜方法加以說明。 圖2為用以說明本發明一實施形態之成膜方法的 流裎圖。 曰。首先，準備表面形成有作為電鍍種晶層的c〇膜之 晶圓W(步驟1)£>c〇膜的厚度較佳為5〜5nm的範圍。 8 201124564 接著，將該晶圓W搬入至藉由電解電鍍來形成Cu膜之 成膜裝置100(步驟2)，而為支承於支承組件1之狀態。 接下來，下降電鑛頭10而成為處理狀態，並將硫 酸銅為主體的電鍍液L供給至上部處理室11内（步驟 3)。然後，如圖3A之概略圖所示，將陽極電極12浸潰 在電鍍液L，並在電鍍液尚未到達晶圓W的狀態下， 從直流電源5對作為陰極電極的晶圓W施加使Co膜 31的表面電位較Co的氧化電位（亦稱為氧化還原電位) 要低之負電壓（步驟4)。 於此狀態下，更進一步地供給電鍍液L，如圖3B 所示，則晶圓W表面（亦即Co膜31)會成為浸潰在電鍍 液L之狀態（步驟5)。此時，由於Co膜31的表面電位 係較Co的氧化電位要低，故即使是硫酸銅為主體的電 鍍液L接觸到晶圓W表面所形成之Co膜，仍不會有 Co溶出至電鍍液L。亦即Co在電化學上為安定狀態。 由於Co的乳化電位為-0.28V ’故將晶圓W表面浸 潰在電鍍液L前，較佳地係在將晶圓W表面浸潰在電 鍍液L之時間點下，施加使得晶圓W(Co膜）與電鍍液 的電位差為0.3V以上之電壓。 如此地使晶圓W表面浸潰在電鍍液後，將來自直 流電源5的電壓調節為實際上Cu電鍍時的電壓，而進 行Cu電鍍處理（步驟6)。此時的電壓較佳為0.1〜3V左 右。藉此晶圓W表面的Co膜上會析出Cu，而形成有 Cu膜。 9 201124564 笔鍍處理結束後’上昇電鏡頭10，來使晶圓W表 面上的電鍍液L排出’並將晶圓w搬出（步驟7)。 由於Co的離子化傾向係較Cll要高，而可溶於硫 酸’故若不進行任何操作地來使以硫酸銅為主體之電鍍 液接觸晶圓W表面的co膜，則c〇會成為c〇+而溶出 至電錢液L中。特別是隨著半導體元件的導線圖樣更加 微細化’電鍍種晶層的膜厚被要求要達到5nm以下， 但如上所述地將薄c〇膜作為電鍍種晶層使用時，當將 Co膜改漬在電鍍液L的時間點下，則隨著c〇的溶出， c〇膜會m肖失產生未形成有Cu電鏟膜的部 分，或發生Cu膜的密接性降低之情況。 主相對於此，本實施形態中，係在將晶圓w表面浸 潰在電鐘液L前，先對作為陰極電極的晶圓w施加使 Co膜的表面電位為較Cg的氧化電位要低之負電壓。因 此’可防止Co溶出至電鍍液，並防止未形成有cu電 鑛的部分產生或CU膜的密接性降低之情況發生，從而 可形成質地均勻且密接性高Cxi膜。 由於Co膜的厚度較5nm愈大，則發生上述問題的 可能性愈小，故本實施形態之方法在c〇膜的厚声 以下時為有效的。另―方面，藉由電解於 Co膜上形成Cu膜時，由於最初係藉由置換電 Co膜姓亥Unm左右，故較佳係使c〇膜的厚 上述被_部份後之厚度。因此，CQ膜的膜厚較^ 1.5〜5nm的範圍。 土句 10 201124564201124564 VI. Description of the Invention: [Technology of the Invention] The present invention relates to a film forming method and a memory medium for forming a Cu film by electrolytic electric forging on a Co seed layer. L圯刖 technology] In recent years, Ik has become more versatile than semiconductors, and has a higher wire-like pattern than A1, and it is also good as a kind of wire. Since the search, the Cu wire is widely formed by electrolysis, and the Cu layer formed by electrolytic plating uses CU1, and the wire pattern is required to be more refined. Therefore, it is evaluated that the CU from ^ is converted to a well-read CG. CG also has the advantages of low electrical resistance and high adhesion to Cu. j and 'by (4) to solve the formation of Cu Lin, although the material is 2 = as a plating solution, but because of c. Will dissolve in sulfuric acid, so when the VU is difficult to crystallize the layer. . It will be fed to the electric shovel. The Lt/lower line pattern is further refined, and the electric mineral seed layer 嵘q :> nm or less is more decimated. When the electric clock is made of a seed layer, the material is processed due to the plating process _ Cqm. When the film is used as a liquid, there is a problem that the Co film disappears and the adhesion to the plated portion or the Cu film is lowered. 1 has Cu electric ore. Therefore, the object of the present invention is to provide a seed layer and form c C 〇 as electroplating by electrolytic electrowinning, which can suppress the dissolution of C〇4 201124564 and exhibit it in Co. Film formation method. _· Forming a Cu having a uniform texture and high adhesion, and the above-described film forming method of the present invention is to provide a memory medium which is useful for holding a memory. SUMMARY OF THE INVENTION In the first step of the present invention, a method for forming a film on a surface is prepared, and a substrate having a surface of Co, which is a surface of a Co film, is applied in the following step; After gasification of the thunder, the negative electric dust is continuously applied to the substrate = the negative electric dust is formed; and the C is exhausted on the Co film which is mainly composed of the copper sulfate solution. According to a second aspect of the present invention, in the second aspect of the present invention, there is provided a film forming step of forming a film on a substrate by CVD, and applying C to the substrate. The surface potential is lower than the negative voltage; after that, the C is kept low on the substrate. The film is impregnated with a copper sulphate solution as a main state and electroplated on the substrate to form a plating solution. The third aspect of the present invention provides a memory medium, which is useful for controlling the brain. The program of the film forming apparatus, the basin is electrically connected to the computer to control the film forming apparatus to perform the film forming method of the program: the surface is formed with a seed crystal as a seed crystal; The substrate is applied with a surface potential of Co: a negative voltage lower than the position of the second 'C'; and thereafter, the Co film is immersed in a plating solution mainly composed of a copper sulfate solution while continuing to the state of 201124564. A Cu film is formed on the Co film of the substrate by electrolytic plating. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. <An example of a film forming apparatus for carrying out the film forming method of the present invention> Fig. 1 is a schematic cross-sectional view showing an example of a film forming apparatus for carrying out the film forming method of the present invention, which is a method of forming a Cu film by electrolytic plating. The impregnated electrolytic plating apparatus is constructed. This film forming apparatus 100 has a support unit 1 on which a substrate (a semiconductor wafer (hereinafter simply referred to as a wafer) W) in which a Co film as a seed layer is formed is formed. The support unit 1 is rotatable by a turning mechanism (not shown), and the surface of the wafer W is rotated by the slewing ring assembly 1. The processed surface of the upper surface of the wafer W is provided with a cylindrical edge seal assembly 2 in a liquid-tight manner with respect to the wafer W along the edge. Then, the plating solution L is stored in a container formed on the surface of the wafer W and the edge seal assembly 2, and these constitute a lower chamber. Further, the outer portion of the edge seal assembly 2 on the surface of the wafer W is provided with electrode contacts 4. A cylindrical plating head 10 that can be moved up and down by the elevating mechanism 17 is disposed above the wafer W supported by the support unit 1. The plating head 10 has: an upper processing chamber 11 in which the plating liquid L is accommodated; an anode electrode 12 disposed opposite to the wafer W in the upper processing chamber 11; and 6 201124564 constitutes an upper processing chamber u assembly 13. Upper treatment 2: impregnation port 14 composed of: a ceramic. Then, the electric portion is provided with a key liquid supply electric ore supply port 14 and ', and the cypsum liquid supply mechanism 16 passes through the electrode 12 up and down to the upper processing chamber 11. The anode electric passage hole 15 is provided with a surface liquid L through which a negative electrode of the active 5 is connected between the direct current (four) poles 12 of the electric ore, and the anode electric contact 4 is connected to the direct current direct steam f*, 7f 5 is connected to the direct current The positive pole of the power source 5. The straight fairy and the Wuyuan 5 series have a variable voltage. When the plating process is performed, the plating head 10 is brought close to the surface of the wafer w, and the liquid supply port 14 supplies the electric forging liquid L to the upper processing chamber π2, and is stored in the upper portion through the impregnation unit 13. The surface formed by the surface of the wafer W and the edge seal assembly 2 is further stored in the upper processing chamber 11 in a further step. At this time, the liquid level of the electric ore liquid L is such a degree that the anode electrode 12 can be impregnated therein. Further, the supplied plating solution can be removed by a liquid discharge mechanism (not shown), and the control unit 20 is provided by the control unit 2, for example. a DC power source 5, a lifting mechanism 17, a plating solution supply mechanism 16, a driving mechanism of the wafer support unit 1, etc. The control unit 2 has a program controller 21 including a microprocessor (computer), a user interface 22, and The memory unit 23. The program controller 21 is connected to each component of the film forming apparatus 1 and can transmit signals to the control unit 201124564. The user interface 22 is connected to the program controller to manage the film forming apparatus. Each of the configurations is constituted by a keyboard that is an input operation or the like, or a display that visually displays the state of the image forming the component of the command, etc., which are connected to the program controller 2, each of which is connected to the program controller 2! The control unit 23 is also controlled by the control unit 21 to realize the film forming device and the processing conditions to make the film forming farm: 〇2 constitutes a control program for specific processing (ie, Processing = various data information, etc.) Process (iv) stored in a storage unit with Μ in mind :: = body Shang not shown). The memory medium can be fixedly set for a long time, and can also be used for mobile OM, _, flash memory, etc., or other devices, such as a dedicated line to properly transfer the process recipe. ...then, as needed, by using the fingering temple from the user interface, the specific processing recipe is called out from the station 23 and executed at the controller 21 to be under the control of the program controller 21. The helium device 100 performs the desired processing. <Method of forming a film according to an embodiment of the present invention> Next, a film forming method according to an embodiment of the present invention will be described with reference to a film forming apparatus configured as described above. Fig. 2 is a flow chart for explaining a film formation method according to an embodiment of the present invention. Hey. First, a wafer W having a c〇 film as a plating seed layer formed on the surface is prepared (step 1). The thickness of the film is preferably in the range of 5 to 5 nm. 8 201124564 Next, the wafer W is carried into a film forming apparatus 100 (step 2) in which a Cu film is formed by electrolytic plating, and is supported by the support unit 1. Next, the electro-mine head 10 is lowered to be in a treated state, and the plating solution L mainly composed of copper sulphate is supplied into the upper processing chamber 11 (step 3). Then, as shown in the schematic view of FIG. 3A, the anode electrode 12 is immersed in the plating solution L, and the wafer W as the cathode electrode is applied from the DC power source 5 in a state where the plating solution has not yet reached the wafer W. The surface potential of the film 31 is lower than the oxidation potential of Co (also referred to as the oxidation-reduction potential) (step 4). In this state, the plating solution L is further supplied, and as shown in Fig. 3B, the surface of the wafer W (i.e., the Co film 31) is immersed in the plating solution L (step 5). At this time, since the surface potential of the Co film 31 is lower than the oxidation potential of Co, even if the plating solution L mainly composed of copper sulfate contacts the Co film formed on the surface of the wafer W, there is no dissolution of Co to the plating. Liquid L. That is, Co is electrochemically stable. Since the emulsification potential of Co is -0.28 V', the surface of the wafer W is immersed in the plating solution L, preferably at a time point when the surface of the wafer W is immersed in the plating solution L, so that the wafer W is applied. The potential difference between the (Co film) and the plating solution is a voltage of 0.3 V or more. After the surface of the wafer W is immersed in the plating solution in this manner, the voltage from the DC power source 5 is adjusted to the voltage at the time of Cu plating, and Cu plating treatment is performed (Step 6). The voltage at this time is preferably about 0.1 to 3 V. Thereby, Cu is deposited on the Co film on the surface of the wafer W, and a Cu film is formed. 9 201124564 After the pen plating process is completed, the electric lens 10 is raised, the plating solution L on the surface of the wafer W is discharged, and the wafer w is carried out (step 7). Since the ionization tendency of Co is higher than C11 and soluble in sulfuric acid, if the electroplating solution mainly composed of copper sulfate is contacted with the co film on the surface of the wafer W without any operation, c〇 will become c. 〇+ and dissolve into the electricity liquid L. In particular, as the wiring pattern of the semiconductor element is further miniaturized, the film thickness of the plating seed layer is required to be 5 nm or less, but when the thin c 〇 film is used as the plating seed layer as described above, when the Co film is changed When the stain is applied to the plating solution L, the c 〇 film may be lost in the portion where the Cu electric shovel film is not formed, or the adhesion of the Cu film may be lowered as the c 〇 is eluted. On the other hand, in the present embodiment, before the surface of the wafer w is immersed in the clock liquid L, the surface potential of the Co film is applied to the wafer w as the cathode electrode to be lower than the oxidation potential of Cg. Negative voltage. Therefore, it is possible to prevent the elution of Co to the plating solution, and to prevent the occurrence of a portion where cu ore is not formed or a decrease in the adhesion of the CU film, thereby forming a Cxi film having a uniform texture and high adhesion. Since the thickness of the Co film is larger than 5 nm, the possibility of occurrence of the above problem is small, so that the method of the present embodiment is effective when the thickness of the c film is below. On the other hand, when a Cu film is formed by electrolysis on a Co film, since the electric Co film is first replaced by a sub-Unm, it is preferable to make the thickness of the c-film thicker. Therefore, the film thickness of the CQ film is in the range of 1.5 to 5 nm. Soil sentence 10 201124564
Co膜的形成方法並未特別限定，可為如濺鍍之物 理蒸鍍(PVD)或化學蒸鍍(CVD)。但隨著導線圖樣的微 細化，為了在微細孔洞亦形成有厚度5nm以下的薄Co 膜，較佳地係利用階梯覆蓋率（step coverage)良好的 CVD。供Co膜形成用之晶圓W係使用於表面形成有作 為底層的SiOxCy絕緣膜(X、y為正的數字）或有機系絕 緣物膜者。 圖4係顯示藉由CVD來形成Co膜之CVD成膜裝 置的一例之概略圖。該CVD成膜裝置200具有處理室 41，該處理室41中的底部係設置有用以水平地支承被 處理基板（晶圓W)之晶座（susceptor)42。晶座42係埋入 有加熱器43，而藉由使加熱器43通電，來加熱晶座42 上的晶圓W。 處理室41的上部處係設置有如同從頂壁向下方突 出般之喷淋頭45。喷淋頭45係將成膜用處理氣體喷出 至處理室41内，而於其上部中央處則設置有導入處理 氣體之氣體導入口 46。喷淋頭45的内部形成有氣體擴 散空間47，噴淋頭45的底板48係設置有多個氣體喷 出孑L 49。氣體導入口 46連接有氣體供給配管51，而氣 體供給配管51則連接有處理氣體供給機構52。然後， 從處理氣體供給機構52經由氣體供給配管51及氣體導 入口 46而被導入至氣體擴散空間47之用以形成Co膜 的處理氣體係從氣體噴出孔49被喷出至處理室41内。 處理室41的底部設置有排氣口 55，該排氣口 55 11 201124564 係連接有排氣配管56。排氣配管56設置有壓力調整閥 及真空幫浦（皆未圖示）。處理室41的側壁處係設置有用 以進行晶圓W的搬出入之搬出入口 57，與開閉該搬出 入口 57之閘閥58。 CVD成膜裝置200係具有與成膜裝置1〇〇之控制 部20相同的控制部60，而與控制部20完全相同地控 制CVD成臈裝置2〇〇。 於上述方式構成的CVD成膜裝置中，將晶圓w 搬入至處理室41内’並使處理室41内真空排氣至特 定的壓力，而從處理氣體供給機構52經由氣體供給配 管51及喷淋頭45來將處理氣體導入至處理室41内， 以於加熱至特定溫度的晶圓W上發生成膜反應而於晶 圓上形成Co膜。 此時的處理氣體只要在實用上能夠形成Co膜的話 並未特別限定。可使用例如雙(1<[_特丁基_N,_乙基_丙酸 脒）姑（II)(Co(tBu-Et-Et-amd)2)之钻脒（cobait amidinate) 與還原劑。還原劑可使用H2氣體、NH3氣體、碳酸氣 體。又，亦可利用八羰基二鈷(C〇2(C〇)8)，而使其於晶 圓W上熱分解來形成Co膜《成膜溫度較佳地前者為 100〜300°c，後者為 120〜300°c。 如此地’藉由於晶圓W上利用CVD來形成· Co膜 後，再如上述般於Co膜上利用電解電鍍來形成cu膜， 則即便是微細圖樣’仍能夠在以良好的階梯覆蓋率下來 形成5nm以下的薄Co膜後，而不會使Cc)膜消失，並 12 201124564 以高密接性來形成Cu膜。 <用以實施本發明成膜方法的成膜農置 上述實施形料，已顯示利用含浸式電解電 來作為成膜裝置100之範例，但此處係顯 鍍政置 電極及表面形成有C。膜的晶w單純地浸潰於3陽極 式的電解電鍍裝置所構成之成膜裝置。、、兒镀液形 圖5係顯示用以實施本發明成膜方 梦 其他範例之概略結構圖。此成膜裝置100，係且胰凌置 鍵液L之電㈣71，該電舰L中浸潰有陽極1存電 然後，將作為陰極電極的晶w浸潰在電 =72。 圓W係藉由驅動機構(未圖示)而 又所。晶 潰在電鐘液L的狀態與被提高至電錄液l=:般浸 .陽極電極72與晶之間係連接有直流 上述方式構成的成膜裝置100,中，如圖6= 3。 晶圓W從電鍍液乙提 士0 6所不，將 為陰極電極的晶圓w:: =從直流電源73對作 的氧化電位要低之負電：、的表面電位為較C。 圓W而將晶圓w 雪:：:之後，即使是下降晶 電位係較Co的Μ ^在電鑛液纟於C〇膜的表面 敏液L。 電位要低’故可防止CO溶出至電 際上cf::4的1:來自直流電源73的電壓調節為實 模上形成有進行CU讀處理，便會在Co 、 ^依辕本實施形態，由於係在將表面形 13 201124564 成有作為電鍍種晶層的Co膜之基板(晶圓”)浸潰在電 鍍液前，先對晶圓w施加使c〇膜的表面電位為較C〇 的氧化電位要低之負電壓，故可防止C〇溶出至U 液，並防止未形成有Cu電鍍的部分產生或Cu膜的^ 接性降低之情況發生，從而可形成質地均勻且密接性^ <實施例> 接下來針對實施例加以說明。 於基板上製作將作為電鍍種晶層的c〇膜形成為严 ，10nm的樣品及形成為厚度5nm的樣品，首先，將詨 等樣品浸潰在電鍍液前不施加電壓而藉由電解電铲= 形j c u臈。又，針對以c 〇膜形成為厚度5 n爪的樣1 , 於浸潰在電鍍液前先施加_2〇v的電壓後再# 鑛來形成^膜。 由私電 一將該等每經過特定時間之電鍍處理狀態的照片顯 示，圖7。如該圖所示，確認了 c〇膜的厚度為之 樣品，即使在電解電鍍處理前不施加電壓，仍可良好地 形成有Cu膜。另一方面，c〇膜的厚度為5nm之樣品， 在電解電鍍處理前不施加電壓的情況下，則c〇會^口失 而未形成有Cu膜。相對於此，針對c〇膜的厚度為允瓜 之樣品，確認了在電氣電鍍處理前先施加-20V的電壓 的情況下’則會良好地形成有Cu膜。 <本發明之其他應用> 此外，本發明不限於上述實施形態而可做各種變 14 201124564 化。例如作為電解電鍍裝置所構成之成膜裝置不限於 上述實施形態所例示者，而可應用於各種形態的裝置。 又，以上已針對使用半導體晶圓作為被處理基板的 情況加以說明，但不限於此，而亦可使用平面顯示器 (FPD)基板等其他的基板。 【圖式簡單說明】 圖1為顯示實施本發明成膜方法之成膜裝置的一 例之概略剖面圖。 圖2為用以說明本發明一實施形態之成膜方法的 流程圖。 圖3A為顯示將晶圓表面浸潰在電鍍液前，對晶圓 施加電壓後的狀態之概略圖。 圖3B為顯示圖3A之狀態後，將晶圓表面浸潰在 電鍍液的狀態之概略圖。 圖4為顯示用以形成作為電鍍種晶層的Co膜之 CVD裝置的一例之概略圖。 圖5為顯示用以實施本發明成膜方法的成膜裝置 其他範例之概略結構圖。 圖6為說明圖5之裝置中，不將晶圓浸潰在電鍍液 的狀態下施加電壓之圖式。 圖7為顯示本發明之實施例結果的照片。 【主要元件符號說明】 15 201124564 L 電鐘液 W 半導體晶圓 1 支承組件 2 密封組件 4 電極接點 5 直流電源 10 電鍍頭 11 上部處理室 12 陽極電極 13 含浸組件 14 電鍍液供給口 15 電鐘液通過孔 16 電鍍液供給機構 17 昇降機構 20 控制部 21 程序控制器 22 使用者介面 23 記憶部 31 Co膜 41 處理室 42 晶座 43 加熱器 45 喷淋頭 46 氣體導入口 16 201124564 47 氣體擴散空間 48 底板 49 氣體喷出孔 51 氣體供給配管 52 處理氣體供給機構 55 排氣口 56 排氣配管 57 搬出入口 58 間閥 60 控制部 71 電鍍槽 72 陽極電極 73 直流電源 100、 100' 成膜裝置 200 CVD成膜裝置 17The method of forming the Co film is not particularly limited, and may be physical vapor deposition (PVD) or chemical vapor deposition (CVD) such as sputtering. However, in order to refine the wire pattern, in order to form a thin Co film having a thickness of 5 nm or less in the fine holes, it is preferable to use CVD having a good step coverage. The wafer W for forming a Co film is formed by forming a SiOxCy insulating film (a number in which X and y are positive) or an organic insulating film as a primer layer on the surface. Fig. 4 is a schematic view showing an example of a CVD film forming apparatus for forming a Co film by CVD. The CVD film forming apparatus 200 has a processing chamber 41 in which a susceptor 42 for horizontally supporting a substrate to be processed (wafer W) is provided. The crystal holder 42 is embedded with a heater 43, and the wafer W on the crystal holder 42 is heated by energizing the heater 43. The upper portion of the processing chamber 41 is provided with a shower head 45 as if protruding downward from the top wall. The shower head 45 discharges the film forming process gas into the processing chamber 41, and a gas introduction port 46 into which the processing gas is introduced is provided at the center of the upper portion. A gas diffusion space 47 is formed inside the shower head 45, and a plurality of gas discharge ports L49 are provided in the bottom plate 48 of the shower head 45. The gas supply port 51 is connected to the gas introduction port 46, and the gas supply pipe 51 is connected to the gas supply pipe 51. Then, the processing gas system for introducing the Co film introduced into the gas diffusion space 47 from the processing gas supply means 52 via the gas supply pipe 51 and the gas inlet port 46 is discharged from the gas discharge hole 49 into the processing chamber 41. An exhaust port 55 is provided at the bottom of the processing chamber 41, and an exhaust pipe 56 is connected to the exhaust port 55 11 201124564. The exhaust pipe 56 is provided with a pressure regulating valve and a vacuum pump (all not shown). The side wall of the processing chamber 41 is provided with a carry-out port 57 for carrying in and out of the wafer W, and a gate valve 58 for opening and closing the carry-out port 57. The CVD film forming apparatus 200 has the same control unit 60 as the control unit 20 of the film forming apparatus 1 and controls the CVD forming apparatus 2 in exactly the same manner as the control unit 20. In the CVD film forming apparatus configured as described above, the wafer w is carried into the processing chamber 41 and the inside of the processing chamber 41 is evacuated to a specific pressure, and the gas is supplied from the processing gas supply unit 52 via the gas supply pipe 51 and the spray. The shower head 45 introduces a processing gas into the processing chamber 41 to form a film formation reaction on the wafer W heated to a specific temperature to form a Co film on the wafer. The processing gas at this time is not particularly limited as long as it can form a Co film practically. For example, a double (1 <[_t-butyl_N,_ethyl-propionate) ruthenium (II) (Co(tBu-Et-Et-amd) 2) can be used as a cobait amidinate and a reducing agent. . As the reducing agent, H2 gas, NH3 gas, or carbonic acid gas can be used. Further, octacarbonylcobalt (C〇2(C〇)8) may be used to thermally decompose on the wafer W to form a Co film. The film formation temperature is preferably 100 to 300 ° C, the latter. It is 120~300°c. In this way, by forming a Co film by CVD on the wafer W and then forming a cu film by electrolytic plating on the Co film as described above, even a fine pattern can be settled with good step coverage. After forming a thin Co film of 5 nm or less, the Cc) film is not removed, and 12 201124564 forms a Cu film with high adhesion. <Formation of the above-mentioned embodiment for performing the film formation method of the present invention, and an example of using the impregnated electrolytic electricity as the film forming apparatus 100 has been shown, but here, the electroplated electrode and the surface are formed with C. . The crystal w of the film was simply impregnated into a film forming apparatus composed of a three-anodic electrolytic plating apparatus. Fig. 5 is a schematic structural view showing another example of the method for forming a film of the present invention. In the film forming apparatus 100, the electric power (4) 71 of the key liquid L is placed in the pan, and the anode 1 is stored in the electric ship L, and then the crystal w as the cathode electrode is immersed in electricity = 72. The circle W is also provided by a drive mechanism (not shown). The state in which the crystal is dissolved in the electric clock liquid L is increased to the electro-acoustic liquid. The anodic electrode 72 is connected to the crystal by a direct current. The film forming apparatus 100 having the above-described configuration is as shown in Fig. 6 = 3. The wafer W is not charged from the plating solution. The wafer w:: = is negatively charged from the DC power source 73. The surface potential is lower than C. After the wafer W w:::, even if the falling crystal potential is lower than the Co Μ ^ in the electro-mineral liquid on the surface of the C 〇 film sensitizing liquid L. The potential is low', so that CO can be prevented from eluting to the electrical environment. cf::4 1: The voltage from the DC power supply 73 is adjusted to form a CU read process on the real mode, and then in Co, according to this embodiment, Since the substrate (wafer) having the surface film 13 201124564 as a Co film as a plating seed layer is immersed in the plating solution, the surface potential of the c 〇 film is first applied to the wafer w. Since the oxidation potential is low and the negative voltage is low, it is possible to prevent the elution of C 至 to the U liquid, and to prevent the occurrence of the portion where the Cu plating is not formed or the decrease of the adhesion of the Cu film, thereby forming a uniform texture and adhesion. [Examples] Next, an example will be described. A c〇 film as a plating seed layer is formed on a substrate, and a sample of 10 nm and a sample having a thickness of 5 nm are formed. First, a sample such as ruthenium is impregnated. No voltage is applied before the plating solution, and by electrolysis shovel = shape jcu 臈. Further, for the sample 1 formed with the c 〇 film as a thickness of 5 n claws, a voltage of _2 〇v is applied before the plating solution is immersed. After the #矿 to form the film. From the private electricity, the plating will be done every time. The photograph of the physical state is shown in Fig. 7. As shown in the figure, it was confirmed that the thickness of the c〇 film was a sample, and even if no voltage was applied before the electrolytic plating treatment, the Cu film was formed satisfactorily. In the case where the thickness of the ruthenium film is 5 nm, if no voltage is applied before the electrolytic plating treatment, the Cu film is not formed and the Cu film is not formed. In contrast, the thickness of the c 〇 film is a sample of the melon film. When it is confirmed that a voltage of -20 V is applied before the electroplating treatment, the Cu film is formed satisfactorily. <Other applications of the present invention> Further, the present invention is not limited to the above embodiment and can be variously changed. For example, the film forming apparatus which is an electrolytic plating apparatus is not limited to the above-described embodiment, and can be applied to various types of apparatuses. Further, the above description has been given of a case where a semiconductor wafer is used as a substrate to be processed. However, the present invention is not limited thereto, and other substrates such as a flat panel display (FPD) substrate may be used. [Brief Description of the Drawings] Fig. 1 is a view showing an example of a film forming apparatus which performs the film forming method of the present invention. Fig. 2 is a flow chart for explaining a film formation method according to an embodiment of the present invention. Fig. 3A is a schematic view showing a state in which a voltage is applied to a wafer before the surface of the wafer is immersed in the plating solution. Fig. 3B is a schematic view showing a state in which the surface of the wafer is immersed in the plating solution after the state of Fig. 3A. Fig. 4 is a schematic view showing an example of a CVD apparatus for forming a Co film as a plating seed layer. 5 is a schematic structural view showing another example of a film forming apparatus for carrying out the film forming method of the present invention. Fig. 6 is a view for explaining the application of a voltage in a state in which the wafer is not impregnated in the plating solution in the apparatus of Fig. 5. Figure 7 is a photograph showing the results of an embodiment of the present invention. [Main component symbol description] 15 201124564 L Electric clock liquid W Semiconductor wafer 1 Support assembly 2 Sealing assembly 4 Electrode contact 5 DC power supply 10 Plating head 11 Upper processing chamber 12 Anode electrode 13 Immersion assembly 14 Plating solution supply port 15 Liquid passage hole 16 Plating solution supply mechanism 17 Lifting mechanism 20 Control unit 21 Program controller 22 User interface 23 Memory unit 31 Co film 41 Processing chamber 42 Crystal holder 43 Heater 45 Sprinkler 46 Gas inlet 16 201124564 47 Gas diffusion Space 48 Base plate 49 Gas discharge hole 51 Gas supply pipe 52 Process gas supply mechanism 55 Exhaust port 56 Exhaust pipe 57 Carry-in port 58 Valve 60 Control unit 71 Plating tank 72 Anode electrode 73 DC power source 100, 100' Film forming device 200 CVD film forming device 17