TW201120970A - Process for packaging semiconductor device with external leads - Google Patents

Process for packaging semiconductor device with external leads Download PDF

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Publication number
TW201120970A
TW201120970A TW098140979A TW98140979A TW201120970A TW 201120970 A TW201120970 A TW 201120970A TW 098140979 A TW098140979 A TW 098140979A TW 98140979 A TW98140979 A TW 98140979A TW 201120970 A TW201120970 A TW 201120970A
Authority
TW
Taiwan
Prior art keywords
lead frame
exposed
lead
cutting
metal
Prior art date
Application number
TW098140979A
Other languages
Chinese (zh)
Other versions
TWI397139B (en
Inventor
Yanxun Xue
Jun Lu
Original Assignee
Alpha & Amp Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Amp Omega Semiconductor Inc filed Critical Alpha & Amp Omega Semiconductor Inc
Priority to TW098140979A priority Critical patent/TWI397139B/en
Publication of TW201120970A publication Critical patent/TW201120970A/en
Application granted granted Critical
Publication of TWI397139B publication Critical patent/TWI397139B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Abstract

This invention discloses a process for packaging semiconductor device with external leads. The process includes Step 1: adhering the semiconductor chips onto the lead frame, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2: providing a plastic molding material to enclose the lead frame; Step 3: removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4: separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads. The said process can enhance the efficiency of packaging and reduce the cost.

Description

201120970 六、發明說明： 【發明所屬之技術領域】 _] 树明涉及—種半導體封裝卫藝，尤其是針對引腳外 露的半導體器件的封裝工藝方法。 【先前技術】 1 %有技術巾肖於㈣外露的半導體料的封裝方法 ，一般採用以下工藝進行，具體包含步驟： 步驟1 Β曰片枯貼·對引線框架上的每個引線框架單 元，分別將晶片枯貼至其栽片臺上;其中，所述的引線 框架包含若干引線框架單元，每個引線框架單元中包含 載片台、以及位於$載片台兩側的若干⑽；相鄰引線 框架單元是通過將各則腳連接至金屬筋而實現連接的 步驟2、聯機鍵合：對於每個引線框架單元，分別用 金屬線鍵合連接其中的晶片和引腳； 步驟3、塑封：對引線框架進持塑封，將晶片、載片 台和部分引腳均封裝在塑封體内;該步驟中，是以引線 框架上的若干金屬筋為分隔，從而形成若干由各個引線 框架單元為單位的塑封腔體；該步驟完成後，所述的每 個引腳被分為塑封在封裝内的引腳内置部分，和暴露在 封裝外的引腳外露部分，所述的金屬筋縱橫連接各個塑封 腔體單元； 步驟4、去溢膠：在塑封過程中，會在塑封體邊緣或 者外路引腳之間等區域殘留有廢料，所以，在該步驟中 ，將所形成的各個塑封腔體邊緣的廢料去除； 098140979 梦驟5、切割分離：衝壓切除各個塑封腔體之間的金 表單編號Α0101 第4頁/共35頁 0983416980-0 屬筋，將各個引線框架單元的引腳之間的連接分割開， 同時保留各個引腳暴露在封裝外的引腳外露部分，從而 形成若干獨立的引腳外露的半導體器件產品。 但是，採用上述封裝方式來封裝形成引腳外露的半導 體器件，具有以下缺點：由於上述步驟中所涉及到的塑 封、去溢膠以及切割分離等工藝，在操作過程中都具有 一定的獨特性，例如，塑封步驟中，需要以金屬筋為分 隔，在整個引線框架上，塑封形成若干條塑封腔體；又 例如，衝壓分離步驟中，需要根據塑封腔體及其間距製 備獨特衝壓模具以分離每個塑封體内的引線框架單元， 最終才能形成若干獨立的半導體器件。針對所提到的這 些獨特的工藝操作要求，並且針對不同類型的引腳外露 的半導體器件的封裝，需要另外來設計並製造能滿足並 實現該些工藝要求的加工模具或者機械工具等，從而不 可避免的導致整個工藝具有較長的準備週期和較高的製 造成本。 综上所述，需要提供一種新的對引腳外露的半導體器 件進行封裝的工藝方法，且該方法所使用的加工模具或 者機械工具等基本上適用于一般封裝工藝，並且同樣適 用於不同類型的引腳外露的半導體封裝，有效提高了封 裝效率，降低了製造成本。 【發明内容】 本發明的目的是提供一種引腳外露的半導體封裝的工 藝方法，其所利用的加工模具以及機械工具均同時適用 于普通封裝工藝及不同類型的引腳外露的半導體封裝工 藝，無需額外設計並製造特有的模具等操作工具，有效 表單編號A0101 第5頁/共35頁 201120970 提高封裝效率，降低製造成本。 為了達到上述目的，本發明的技術方案是提供一種引 腳外露的半導體封裝的工藝方法，包括以下步驟： 步驟1、在引線框架上進行晶片粘貼和連接鍵合；其 中： 所述的引線框架包含若干排列分佈的引線框架單元、以 及用於連接該引線框架單元的金屬筋；所述的每個引線 框架單元包含載片台、以及位於該載片台兩側的若干引 腳；該引腳包含封裝後位於塑封體内的内置部分以及暴 露在塑封體外的外露部分； 在每個引線框架單元上，分別將晶片粘貼至載片台，並 用金屬連接體連接鍵合所述的晶片和引腳； 步驟2、塑封：對整個引線框架進行塑封，利用封裝 模具將所有引線框架單元，包括晶片、載片台和引腳均 封裝在塑封體内；其中，所述引腳的下表面可通過塑封 體的底部暴露； 步驟3、第一次封裝切割：利用切割具將位於金屬筋 以及各個引腳的外露部分上方的塑封材料通過切割除去 ，形成以金屬筋分隔的若干塑封條； 步驟4、第二次封裝切割：利用切割具對整個引線框 架進行橫向和縱向的切割後，分離各個引線框架單元， 形成若干獨立的引腳外露的半導體封裝器件。 進一步，所述的相鄰引線框架單元之間通過將各個引 腳的外露部分連接至金屬筋而實現連接。 所述的相鄰引線框架單元的載片台之間無金屬連接， 相對獨立。 098140979 表單編號A0101 第6頁/共35頁 0983416980-0 201120970 所述的步驟3中，切割過程為：從整個塑封體封裝的 頂部表面處沿金屬筋的設置方向垂直向下切割塑封材料 ，且切割至引線框架的引腳外露部分的上表面為止。 所述的步驟3中，在完成第一次封裝切割後，露出整 條金屬筋的表面，以及露出每個引線框架單元中與該金 屬筋連接的各個引腳外露部分的表面。 本發明的一個實施方式中，所述的步驟3之後進一步 包刮步驟3. 5,將在塑封過程中形成在相鄰引腳的外露部 分之間的塑封材料去除. 在所述步驟3. 5中可以通過去溢膠的方式去除相鄰引 腳的外露部分之間的塑封材料。本發明的另一個實施方 式中，在所述步驟3. 5中也可以利用鐳射去除相鄰引腳的 外露部分之間的塑封材料。 本發明的一個實施方式中，所述的步驟4中，還包含 :步驟4. 1、切筋：切除相鄰塑封條之間的金屬筋，將各 個引線框架單元的引腳之間的連接分割獨立，並保留各 個引腳的外露部分；步驟4. 2、切割：在塑封條的各個引 線框架單元間進行切割，分離後形成若干獨立的引腳外 露的半導體器件。 本發明的另一個實施方式中，所述的步驟4中也可以 先進行切割步驟，再進行切筋步驟，即：步驟4. 1、切割 :在塑封條的各個引線框架單元間進行切割；步驟4. 2、 切筋：再分別切除相鄰引線框架單元之間的金屬筋，將 各個引線框架單元的引腳之間的連接分割獨立，並保留 各個引腳的外露部分，形成若干獨立的引腳外露的半導 體器件。 098140979 表單編號A0101 第7頁/共35頁 0983416980-0 201120970 [0004] 098140979 本發明的另一種技術方案是提供—種引腳外露的半導 體封裝的工藝方法，包括以下步驟： 步驟1、在引線框架上進行晶片粘貼和連接鍵合；其 中： 所述的引線框架包含若干排列分佈的引線框架單元以 及用於連接該引線框架單元的金屬筋；所述的每個引線 框架單元包含載片台、以及位於該裁片台兩侧的若干引 腳；該引腳包含封裝後位於塑封體内的内置部分以及暴 露在塑封體外的外露部分； 在每個引驗架單元上，分_w馳㈣片台，並 用金屬連接體連接鍵合所述的晶片和引腳； 步驟2、塑封：對整個引線框架進行塑封，利用封裝 模具將所有引線框架單元’包括晶片、載片台和引腳均 封裝在塑封體内，其中，所述引腳的下表面可通過塑封 體的底部暴露； 步驟3、第-次封裳切割：利用切割具將位於金屬筋 以及各個引腳的外露部分上方的塑封材料通過切割除去 ，形成以金屬筋分隔的若干塑封.條 步驟4、第一次封裝切割：利用切割具對整個引線框 架進行橫向和縱向的切割後，分離各個引線框架單元， 形成若干獨立的引腳外露的半導體封裝器件。 進-步’所述的相鄰引線框架單元之間通過將引腳的 外露部分連接至金屬筋而實現連接且相鄰引腳的外露部 分之間通過金屬無間隙連接。 所述的相鄰引線框架單元的載片台之間無金屬連接， 相對獨立。 表單編號A0101 第8頁/共35買 0983416980- 201120970 Ο 本發明的一個實施方式中，所述的步驟2之後進一步包刮 步驟2. 5，由塑封體底部去除相鄰引腳的外露部分之間的 金屬。 在所述步驟2. 5中可以通過對封裝後的塑封體進行底 部蝕刻，以去除相鄰引腳的外露部分之間的金屬。本發 明的另一個實施方式中，在所述步驟3中也可以利用鐳射 切割去除封裝底部的相鄰引腳的外露部分之間的金屬。 所述的步驟3中，切割過程為：從整個塑封體封裝的 頂部表面處沿金屬筋的設置方向垂直向下切割塑封材料 ，且切割至引線框架的引腳外露部分的上表面為止。 所述的步驟3中，在完成第一次封裝切割後，露出整 條金屬筋的表面，以及露出每個引線框架單元中與該金 屬筋連接的各個引腳外露部分的表面。 本發明的一個實施方式中，所述的步驟4中，還包含 :步驟4. 1、切筋：切除相鄰塑封條之間的金屬筋，將各 個引線框架單元的引腳之間的連接分割獨立，並保留各 ❹ 個引腳的外露部分；步驟4. 2、切割：在塑封條的各個引 線框架單元間進行切割，分離後形成若干獨立的引腳外 露的半導體器件。 本發明的另一個實施方式中，所述的步驟4中也可以 先進行切割步驟，再進行切筋步驟，即：步驟4. 1、切割 :在塑封條的各個引線框架單元間進行切割；步驟4. 2、 切筋：再分別切除相鄰引線框架單元之間的金屬筋，將 各個引線框架單元的引腳之間的連接分割獨立，並保留 各個引腳的外露部分，形成若干獨立的引腳外露的半導 體器件。 098140979 表單編號Α0101 . 第9頁/共35頁 0983416980-0 201120970 本發明提供的引腳外露的半導體封裝的工藝方法，具 有以下有益的技術效果和優點：本方法所利用的加工模 具以及機械工具均同時適用于普通封裝工藝及不同類型 的引腳外露的半導體封裝工藝，無需額外設計並製造特 有的模具等操作工具，有效提高封裝效率，降低製造成 本。 【實施方式】 [0005] [0006] 以下根據第1圖〜第7圖，詳細說明本發明的較佳實施 例，以更好的理解本發明的技術方案和有益效果。 實施例1 如第2A圖〜第2F圖，第3A圖〜第3F圖以及第4圖所示 ，為本發明所提供的引腳外露的半導體封裝的工藝方法 的一種具體實施例，其是針對具有如下結構特徵的引線 框架來封裝形成引腳外露的半導體器件的。 如第2A圖和第3A圖所示，所述的引線框架包含若干排 列分佈的引線框架單元1、以及用於連接該引線框架單元 的金屬筋2。為了清楚簡潔的顯示說明該引線框架的結構 ，在本實施例中，以包含4個引線框架單元（第2A圖中通 過虛線框出）為例。其中，每個引線框架單元1包含載片 台11、以及位於該載片台11兩側的若干引腳12 ;每個引 腳又包含封裝後位於塑封體内的内置部分121以及預定暴 露在塑封體外的外露部分12 2。進一步，所述的相鄰引線 框架單元1之間通過將各個引腳12的預定外露部分12 2連 接至金屬筋2而實現連接。相鄰引腳12的預定外露部分 122之間由一空間相互分離。 098140979 表單編號A0101 第10頁/共35頁 0983416980-0 201120970 針對上述結構的引線框架，如第4 所提供的封裝工藝方法包含以下步驟 圖所示，本實施例 步驟1、晶片粘貼和連接鍵合： 對於引線框架上的每個引線框架單元1 如第2β圖和第3B圖所示， ’分別將晶片13粘 貼至載片台^上，再利用金屬線14連接鍵合該晶片_ 引聊12 ·’其中’所述的金屬線也可被金屬平板，或金屬 帶等金屬連接體替代來實現晶片13和—12之間的連接 〇201120970 VI. Description of the invention: [Technical field to which the invention pertains] _] Shuming relates to a semiconductor package, in particular, a packaging process for a semiconductor device with exposed pins. [Prior Art] 1% has a technical towel Xiao (4) The method of encapsulating the exposed semiconductor material is generally carried out by the following process, including the steps: Step 1 Bake the film · For each lead frame unit on the lead frame, respectively Pasting the wafer onto its wafer stage; wherein the lead frame comprises a plurality of lead frame units, each of the lead frame units including a stage, and a plurality of (10) on both sides of the stage; adjacent leads The frame unit is a step 2 of connecting by connecting the legs to the metal ribs. The online bonding: for each lead frame unit, the wires and pins are respectively connected by metal wires; Step 3: Plastic sealing: The lead frame is plastically encapsulated, and the wafer, the stage and a part of the lead are encapsulated in the plastic body; in this step, the metal ribs on the lead frame are separated, thereby forming a plurality of units of the lead frame unit. Molding the cavity; after the step is completed, each of the pins is divided into a built-in part of the pin encapsulated in the package, and an exposed part of the pin exposed outside the package, The metal ribs are connected vertically and horizontally to each of the plastic cavity units; Step 4: De-filling glue: During the molding process, waste remains in the area between the edge of the plastic body or the external pins, so in this step, Scrap removal at the edges of each plastic cavity formed; 098140979 Dream Step 5, Cutting Separation: Stamping and cutting the gold form number between each plastic cavity Α0101 Page 4 of 35 pages 1093416980-0 ribs, each lead frame unit The connections between the pins are split, while leaving the exposed portions of the pins exposed outside the package, thereby forming a number of separate exposed semiconductor device products. However, the above-mentioned package method for packaging and forming a lead-exposed semiconductor device has the following disadvantages: due to the processes of plastic sealing, de-filling, and cutting separation involved in the above steps, the process has certain uniqueness in operation. For example, in the plastic sealing step, it is required to be separated by metal ribs, and a plurality of plastic sealing cavities are formed by molding on the entire lead frame; for example, in the stamping and separating step, a unique stamping die needs to be prepared according to the laminating cavity and the spacing thereof to separate each The lead frame unit in the plastic body can finally form several independent semiconductor devices. For the unique process operation requirements mentioned, and for the packaging of different types of exposed semiconductor devices, it is necessary to additionally design and manufacture processing molds or machine tools that can meet and fulfill the requirements of the process, so that Avoidance leads to a longer preparation cycle and higher manufacturing costs for the entire process. In summary, there is a need to provide a new process for packaging a lead-exposed semiconductor device, and the processing die or machine tool used in the method is basically suitable for general packaging processes, and is equally applicable to different types of The exposed semiconductor package leads to improved package efficiency and lower manufacturing costs. SUMMARY OF THE INVENTION An object of the present invention is to provide a process for a lead-exposed semiconductor package, which utilizes both a processing die and a machine tool for a common package process and different types of exposed semiconductor packages. Additional design and manufacture of unique tooling tools, effective form number A0101 Page 5 of 35 201120970 Improve package efficiency and reduce manufacturing costs. In order to achieve the above object, the technical solution of the present invention is to provide a process for a lead-exposed semiconductor package, comprising the following steps: Step 1. Perform wafer bonding and connection bonding on a lead frame; wherein: the lead frame includes a plurality of arranged lead frame units, and metal ribs for connecting the lead frame unit; each of the lead frame units includes a stage, and a plurality of pins on both sides of the stage; the pin includes a built-in portion of the molded body after encapsulation and an exposed portion exposed to the outside of the molded body; on each lead frame unit, respectively, the wafer is pasted to the stage, and the wafer and the lead are bonded by a metal connecting body; Step 2: Molding: molding the entire lead frame, and packaging all the lead frame units, including the wafer, the stage and the lead, in the molding body by using the packaging mold; wherein the lower surface of the pin can pass through the molding body The bottom of the exposure; Step 3, the first package cut: the use of cutting tools will be located outside the metal ribs and each pin The molding material above the exposed portion is removed by cutting to form a plurality of plastic sealing strips separated by metal ribs; Step 4, second packaging cutting: after cutting the entire lead frame horizontally and longitudinally by using a cutting tool, separating the respective lead frame units, A plurality of independent lead-exposed semiconductor package devices are formed. Further, the adjacent lead frame units are connected by connecting the exposed portions of the respective pins to the metal ribs. There is no metal connection between the stages of the adjacent lead frame units, and are relatively independent. 098140979 Form No. A0101 Page 6 / Total 35 page 0983416980-0 201120970 In the step 3, the cutting process is: cutting the molding material vertically downward from the top surface of the entire package package along the direction of the metal ribs, and cutting Up to the upper surface of the exposed portion of the lead frame. In the step 3, after the first package cutting is completed, the surface of the entire metal rib is exposed, and the surface of each lead exposed portion of each lead frame unit connected to the metal rib is exposed. In the embodiment of the present invention, the step 3 is further followed by a step of squeezing the squeezing of the squeezing material between the exposed portions of the adjacent pins during the molding process. The plastic encapsulation material between the exposed portions of adjacent pins can be removed by means of de-glue. In another embodiment of the present invention, the molding material between the exposed portions of adjacent pins may also be removed by laser in the step 3.5. In an embodiment of the present invention, the step 4 further includes: step 4. 1. cutting the ribs: cutting the metal ribs between the adjacent plastic sealing strips, and dividing the connection between the pins of the respective lead frame units Independent, and retain the exposed parts of each pin; Step 4. 2, cutting: cutting between the various lead frame units of the plastic strip, after separation to form a number of independent exposed semiconductor devices. In another embodiment of the present invention, in the step 4, the cutting step may be performed first, and then the step of cutting the ribs, that is, step 4.1, cutting: cutting between the lead frame units of the plastic strip; 4. Cutting the ribs: separately removing the metal ribs between the adjacent lead frame units, separating the connections between the pins of the respective lead frame units, and retaining the exposed portions of the respective pins to form a plurality of independent leads. A semiconductor device with exposed feet. 098140979 Form No. A0101 Page 7 / Total 35 Page 0983416980-0 201120970 [0004] Another technical solution of the present invention is to provide a process for a lead-exposed semiconductor package, comprising the following steps: Step 1, in the lead frame Performing wafer bonding and bonding bonding; wherein: the lead frame comprises a plurality of arranged lead frame units and metal ribs for connecting the lead frame unit; each of the lead frame units includes a stage, and a plurality of pins on both sides of the panel; the pin includes a built-in portion in the package after encapsulation and an exposed portion exposed to the outside of the package; on each of the inspection frame units, a _w (four) stage And bonding the wafer and the lead with a metal connector; Step 2: Molding: molding the entire lead frame, and packaging all the lead frame units 'including the wafer, the stage and the lead in the plastic package by using a package mold In the body, wherein the lower surface of the pin can be exposed through the bottom of the molding body; Step 3, the first-seal cutting: using a cutting tool The plastic sealing material located above the metal ribs and the exposed portions of the respective pins is removed by cutting to form a plurality of plastic seals separated by metal ribs. Step 4: First package cutting: horizontal and vertical use of the cutting tool for the entire lead frame After dicing, the individual leadframe units are separated to form a plurality of discrete lead-exposed semiconductor package devices. The adjacent lead frame units described in the further step are connected by connecting the exposed portions of the leads to the metal ribs and the exposed portions of the adjacent pins are connected by metal without gaps. There is no metal connection between the stages of the adjacent lead frame units, and are relatively independent. Form No. A0101 Page 8 / Total 35 Buy 0983416980-201120970 Ο In one embodiment of the present invention, the step 2 is further followed by a step of scraping the step 2. 5, between the exposed portions of the adjacent pins by the bottom of the molded body Metal. In the step 2.5, the encapsulated package can be bottom etched to remove metal between the exposed portions of adjacent pins. In another embodiment of the invention, laser cutting can also be used in the step 3 to remove metal between the exposed portions of adjacent pins at the bottom of the package. In the step 3, the cutting process is: cutting the molding material vertically downward from the top surface of the entire package package along the direction in which the metal ribs are disposed, and cutting to the upper surface of the exposed portion of the lead of the lead frame. In the step 3, after the first package cutting is completed, the surface of the entire metal rib is exposed, and the surface of each lead exposed portion of each lead frame unit connected to the metal rib is exposed. In an embodiment of the present invention, the step 4 further includes: step 4. 1. cutting the ribs: cutting the metal ribs between the adjacent plastic sealing strips, and dividing the connection between the pins of the respective lead frame units Independent, and retain the exposed parts of each pin; Step 4. 2. Cut: Cut between the lead frame units of the plastic strip, and separate to form a number of independent exposed semiconductor devices. In another embodiment of the present invention, in the step 4, the cutting step may be performed first, and then the step of cutting the ribs, that is, step 4.1, cutting: cutting between the lead frame units of the plastic strip; 4. Cutting the ribs: separately removing the metal ribs between the adjacent lead frame units, separating the connections between the pins of the respective lead frame units, and retaining the exposed portions of the respective pins to form a plurality of independent leads. A semiconductor device with exposed feet. 098140979 Form No. Α0101. Page 9 of 35 pages 0983416980-0 201120970 The present invention provides a method for lead-exposed semiconductor package having the following beneficial technical effects and advantages: the processing tool and the machine tool utilized in the method are both At the same time, it is suitable for common packaging process and different types of lead-exposed semiconductor packaging processes, without the need to additionally design and manufacture unique operation tools such as molds, thereby effectively improving packaging efficiency and reducing manufacturing costs. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 through 7 to better understand the technical aspects and advantages of the present invention. Embodiment 1 As shown in FIG. 2A to FIG. 2F, FIG. 3A to FIG. 3F and FIG. 4 show a specific embodiment of a method for a lead-exposed semiconductor package provided by the present invention, which is directed to A lead frame having the following structural features is packaged to form a lead-exposed semiconductor device. As shown in Figs. 2A and 3A, the lead frame comprises a plurality of arranged lead frame units 1, and metal ribs 2 for connecting the lead frame units. For the sake of clarity and conciseness, the structure of the lead frame will be described. In the present embodiment, four lead frame units (indicated by a broken line in Fig. 2A) are taken as an example. Each of the lead frame units 1 includes a stage 11 and a plurality of pins 12 on both sides of the stage 11; each of the pins further includes a built-in portion 121 inside the package and a predetermined exposure to the plastic package. Exposed portion 12 2 in vitro. Further, the adjacent lead frame units 1 are connected by connecting the predetermined exposed portions 12 2 of the respective pins 12 to the metal ribs 2. The predetermined exposed portions 122 of adjacent pins 12 are separated from each other by a space. 098140979 Form No. A0101 Page 10 / Total 35 Page 0983416980-0 201120970 For the lead frame of the above structure, the packaging process method as provided in the fourth step includes the following steps, the first step of the embodiment, the wafer bonding and the bonding bonding : For each lead frame unit 1 on the lead frame, as shown in the 2β and 3B, respectively, 'the wafer 13 is pasted onto the carrier table, and the wafer is bonded and bonded by the metal wire 14 _ 12 12 The metal wire described in 'where' can also be replaced by a metal plate or a metal connector such as a metal tape to realize the connection between the wafers 13 and 12.

098140979 步驟2、塑封：如第2C圖和第3C圖所示，對整個引線 框架進行塑封’利用-個通用的封裝模具將4個引線框架 單元1 ’包括晶片13、載片台η和引卿12均封裝在塑封體 15内’其中’所述引腳的下表面可通過塑封體的底部暴 露。 步驟3、第一次封裝切割：如第⑼圖和第⑽圖所示， 利用-個較厚的切割具將位於金屬筋2以及各則腳的預 定外露部分122上方的塑封材料通過切割除去形成以金 屬筋2分隔的若干塑封條151 ;具#:切:割方法是：從整個 塑封體15的頂部表面處沿金屬筋2的設置方向垂直向下切 割塑封材料，且切割至引線框架的引腳預定外露部分122 的上表面為止，生產過程中，可通過將塑封體15的高度 減去引線框架的高度，來預估得到需要向下切割的厚度 ，通過對切割具預先設定該切割厚度，以使得該切割步 驟達到所需的精度。 在實際操作過程中，為避免發生未將塑封材料完全切 割去除的情況，可對預估得到的切割厚度稍作提高，保 證切割操作一次性完成’並露出整條金屬筋2的表面，以 表單編能Α0101 第u頁/共35頁 〇_ 201120970 及露出每個引線框架單元中與該金層筋2連接的各個引腳 預定外露料122的表面。錢㈣程t，即㈣切割厚 度增大，錢得在切除引線㈣上方的塑封材料的同時 ，也將引線框架表面向下切除極小—部分，都不會對效 個封裝工藝產生影響。相反，若是該切割操作完成後Γ 仍然有極小部分的輯材料未被去除，勢轉致 操作-次該切割步驟，從而將殘__材料去 ，由此導致整個封裝卫藝的週期加長，生產效率=淨 +步驟3.5、將在塑封過程中形成在相鄰引腳的預定 露部分122之間的塑封材料152通過衝壓去溢膠的 除。在本發明的又-較佳實施财，也可以彻錯心去 割來去除所述的相鄰引腳的預定外露部分122之門刀 材料152。如第1D圖，第2E圖和第3 E圖所示，為去塑封 述塑封材料152後的示意圖，此時，相鄰引腳的外， 122之間不存在任何塑封材料。 分 步驟4、第二次封裝切較薄的切割具對 引線框架進行橫向和縱向的切割後，分離各個弓,線樞固 早疋卜％成4個獨:t的引腳外愈的半導體#裝器件^架 第Μ圖和第3F圖所示）；具體包含以下步驟：步驟A如 切筋：縱向切除相鄰塑封條151之間的金屬筋2，將.、 引線框架單元的引腳12之間的連接分割獨立，並保^個 個引腳的預定外露部分122 ;步驟4 2、 :留各 •任塑封γ乞 151的各個弓丨線框架單元間進行橫向切割，分離後形成、 干獨立的引腳外露的半導體器件3 (如第j圖所示）。右 098140979 在本發明的又一較佳實施例中，步驟4中也可以先 行橫向切割步驟，再進行縱向切筋步驟，即：步 第丨2頁/共35頁 表單編號 A〇im *____ — — ^ 4·1、 201120970 切割：在塑封條151的各個引線框架軍元間進行橫向切割 :步驟4.2、切筋：再縱向分別切除相鄰引線框架單元之 間的金屬筋2，將各個引線框架單元的制12之間的連接 分割獨立，並保留各個引腳的預定外露部分122，形成若 干獨立的引腳外露的半導體器件3 (如第】圖所示）。 [0007] 實施例2 如第5A圖〜第5F圖，第6A圖〜第6ρ圖以及第7圖所示 ’為本發明所提供的引腳外露的半導體封裝的工藝方法 ❹ ㈤另一種具體實施例’其是針對具有如下結構特徵的引 線框架來封裝形成引腳外露的半導體器件的。 如第5A圖和第6A囷所示，所述的引線框架包含若干排 列分佈的引線框架單元1’、以及用於連接該引線框架單 兀的金屬筋2 〇為了清楚簡潔的顯示說明該引線框架的 結構，在本實施例中，同樣以包含4個引線框架單元（第 5A圖中通過虛線框出）為例。其中，每個引線框架單元i ，包含載片台11，、以及位於該載片台n，兩側的若干 Q 引腳12，：每個引腳又包含封裝後位於塑封體内的内置 部分121’以及預定暴露在塑封體外的外露部分122，， 且相鄰引腳的預定外露部分丨22，之間通過金屬無間隙連 接而开> 成一體。進一步，所述的相鄰引線框架單元1，之 間通過將各個引腳12，的預定外露部分丨22’連接至金屬 筋2而實現連接。實施例2的引線框架與實施例丨的引線 框架差別在於，預定外露部分122，之間通過金屬無間隙 連接而形成一體而使金屬筋2，顯得較寬。 針對上述結構的引線框架，如第7圖所示，本實施例 098140979 表單編號A0101 第13頁/共35頁 0983416980-0 201120970 提供的封裝工藝方法包含以下步驟： 步驟1、晶片枯貼和連接鍵合：如第5B圖和第〇圖所示， 對於引線框架上的每個引線框架單元1，，分別將晶片13 枯貼至載片台11，上’再湘金屬線14連接鍵合該晶片 13和引腳12’ ；其中，所述的金屬線也可被金屬平板， 或金屬帶等金屬連接體替代來實現晶片13和引腳12，之 間的連接。 步驟2、塑封：如第5C圖和第6C圖所示，對整個引線 框架進行塑封，利用一個通用的封裝模具將4個引線框架 單兀1，包括晶片13、載片台11，和引腳12，均封裝在塑 f 封體15内，其中，所述的引腳下表面可通過塑封體的 底部暴露，其中第5C圖為塑封後封裝的底部示意圖。 步驟2. 5 '通過對封裝後的塑封體15，進行底部掩膜 姓刻，去除相鄰引腳的預定外露部分122’之間的金屬。 在本發明的又一較佳實施例中，也可以利用鐳射切割來 去除塑封體15底部的相鄰引腳的預定外露部分丨22，之間 的金屬。如第5D圖和第6D商所示，其令，第51)圖為底部 俯視圖’顯示了相鄰引腳的預定外露部分122，之間的金 〇 屬被去除後的示意圖，此時，相鄰引腳的外露部分122， 之間不存在任何物質，從而在第5D圖中可見位於引腳上 方的塑封材料。金屬筋2，也顯得較窄》 步驟3、第一次封裝切割：如第5£；圖和第⑽圖所示， 利用一個較厚的切割具將位於金屬筋2’以及各個引腳的 預定外露部分122’上方的塑封材料通過切割除去，形成 以金屬筋2’分隔的若干塑封條151，；具體切割方法是 0983416980-0 :從整個塑封體15’的頂部表面處沿金屬筋2’的設置方 098140979 表單編號A0101 第14頁/共35頁 201120970 向垂直向下切割塑封材料，且切割至引線框架的引腳外 露部分122’的上表面為止，生產過程中’可通過將塑封 體15’的高度減去引線框架的高度，來預估得到需要向 下切割的厚度，通過對切割具預先設定該切割厚度，以 使得該切割步驟達到所需的精度。 Ο 該步驟在實際操作過程中，仍然和實施例1中所述的 一致’為避免發生未將塑封材料完全切割去除的情況， 可對預估得到的切割厚度稍作提高，保證切割操作一次 性元成’並露出整條金屬筋2，"的表面’以及露出每個引 線框架單元中與該金屬筋2，連接的各個引腳預定外露部 分122’的表面，有效提高切割品質和封裝效率。 步驟4、第一次封裝切割：利用較薄的切割具對整個 引線框架進行橫向和縱向的切割後，分離各個引線框架098140979 Step 2: Molding: As shown in Figures 2C and 3C, the entire lead frame is molded. 'Using a common package mold, the four lead frame units 1' include the wafer 13, the wafer stage η and the introduction 12 is packaged in the molding body 15 'wherein the lower surface of the pin can be exposed through the bottom of the molding body. Step 3, the first package cutting: as shown in the (9) and (10) drawings, the plastic sealing material located above the metal rib 2 and the predetermined exposed portion 122 of each foot is removed by cutting with a thicker cutting tool. a plurality of plastic sealing strips 151 separated by metal ribs 2; with #: cutting: cutting method: cutting the molding material vertically downward from the top surface of the entire molding body 15 along the direction in which the metal ribs 2 are disposed, and cutting to the lead frame The foot is predetermined to the upper surface of the exposed portion 122. During the production process, the thickness of the lead frame can be estimated by subtracting the height of the lead frame from the height of the molded body 15, and the thickness of the cutting is predetermined by cutting the cutting tool. In order to achieve the required precision of the cutting step. In the actual operation process, in order to avoid the case where the molding material is not completely cut and removed, the estimated cutting thickness can be slightly improved to ensure that the cutting operation is completed once and the surface of the entire metal rib 2 is exposed to the form. The 编 Α 101 101 101 101 101 101 101 101 101 101 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 The money (4) process t, that is, (4) the thickness of the cut increases, and the money has to cut off the surface of the lead frame at the same time as the plastic material above the lead (4), and the part of the lead frame is cut down to a small part, which will not affect the packaging process. On the contrary, if the cutting operation is completed, there is still a very small part of the material that has not been removed, and the potential is transferred to the cutting step, thereby removing the residual material, thereby causing the cycle of the entire package to be lengthened, and the production is completed. Efficiency = Net + Step 3.5, the molding material 152 formed between the predetermined exposed portions 122 of adjacent pins during the molding process is removed by stamping. In still another preferred embodiment of the present invention, the doorknife material 152 of the predetermined exposed portion 122 of the adjacent pins can also be removed with care. As shown in Fig. 1D, Fig. 2E and Fig. 3E, in order to deplasticize the molding material 152, at this time, there is no molding material between the outer pins 122 of the adjacent pins. Sub-step 4, the second package cut thinner cutting tool to cut the horizontal and vertical direction of the lead frame, separate each bow, the line pivoting early and then into a single: t-pin outside the semiconductor # The device is shown in FIG. 3 and FIG. 3F; specifically includes the following steps: Step A: cutting the ribs: longitudinally cutting the metal ribs 2 between the adjacent molding strips 151, and the lead pins of the lead frame unit The connection between the divisions is independent, and the predetermined exposed portion 122 of each pin is secured; step 4: 2: each of the 丨 乞 151 of each of the 丨 乞 151 is cut transversely, separated and formed, dried Separate pin exposed semiconductor device 3 (as shown in Figure j). Right 098140979 In another preferred embodiment of the present invention, in step 4, the horizontal cutting step can also be performed first, followed by the longitudinal cutting step, that is, step 2 page / total 35 page form number A〇im *____ — — ^ 4·1, 201120970 Cutting: transverse cutting between the individual lead frame arms of the plastic strip 151: Step 4.2, cutting the ribs: and then separately cutting the metal ribs 2 between the adjacent lead frame units, respectively, and each lead frame The connections between the cells 12 are separated independently, and the predetermined exposed portions 122 of the respective pins are retained to form a plurality of separate exposed semiconductor devices 3 (as shown in the figure). Embodiment 2 As shown in FIG. 5A to FIG. 5F, FIG. 6A to FIG. 6p and FIG. 7 show a process of the lead-exposed semiconductor package provided by the present invention. (5) Another specific implementation For example, it is to form a lead-exposed semiconductor device for a lead frame having the following structural features. As shown in FIGS. 5A and 6A, the lead frame includes a plurality of lead frame units 1' arranged in a distributed arrangement, and a metal rib 2 for connecting the lead frame unit. The lead frame is illustrated for clarity and simplicity. In the present embodiment, the structure is also included as an example including four lead frame units (indicated by a broken line in FIG. 5A). Each of the lead frame units i includes a stage 11 and a plurality of Q pins 12 on both sides of the stage n, each of which further includes a built-in portion 121 inside the package after being packaged. 'and the exposed portion 122 that is intended to be exposed outside the plastic package, and the predetermined exposed portion 丨22 of the adjacent pins is opened by a metal-free connection. Further, the adjacent lead frame units 1 are connected by connecting the predetermined exposed portions 丨 22' of the respective leads 12 to the metal ribs 2. The lead frame of the second embodiment differs from the lead frame of the embodiment 在于 in that the predetermined exposed portions 122 are integrally formed by a metal-free gap connection to make the metal ribs 2 appear wider. For the lead frame of the above structure, as shown in FIG. 7, the package process method provided in this embodiment 098140979 Form No. A0101 Page 13/35 pages 0983416980-0 201120970 includes the following steps: Step 1, wafer dry and connection keys As shown in FIG. 5B and FIG. 5, for each lead frame unit 1 on the lead frame, the wafer 13 is respectively pasted to the stage 11, and the upper metal wire 14 is bonded to the wafer. 13 and pin 12'; wherein the metal wire can also be replaced by a metal plate, or a metal strip or the like to realize the connection between the chip 13 and the pin 12. Step 2: Molding: As shown in Figures 5C and 6C, the entire lead frame is plastically sealed, and four lead frames are singulated by a common package mold, including the wafer 13, the stage 11, and the leads. 12, both of which are encapsulated in the plastic f body 15, wherein the lower surface of the pin can be exposed through the bottom of the molding body, wherein FIG. 5C is a schematic view of the bottom of the plastic package. Step 2. 5' By performing a bottom mask on the packaged molding body 15, the metal between the predetermined exposed portions 122' of the adjacent pins is removed. In still another preferred embodiment of the present invention, laser cutting may also be utilized to remove the metal between the predetermined exposed portions 22 of adjacent pins at the bottom of the molded body 15. As shown in FIG. 5D and FIG. 6D, FIG. 51) is a bottom plan view showing a predetermined exposed portion 122 of an adjacent pin, and the metal genus between them is removed. There is no substance between the exposed portions 122 of the adjacent pins, so that the molding material above the pins can be seen in Figure 5D. Metal rib 2, also appears narrower. Step 3, the first package cut: as shown in Figure 5 and Figure (10), using a thicker cutting tool will be placed on the metal rib 2' and each pin is scheduled The molding material above the exposed portion 122' is removed by cutting to form a plurality of molding strips 151 separated by metal ribs 2'; the specific cutting method is 0983416980-0: from the top surface of the entire molding body 15' along the metal ribs 2' Set side 098140979 Form No. A0101 Page 14 of 35 201120970 Cutting the molding material vertically downwards and cutting it to the upper surface of the exposed portion of the lead of the lead frame 122', during the production process, 'through the molding body 15' The height of the lead frame is subtracted to estimate the thickness required to cut downwards, and the cutting thickness is preset by cutting the cutting tool so that the cutting step achieves the required precision. Ο This step is still consistent with the one described in Example 1 during the actual operation. In order to avoid the case where the molding material is not completely cut and removed, the estimated cutting thickness can be slightly improved to ensure the cutting operation is one-off. Yuan Cheng' reveals the entire surface of the metal rib 2, " and the surface of each of the lead frame units and the predetermined exposed portion 122' of the respective pins connected to the metal rib 2, thereby effectively improving the cutting quality and packaging efficiency. . Step 4. First package cutting: After cutting the entire lead frame horizontally and longitudinally with a thinner cutting tool, separate the lead frames

單兀1 ，形成4個獨立的引腳外露的半導體封裝器件3， (如第5F圖和第6F圖所示）；具體包含以下步驟··步驟 4· 1、切筋：縱向切除相鄰塑封條151;之間的金屬筋2，， 將各個引線框架單元的引腳12,之間的連接分割獨立， 並保留各個引腳的外露部分122，，步驟4. 2、切割：在 塑封條151’ @各個引線框架單元間進行橫向切割，分離 後形成若干獨立的引腳外露的半導體器件3,。 098140979 在本發明的又一較佳實施例中，步驟4中也可以先進 行橫向切割步驟，再進行縱㈣筋步驟，βρ :步驟4. 1、 切割.在塑封條151，&各個引線框架單元間進行橫向切 '步驟4.2切肋.再縱向分別切除相鄰引線框架單元 之間的金屬筋2’，將各個弓丨線框架單元的引則2，之間 的連接分觸立’並㈣各则㈣衫部分122 表單編號Α0101 第15頁/共35頁 ，形 0983416980-0 201120970 成若干獨立的引腳外露的半導體器件3’ 。 本發明提供的引腳外露的半導體封裝的工藝方法，所 利用的加工模具以及機械工具均同時適用于普通封裝工 藝及不同類型的引腳外露的半導體封裝工藝，無需額外 設計並製造特有的模具等操作工具，有效提高封裝效率 ，降低製造成本。 儘管本發明的内容已經通過上述優選實施例作了詳細 介紹，但應當認識到上述的描.述不應被認為是對本發明 的限制。在本領域技術人員閱讀了上述内容後，對於本 發明的多種修改和替代都將是顯而易見的。因此，本發 明的保護範圍應由所附的權利要求來限定。 【圖式簡單說明】 [0008] 第1圖為本發明引腳外露的半導體封裝的結構示意圖 ， 第2A圖〜第2F圖為本發明引腳外露的半導體封裝的工 藝方法的第一種具體實施例的各步驟俯視圖； 第3A圖〜第3F圖為本發明引腳外露的半導體封裝的工 藝方法的第一種具體實施例的各步驟側面剖面圖； 第4圖為本發明引腳外露的半導體封裝的工藝方法的 第一種具體實施例的流程圖； 第5A圖〜第5F圖為本發明引腳外露的半導體封裝的工 藝方法的第二種具體實施例的各步驟俯視圖； 第6A圖〜第6F圖為本發明引腳外露的半導體封裝的工 藝方法的第二種具體實施例的各步驟側面刳面圖； 第7圖為本發明引腳外露的半導體封裝的工藝方法的 098140979 表單編號A0101 第16頁/共35頁 0983416980-0 201120970 第二種具體實施例的流程圖。 【主要元件符號說明】Single 兀1, forming four independent lead-exposed semiconductor package devices 3, as shown in Figures 5F and 6F; specifically including the following steps: Step 4·1, cutting ribs: longitudinally cutting adjacent plastic seals Strip 151; between the metal ribs 2, separate the connection between the pins 12 of each lead frame unit, and retain the exposed portion 122 of each pin, step 4. 2, cutting: in the plastic strip 151 @ @ Each lead frame unit is laterally cut, and after separation, a plurality of independent lead-exposed semiconductor devices 3 are formed. 098140979 In another preferred embodiment of the present invention, in step 4, the transverse cutting step may be performed first, followed by the vertical (four) rib step, βρ: step 4.1, cutting. In the plastic sealing strip 151, & each lead frame Perform transverse cutting between the units' step 4.2. Cut the ribs. Then cut the metal ribs 2' between the adjacent lead frame units in the longitudinal direction, respectively, and connect the joints between the guides 2 of the respective bow line frame units. Each (four) shirt part 122 form number Α 0101 page 15 / total 35 pages, shape 0983416980-0 201120970 into a number of independent pins exposed semiconductor device 3 '. The method for the lead-exposed semiconductor package provided by the invention utilizes the processing die and the mechanical tool both for the common packaging process and different types of lead-exposed semiconductor packaging processes, without the need to additionally design and manufacture a unique mold, etc. Operating tools to effectively improve packaging efficiency and reduce manufacturing costs. Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Accordingly, the scope of the invention should be defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0008] FIG. 1 is a schematic structural view of a lead-exposed semiconductor package according to the present invention, and FIG. 2A to FIG. 2F are first embodiment of a process method for a lead-exposed semiconductor package of the present invention. FIG. 3A to FIG. 3F are side cross-sectional views showing respective steps of a first embodiment of a method for exposing a semiconductor package of the present invention; FIG. 4 is a lead exposed semiconductor of the present invention; A flow chart of a first embodiment of a package process; FIGS. 5A-5F are top views of steps of a second embodiment of a process for exposing a lead-exposed semiconductor package; FIG. 6F is a side elevational view showing the steps of a second embodiment of the process of the lead-exposed semiconductor package of the present invention; FIG. 7 is a process view of the lead-exposed semiconductor package of the present invention 098140979, Form No. A0101 Page 16 of 35 pages 0983416980-0 201120970 A flow chart of a second embodiment. [Main component symbol description]

[0009] 1、Γ 引線框架單元 [0010] 2、2’金屬筋 [0011] 3、3’半導體器件 [0012] 13、13， 晶片 [0013] 14、14， 塑封條 [0014] 15、15’ 塑封體 [0015] 11 、 11， 載片台 [0016] 12、12， 引腳 [0017] 121、121’内置部分 [0018] 122、122’外露部分 [0019] 151 、 151 ’金屬線 [0020] 152、152’塑封材料 098140979 表單編號A0101 第17頁/共35頁 0983416980-0[0009] 1, 引线 lead frame unit [0010] 2, 2' metal ribs [0011] 3, 3' semiconductor device [0012] 13, 13, wafer [0013] 14, 14, plastic seal [0014] 15, 15 'Plastic body [0015] 11 , 11, stage [0016] 12, 12, pin [0017] 121, 121' built-in part [0018] 122, 122 'exposed part [0019] 151, 151 'metal wire [ 0020] 152, 152' molding material 098140979 Form No. A0101 Page 17 / Total 35 page 0983416980-0

Claims (1)

201120970 七、申請專利範圍： 1 . 一種引腳外露的半導體封裝的工藝方法，其特徵在於，具 體包括以下步驟： 步驟1、在引線框架上進行晶片粘貼和連接鍵合； 所述的引線框架包含若干排列分佈的引線框架單元、以及 用於連接該引線框架單元的金屬筋；所述的每個引線框架 單元包含載片台、以及位於該載片台兩側的若干引腳；該 引腳包含封裝後位於塑封體内的内置部分以及暴露在塑封 體外的外露部分； 在每個引線框架單元上，分別將晶片粘貼至載片台，並用 金屬連接體連接鍵合所述的晶片和引腳； 步驟2、塑封：對整個引線框架進行塑封，利用封裝模具 將所有引線框架單元，包括晶片、載片台和引腳均封裝在 塑封體内； 步驟3、第一次封裝切割：利用切割具將位於金屬筋以及 各個引腳的外露部分上方的塑封材料通過切割除去，形成 以金屬筋分隔的若干塑封條； 步驟4、第二次封裝切割：利用切割具對整個引線框架進 行橫向和縱向的切割後，分離各個引線框架單元，形成若 干獨立的引腳外露的半導體封裝器件。 2 .如申請專利範圍第1項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，在所述步驟3之後進一步包括步驟 3. 5 :去除相鄰引腳的外露部分之間的塑封材料。 3 .如申請專利範圍第2項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，所述步驟3. 5中，通過去溢膠的方 098140979 表單編號A0101 第18頁/共35頁 0983416980-0 201120970 式去除相鄰引腳的外露部分之間的塑封材料。 4 .如申請專利範圍第2項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，所述步驟3. 5中，利用鐳射去除相 鄰引腳的外露部分之間的塑封材料。 5 .如申請專利範圍第1項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，所述的相鄰引線框架單元之間通過 將各個引腳的外露部分連接至金屬筋而實現連接且相鄰引 腳的外露部分之間通過金屬無間隙連接。 6 .如申請專利範圍第5項所述的引腳外露的半導體封裝的工 〇 藝方法，其特徵在於，在所述步驟2之後進一步包括步驟 2.5 :由塑封體底部去除相鄰引腳的外露部分之間的金屬 〇 7 .如申請專利範圍第6項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，所述步驟2. 5中，通過對封裝後的 塑封體進行底部蝕刻，以去除相鄰引腳的預定外露部分之 間的金屬。 8 .如申請專利範圍第6項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，所述步驟2. 5中，利用鐳射去除塑 封體封裝底部的相鄰引腳的預定外露部分之間的金屬。 9 .如申請專利範圍第1項或第2項或第6項所述的引腳外露的 半導體封裝的工藝方法，其特徵在於，所述的相鄰引線框 架單元之間通過將各個引腳的外露部分連接至金屬筋而實 現連接。 10 .如申請專利範圍第1項或第2項或第6項所述的引腳外露的 半導體封裝的工藝方法，其特徵在於，所述的相鄰引線框 架單元的載片台之間通過連接至金屬筋而實現連接。 098140979 表單編號A0101 第19頁/共35頁 0983416980-0 201120970 11 .如申請專利範圍第1項或第2項或第6項所述的引腳外露的 半導體封裝的工藝方法，其特徵在於，所述的步驟3中， 切割過程為：從整個塑封體封裝的頂部表面處沿金屬筋的 設置方向垂直向下切割塑封材料，且切割至引線框架的引 腳外露部分的上表面為止。 12 .如申請專利範圍第11項所述的引腳外露的半導體封裝的工 藝方法，其特徵在於，完成步驟3所述的切割步驟後，露 出整條金屬筋的表面，以及露出每個引線框架單元中與該 金屬筋連接的各個引腳外露部分的表面。 13 .如申請專利範圍第1項或第2項或第6項所述的引腳外露的 半導體封裝的工藝方法，其特徵在於，所述的步驟4中， 還包含以下步驟： 步驟4. 1、切筋：切除相鄰塑封條之間的金屬筋，將各個 引線框架單元的引腳之間的連接分割獨立，並保留各個引 腳的外露部分； 步驟4. 2、切割：在塑封條的各個引線框架單元間進行切 割，分離後形成若干獨立的引腳外露的半導體器件。 14 .如申請專利範圍第1項或第2項或第6項所述的引腳外露的 半導體封裝的工藝方法，其特徵在於，所述的步驟4中， 還包含以下步驟： 步驟4. 1、切割：在塑封條的各個引線框架單元間進行切 割； 步驟4. 2、切筋：再分別切除相鄰引線框架單元之間的金 屬筋，將各個引線框架單元的引腳之間的連接分割獨立， 並保留各個引腳的外露部分，形成若干獨立的引腳外露的 半導體器件。 098140979 表單編號A0101 第20頁/共35頁 0983416980-0201120970 VII. Patent application scope: 1. A method for soldering a semiconductor package with a lead, characterized in that it comprises the following steps: Step 1. Perform wafer bonding and connection bonding on a lead frame; the lead frame includes a plurality of arranged lead frame units, and metal ribs for connecting the lead frame unit; each of the lead frame units includes a stage, and a plurality of pins on both sides of the stage; the pin includes a built-in portion of the molded body after encapsulation and an exposed portion exposed to the outside of the molded body; on each lead frame unit, respectively, the wafer is pasted to the stage, and the wafer and the lead are bonded by a metal connecting body; Step 2: Molding: The entire lead frame is plastically sealed, and all the lead frame units, including the wafer, the stage and the leads, are packaged in the plastic body by using the packaging mold; Step 3, the first package cutting: using the cutting tool The molding material located above the metal ribs and the exposed portions of the respective pins is removed by cutting to form gold A plurality of ribs separated plastic; step 4, the second package cutting: After using the cutting tool to carry out the entire lead frame horizontal and vertical cut, separation of the individual lead frame unit, if a dry form individual semiconductor device package pins exposed. The process of the lead-exposed semiconductor package of claim 1, wherein after step 3, step 3. 5 is further removed between the exposed portions of adjacent pins. Plastic sealing material. 3. The method of the lead-exposed semiconductor package according to claim 2, wherein in the step 3.5, the side that passes the glue is 098140979, the form number A0101, page 18/total 35 Page 0983416980-0 201120970 removes the molding material between the exposed portions of adjacent pins. 4. The process of the lead-exposed semiconductor package of claim 2, wherein in step 3.5, the molding material between the exposed portions of the adjacent pins is removed by laser. 5. The method of the lead-exposed semiconductor package of claim 1, wherein the adjacent lead frame units are connected to each other by connecting the exposed portions of the respective leads to the metal ribs. Connected and exposed portions of adjacent pins are connected by metal without gaps. 6. The method of the lead-exposed semiconductor package of claim 5, further comprising the step of: after step 2, removing the exposure of adjacent pins by the bottom of the molded body. The process of the lead-exposed semiconductor package according to claim 6 is characterized in that, in the step 2.5, the bottom of the packaged package is etched. To remove metal between predetermined exposed portions of adjacent pins. 8. The method of the lead-exposed semiconductor package of claim 6, wherein in step 2.5, the predetermined exposed portion of the adjacent pin at the bottom of the package is removed by laser. The metal between. 9. The method of the lead-exposed semiconductor package of claim 1 or 2 or 6, wherein the adjacent lead frame units are passed between respective leads The exposed portion is connected to the metal ribs to achieve the connection. 10. The method of the lead-exposed semiconductor package of claim 1 or 2 or 6, wherein the adjacent lead frame unit is connected by a carrier. Connect to the metal ribs. 098140979 Form No. A0101 Page 19 of 35 0983416980-0 201120970 11. A method of manufacturing a lead-exposed semiconductor package as described in claim 1 or 2 or 6 of the patent application, characterized in that In the step 3 described, the cutting process is: cutting the molding material vertically downward from the top surface of the entire package package along the direction in which the metal ribs are disposed, and cutting to the upper surface of the exposed portion of the lead of the lead frame. 12. The method of the lead-exposed semiconductor package of claim 11, wherein after the cutting step of step 3 is completed, the surface of the entire metal rib is exposed, and each lead frame is exposed. The surface of the exposed portion of each pin in the unit that is connected to the metal rib. The process of the lead-exposed semiconductor package of claim 1 or 2, wherein the step 4 further comprises the following steps: Step 4. 1 Cutting the ribs: cutting off the metal ribs between the adjacent plastic sealing strips, separating the connections between the pins of the respective lead frame units, and retaining the exposed portions of the respective pins; Step 4. 2. Cutting: in the plastic sealing strip Each lead frame unit is cut and separated to form a plurality of independent lead-exposed semiconductor devices. The process of the lead-exposed semiconductor package of claim 1 or 2, wherein the step 4 further comprises the following steps: Step 4. 1 Cutting: cutting between the lead frame units of the plastic strip; Step 4. 2. Cutting the ribs: separately cutting the metal ribs between the adjacent lead frame units, and dividing the connections between the pins of the respective lead frame units Independent, and retaining the exposed portion of each pin, forming a number of independent exposed semiconductor devices. 098140979 Form No. A0101 Page 20 of 35 0983416980-0
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Publication number Priority date Publication date Assignee Title
TWI469292B (en) * 2011-07-26 2015-01-11 萬國半導體股份有限公司 Stacked power semiconductor device using dual lead frame and manufacturing method
TWI497670B (en) * 2012-12-21 2015-08-21 Alpha & Omega Semiconductor Semiconductor devices based on aluminumalloy lead frame and fabricating method thereof

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JP3461332B2 (en) * 1999-09-10 2003-10-27 松下電器産業株式会社 Lead frame, resin package and optoelectronic device using the same
TW200847375A (en) * 2007-05-25 2008-12-01 Chipmos Technologies Inc Lead-frame array package structure
TWI358116B (en) * 2008-02-05 2012-02-11 Advanced Semiconductor Eng Packaging structure and packaging method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI469292B (en) * 2011-07-26 2015-01-11 萬國半導體股份有限公司 Stacked power semiconductor device using dual lead frame and manufacturing method
TWI497670B (en) * 2012-12-21 2015-08-21 Alpha & Omega Semiconductor Semiconductor devices based on aluminumalloy lead frame and fabricating method thereof

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