200847375 • 九、發明說明： 【發明所屬之技術領域】 本發明主要是揭露-種雜結構，更特麟是揭露—種以導線架形成 陣列之封裝結構。 【先前技術】 近年來’由於3C產品的盛行，因此要求半導體元件的尺寸必須進一步 的縮小。為此’近_半導體的後段製大都使用晶圓級的 ：LEVEL CHIP — — ； ^-CSP) 例如’闕專利f 7129581號即揭露一種使用重配置層 七圖麵BUTI0N LAYER)來形成球陣列（BGA)的封裝結構，如第 :不。很明顯地，當使用到晶圓級的封裝製程時，就必須在完成所有 有=如肋_，方能進行G(X)D咖的職，若當日㈣製造過程中 ，則可能會浪費非常多的封裝成本，·同時，重配置層的製造是— 種喊本與費時的技術，往往對單晶片的封裝而言，是不符合經濟效益的。 【發明内容】 2發明背景令’所述之單晶片封裝方式之缺點及問題，本發明的主 件以陣列配置的方式，設置在導線架車Γ封衣^，猎·複數個導電元 複數提供—種以導線架形成陣列之封裝結構，藉以將 導4件_顺制綠，_小《_及降鋪程成本。 含·· 3線種以導線架形成陣列之龍結構。其結構包 羥由複引腳以及複數個較長的引腳所組成，並 由複數個从㈣取及複數她長的⑽構成_第 200847375 面；藉由-黏著層將晶片之背面固接於導線架之第—表面，且晶片的 面上的側邊附近配置有複數個金屬焊塾；複數條金屬導線，用以電性 晶片上之複數個金屬焊墊與導線架之複數個引腳；封膠材料，係用以 晶片、複數條金屬導線、導線架之第—表面及第二表面，並曝露第 士的上的部份金屬；及複數個導電元件，係與曝露的部份金屬電性連接， 精以在導線架之第二表面上形成陣列配置之封裝結構。 本發明還提供-_導_形成陣狀封驗構的方法，包含 由=較__爾獅細丨_狀軸，並且複數個 用：：：复，長的引聊構成導線架的第-表面及第二表面;利 用黏者層將晶片之背面固接在導線架之第—表面，且晶片的主動 ^具有魏個金屬焊墊；形錢雜金料祕複數個 個i腳上，_性連接⑼上之主動面上之複數 = 複數腳；接著’利用封膠材料包覆晶片、金屬導線及導線架 表Γ接著’使用移除製程以移除第二表面的部份封膠材料，200847375 • Nine, invention description: [Technical field to which the invention pertains] The present invention mainly discloses a hybrid structure, and more specifically discloses a package structure in which an array is formed by a lead frame. [Prior Art] In recent years, due to the prevalence of 3C products, the size of semiconductor elements has to be further reduced. For this reason, the near-semiconductor's back-end system uses wafer-level: LEVEL CHIP — — ; ^-CSP. For example, '阙 Patent f 7129581 discloses a reconfigurable layer seven-picture BUTI0N LAYER) to form a ball array ( BGA) package structure, such as: No. Obviously, when using the wafer-level packaging process, it is necessary to complete all the jobs with the G(X)D coffee, if it is in the manufacturing process, it may be wasted very much. More packaging costs, and at the same time, the reconfiguration layer is a kind of shouting and time-consuming technology, which is often not economical for single-chip packaging. SUMMARY OF THE INVENTION [Background of the Invention] The shortcomings and problems of the single-chip package method described in the present invention, the main component of the present invention is arranged in an array configuration manner, and is provided in a lead frame rut seal, and a plurality of conductive elements are provided. A kind of package structure in which the lead frame is formed into an array, so that the guide piece 4 is _ green, _ small "_ and down-laying cost. The three-wire type consists of a lead frame to form an array of dragon structures. The structure of the hydroxyl group is composed of a complex pin and a plurality of longer pins, and is composed of a plurality of (4) and a plurality of long (10) faces thereof. The surface of the wafer is fixed by the adhesive layer. a first surface of the lead frame, and a plurality of metal soldering holes disposed near the side of the surface of the wafer; a plurality of metal wires for the plurality of metal pads and the plurality of pins of the lead frame on the electrical chip; The sealing material is used for the wafer, the plurality of metal wires, the first surface and the second surface of the lead frame, and exposes a part of the metal of the taxi; and the plurality of conductive elements are electrically connected to the exposed part of the metal The connection is made by forming an array structure of the package structure on the second surface of the lead frame. The invention also provides a method for forming a matrix-like seal structure, comprising: a = _ _ _ _ _ _ _ _ _ axis, and a plurality of::: complex, long chat constitutes the first of the lead frame The surface and the second surface; the back surface of the wafer is fixed to the first surface of the lead frame by the adhesive layer, and the active of the wafer has a Wei metal pad; the shape of the money is complicated by a plurality of i feet, _ Complex number on the active surface (9) = plural feet; then 'covering the wafer, metal wire and lead frame with the sealing material, then 'using the removal process to remove part of the sealing material of the second surface,
Lr ⑽上的部份金屬；及形紐數個導電元件於複數 個引腳之曝露的金屬部份， 複數 藉此可以在_之第：表面上形目互電性連接， (:::::與配合圖示作最佳實施例詳細說明如下。 實施例詳細鳴τ Λ、触、綱咖肩瞭解，兹配合 【實施方式】 《本^月以則述之較佳實施例揭露如上，缺豆並非用以—太A 明，任何熟習相像技蓺者 …、_以限疋本叙 之更動與潤飾，因此直發明之精神和範圍内，當可作些許 範圍所界定者為準明之專利保護範圍須視本說明書所附之申請專利 200847375 首先三在本發明所揭露的實施例巾，導線架是利財壓⑽哪)技術， 在片銅4上七成具有複數個引腳之導線架結構，其中複數個引腳圖案可 以視需要所設計。由於沖壓技We^習知技藝，且非本發明所強調之重點， 口此、以冲壓(stamp)技術來形成複數個導線架之詳細過程不在此資述。 首先，請參考第-圖，係本發明之一種導線架之結構上視圖。如第〆 圖所4線架10係由複數個第一引腳埘及複數個第二引腳撤所組成， 且由第一引腳m及第二引腳102構成第一表面及第二表面(未在圖中表 )"，、特欲气於每個第一引腳1〇1與每一個第二引腳撤呈相互間隔之 配且每第一引腳1〇1與每一第二引腳102之間具有一適當距離， 曰、、坐第一引腳102之^部係以一種幾何形狀形成，例如L形或是彎形， Μ二成何形狀之端部104與第一引腳101之端部則位於同-水平線U 上。 個第二引^本^、-月之另^種導線架結構之上視圖。導線架20至少由複數 第引腳、複數個第二引腳202、 引腳2〇4所_，m *數個弟三引腳2G3及複數個第四 每-第1 η 腳構成第—表面及第二表面，其特徵在於： 母一弟一引腳201、每一箆-g丨獅^ 观m —引腳202、母-第三引腳203及每-第四引腳 一腳203及弟四引腳204以异招古4 第二引_2fn 、方式形成，且除了最短的引腳外，例如 弟一引腳203,其餘較長的引腳，例 —# 每一第四引腳204之端部係以 、母1 一引腳202、 第四引_之端部與第形或是:形’且 之幾合形狀之端部位於同一水平線u上。弟—引腳施、母一弟二引腳2〇3 接下來，第三A圖至第三·R岡爲楚 A 及第二圖所揭露之導線第四B圖分別根據第一圖 示，二導Γ力，係本發明之—種封裝結構之剖視圖。如第三Α圖所 百先減-_ 1G，錢由複數個較短之⑽m及複數個較^ 7 200847375 才二全構成導線架1G所組成，並且形成第—表面1G11及第二表面觀； 禮甘1°周的疋’在實際的結構中，一片鋼箱上有複數個導線帛10，在此 接=二3線架1G來說明’其他導線架料封裝過程均完全相同。 50。 *曰曰# 40 ’其主動面402的一側邊附近配置有複數個金屬焊塾 im二40错由黏著層30將晶片40的背面401固接於複數個較短之引腳 複數個較長之引腳102所形成之第一表面1011上，其中晶片40的主 動:搬上的—側邊附近配置複數個金屬焊墊％。在此要強調，在本實施 L ·’其黏者層30的材料可以是一種高分子材料，特別是一種之 ;斗此卜黏著層3〇可以直接貼附於晶片的背面4〇ι上，戋是直接 貼附料_ 1G之第—表社，本發·杨以限制。 —接者’進行打線製程（wire bonding pr〇cess)，係以複數條金屬導線6〇 字複數個引腳101、1G2與晶片4G的主動面上的複數個金屬焊墊％電性連 接。再接著，進行鑄模製程（m〇ldingpr〇cess)，以一封膠材料％包覆住晶 片40的主動面術、複數條金屬導線6〇、導線架ι〇之第一表面聰及第曰 二表面m2。然後，在導線架1G的第二表面進行—移除製程，將位 在第-引腳而之端部103以及第二引腳繼之端部刚上的封膠材料70 移除、，以曝露出端部103以及端部104上的金屬（未在圖中表示）；最後， 進仃導電請8G的連接製程，例如使用回焊製程（reflQws物㈣），依序 在每-端部103以及端部104上的金屬形成金屬凸塊，此導電元件8〇也可 以疋金屬球。㈣顯地，在本實施例巾，由於導線架1()的結構，因此可以 形成一種雙排配置的封裝結構，如第圖所示。 因此，根據以上所述，在本實施例中的複數個導電元件8〇係以2迎之 排列的形式設置於導線架10之第二表面觀上，其中陣列排列的η係視 需求而定。另外，在本實施例中，導電元件80可以是金屬凸塊^ bump)或是錫球(solder ball)，且設置在每一個引腳(較短之引腳1〇1及較長之 引腳102)上的複數個導電元件80，其彼此之間具有相同的高度。 8 200847375 請繼續參考第四A酿第四B圖， 之剖視圖及下視圖。如第四A圖至第四B_表示，構之另—實施例 構與弟二A圖至第三B圖之差異在於導線竿之=所揭路之封裝結 ^ 20 2〇1 ^ t 介卜 ★ 母弟一引腳202一穿一 及母一弟四引腳綱係以相互間隔之平行 :=二$丨腳203 二引腳纖、㈣物及㈣丨職以長短方 ?丨物、第 引聊外，例如第三引腳加，其餘較長的的引腳，例如第—引且除了最短的 第二引職、每-第四_Q4之雜以=丨職、每— 或是f形，且細丨腳綱之端部與n ’例如L形 一第三引職之幾合形狀之端部位於同—水平線:―弟二引職、每 成晶片40的黏貼、打σ 、 上。因此，可以在完 的郷打線!她製程、移除部份封膠材料以及 後’可以將稷數個導電元件8〇形成陣列的形式排列，係如第四A = r圖之俯視圖所示。在此要強調的是，4xn 方式 ^弟 以本發明所揭露之特徵所形成之以導線架為載體之二 …構’均為本發明之實施例。 又 接著，請參考第五A圖至第圖，係本發明之封裝結構之再—實施 例之剖視鼠下。在本實補巾的導線架結構如細—種沖卿程 銅紅形祕數侧導_結構。在本實施财料物Μ係由複數 ^腳群刪及複數個第二引腳群规所組成，第一引腳群及複數個 弟-引腳群902以-間隔成相對排列，其中第一引腳群9〇1具有複數個較 長之引腳9011及複數個較短之引腳9()12 ;而第二引腳群術具有複數個較 長之引腳鹽及複數個較短之引腳9〇22所組成，同時，第一引腳群则 及第二引腳群902中的較長之引腳规、搬1及較短之引腳9〇12、9〇22 呈相互間隔之平行配置，且較長之引腳规卜⑽及較短之引腳·、9〇22 200847375 之間具有一適當距離，豆中笛一 _、簡的端部係以1 ^ ^二引腳群902之較長引腳 何雜——林㈣上=rBW：rM是物，且這些幾 復參閱第五A圖，伤脾a y 固定於在導線架Γ晴面401使用黏著層30黏附並 上，其中在本實施例中的日曰片腳:901及稷數個第二引腳群衝之 金屬焊塾50。接著谁動面402的兩側邊附近配置有複數個 之主動面402之祝丨/丁線技術，以複數條金屬導線60將晶片40 晶L 二引腳群902電性連接。然後，使用封膠材㈣包覆 子旻數條金屬導線6〇及導線竿2〇之彳楚. 個第二引腳群9〇2。 良木20之複數個弟一引腳群則及複數 9〇1及福數伽匕木20的月面進行一移除製程，將位在複數個第一引料 901 %弟·一引1群902上的封膠材料70移除，以曝露出複數個第一 _個第二引腳群9G2端部上的金属（未在圖中表示)，·最後， 80 , (reflowsoldering) . r, 數個第-引腳群剛及複數個第二引腳群9〇2之端部上的金屬形成 電轉80，此導電元件8G也可以是金屬球也可以是金屬凸塊。很明顯地， 在本貫施例中，由於導線架2〇的結構，可以形成由複數個導電元件8〇所 組成的陣列形式排列，如第五β圖所表示。 〃此外’無論是第三Α圖至第三Β圖、第四Α圖至第四Β圖所揭露之實 也例或疋第五A圖至第五β圖所揭露之實施例，在封膠材料％包覆晶片 40、複數條金屬導線6G、導線架之第—表面及第二表面之後，還需包括一 =割步驟(sawing process)，依據切割線9〇之位置進行切割，以便將每一顆 凡成封裝的晶片分開。由於本實施例可以蝴並移除未打線的部份引腳， 、縮】、封I結構之尺寸，故不需要考慮如習知封裝結構中，使用重分佈層 _L)的問題，也不須在切割封裝結構時，須計算晶片與晶片之間的間距， 200847375 也不需要钱刀具會影_職結構，㈣換刀具等_，因此藉由本發 ==^彡顺咖構，顺输縣. 陣列It根據以上所述，可以得到本發明主要是揭露—種以導線架形成 私具_衣結構，、其包含：—導線架，係由複數個較短的引腳以及複數個 一:’卿恤成，並經由該些較短㈣朗及該些較長的引腳構成一第 第二表面；—晶片’藉由—黏著層固接於導線架之第一表面， 用面上的側邊附近配置有複數個金屬焊墊；複數條金屬導線， 日日片、複數條金屬導線、導線架之第一表面及導線架 復 及:數個導電元件，與曝露之引聊電性連接，藉以在： 琛木之弟一表面上形成雙排或陣列的配置。 結』揭露轉_形成陣列配置之封裝 ' '、匕各·提供一個據金屬片上配置有複數個導绩加 _具有複數個較短之引腳及複數個較長之引聊，如;母一導 者’如步驟620所示，進行晶片黏著之步驟，係將複數個曰片的主^，接 上’精由-黏著層將晶片的背面固接於導線架 :，面朝 :悍，《個引腳電性連接，如步驟63。所 :： 所不，使用膠材料來將晶片、複數 η，630 :刻技術’將相對於⑽之端點處的部份 2 ’例 如金屬凸塊(bUmping)或錫球等，與複數個 仏件，例 接，而在導線架之第二表面上形成雙《陣列的配置上電性連 所示，再以切割製程A 攻後，如步驟670 將母顆凡成封裝後的之晶片分開，即完成本發明之 200847375 封裝製程。 顯然地’依照上面實施例中的描述，本發明可能有許多的修正與差異。 因此需要在其附加的權利要求項之範圍内加以理解，除了上述詳細的描述 外，本發明還可以廣泛地在其他的實施例中施行。上述僅為本發明之^ 實施例而已，並義以限定本發明之巾請專利範圍；凡其它未脫離本發^ 所揭示之精神下所完成的等效改變或修飾，均應包含在下述中請專利範 内。 【圖式簡單說明】 第一圖係根據本發明所揭露之技術，具有相互交錯排列之複數個較 長之引腳及複數個較短之引腳之導線架之上視圖； 第二圖係根據本發明所揭露之技術，具有多數個相互交錯排列之長 度不同之複數個引腳之導線架之上視圖； ' 第一 A圖係根據本發明所揭露之技術，係表示具有以^^配置之導電 元件没置於導線架上之封裝結構之剖面圖； 第三B圖係根據本發明所揭露之技術，於相互交錯排列之複數個較長 之引腳及複數個較短之引腳上，設置複數個導電元件之上視圖； 第四A ®係根據本發明所揭露之技術，係表示具有以4xn配置之複數 個導電元件設置於導_上之封裝㈣之剖面圖； 第四B ®係、根據本發明所揭露之技術，係表示於相互交錯排列之複數 個較長之引腳及魏個較短之引腳上，設置複數個導電元件之上視圖； 第五A圖、係、根據本發明所揭露之技術，表示以雙邊打線、且具有以如 配置之複數個導電元件設置於導線架上之封裝結構之剖面圖； 第五6 ®係姻康本發明所揭露之技術，表示於相互交錯排列之複數個 12 200847375 較長之引腳及複數個較短之引腳上，設置複數個導電元件之上視圖 第六圖係根據本發明所揭露之技術的製程流程圖；及 第七圖係根據習知之晶HJ級的封裝製程之示意圖。 【主要元件符號說明】 f' 10導線架 101複數個第一引腳 102複數個第二, 1011第一表面 1012第二表面 11水平線 103，104 端部 20導線架 201第一弓|腳 202第二引腳 203第三弓丨腳 204第四引腳 30黏著層 40晶片 401晶片之背面 402晶片之主動面 50金屬焊塾 60金屬導線 70封膠材料 80導電元件 9〇 切割線 610提供一金屬片所形成的複數個導線架 620提供複數個晶粒並固接於複數個導線, 630進行金屬導線打線製程 13 200847375 640 650 660 670 901 9011 9012 進行封膠製程 曝露導線架部份引腳之金屬 形成複數個金屬元件於曝露引腳之金屬上 進行切割製程 第一引腳群 902第二引腳群 、9021複數個第一引腳 、9022複數個第二引腳 14a part of the metal on Lr (10); and a metal part of the plurality of conductive elements exposed to the plurality of pins, the plurality of which can be connected to each other on the surface: (:::: The detailed description of the preferred embodiment is as follows. The detailed description of the embodiment is as follows: τ 触 触 触 触 、 、 纲 了解 了解 了解 了解 兹 兹 兹 兹 兹 兹 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳Beans are not used - too A Ming, any familiar with the likes of technology ..., _ to limit the changes and refinements of this narrative, so within the spirit and scope of the direct invention, when the scope can be defined as the scope of the patent protection The scope is subject to the patent application 200847375 attached to the present specification. First, in the embodiment of the present invention, the lead frame is a technology of profit and pressure (10), and 70% of the lead frame structure having a plurality of pins on the copper 4 , in which a plurality of pin patterns can be designed as needed. Due to the skill of the stamping technique and not the emphasis of the present invention, the detailed process of forming a plurality of lead frames by stamping techniques is not described herein. First, please refer to the first drawing, which is a structural top view of a lead frame of the present invention. For example, the 4-wire frame 10 is composed of a plurality of first pins 埘 and a plurality of second pins, and the first surface m and the second pin 102 form a first surface and a second surface. (not shown in the figure) ", deliberately, each first pin 1〇1 and each second pin are mutually spaced apart and each first pin is 1〇1 and each first The second pin 102 has an appropriate distance between the two pins 102, and the first pin 102 is formed in a geometric shape, such as an L shape or a curved shape, and the end portion 104 and the first shape are formed. The end of the pin 101 is located on the same-horizontal line U. A second view of the second lead frame ^, - month of the other type of lead frame structure. The lead frame 20 is composed of at least a plurality of pins, a plurality of second pins 202, pins 2〇4, m*, a number of three pins 2G3, and a plurality of fourth every -1st feet forming a first surface And a second surface, wherein: a mother pin 110, each 箆-g 丨 ^ ^ m - pin 202, a mother - third pin 203 and each - fourth pin 203 and The four-pin 204 is formed in the same way as the shortest pin, except for the shortest pin, for example, the first pin 203, the other long pin, for example - each fourth pin The end portion of the 204 is located on the same horizontal line u as the end of the parent 1st pin 202, the end of the fourth lead, and the end or the shape of the shape. Brother - pin, mother, brother, two pin 2〇3 Next, the third A to the third · R Gang is Chu A and the second figure disclosed in the second figure according to the first figure, The two-conducting force is a cross-sectional view of the package structure of the present invention. For example, if the third map is reduced by -1G, the money consists of a plurality of shorter (10) m and a plurality of more than 7 200847375, which form a lead frame 1G, and form a first surface 1G11 and a second surface view; In the actual structure, there is a plurality of wires 帛10 on a steel box. In this case, the 2G line frame 1G is used to illustrate that the other lead frame materials are completely identical. 50. *曰曰# 40 'There are a plurality of metal soldering pads disposed near one side of the active surface 402. The second surface of the wafer 40 is fixed to the plurality of shorter pins by the adhesive layer 30. On the first surface 1011 formed by the pins 102, a plurality of metal pads % are disposed near the active side of the wafer 40. It should be emphasized here that in the present embodiment, the material of the adhesive layer 30 may be a polymer material, in particular, the adhesive layer 3 can be directly attached to the back surface of the wafer.戋 is directly attached to the material _ 1G of the first - table club, this hair · Yang to limit. The "connection" is a wire bonding pr〇cess in which a plurality of pins 101 and 1G2 of a plurality of metal wires are electrically connected to a plurality of metal pads on the active surface of the wafer 4G. Then, the molding process (m〇ldingpr〇cess) is performed, and the active surface of the wafer 40, the plurality of metal wires 6〇, the first surface of the lead frame 聪, and the second surface of the lead frame are covered with a glue material%. Surface m2. Then, the removal process is performed on the second surface of the lead frame 1G, and the sealing material 70 located at the end portion 103 of the first pin and the second pin followed by the end portion is removed to expose The metal at the end portion 103 and the end portion 104 (not shown in the figure); finally, the connection process for the 8G conduction, for example, using a reflow process (reflQws (4)), sequentially at each end 103 and The metal on the end portion 104 forms a metal bump, and the conductive member 8 can also be a metal ball. (4) Explicitly, in the towel of the present embodiment, due to the structure of the lead frame 1 (), a package structure of a double row configuration can be formed as shown in the figure. Therefore, according to the above, the plurality of conductive elements 8 in the present embodiment are disposed on the second surface of the lead frame 10 in a two-arranged arrangement, wherein the array of η is determined depending on the requirements. In addition, in this embodiment, the conductive element 80 may be a metal bump or a solder ball, and is disposed on each of the pins (the shorter pin 1〇1 and the longer pin) 102) A plurality of conductive elements 80 having the same height with each other. 8 200847375 Please continue to refer to Section 4B of Section 4A, section and bottom view. As shown in the fourth A to fourth B_, the difference between the other embodiment and the second to the third B is that the wire = = the package junction of the road is 20 2 〇 1 ^ t Bu ★ mother-in-law one pin 202 one wear one and the mother one younger four-pin series are parallel to each other: = two $ 丨 203 two-pin fiber, (four) and (four) dereliction of duty to long and short? In addition to the third comment, for example, the third pin is added, and the remaining longer pins, for example, the first and the second, except for the shortest second referral, each of the fourth _Q4 are mixed, each, or The shape of the f-shaped, and the end of the fine-footed foot is located at the same level as the end of the shape of the n-type, such as the L-shaped and the third-introducing position: the second line of the work, the affixing of each wafer 40, the σ, on. Therefore, it is possible to finish the beating line! Her process, removal of part of the encapsulant material, and rearrangement of the plurality of conductive elements 8〇 can be arranged as shown in the top view of the fourth A = r diagram. It is to be emphasized that the 4xn mode, which is formed by the features of the present invention and which is formed by the lead frame as the carrier, is an embodiment of the present invention. Further, please refer to FIG. 5A to FIG. 3, which is a cross-sectional view of a re-embodiment of the package structure of the present invention. In the wire frame structure of this real towel, such as fine - kind of qingqing Cheng copper red secret number side guide _ structure. In the present embodiment, the financial material system is composed of a plurality of pin groups and a plurality of second pin group rules, and the first pin group and the plurality of pin-pin groups 902 are arranged in an interval of -, wherein the first Pin group 9〇1 has a plurality of longer pins 9011 and a plurality of shorter pins 9()12; and the second pin group has a plurality of longer pin salts and a plurality of shorter ones The pin 9〇22 is composed of the first pin group and the longer pin gauge of the second pin group 902, the moving 1 and the shorter pins 9〇12, 9〇22 are spaced apart from each other. Parallel configuration, and the longer pin gauge (10) and the shorter pin ·, 9〇22 200847375 have an appropriate distance, the bean flute _, the simple end is 1 ^ ^ two pins The longer pin of the group 902 is miscellaneous - Lin (four) on = rBW: rM is the object, and these several refer to the fifth A picture, the spleen ay is fixed on the lead frame Γ 面 401 using the adhesive layer 30 adhered and In the present embodiment, the corrugated chip legs: 901 and a plurality of second pin groups are punched by the metal pad 50. Then, a plurality of active surfaces 402 are arranged in the vicinity of the two sides of the moving surface 402, and the plurality of metal wires 60 are electrically connected to the wafer 40 L-pin group 902. Then, the sealing material (4) is used to coat the plurality of metal wires 6〇 and the wires 竿2〇. The second pin group 9〇2. A number of younger brothers and sisters of Liangmu 20 and a complex of 9〇1 and Fuji Gayamu 20 have a removal process, which will be located in a plurality of first materials, 901%, and a group of 902. The upper sealing material 70 is removed to expose the metal on the ends of the plurality of first and second second pin groups 9G2 (not shown in the figure), and finally, 80, (reflowsoldering). r, several The metal on the end of the first-pin group and the plurality of second pin groups 9〇2 forms an electrical rotation 80, and the conductive element 8G may also be a metal ball or a metal bump. Obviously, in the present embodiment, due to the structure of the lead frame 2, an array of a plurality of conductive elements 8A can be formed, as shown in the fifth ? diagram. 〃In addition, the embodiments disclosed in the third to third figures, the fourth to fourth figures, or the fifth to fifth figures are disclosed in the sealant. After the material % covers the wafer 40, the plurality of metal wires 6G, the first surface and the second surface of the lead frame, a sawing process is also included, and the cutting is performed according to the position of the cutting line 9〇, so that each A wafer that is packaged is separated. Since this embodiment can butterfly and remove the size of the unpinned part of the pin, the shrinkage, and the I structure, there is no need to consider the problem of using the redistribution layer _L in the conventional package structure, nor When cutting the package structure, the distance between the wafer and the wafer must be calculated. 200847375 does not need the money tool to shadow the job structure, (4) change the tool, etc., so by this hair ==^彡顺咖社, Shun lose county Array It According to the above, it can be obtained that the invention is mainly disclosed in the form of a lead frame forming a private structure, which comprises: a lead frame, which is composed of a plurality of shorter pins and a plurality of ones: Forming a second surface by means of the shorter (four) langes and the longer pins; the wafer is affixed to the first surface of the lead frame by the adhesive layer, A plurality of metal pads are arranged near the sides; a plurality of metal wires, a plurality of metal wires, a plurality of metal wires, a first surface of the lead frame, and a lead frame are combined: a plurality of conductive elements are electrically connected to the exposure. To form a double row or array on the surface of a younger brother Configuration. The knot reveals that the package of the array configuration is '', and each of them provides a plurality of leads on the metal sheet. _ has a plurality of shorter pins and a plurality of longer chats, such as; As shown in step 620, the leader performs the step of bonding the wafers by attaching the main pieces of the plurality of cymbals to the 'fine-adhesive layer to fix the back side of the wafer to the lead frame: facing: 悍, The pins are electrically connected, as in step 63. :: No, use glue material to wafer, complex η, 630: engraving technology 'will be relative to the end of (10) part 2 'such as metal bumps (bUmping) or solder balls, etc., and a plurality of 仏And exemplarily connected to form a dual "array configuration on the second surface of the lead frame", and then after the cutting process A is attacked, as in step 670, the parent wafer is separated from the packaged wafer. That is, the 200847375 packaging process of the present invention is completed. Obviously, the present invention may have many modifications and differences in accordance with the description in the above embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be The above is only the embodiment of the present invention, and is intended to limit the scope of the invention of the present invention; any equivalent changes or modifications made without departing from the spirit of the present invention should be included in the following. Please patent the scope. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a top view of a lead frame having a plurality of longer pins and a plurality of shorter pins arranged in a staggered manner according to the disclosed technology; The technology disclosed in the present invention has a top view of a plurality of lead frames having a plurality of pins having different lengths arranged in a staggered manner; 'The first A figure is a configuration according to the present invention, which is characterized by A cross-sectional view of a package structure in which the conductive member is not placed on the lead frame; and a third B diagram is based on the technique disclosed in the present invention, on a plurality of longer pins and a plurality of shorter pins staggered with each other, A top view of a plurality of conductive elements is provided; the fourth A ® is a cross-sectional view of a package (4) having a plurality of conductive elements arranged in a 4xn arrangement on the lead according to the technique disclosed in the present invention; According to the technology disclosed in the present invention, a plurality of conductive elements are arranged on a plurality of long pins and a short pin which are staggered with each other, and a plurality of conductive elements are disposed on top view; this The technology disclosed in the prior art, which is a cross-sectional view of a package structure which is disposed on a lead frame by a plurality of conductive elements, such as a plurality of conductive elements, is disposed on the lead frame. The fifth 6® system is disclosed in the present invention. a plurality of staggered 12 200847375 on a longer pin and a plurality of shorter pins, a plurality of conductive elements are disposed. FIG. 6 is a process flow diagram according to the disclosed technology; and a seventh diagram It is a schematic diagram of a packaging process according to the conventional crystal HJ level. [Main component symbol description] f' 10 lead frame 101 plural first pins 102 plural second, 1011 first surface 1012 second surface 11 horizontal line 103, 104 end portion 20 lead frame 201 first bow|foot 202 Two pins 203 third bow foot 204 fourth pin 30 adhesive layer 40 wafer 401 wafer back surface 402 wafer active surface 50 metal soldering wire 60 metal wire 70 sealing material 80 conductive element 9 〇 cutting line 610 provides a metal The plurality of lead frames 620 formed by the sheet provide a plurality of crystal grains and are fixed to the plurality of wires, and the 630 is used for the metal wire bonding process. 13 200847375 640 650 660 670 901 9011 9012 The metal of the lead wire of the lead frame is exposed by the sealing process Forming a plurality of metal components on the metal of the exposed pin to perform a dicing process, the first pin group 902, the second pin group, the 9021 plurality of first pins, and the 9022 plurality of second pins 14