201118996 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之封裝構造，特別係有關 於一種銅製程晶片之封裝構造。 【先前技術】 關於半導體裝置元件，現今正朝向更小線寬、更高積 極密度的方向發展。當積體電路最小線寬降低至〇.25微 米以下時，由金屬導線本身的電阻及介電層寄生電容所201118996 VI. Description of the Invention: [Technical Field] The present invention relates to a package structure of a semiconductor device, and more particularly to a package structure of a copper process wafer. [Prior Art] With regard to semiconductor device components, development is now progressing toward a smaller line width and a higher collector density. When the minimum line width of the integrated circuit is reduced to less than 2525 μm, the resistance of the metal wire itself and the parasitic capacitance of the dielectric layer
引起的時間延遲（RC delay)，已成為影響元件運算速度的 主要關鍵。因此，為了提高元件的運算速度，目前業者 於0.13微米以下之高階製程已逐漸改採銅金屬導線來取 代傳統的鋁/鶴或鋁/銅導線，銅製程已成為全世界高階 積體電路多層導線技術的主流n銅是較為活潑的 金屬，對矽晶材料以及大多數之介電質材料而言，由晶 片或基板散發出的銅離子都是影響性質的污染物。矽晶 片的半㈣層-旦受到銅離子之渗將使少數載子生 命週期縮短及元件漏電流增加。再者，若銅離子滲入石夕 晶片内介㈣，也會使晶片的崩潰電場降低及漏電流增 加。 習知銅製程晶片之封裝構造中， 道 γ除了晶片具有銅金 導線’在基板上也形成有細密 在的鋼線路層，各銅線路 上的I/O連接墊通常另需再 ^ ^ _ 層金（Au)層，藉以防 氧化並幫助接合，並可藉由打 .^ a 線方式而電性連接至晶片， 在金層與銅線路層之間形成有一 阻障層，以避免金層與 201118996 線路層之間產生金屬擴散。然此阻障層僅局部形成卯 連接墊下且相當的局部化且薄’無法阻止由銅線路層之 線路π位散發出之銅離子擴散到銅製程晶#之半導體 層加上鋼製程晶片之本身銅離子的散發更容易造成晶 片功能失效，是銅製程晶片之堆疊封裝構造中，介 設在上晶片與基板之間的中間晶片更容易有晶片功能失 效的問題。 【發明内容】 本發明之主要目的係在於提供一種銅製程晶片之封 裝構造與其使用之銅製程晶片，可防止銅離子從基板之 鋼線路層擴散至鋼製程晶片之主動面，進而避免誘發銅 製程晶月的功能失效。 本發明之次一目的係在於提供一種銅製程晶片之封 裝構造與其使用之鋼製程晶片，應用於多晶片堆疊結構 時，能使銅製程晶片堆疊之間不會有銅離子擴散污染， 提高產品信賴度。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種鋼製程晶片之封裝構造， 主要包含一基板、一第一銅製程晶片以及至少一第一電 性連接元件。該基板係具有一核心層、一具有連接塾之 鋼線路層、一圖案化擴散障蔽層以及一防銲層，該銅線 路層係形成於該核心層上，該圖案化擴散障蔽層之圖案 係與該銅線路層之圖案完全一致，以完整覆蓋於該銅線 路層之上’該防銲層係覆蓋該圖案化擴散障蔽層與該核 201118996 心層’該防銲層係具有至少一開孔，係顯露該圖案化擴 散障蔽層在該連接墊上的部位，該基板係更具有—接合 層，係附著於該圖案化擴散障蔽層在該開孔内之部位。 該第一銅製程晶片係設置於該基板上，該第一鋼製程晶 片係具有至少一第一銅墊。該第一電性連接元件係連接 該第一銅墊與該接合層。本發明還揭示一種上述封裝構 造使用之鋼製程晶片。The resulting RC delay has become the main factor affecting the speed of component operation. Therefore, in order to improve the computing speed of components, the current high-order process of 0.13 micron or less has gradually changed the copper metal wire to replace the traditional aluminum/heel or aluminum/copper wire. The copper process has become a high-order integrated circuit multilayer wire in the world. The mainstream n-copper of technology is a more active metal. For twinned materials and most dielectric materials, the copper ions emitted by the wafer or substrate are all pollutants that affect the properties. The half (four) layer of the germanium wafer will be exposed to copper ions, which will shorten the minority carrier life cycle and increase the component leakage current. Furthermore, if copper ions penetrate into the inner layer of the silicon wafer, the collapse electric field of the wafer is reduced and the leakage current is increased. In the package structure of the conventional copper process wafer, the channel γ except the wafer has a copper gold wire 'there is also a fine steel circuit layer formed on the substrate, and the I/O connection pads on each copper line usually need another layer. The gold (Au) layer is used to prevent oxidation and assist bonding, and can be electrically connected to the wafer by means of a wire, and a barrier layer is formed between the gold layer and the copper circuit layer to avoid the gold layer and 201118996 Metal diffusion occurs between circuit layers. However, the barrier layer is only partially formed under the germanium connection pad and is relatively localized and thin 'cannot prevent the copper ions emitted from the π-position of the copper circuit layer from diffusing to the semiconductor layer of the copper process crystal plus the steel process wafer. The emission of copper ions is more likely to cause the function failure of the wafer. In the stacked package structure of the copper process wafer, the intermediate wafer disposed between the upper wafer and the substrate is more susceptible to the failure of the wafer function. SUMMARY OF THE INVENTION The main object of the present invention is to provide a copper process wafer package structure and a copper process wafer thereof, which can prevent copper ions from diffusing from the steel circuit layer of the substrate to the active surface of the steel process wafer, thereby avoiding induced copper process crystal The function is invalid. A second object of the present invention is to provide a package structure for a copper process wafer and a steel process wafer for use thereof. When applied to a multi-wafer stack structure, copper ions can be prevented from being diffused and contaminated between the copper wafer stacks, thereby improving product reliability. degree. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a package structure of a steel process wafer, which mainly comprises a substrate, a first copper process wafer and at least one first electrical connection component. The substrate has a core layer, a steel circuit layer having a connection 、, a patterned diffusion barrier layer, and a solder resist layer formed on the core layer, and the patterned diffusion barrier layer is patterned. Consistent with the pattern of the copper circuit layer to completely cover the copper circuit layer. The solder resist layer covers the patterned diffusion barrier layer and the core 201118996 core layer. The solder resist layer has at least one opening. And exposing the portion of the patterned diffusion barrier layer on the connection pad, the substrate further having a bonding layer attached to the portion of the patterned diffusion barrier layer in the opening. The first copper process wafer is disposed on the substrate, and the first steel process wafer has at least one first copper pad. The first electrical connection component connects the first copper pad to the bonding layer. The present invention also discloses a steel process wafer for use in the above package construction.
本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在則述的封裝構造中，該圖案化擴散障蔽層之材質係 可為鎳（Ni)。 、 在前述的封裝構造中，該第一電性連接元件係可為打 線形成之銲線。 在刖述的封裝構造中，該第一電性連接元件之材質係 可為金，該接合層之材質亦可為金。 在前述的封裝構造中，該圖案化擴散障蔽層係可作為 一形成該銅線路層之蝕刻遮罩，而使該銅線路層不延伸 至該核心層之邊緣。 在前述的封裝構造中，該第一銅製程晶片係可包含一 第半導體層、-第-晶背黏著層以及-第一擴散障蔽 層，其中該第一擴散障蔽層係介設於該第一半導體層與 該第一晶背黏著層之間，且全面覆蓋該第一半導體層。 在前述的封駿構造中’可另包含一第二銅製程晶片以 及至v第一電性連接元件。該第二銅製程晶片係設置 201118996 於該第一鋼製程晶片上，該第二銅製程晶片係具有至少 一第二銅墊。該第二電性連接元件係連接該第二鋼墊與 該第銅墊。 在前述的封裝構造中’該第二銅製程晶片係可包含一 第一爭導體層、一第二晶背黏著層以及一第二擴散障蔽 層，其中該第二擴散障蔽層係介設於該第二半導體層與 該第；晶背黏著層之間，且全面覆蓋該第二半 β前述的封裝構造中，該第二擴散障蔽層係可為晶圓 擊 級濺键形成。 在前述的封裝構造中，該第二擴散障蔽層之材質係可 為鎳（Ni) 9 在前述的封裝構造中，該第二半導體層係可具有經晶 背研磨之厚度。 由以上技術方案可以看出，本發明之銅製程晶片之封 裝構造與其使用之銅製程晶片，具有以下優點與功效： # 、巧"藉由基板之圖案化擴散障蔽層之圖案與該銅線路 層之圖案完全一致作為其中之一技術手段，圖案化 擴散障蔽層能完整覆蓋於銅線路層之上，可防止銅 離子從基板之銅線路層擴散至鋼製程晶片之主動 面，進而避免誘發銅製程晶片的功能失效。本發明 特別適用於解決銅製程晶片之堆疊封裝構造中使中 間晶片之功能失效的問題。 可藉由銅製程晶片在半導體層背面增設的全面覆蓋 擴散障蔽層作為其中之一技術手段，應用於多晶片 201118996 堆疊結構時，能使銅製程晶片堆疊之間不會有銅離 子擴散污染’提高產品信賴度。 一 了藉由圖案化擴散障蔽層完整覆蓋於銅線路層之上 作為其t之一技術手段，使圖案化擴散障蔽層作為 形成銅線路層之蝕刻遮罩，能使銅線路層不延伸至 核心層之邊緣，即不需要習知的電鍍導線也不會有 外露在核心層邊緣的電鍍導線斷面，以避免靜電放 電。 _ 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係’圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 Φ 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設汁’詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種銅製程晶片之封 裝構造舉例說明於第丨圖之局部截面示意圖與第2圖之 截面不意圖。該封裝構造1〇〇主要包含一基板11〇、一 第一銅製程晶片120以及至少一第一電性連接元件13〇。 該基板110係具有一核心層111、一具有連接墊112 之銅線路層113、一圖案化擴散障蔽層114以及一防銲 層11 5 °該基板1丨〇係作為晶片載體與對晶片電性轉接 201118996 之用，通常係為印刷電路板。該核心層111係作為該基 板11 〇之中心結構層，一般是玻璃纖維強化樹脂’選用 的樹脂材質可為環氧樹脂（epoxy resin)、聚亞醯胺 (polyimide)樹脂、BT(bismaleimide trazine)樹脂、FR4 樹脂等。 該銅線路層113係形成於該核心層111上。該銅線路 層 113係為由銅箔蝕刻的線路結構，使銅層經曝光 (exposing)、顯影（developing)、银刻（etching)等製程而The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the package structure described above, the material of the patterned diffusion barrier layer may be nickel (Ni). In the foregoing package structure, the first electrical connection component may be a wire formed by wire bonding. In the package structure described above, the material of the first electrical connection element may be gold, and the material of the bonding layer may also be gold. In the foregoing package construction, the patterned diffusion barrier layer can serve as an etch mask for forming the copper wiring layer such that the copper wiring layer does not extend to the edge of the core layer. In the foregoing package structure, the first copper process wafer system may include a first semiconductor layer, a first-crystalline back adhesion layer, and a first diffusion barrier layer, wherein the first diffusion barrier layer is disposed in the first The semiconductor layer and the first crystal back adhesion layer are completely covered by the first semiconductor layer. In the foregoing seal structure, a second copper process wafer and a v first electrical connection element may be further included. The second copper process wafer is disposed on the first steel process wafer, and the second copper process wafer has at least one second copper pad. The second electrical connection element connects the second steel pad and the second copper pad. In the foregoing package structure, the second copper process wafer layer may include a first contiguous conductor layer, a second crystal back adhesion layer, and a second diffusion barrier layer, wherein the second diffusion barrier layer is disposed in the Between the second semiconductor layer and the first back-adhesive layer, and covering the second half of the package structure as described above, the second diffusion barrier layer may be formed by wafer-level splash bonding. In the foregoing package structure, the material of the second diffusion barrier layer may be nickel (Ni) 9 in the foregoing package structure, and the second semiconductor layer may have a back-grind thickness. It can be seen from the above technical solutions that the package structure of the copper process wafer of the present invention and the copper process wafer used therein have the following advantages and effects: #,巧巧"The pattern of the diffusion barrier layer by the substrate and the copper line The layer pattern is completely consistent as one of the technical means. The patterned diffusion barrier layer can completely cover the copper circuit layer, preventing copper ions from diffusing from the copper circuit layer of the substrate to the active surface of the steel processing chip, thereby avoiding induced copper. The function of the process chip is invalid. The present invention is particularly useful for solving the problem of ineffectively functioning the intermediate wafer in a stacked package configuration of a copper process wafer. The full coverage diffusion barrier layer added to the back side of the semiconductor layer by the copper process wafer can be used as one of the technical means, and can be applied to the multi-wafer 201118996 stack structure, so that there is no copper ion diffusion contamination between the copper process wafer stacks. Product reliability. By patterning the diffusion barrier layer over the copper circuit layer as a technical means of t, the patterned diffusion barrier layer is used as an etching mask for forming the copper circuit layer, so that the copper circuit layer does not extend to the core. At the edge of the layer, there is no need for conventional plating wires and there is no cross section of the plated wire exposed at the edge of the core layer to avoid electrostatic discharge. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description of Φ. The actual number, shape, and size ratios of the implementation are an alternative design. The detailed component layout may be more complicated. According to a first embodiment of the present invention, a sealing structure of a copper process wafer is exemplified in a partial cross-sectional view of the second drawing and a cross-sectional view of the second drawing. The package structure 1 〇〇 mainly includes a substrate 11 , a first copper process wafer 120 and at least one first electrical connection element 13 . The substrate 110 has a core layer 111, a copper wiring layer 113 having a connection pad 112, a patterned diffusion barrier layer 114, and a solder resist layer 11 5 . The substrate 1 is used as a wafer carrier and a wafer. Transfer to 201118996, usually for printed circuit boards. The core layer 111 is used as the central structural layer of the substrate 11 and is generally made of a glass fiber reinforced resin. The resin material selected may be an epoxy resin, a polyimide resin, or a BT (bismaleimide trazine). Resin, FR4 resin, etc. The copper wiring layer 113 is formed on the core layer 111. The copper wiring layer 113 is a wiring structure etched by a copper foil, and the copper layer is subjected to exposing, developing, etching, and the like.
圖案化（patterning)以形成多數導電跡線（conductive trace) ’並形成有連接墊（bonding pad) 112。其中一條導 電跡線與對應連接之連接墊112可見於第4圖。 如第4圖所示’該圖案化擴散障蔽層H4之圖案係與 該銅線路層113之圖案完全一致，以完整覆蓋於該鋼線 路層113之上，可用於保護該銅線路層113之金屬層不 易被氧化’並用以避免銅離子從該銅線路層113散發擴 散至該第一銅製程晶片12〇,進而避免誘發該第一鋼製 程晶片120的功能失效。特別是避免銅離子從該銅線路 層113的導電跡線散發擴散至該第一銅製程晶片12〇之 -第-半導體们22。較佳地，該圖案化擴散障蔽層ιΐ4 .之材質係可為錄（Ni)，具有良好之銅離子擴散障蔽能 力。該圖案化擴散障蔽層114之厚度介於1至2〇微米 (μιη)。 該防銲層115係覆蓋該圖案化擴散障蔽層ιΐ4與該杉 心層m，該防㈣115係具有至少一開孔u6，該開巩 201118996 116係顯露該圖案化擴散障蔽層ii4在該連接墊112上 的部位。該基板110係更具有一接合層117，係附著於 該圖案化擴散障蔽層114在該開孔116内之部位。較佳 地，該接合層117係可為金（Au)層，可提升該基板110與 i 該第一銅製程晶片120之間在進行打金線過程中構成穩 固的電性連接。 具體而言，如第2圖所示，該基板11〇可另包含複數 個外接墊118與一防銲層119。該些外接墊118係形成 於該核心層111下表面’用以設置複數個銲球16〇。該 些外接墊118經内部線路結構電性連接至對應之連接墊 112。該些銲球160可供與一外部之印刷電路板（pHnted circuit board’ PCB)電性連接或堆疊另一半導體封裝構 造。該些外接墊118之材質亦可為銅。該基板11〇係為 積層式（laminate)且為雙面導通之電路板。 詳細而言，該些防銲層115、119係分別塗佈於該基 板110之上下表面，以形成一能遮覆導電跡線以免於受 外界水氣、污染物侵害之保護層。該些防銲層115、119 可為俗稱之「綠漆」（Solder mask or solder Resist)，以 環氧樹脂及感光樹脂為主要成份。但該些防銲層ιι5、 119不限定綠色，亦可為黑色、紅色、藍色或其它任意 顏色等。 凊再參閱第1圖所不，該第一鋼製程晶片12〇係設置 於該基板110上，該第一鋼製程晶片12〇係具有至少一 第一銅墊121。該第一銅製程晶片12〇係可包含該第一 201118996 • 半導體層122以及一第一晶背黏著層123。該第一半導 體層122之材質可為矽、砷化鎵或其它半導體材質，其 係可具有經晶背研磨之厚度。即該第一半導體層122係 經研磨至適當之厚度後再黏貼該第一晶背黏著層】23， 再利用該第一晶背黏著層〗2 3黏點該第一銅製程晶片 120之背面至該基板11〇上。該第一晶背黏著層123係 可利用網印或針筒點膠、貼附等方法形成在該第一銅製 _ 程晶片120之背面，其材質係可為樹脂、B階膠體、黏 性膠片（Film)、環氧黏膠（Ep〇xy)、非導電膠或液態膠體。 該第一銅製程晶片120係為鋼製程製作之積體電路，該 些第一銅墊（copperbond pad)121係可單（多）排排列在該 第一銅製程晶片120主動面之周邊，並以銅互連線路124 連接’作為連接積體電路之對外端點。在本實施例中， 該第一銅製程晶片1 20係可為一種記憶體晶片，例如同 步動態隨機存取記憶體（SDRAM)或雙倍速率傳輸動態隨 _ 機存取記憶體（DDRDRAM)等等。 如第1圖所示，該第一電性連接元件13〇係連接該第 一銅墊121與該接合層117。該第一電性連接元件13〇 係可為打線形成之銲線。較佳地，該第一電性連接元件 130之材質係可為金，該接合層U7之材質亦可為金， 藉此達到良好之鍛接接合力。另外，也可以使用導電性 較佳的銅銲線來代替。 如第2圖所示，該封裝構造1〇〇可另包含一第二銅製 程晶片140以及至少一第二電性連接元件15〇。該第二 10 201118996 銅製程晶片140係設置於該第一銅製程晶片ι2〇上該 第二銅製程晶片140係具有至少一第二銅墊141，該些 第二銅墊141係以銅互連線路144連接。該第二電性連 接元件150係連接該第二鋼墊141與該第一鋼墊ι2ΐ。 具體而言，該第二銅製程晶片14〇係可包含一第二半導 體層142以及一第二晶背黏著層143。該第二銅製程晶 片140之結構係可相同於該第一銅製程晶片12〇，不再 贅述。在其他實施例中，在該第二銅製晶片12〇上亦可 往上再堆疊設置更多之銅製晶片，以達到較高之容量或 達到較多之功能應用。 如第2圖所示，該封裝構造1〇〇可更包含一封膠體 170其係為環氧模封化合物（Epoxy Molding Compound，EMC) ’以壓模或點膠方式密封該些晶片 120、140與該些電連接元件13〇、ι5〇，以提供適當的封 裝保護以防止電性短路與塵埃污染。 φ 请參閱第3A至3E圖所示，本發明進一步說明該基 板110之該圖案化擴散障蔽層114與該銅線路層113之 一種可行但非限定之形成方法，以彰嚷本案的功效。 首先’請參閱第3A圖所示’提供上述之基板之 該核心層111，在該基板11〇之該核心層U1之上表面全 面形成有一銅箔10。接著，如第3B圖所示，於該銅箔 10上形成一光阻層20，以曝光（eXp0Sing)與顯影 (developing)方式使其具有複數個開口 21。該些開口 21 係為上述之圖案化擴散障蔽層114的預定形成區域。該 201118996 光阻層2 0較佳梅i &Patterning to form a plurality of conductive traces' and forming a bonding pad 112. One of the conductive traces and the corresponding connection pads 112 can be seen in Figure 4. As shown in FIG. 4, the pattern of the patterned diffusion barrier layer H4 is completely identical to the pattern of the copper wiring layer 113 to completely cover the steel wiring layer 113, and can be used to protect the metal of the copper wiring layer 113. The layer is not easily oxidized' and is used to prevent copper ions from diffusing from the copper wiring layer 113 to the first copper processing wafer 12, thereby avoiding inducing functional failure of the first steel processing wafer 120. In particular, copper ions are prevented from diffusing from the conductive traces of the copper wiring layer 113 to the first semiconductor wafers 12. Preferably, the patterned diffusion barrier layer ι4 is made of Ni (Ni) and has good copper ion diffusion barrier capability. The patterned diffusion barrier layer 114 has a thickness of between 1 and 2 Å micrometers. The solder resist layer 115 covers the patterned diffusion barrier layer ι 4 and the cedar layer m. The anti-four (115) 115 has at least one opening u6, and the opening of the patterned diffusion barrier layer ii4 is exposed on the connection pad. The part on 112. The substrate 110 further has a bonding layer 117 attached to the portion of the patterned diffusion barrier layer 114 within the opening 116. Preferably, the bonding layer 117 is a gold (Au) layer, which can enhance the electrical connection between the substrate 110 and the first copper processing wafer 120 during the golding process. Specifically, as shown in Fig. 2, the substrate 11A may further include a plurality of external pads 118 and a solder resist layer 119. The external pads 118 are formed on the lower surface of the core layer 111 for setting a plurality of solder balls 16A. The external pads 118 are electrically connected to the corresponding connection pads 112 via internal wiring structures. The solder balls 160 are electrically connectable to an external printed circuit board (PCB) or stacked to another semiconductor package. The material of the external pads 118 may also be copper. The substrate 11 is a laminated circuit board which is laminated and double-sided. In detail, the solder resist layers 115, 119 are respectively coated on the upper surface of the substrate 110 to form a protective layer capable of covering the conductive traces from external moisture and contaminants. The solder resist layers 115 and 119 are commonly known as "Solder mask or solder resist", and are mainly composed of an epoxy resin and a photosensitive resin. However, the solder resist layers ιι, 119 are not limited to green, and may be black, red, blue or any other color. Referring to FIG. 1 again, the first steel processing wafer 12 is disposed on the substrate 110, and the first steel processing wafer 12 has at least one first copper pad 121. The first copper process wafer 12 can include the first 201118996 semiconductor layer 122 and a first back adhesion layer 123. The first semiconductor layer 122 may be made of tantalum, gallium arsenide or other semiconductor materials, which may have a back-grinded thickness. That is, the first semiconductor layer 122 is pasted to a suitable thickness and then pasted to the first crystal back adhesion layer 23, and then the first crystal back adhesion layer is used to bond the back surface of the first copper processing wafer 120. Up to the substrate 11〇. The first crystal back adhesive layer 123 can be formed on the back surface of the first copper wafer 120 by screen printing or syringe dispensing, attaching, etc., and the material thereof can be resin, B-stage colloid, adhesive film. (Film), epoxy adhesive (Ep〇xy), non-conductive glue or liquid colloid. The first copper process wafer 120 is an integrated circuit fabricated by a steel process, and the first copper bond pads 121 are arranged in a single (multiple) row around the active surface of the first copper process wafer 120, and The copper interconnect line 124 is connected 'as the external end point of the connected integrated circuit. In this embodiment, the first copper processing chip 120 can be a memory chip, such as synchronous dynamic random access memory (SDRAM) or double rate transmission dynamic memory access memory (DDRDRAM). Wait. As shown in Fig. 1, the first electrical connecting member 13 is connected to the first copper pad 121 and the bonding layer 117. The first electrical connecting element 13 can be a wire formed by wire bonding. Preferably, the material of the first electrical connecting component 130 can be gold, and the material of the bonding layer U7 can also be gold, thereby achieving good forging bonding force. Alternatively, a brazing wire having better conductivity may be used instead. As shown in FIG. 2, the package structure 1 can further include a second copper process wafer 140 and at least a second electrical connection element 15A. The second 10 201118996 copper process wafer 140 is disposed on the first copper process wafer 126, the second copper process wafer 140 has at least one second copper pad 141, and the second copper pads 141 are interconnected by copper. Line 144 is connected. The second electrical connecting component 150 is coupled to the second steel pad 141 and the first steel pad ΐ2. Specifically, the second copper process wafer 14 can include a second semiconductor layer 142 and a second back adhesion layer 143. The structure of the second copper process wafer 140 can be the same as that of the first copper process wafer 12, and will not be described again. In other embodiments, more copper wafers may be stacked on the second copper wafer 12 to achieve higher capacity or to achieve more functional applications. As shown in FIG. 2, the package structure 1 further includes a gel 170 which is an epoxy resin compound (EMC) to seal the wafers 120, 140 by compression molding or dispensing. The electrical connection elements 13〇, ι5〇 are provided to provide proper package protection against electrical shorts and dust contamination. φ Referring to Figures 3A through 3E, the present invention further illustrates a possible but non-limiting method of forming the patterned diffusion barrier layer 114 of the substrate 110 and the copper wiring layer 113 to demonstrate the efficacy of the present invention. First, the core layer 111 of the above substrate is provided as shown in Fig. 3A, and a copper foil 10 is entirely formed on the upper surface of the core layer U1 of the substrate 11. Next, as shown in Fig. 3B, a photoresist layer 20 is formed on the copper foil 10 to have a plurality of openings 21 by exposure (eXp0Sing) and development. The openings 21 are predetermined formation regions of the patterned diffusion barrier layer 114 described above. The 201118996 photoresist layer 2 0 preferably plum i &
- 係可為一乾膜光阻。之後，請參閱第3C 圖所不&電鑛方式在該些開口 21内設置該圖案化擴散 障蔽層114，其係沉積於該銅領1 0預定保留為線路之部 位。之後，請參閱第3D圖所示，以去光阻（photoresist stripping)方式移除該光阻層2〇。請參閱第π圖所示， 再以蝕刻（etching)方式移除該銅箔1〇未被該圖案化擴散 障蔽層114覆蓋之外露部份，並形成上述具有連接墊ιΐ2 • 之鋼線路層113。因此，如第4圖所示，該圖案化擴散 障蔽層114之圖案能與該銅線路層113之圖案完全一 致，以完整覆蓋於該鋼線路層113之上表面。值得一提 的’如第3D與3E圖所示，該圖案化擴散障蔽層114係 作為形成該銅線路層113之蝕刻遮罩，而使該銅線路層 11 3不延伸至該核心層i丨i之邊緣，即不需要習知的電 鑛導線，也不會有外露在核心層ιη邊緣的電鑛導線斷 面，以避免靜電放電。因此，本發明不需要另外形成電 • 鑛延伸導線’藉此提昇封裝基板的佈線密度，並且可以 避免電鍵延伸導線所導致的訊號干擾及雜訊問題。 依據本發明之第一具體實施例’另一種銅製程晶片之 封裝構造說明於第5圖之局部截面示意圖。該封褒構造 200主要包含一基板110、一第一銅製程晶片12〇以及至 少一第一電性連接元件130。其中與第一實施例相同的 主要元件將以相同符號標示，故可理解亦具有上述之相 同作用，在此不再予以贅述。 在本實施例中，該第一鋼製程晶片120係可另包含一 12 201118996 第-擴散障蔽層224,其係介設於第—半導㈣i22與 第-晶背黏著$ 123之間，且全面覆蓋該第一半導體層 122。該第二銅製程晶片140係可另包含一第二擴散障蔽 層244’其係介㈣上述之第二半導體層142與上述之 第二晶背黏著143之間’且全面覆蓋該第二半導體層 142 〇- The system can be a dry film photoresist. Thereafter, referring to FIG. 3C, the patterned diffusion barrier layer 114 is disposed in the openings 21, and is deposited on the copper collar 10 to be reserved as a portion of the line. Thereafter, as shown in FIG. 3D, the photoresist layer 2 is removed by photoresist stripping. Referring to FIG. π, the copper foil 1 is removed by etching, and the exposed portion is not covered by the patterned diffusion barrier layer 114, and the steel circuit layer 113 having the connection pad •2 is formed. . Therefore, as shown in Fig. 4, the pattern of the patterned diffusion barrier layer 114 can be completely aligned with the pattern of the copper wiring layer 113 to completely cover the upper surface of the steel wiring layer 113. It is worth mentioning that, as shown in FIGS. 3D and 3E, the patterned diffusion barrier layer 114 serves as an etch mask for forming the copper wiring layer 113, so that the copper wiring layer 11 does not extend to the core layer. The edge of i, that is, the conventional electric ore wire is not required, and there is no cross section of the electric ore wire exposed at the edge of the core layer to avoid electrostatic discharge. Therefore, the present invention does not require the formation of an electric extension conductor wire, thereby increasing the wiring density of the package substrate, and avoiding signal interference and noise problems caused by the extension of the conductor. According to a first embodiment of the present invention, a package structure of another copper process wafer is illustrated in a partial cross-sectional view of Fig. 5. The package structure 200 mainly includes a substrate 110, a first copper process wafer 12A, and at least one first electrical connection component 130. The same elements as those in the first embodiment will be denoted by the same reference numerals, and it is understood that they have the same functions as described above, and will not be further described herein. In this embodiment, the first steel processing wafer 120 may further include a 12 201118996 first diffusion barrier layer 224 disposed between the first semi-conductive (four) i22 and the first crystal back adhesion $ 123, and comprehensively The first semiconductor layer 122 is covered. The second copper process wafer 140 can further include a second diffusion barrier layer 244 ′ between the fourth semiconductor layer 142 and the second crystal back adhesion 143 and completely cover the second semiconductor layer. 142 〇
具體而言，較佳地，該第一擴散障蔽層224與該第二 擴散障蔽& 244之材質係可為鎳㈤）。該第—擴散障蔽 層m與該第二擴散障蔽層244係可為晶圓級崎形 成。即在晶圓階級時，將晶圓之背面研磨至適當厚度後， 再於晶圓背面藏鍍形成，之後再進行切割以形成複數個 銅製程晶片。在擴散障蔽層上形成之晶背黏著層可在切 割之前或之後實施。在本實施例中，該第二銅製晶片14〇 小於該第一銅製程晶片！2〇。在其他實施例中該第一 銅製程晶片12〇與該第二銅製晶片14〇亦可為實質相同 之晶片，具有相同之晶片尺寸與構造，並可由同一晶圓 製程中形成。 因此’本發明藉由將該第二銅製程晶片14〇在該第二 半導體層142背面增設的全面覆蓋擴散障蔽層244，應 用於多晶片堆疊結構時’該第一鋼製程晶片j 2〇主動面 之該第一銅墊121與銅互連線路} 24散發之銅離子，能 被該第二擴散障蔽層244與該第一擴散障蔽層224(或該 圖案化擴散障蔽層114)有效限制在該第一鋼製程晶片 120内’該第二銅製程晶片14〇主動面之該第二銅整I。 Γ 5； 13 201118996 • 與銅互連線路144散發之鋼離子能被該第二擴散障蔽層 244有效限制在該第二鋼製程晶片140内，該基板11〇 之銅線路層113散發之銅離子，能被該圖案化擴散障蔽 層1 1 4有效限制在該基板丨丨〇内，故能使多個銅製程晶 片堆疊之間不會有銅離子擴散污染的問題，提高產品信 賴度。 以上所述，僅是本發明的較佳實施例而已並非對本 發月作任何形式上的限制，雖然本發明已以較佳實施例 才I ^ 上，然而並非用以限定本發明，任何熟悉本項技 術者，y· 不脫離本發明之技術範圍内，所作的任何簡單 效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖：依據本發明之第一具體實施例的銅製程晶片之 封裝構造之截面示意圖。 •第2圖：依據本發明之第一具體實施例的一種銅製程晶 第3 片之封裝構造在未封膠前之局部截面示意圖。 3E圖‘依據本發明之第一具體實施例的銅製程 晶片之封裝構造形成圖案化擴散障蔽層中元件 之截面示意圖。 圖依據本發明<第一&體實施例的銅製程晶片之 封裝構造中圖案化擴散障蔽層與銅線路層之局 部立體示意圖。 依據本發明之第二具體實施例的一種銅製程晶 r 14 201118996 片之封裝構造之未封膠前之局部截面示意圖。 【主要元件符號說明】Specifically, preferably, the material of the first diffusion barrier layer 224 and the second diffusion barrier layer 244 may be nickel (f). The first diffusion barrier layer m and the second diffusion barrier layer 244 may be wafer level. That is, in the wafer level, the back surface of the wafer is ground to a suitable thickness, and then deposited on the back side of the wafer, and then diced to form a plurality of copper process wafers. The crystalline back adhesion layer formed on the diffusion barrier layer can be applied before or after the cutting. In this embodiment, the second copper wafer 14 is smaller than the first copper wafer! 2〇. In other embodiments, the first copper process wafer 12 and the second copper wafer 14 can also be substantially identical wafers having the same wafer size and configuration and can be formed by the same wafer process. Therefore, the present invention applies the first copper process wafer to the multi-wafer stack structure by applying the second copper process wafer 14 to the full-surface diffusion barrier layer 244 provided on the back surface of the second semiconductor layer 142. The copper ions emitted from the first copper pad 121 and the copper interconnections 24 can be effectively limited by the second diffusion barrier layer 244 and the first diffusion barrier layer 224 (or the patterned diffusion barrier layer 114). In the first steel processing wafer 120, the second copper processing wafer 14 is the second copper I of the active surface. 2011 5; 13 201118996 • The steel ions emitted from the copper interconnection 144 can be effectively confined by the second diffusion barrier layer 244 in the second steel processing wafer 140, and the copper ions emitted from the copper circuit layer 113 of the substrate 11 The patterned diffusion barrier layer 141 can be effectively confined in the substrate raft, so that there is no problem of copper ion diffusion contamination between the plurality of copper process wafer stacks, thereby improving product reliability. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been described in the preferred embodiments, it is not intended to limit the present invention. It is still within the technical scope of the present invention to make any simple change and modification made by the present invention without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a package structure of a copper process wafer according to a first embodiment of the present invention. • Fig. 2 is a partial cross-sectional view showing the package structure of the copper process crystal according to the first embodiment of the present invention before unsealing. 3E is a schematic cross-sectional view showing the elements in the patterned diffusion barrier layer formed by the package structure of the copper process wafer according to the first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 3 is a perspective view showing a portion of a patterned diffusion barrier layer and a copper wiring layer in a package structure of a copper process wafer according to a first & embodiment of the present invention. A partial cross-sectional view of a package structure of a copper process crystal according to a second embodiment of the present invention before unsealing. [Main component symbol description]
10 銅笛 20 光阻層 21 開口 100 封裝構造 110 基板 111 核心層 112 連接墊 113 銅線路層 114 圖案化擴散障蔽層 115 防銲層 116 開孔 117 接合層 118 外接墊 119 防銲層 120 第一銅製程晶片 121 第一銅塾 122 第一半導體層 123 第一晶背黏著層 124 銅互連線路 130 第一電性連接元件 140 第二銅製程晶片 141 第二銅墊 142 第二半導體層 143 第二晶背黏著層 144 銅互連線路 150 第二電性連接元件 160 鲜球 170 封膠體 200 封裝構造 224 第一擴散障蔽層 244 第二擴散障蔽層 Γ Sil 1510 copper flute 20 photoresist layer 21 opening 100 package structure 110 substrate 111 core layer 112 connection pad 113 copper circuit layer 114 patterned diffusion barrier layer 115 solder mask 116 opening 117 bonding layer 118 external pad 119 solder resist layer 120 first Copper process wafer 121 first copper crucible 122 first semiconductor layer 123 first crystal back adhesion layer 124 copper interconnection line 130 first electrical connection element 140 second copper process wafer 141 second copper pad 142 second semiconductor layer 143 Two-crystal back adhesion layer 144 copper interconnection line 150 second electrical connection element 160 fresh ball 170 encapsulant 200 package structure 224 first diffusion barrier layer 244 second diffusion barrier layer Γ Sil 15