201118986 六、發明說明： . 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種金屬 柱焊接晶片連接（Metal Post Solder-Chip Connection， MPS-C2)之封裝構造及其電路基板。 【先前技術】 按，習知覆晶接合技術（flip_chip bonding technology) 是在晶片主動面上設置複數個直徑約為2〇微米或更大 _ 的銲料凸塊，藉由翻轉晶片與迴焊成球的方式，使銲料 凸塊電性與機械性接合至在一電路基板上的對應銲墊， 以疋成覆晶接合。由於覆晶接合技術可應用於相對較高 接腳數（High Pin Count)之晶片封裝結構，相較於使用打 線連接（wire bond)之電性連接方式，提供了晶片至基板 之較短電性連接路徑與適用於高密度輸出/入接點數量 之產品製造，具有良好的高頻訊號的傳輸品質。然，銲 φ 料凸塊迴焊成球形會有形狀改變的空間佔用，銲料凸塊 之間的間距必須擴大到5〇微米以上，以避免成球凸塊的 碰觸或橋接焊連。故銲料凸塊不可設置於晶片銲墊上， 曰曰片内須以重配置線路層以使銲料凸塊為格狀陣列。當 半導體封裝技術進一步發展到微間距（fine pitch)之微小 化封裝結構，而使凸塊間距在5〇微米以下與凸塊直徑 (或長度）在20微米以下，習知覆晶接合技術便無法再採 用銲料凸塊。 故而，IBM公司發展出一種更新的技術，採用金屬柱 201118986 •取代以往的銲料凸塊’以銲料連接金屬柱與電路基板上 的接塾’在迴焊時無成球的形狀改變，故金屬柱的間距 可容許降低至晶片銲墊之間距（小於5 〇微米，如3 〇微 米）’達到更高密度的配置，稱之為「金屬柱焊接的晶片 連接」（MPS-C2，Metal Post Solder-Chip Connection)技 術。此一 MPS-C2技術已可見於美國專利US 6,229,220 B1 遗 bump structure, bump forming method and package connecting body」，其中所使用之金屬柱為高溫焊料，基 • _ 板上的連接墊為非防銲界定型態（n〇n_s〇ldei· mask defined，NSMD)，連接墊被金屬柱下的低溫焊料的焊接 面積完全取決於連接墊的大小尺寸。當連接墊以跡線連 接或為引腳型態時，·會有焊料擴散的污染問題，即過度 焊錫（excessive solder ability)的問題。此外，以 NSMD 接墊供金屬柱下焊料焊接的結構中，NSMD接墊的基板 附著性較差，在金屬柱下焊料的應力作用下，NSMD接 φ 墊容易由基板的上表面剝離。 為了解決過度焊錫性與基板上連接墊的剝離等問 題’ MPS-C2技術有進一步改良之必要。如第1圖所示， 一種習知的金屬柱焊接晶片連接之封裝構造1〇〇主要包 含一電路基板110、一晶片120以及一底部填充膠130。 第2圖為該電路基板11〇之上表面U1示意圖。如第1 及2圖所示，該電路基板11〇之上表面丨丨丨係具有複數 個防鲜界定接塾（solder mask defined pads，SMD Pad)112，即是以一防銲層113覆蓋該些防銲界定接墊 201118986 112之周邊以及連接該些防銲界定接墊112之跡線（圖中 未繪出）。換言之，該防銲層113係具有複數個凸塊開孔 114 ’是以該些凸塊開孔114定義該些防銲界定接墊112 之可焊接面積（如第2圖所示。該晶片120係具有一主動 面121以及複數個設於該主動面121之金屬柱丨22，並 且該些金屬柱122之突出端面122A設有複數個銲料 123。在迴焊時該銲料in將熔化以焊接至該些防銲界定 接墊112，但該些金屬柱122不可熔化，以提供支撐效 果並避免微間距凸塊的橋接短路。在該防銲層113的該 些凸塊開孔114的尺寸限制下’該些鮮料123不會過度 悍接至該些防銲界定接墊112之周邊或其它金屬線路結 構。另，該底部填充膠130係形成於該晶片120與該電 路基板110之間’以密封該些金屬柱122。然，在底膠 的填充製程中，若該晶片120與該電路基板11〇之間的 間隙不足’則會降低了該底部填充膠丨3〇的膠流動速 度’使得該底部填充膠130無法順利填入該晶片12〇之 底部。此外，當接合該晶片120與該電路基板ι10時， 必須要將該些金屬柱122 —對一對準至該防銲層113之 該些凸塊開孔11 4，以使該些金屬柱122能順利接合至 該些防銲界定接墊112。；然而，該些凸塊開孔114的形 成是印刷電路板製程’與積體電路製程的精細精度不 同’易有偏移問題，而且該電路基板11〇與該晶片120 因材質不同會有熱膨脹係數的不匹配。在MPS-C2接合 時’該些金屬柱122常無法對準在該些凸塊開孔114内， 201118986 •:易有空輝或假谭之情況，甚至降低了封裝產品的可靠 【發明内容】 金屬為柱了焊解接決上述之問題，本發明之主要目的係在於一種 與導膠效果1連接之封裝構造，能提供適當覆晶間隙 金眉扭料兄製程之進仃，同時能避免 ’屬柱下銲料在引腳上過度塌陷，維持足夠的金屬柱下 鲜料有效焊接量，以達到MPS C2基〇沾私 φ 磲Θ 產品的較佳可靠度。 本發明之次一目的係在於提供一種金屬柱烊接晶片 連接之封裝構造，排除了以往防銲層之限制，能提供較 佳的空間配置，更適用於微間距凸塊之封裝結構。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種金屬柱蟬接晶片連接之封 裝構造 > 主要包含—Φ A Jc a u ^電路基板、一晶片以及一底部填充 膠。在該電路基板之一上表面係設有複數個引腳並覆蓋 鲁有-防銲廣，該防銲層係具有一導膠開口，以顯露該些 引腳。該晶片係覆晶接合於該電路基板上，該晶片係具 有一主動面以及複數個設於該主動面之金屬柱並且該 些金屬柱之突出端面係設有複數個銲料，以焊接至該些 引腳。該底部填充膠係形成於該電路基板與該晶片之 間，並填入該導膠開口。其中，該導膠開口之外周邊係 位於該晶片之底面積之外，該防銲層係具有複數個第一 引腳覆蓋指，係延伸進入該晶片之底面積内並局部覆蓋 該些引腳，以使該外周邊係形成為鋸齒狀。本發明另揭 201118986 示應用於上述封裝構造之電路基板。 本發明的目的及解杰甘 、其技術問題還可採用以下技術 措施進一步實現。 在前述之金屬桂烊接晶片連接之封裝構造中，該防鲜 層係可更具有-中央島部’係形成於該導膠開口内且小 於該晶J之底面積，以覆蓋該些引腳之内端。 在j述之金屬柱烊接晶片連接之封裝構造中，該導膠 開口係可為回字形導槽。 在前述之金屬柱焊接晶片連接之封裝構造中，該中央 島部之周邊係可設有複數個第二引腳覆蓋指，係局部覆 蓋該些^腳’以使該中央島部之周邊係、形成為鑛齒狀。 在月j述之金屬柱焊接晶片連接之封裝構造中該些引 腳不被該防銲層n+ e 覆蓋之長度係可為該導膠開口之寬度之 三分之一以下。 在前述之金屬柱焊接晶片連接之封I構造中，該電路 •基板係可另具有_電鍍接合層，係形成於該些引腳不被 該防銲層覆蓋之部位。 在前述之金屬桎焊接晶片連接之封裝構造中，可另包 含複數個外接端子，係設置於該基板之_下表面。 、上技術方案可以看出，本發明之金屬柱焊接晶片 j接，封裝構造及其電路基板，有以下優點與功效： -、可藉由防銲層之導膠開口與引腳之特定組合關係作 為其中一技術手段，由於導膠開口之外周邊係位於 晶片之底面積之外並且形成為鋸齒狀，能提供適當 201118986 覆晶間隙與導膠效果，有利於底膠填充製程之進 行，同時能避免金屬柱下銲料在引腳上過度塌陷， 維持足夠的金屬柱下銲料有效焊接量，以達到 MPS-C2產品的較佳寸靠度。 二、可藉由引腳、防銲層與導膠開口之特定組合關係作 為其中一技術手段，由於防銲層之導膠開口能對應 於引腳的大小與形狀作調整變化，以提供引腳較佳 的空間配置，特別適用於微間距（fine pitch)凸塊之 封裝結構。 【實施方式】201118986 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a package structure and circuit for a Metal Post Solder-Chip Connection (MPS-C2) Substrate. [Prior Art] According to the conventional flip-chip bonding technology, a plurality of solder bumps having a diameter of about 2 μm or more are disposed on the active surface of the wafer by flipping the wafer and reflowing the balls. In a manner, the solder bumps are electrically and mechanically bonded to corresponding pads on a circuit substrate to form a flip chip bond. Since the flip chip bonding technique can be applied to a relatively high pin count wafer package structure, the wafer-to-substrate short electrical property is provided compared to the electrical connection using a wire bond. The connection path is manufactured with products suitable for the number of high-density output/incoming contacts, and has good transmission quality of high-frequency signals. However, the reflow of the solder φ bumps into a sphere has a space-changing space, and the spacing between the solder bumps must be increased to more than 5 μm to avoid bumping or bridging of the ball bumps. Therefore, the solder bumps may not be disposed on the wafer pads, and the wiring layers shall be reconfigured in the germanium to make the solder bumps into a lattice array. When the semiconductor packaging technology is further developed into a micro pitch package structure with fine pitch, and the bump pitch is below 5 μm and the bump diameter (or length) is below 20 μm, the conventional flip chip bonding technology cannot Solder bumps are used again. Therefore, IBM has developed a newer technology that uses metal pillars 201118986. • Replaces the previous solder bumps. The solder joints the metal pillars and the joints on the circuit board. The shape of the ball is not changed during reflow, so the metal pillars. The spacing can be reduced to the distance between the wafer pads (less than 5 〇 micron, such as 3 〇 micron) 'to achieve a higher density configuration, called "metal column soldered wafer connection" (MPS-C2, Metal Post Solder- Chip Connection) technology. This MPS-C2 technology can be found in U.S. Patent No. 6,229,220 B1, bump forming, bump forming method and package connecting body", wherein the metal column used is a high temperature solder, and the connection pads on the base plate are non-welded. Type (n〇n_s〇ldei·mask defined, NSMD), the soldering area of the solder pad under the metal post is completely dependent on the size of the connection pad. When the connection pads are connected by traces or in a pin type, there is a problem of contamination of solder diffusion, that is, an issue of excessive soldering ability. In addition, in the structure in which the NSMD pads are used for soldering under the metal pillars, the substrate adhesion of the NSMD pads is poor, and the NSMD-connected φ pads are easily peeled off from the upper surface of the substrate by the stress of the solder under the metal pillars. In order to solve the problem of excessive solderability and peeling of the connection pads on the substrate, the MPS-C2 technology has been further improved. As shown in FIG. 1, a conventional metal pillar solder wafer connection package structure 1A mainly includes a circuit substrate 110, a wafer 120, and an underfill 130. Fig. 2 is a schematic view showing the upper surface U1 of the circuit board 11''. As shown in FIGS. 1 and 2, the surface of the circuit substrate 11 has a plurality of solder masks (SMD Pads) 112, which are covered by a solder mask 113. The solder resists define the perimeter of the pads 201118986 112 and the traces (not shown) that connect the solder resist defining pads 112. In other words, the solder resist layer 113 has a plurality of bump openings 114' defining the solderable areas of the solder resist defining pads 112 by the bump openings 114 (as shown in FIG. 2. The wafer 120 The utility model has an active surface 121 and a plurality of metal pillars 22 disposed on the active surface 121, and the protruding end faces 122A of the metal pillars 122 are provided with a plurality of solders 123. The solder in will be melted for soldering to the solder reflow to The solder resists define the pads 112, but the metal posts 122 are not meltable to provide a support effect and avoid bridging shorts of the micro pitch bumps. Under the size limitations of the bump openings 114 of the solder resist layer 113 The fresh material 123 is not excessively spliced to the periphery of the solder resist defining pads 112 or other metal wiring structures. Further, the underfill 130 is formed between the wafer 120 and the circuit substrate 110. Sealing the metal pillars 122. However, in the filling process of the primer, if the gap between the wafer 120 and the circuit substrate 11〇 is insufficient, the glue flow velocity of the underfill capsule 3〇 is lowered. The underfill 130 cannot fill the crystal smoothly In addition, when the wafer 120 and the circuit substrate ι10 are bonded, the metal pillars 122 must be aligned to the bump openings 11 4 of the solder resist layer 113, so that The metal pillars 122 can be smoothly joined to the solder resist defining pads 112. However, the bump opening 114 is formed by a printed circuit board process that is different from the fine precision of the integrated circuit process. The problem is that the circuit board 11 〇 and the wafer 120 have a thermal expansion coefficient mismatch due to different materials. When the MPS-C2 is joined, the metal pillars 122 are often unable to be aligned in the bump openings 114, 201118986 •: It is easy to have empty or fake Tan, and even reduce the reliability of the packaged product. [Inventive content] The metal is pillared and welded to solve the above problems. The main purpose of the present invention is to connect with the glue guiding effect 1 The package structure can provide the appropriate flip-chip clearance, and avoid the excessive collapse of the solder under the column, and maintain enough effective amount of fresh material under the metal column to reach MPS C2. Based on φ 〇 The second object of the present invention is to provide a package structure for metal post splicing wafer connection, which eliminates the limitation of the conventional solder resist layer, can provide a better space configuration, and is more suitable for fine pitch convex. The package structure of the block. The object of the present invention and the technical problem thereof are achieved by the following technical solutions. The present invention discloses a package structure for metal post splicing wafer connection > mainly comprising - Φ A Jc au ^ circuit substrate, The wafer and an underfill layer have a plurality of pins on the upper surface of the circuit substrate and are covered with a plurality of solder joints, and the solder resist layer has a conductive adhesive opening to expose the pins. The chip is flip-chip bonded to the circuit substrate, the wafer has an active surface and a plurality of metal pillars disposed on the active surface, and the protruding ends of the metal pillars are provided with a plurality of solders for soldering to the Pin. The underfill is formed between the circuit substrate and the wafer and fills the via opening. The periphery of the conductive adhesive opening is located outside the bottom area of the wafer, and the solder resist layer has a plurality of first pin covering fingers extending into the bottom area of the wafer and partially covering the pins. So that the outer peripheral system is formed in a zigzag shape. Further, the present invention discloses a circuit board applied to the above package structure. The object of the present invention and the technical problems thereof can be further realized by the following technical measures. In the above-mentioned metal cassia-joined wafer-attached package structure, the anti-fresh layer may have a central island portion formed in the adhesive opening and smaller than the bottom area of the crystal J to cover the pins. The inner end. In the package construction of the metal post splicing wafer connection, the conductive adhesive opening may be a retro-shaped guide groove. In the above-mentioned metal pillar soldering wafer connection package structure, the periphery of the central island portion may be provided with a plurality of second pin covering fingers, which partially cover the legs to make the central island portion Formed into a mineral tooth shape. The length of the pins that are not covered by the solder mask n+e may be less than one third of the width of the via opening in the package structure of the metal pillar solder wafer connection described in the month. In the above-described structure of the metal pillar soldering wafer connection, the circuit substrate may have an electroplated bonding layer formed on a portion where the pins are not covered by the solder resist layer. In the package structure of the metal tantalum solder wafer connection described above, a plurality of external terminals may be additionally provided on the lower surface of the substrate. It can be seen from the above technical solution that the metal pillar soldering wafer j of the present invention, the package structure and the circuit substrate thereof have the following advantages and effects: - a specific combination relationship between the conductive adhesive opening and the lead of the solder resist layer As one of the technical means, since the periphery of the adhesive opening is outside the bottom area of the wafer and formed into a zigzag shape, the appropriate 201118986 flip-chip gap and the guiding effect can be provided, which is beneficial to the underfill filling process and can be performed at the same time. Avoid excessive collapse of the solder under the metal post on the pins, and maintain sufficient soldering capacity under the metal post to achieve better insulation of the MPS-C2 product. Second, the specific combination of the lead, the solder resist layer and the conductive adhesive opening can be used as one of the technical means, since the solder paste opening of the solder resist layer can be adjusted corresponding to the size and shape of the pin to provide a pin. The preferred spatial configuration is particularly suitable for the package structure of fine pitch bumps. [Embodiment]
以下將配合所附圖示.詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為;;種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種金屬柱焊接晶片連 接之封裝構造舉例說明於第3圖之截面示意圖與第4圖 繪示其電路基板之上視示意圖1金屬柱焊接晶片連接 之封袭構造200係主要包含一電路基板210、一晶片22〇 以及一底部填充膠230 ^詳細而言 之—上表面211係設有複數個引腳 ’在該電路基板210 212並覆蓋有一防銲 201118986 ' 層213，該防銲層213係具有一導膠開口 214，以顯露該 些引腳212。一般而言，該電路基板21〇係可為一印刷 電路板（printed circuit board，PCB)，作為在安裝或互連 時的主要支撐體。該些引腳212係可為導電材質，以作 為電性傳輸之用，並為該電路基板21〇内部線路結構的 一部分。該防銲層213係為表面絕緣層，用以保護内部 線路結構’亦能隔絕空氣預防氧化。 籲 該晶片220係覆晶接合於該電路基板210上，該晶片 220係具有一主動面221以及複數個設於該主動面22 ι 之金屬柱222’並且該些金屬柱222之突出端面222a係 設有複數個銲料223 ’以焊接至該些引腳212。具體而 & ’該晶片220係為集成電路（integrated circuit, 1C)的 載體，由一晶圓（wafer)分割而成。更進一步地，該晶片 220係可為以半導體作基層之積體電路元件，例如記憶 體、邏輯元件以及特殊應用積體電路（ASIC)。在本實施 _ 例中，該些金屬柱222之材質係可為銅（Cu)，而具有良 好的導電性》 該底部填充膠230係形成於該電路基板210與該晶片 22〇之間，並填入該導膠開口 2丨4(如第4與5圖所示）。 較佳地’可藉由該底部填充膠230保護該晶片220之主 動面221與該些金屬柱222，更可完全包覆住該些引腳 212與該些銲料223，加強了該晶片220與該電路基板 210之間的結合強度。此外，如第4與5圖所示，由於 該導膠開口 2 14係大於該晶片220之尺寸，有利於該底 201118986 部填充膠230之充填。 在本實施例中，請參閱第3、5與6圖所示，該導勝 開口 214之外周邊214A係位於該晶片22〇之底面積之 外’並且該防銲層213係具有複數個第一引腳覆蓋指 213A’係延伸進入該晶片220之底面積内並局部覆蓋該 些引腳212,以使該外周邊214A係形成為鋸齒狀（如第6 圖所示）。此外’該防銲層213係可更具有一中央島部 215’係形成於該導膠開口 214内且小於該晶片220之底 鲁 面積，以覆蓋該些引腳212之内端。其中，所述之「内 端」係指該些引腳212往該電路基板21〇中央之一端。 在一較佳實施例中’該導膠開口 2 1 4係可為回字形導 槽。更進一步地’該中央島部215之周邊係可設有複數 個第二引腳覆蓋指21 3B’係局部覆蓋該些引腳21 2(如第 3圖所示），以使該中央島部215之周邊係形成為鋸齒狀。 請參閱第7A與7B圖所示，該些引腳212不被該防 φ 銲層213覆蓋之長度係小於該導膠開口 214之寬度，更 能藉由該些第一引腳覆蓋捐213A與該些第二引聊覆蓋 指2 13B能部份覆蓋該些引腳212原本顯露在該導膠開 口 2 14之部位’使該些引腳2 1 2的顯露部位縮小為墊狀， 並可得到較佳的引腳固定效果。特別是如第7B圖所示， 該些第一引腳覆蓋指213A與該些第二引腳覆蓋指213B 不僅局部覆蓋於該些引腳212之上，更局部包覆住該些 引腳212之側面，進一步地強化了上述的引腳固定效 果。在一較佳實施例中，該些引腳212不被該防銲層213 10 201118986 214之寬度之三分之一以 覆蓋之長度係可為該導膠開口 下。 請參閱第7B圖所千，.并& Δ 所不座句參酌第3圖。該電路基板 210係另具有一電鍍接合婦216，係形成於該些引腳212 不層213覆蓋之部位。在本實施例中該電鑛 接合層216係可為一厶藤, ^ 金層（Au) ’以提供較佳的導電性與The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related dimensions or have been exaggerated or simplified to provide clearer description of. The actual implementation of the number, shape and size ratio is;; the choice of design, the detailed component layout may be more complicated. According to an embodiment of the present invention, a package structure of a metal pillar soldering wafer connection is illustrated in a cross-sectional view of FIG. 3 and FIG. 4 is a diagram showing a sealed structure of a metal pillar solder wafer connection on the circuit substrate. The 200 series mainly includes a circuit substrate 210, a wafer 22, and an underfill 230. In detail, the upper surface 211 is provided with a plurality of pins 'on the circuit substrate 210 212 and covered with a solder resist 201118986' layer. 213, the solder resist layer 213 has a conductive opening 214 to expose the pins 212. In general, the circuit substrate 21 can be a printed circuit board (PCB) as a primary support during mounting or interconnection. The pins 212 are electrically conductive for electrical transmission and are part of the internal circuit structure of the circuit substrate 21 . The solder resist layer 213 is a surface insulating layer for protecting the internal wiring structure and also isolating the air from oxidation. The wafer 220 is flip-chip bonded to the circuit substrate 210. The wafer 220 has an active surface 221 and a plurality of metal pillars 222' disposed on the active surface 22 and the protruding end faces 222a of the metal pillars 222. A plurality of solders 223' are provided to be soldered to the pins 212. Specifically, the wafer 220 is a carrier of an integrated circuit (1C) and is divided by a wafer. Further, the wafer 220 may be an integrated circuit component such as a memory, a logic element, and an application specific integrated circuit (ASIC) using a semiconductor as a base layer. In this embodiment, the metal pillars 222 may be made of copper (Cu) and have good electrical conductivity. The underfill 230 is formed between the circuit substrate 210 and the wafer 22〇, and Fill in the guide opening 2丨4 (as shown in Figures 4 and 5). Preferably, the active surface 221 of the wafer 220 and the metal pillars 222 are protected by the underfill 230, and the pins 212 and the solders 223 are completely covered, thereby reinforcing the wafer 220 and The bonding strength between the circuit substrates 210. In addition, as shown in Figures 4 and 5, since the adhesive opening 2 14 is larger than the size of the wafer 220, it is advantageous for the filling of the filling portion 230 of the 201118986 portion. In the present embodiment, as shown in FIGS. 3, 5 and 6, the outer periphery 214A of the guide opening 214 is located outside the bottom area of the wafer 22, and the solder resist layer 213 has a plurality of A pin cover finger 213A' extends into the bottom area of the wafer 220 and partially covers the pins 212 such that the outer perimeter 214A is formed in a zigzag shape (as shown in FIG. 6). In addition, the solder resist layer 213 may have a central island portion 215' formed in the via opening 214 and smaller than the bottom surface of the wafer 220 to cover the inner ends of the pins 212. The term "inner end" means that the pins 212 are located at one end of the center of the circuit board 21 . In a preferred embodiment, the conductive adhesive opening 214 can be a retro-shaped guide. Further, the periphery of the central island portion 215 may be provided with a plurality of second pin covering fingers 21 3B' to partially cover the pins 21 2 (as shown in FIG. 3) so that the central island portion The periphery of 215 is formed in a zigzag shape. Referring to FIGS. 7A and 7B, the lengths of the pins 212 not covered by the anti-φ solder layer 213 are smaller than the width of the via opening 214, and can be covered by the first pins. The second chat cover finger 2 13B can partially cover the portions of the pins 212 that are originally exposed in the conductive adhesive opening 2 14 'to reduce the exposed portions of the pins 2 1 2 to a pad shape, and Better pinning effect. In particular, as shown in FIG. 7B, the first pin cover fingers 213A and the second pin cover fingers 213B not only partially cover the pins 212, but also partially cover the pins 212. On the side, the pin fixing effect described above is further enhanced. In a preferred embodiment, the lengths of the leads 212 that are not covered by one third of the width of the solder mask layer 213 10 201118986 214 may be under the opening of the solder paste. Please refer to Figure 3, Figure 5, and & Δ. The circuit board 210 further has a plating joint 216 formed on a portion of the pins 212 not covered by the layer 213. In this embodiment, the electric ore bonding layer 216 can be a vine, a gold layer (Au) to provide better conductivity and
銲料接合性。藉此，争女L 更了防止該些弓丨腳2 12接觸至空氣， 以避免產生氡化之情形。^ ^Solder bondability. In this way, the female L is prevented from touching the air to the air to avoid the occurrence of deuteration. ^ ^
^ 在一較佳實施例中，如第3圖 所丁 1¾金屬柱焊接晶片連接之封裝構造2⑽係可另包 含複數個外接端子24G，錢置於該基板之—下表面 2 1 7 ’以作為對外電性連接之用。 在本發明中，利用防銲層與導膝開口之特定組合關係 作為其中一技術手段，由於該導膠開口 214之外周邊 2 14A係位於該晶片22〇之底面積之外，有利於底部填充 膠的點塗流入，也就是說，該導膠開口 214之外周邊是 不被該晶片220所覆蓋，故能在該電路基板21〇和該晶 片220之間提供適當覆晶間隙與導膠效果，有利於底膠 填充製程進行，而使得該金屬柱焊接晶片連接之封裝構 造2 00内部結構更緊密的結合。此外，在接合該晶片22〇 與該電路基板210時’亦能藉由該防銲層213之該些第 一引腳覆蓋指213A與該些第二引腳覆蓋指213B限制該 些^f·料223之塌陷範園’以避免該些金屬柱222下之該 些鲜料223在該些引腳212上過度塌陷，維持該些金屬 柱222下之該些薛料223能有足夠的有效烊接量，達到 201118986 MPS-C2產品的較佳可靠度。在一較佳實施例中，由於 本發明之該防銲層213係可對應於該些引腳212的大小 與形狀作調整變化，以提供引腳較佳的空間配置，特別 適用於微間距（fine pitch)凸塊之封裝結構，也能使該晶 片220與該電路基板210綽合得更加緊密。In a preferred embodiment, the package structure 2 (10) of the metal pillar soldering wafer connection as shown in FIG. 3 may further include a plurality of external terminals 24G, and the money is placed on the lower surface of the substrate 2 1 7 ' For external electrical connection. In the present invention, a specific combination of the solder resist layer and the knee opening is used as one of the technical means. Since the outer periphery of the conductive opening 214 is located outside the bottom area of the wafer 22, it is advantageous for the underfill. The dot coating of the glue flows in, that is, the periphery of the adhesive opening 214 is not covered by the wafer 220, so that a proper flip gap and a glue guiding effect can be provided between the circuit substrate 21A and the wafer 220. The primer filling process is facilitated, and the inner structure of the metal pillar soldering wafer connection package structure is more tightly combined. In addition, when the wafer 22 and the circuit substrate 210 are bonded, the first pin cover fingers 213A and the second pin cover fingers 213B of the solder resist layer 213 can also be used to limit the portions. The collapse of the material 223 is to prevent the fresh materials 223 under the metal pillars 222 from excessively collapsing on the pins 212, and the materials 223 under the metal pillars 222 can be sufficiently effective. The throughput is up to the reliability of the 201118986 MPS-C2 product. In a preferred embodiment, the solder resist layer 213 of the present invention can be adjusted and adjusted according to the size and shape of the pins 212 to provide a preferred spatial configuration of the leads, and is particularly suitable for micro pitch ( The fine pitch of the bump structure also enables the wafer 220 to be more closely coupled to the circuit substrate 210.
本發明還揭示上述的金屬柱焊接晶片連接之封裴構 造之電路基板210舉例說明於第4圖。一種金屬柱焊接 晶片連接之封裝構造之電路基板21〇，在該電路基板21〇 之上表面211係設有複數個引腳212並覆蓋有一防銲 層213。該防銲層213係具有一導膠開口 214，以顯露該 a引腳212’其中’該導膠開口川之外周邊係位 於一晶片接合區218之外，該防銲層213係具有複數個 第引腳覆蓋指213A’係延伸進入該晶片接合區218内 並局部覆蓋該些引腳212，以使該外周邊2i4A係形成為 鑛齒狀。在本實施例中，兮 ^ T該防銲層213係可更具有一中 央島部215>係形成於琴道膜日目 风於这導膠開口 2 1 4内且小於該晶片 接合區218，以覆蓋該也引 a 〇& -r- 一 Ή聊212之内端。具體而言， 該導膠開口 214伤0Γ盏η〜 « 係了為回子形導槽（如第6圖所示）。此 外，該中央島部215之用这 n 之周邊係可設有複數個第二引腳覆 蓋指213B，倍Rjcg费焚从 係局部覆蓋該些引腳212，以使該中央島部 215之周邊係形成為鑛齒 茴狀。在一較佳實施例中，該些 引腳212不被該防銲層 一 復213覆蓋之長度係可為該導膠開 口 214之寬度之：分夕、 心一刀之一以下。更進一步地，該電路 板210係可另具有一雷 電鍍接合層2丨6(如第3與7Β圖所 201118986 示）’係形成於該些引腳212不被該防銲層213覆蓋之部 位。因此，本發明之電路基板2丨〇能提供適當覆晶間隙 與導膠效果，有利於底膠填充製程之進行，同時能夠限 制銲料的柄陷範圍，避免銲料在該些引腳^以上過度塌 陷，以維持足夠的有效焊接量。 以上所述，僅是本發明的較佳實施例而已並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 :者’在不脫離本發明之技術範圍内，所作的任何簡單 冑效性變化與修飾，均仍屬於本發明的技術範圍 【圖式簡單說明】 第1圖：為習知金屬柱焊接晶片連接之封裝構造之截 示意圖。 第3圖 :為習知的金屬柱焊接晶片連接之封裝構造之 路基板之上視示意圖。 :曰依據本發明之-具體實關的—種金屬柱輝 B曰片連.接之封裝構造沿著引腳剖切之截面 圖。 、 依據本發明之一具體實施例的金屬柱焊 連接之封袭構造之電路基板之上視示意圖。 依據本發明之-具體實施例的金屬挺焊接晶 連接之封裝構造繪示未沿著引腳剖切之截 意圖。 ^面 13 201118986 第6圖：依據本發明之一具體實施例的金屬柱焊 連接之封裝構造之防銲層之上視示意圖。阳 第7…圖：依據本發明之一具體實施例的金 接晶片連接之封裝構造繪示其防銲層覆蓋弓！腳 之局部上視透視圖與局部立 【主要元件符號說明】 見圖The present invention also discloses a circuit board 210 of the above-described metal pillar solder wafer connection package structure, which is illustrated in Fig. 4. A metal substrate is soldered to a circuit board 21A having a package structure, and a plurality of pins 212 are provided on the upper surface 211 of the circuit substrate 21A and covered with a solder resist layer 213. The solder resist layer 213 has a conductive adhesive opening 214 to expose the a-pin 212', wherein the outer periphery of the adhesive opening is outside a wafer bonding region 218, and the solder resist layer 213 has a plurality of The first pin cover 213A' extends into the wafer land 218 and partially covers the pins 212 such that the outer perimeter 2i4A is formed into a mineral tooth shape. In this embodiment, the solder resist layer 213 may further have a central island portion 215> formed in the channel film, the wind is in the conductive adhesive opening 214 and smaller than the wafer bonding region 218. To cover this also cited a 〇 & -r- a chat 212 inside. Specifically, the guide opening 214 is wound 0Γ盏η~« as a sub-shaped guide groove (as shown in Fig. 6). In addition, the central island portion 215 can be provided with a plurality of second pin covering fingers 213B for the periphery of the n, and the Rjcg is used to partially cover the pins 212 so as to surround the central island portion 215. It is formed into a mineral-shaped analoid. In a preferred embodiment, the length of the pins 212 not covered by the solder resist layer 213 may be the width of the adhesive opening 214: one of the eves and one of the cores. Further, the circuit board 210 may further have a lightning plating bonding layer 2丨6 (as shown in FIGS. 3 and 7 and 201118986) formed on the portions of the pins 212 not covered by the solder resist layer 213. . Therefore, the circuit substrate 2 of the present invention can provide an appropriate flip-chip gap and a conductive adhesive effect, which is beneficial to the underfill filling process, and can limit the range of the handle of the solder to prevent the solder from excessively collapsing on the pins. To maintain a sufficient amount of effective welding. The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, Any simple changes and modifications made by the present invention without departing from the technical scope of the present invention are still within the technical scope of the present invention. [Simplified Drawing] FIG. 1 is a conventional metal post soldering wafer connection. A schematic view of the package structure. Fig. 3 is a top plan view of a substrate for a conventional metal pillar solder wafer connection package structure. : 曰 According to the invention - a specific embodiment of the metal column 曰 B 曰 . 接 接 封装 封装 封装 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 A top view of a circuit board of a sealed structure of a metal pillar welded joint according to an embodiment of the present invention. The package construction of the metal solder joint in accordance with the embodiment of the present invention is shown without the cut along the lead. ^面 13 201118986 FIG. 6 is a top plan view of a solder resist layer of a package structure constructed in accordance with an embodiment of the present invention. Yang 7: Fig.: The package structure of the gold wafer connection according to an embodiment of the present invention shows the solder mask covering the bow! Partial top perspective and partial standing of the foot [Description of main component symbols]
100金屬柱焊接晶片連接之封裝構造 110電路基板 ill上表面 112防銲界定接墊 11 3防銲層 114凸塊開孔 120晶片 123銲料 121主動面 122金屬柱 130底部填充膠 2〇〇金屬柱焊接晶片連接之封裝構造 210電路基板 211上表面 213Α第一引腳覆蓋指 213Β第二引腳覆蓋指 212引腳 2 1 3防銲層 214導膠開口 216電鍍接合層 218 晶片接合區 220晶片 2 2 1主動面 2 2 3鲜料 214Α外周邊 2 1 7下表面 222金屬柱 230底部填充膠 215中央島部 222Α突出端面 240外接端子 14100 metal pillar soldering wafer connection package structure 110 circuit substrate ill upper surface 112 solder resist defining pad 11 3 solder resist layer 114 bump opening 120 wafer 123 solder 121 active surface 122 metal pillar 130 underfill rubber 2 〇〇 metal pillar Solder wafer connection package structure 210 circuit substrate 211 upper surface 213 Α first pin cover finger 213 Β second pin cover finger 212 pin 2 1 3 solder mask 214 adhesive opening 216 plating bonding layer 218 wafer bonding region 220 wafer 2 2 1 active surface 2 2 3 fresh material 214 Α outer periphery 2 1 7 lower surface 222 metal column 230 underfill rubber 215 central island portion 222 Α protruding end surface 240 external terminal 14