201111979 六、發明說明： 【發明所屬之技術領域】 ' [咖1] 本發明係關於一種測試系統及方法，尤指一種休眠喚醒 ' 測試系統及方法。 【先前技術】 [0002] 休眠喚醒測試是電腦測試中必不可少的專案，為了確保 電腦的品質，常常需要採用多種不同的方法來進行休眠 喚醒測試。當透過按電腦電源按鈕來進行休眠喚醒測試 時，測試人員需一直重複按電源按鈕，此重複性勞動易 Ο ^ 使測試人員疲勞，故，易造成誤操作。又由於測試時休 眠與喚醒之間需有一段延時，但測試人員每次的延時不 可能完全相同，故，測試誤判率較高。由此可見，此測 試方法不僅耗費人力、誤測率高且效率較低。 【發明内容】 [0003] 鑒於以上内容，有必要一種休眠喚醒測試枣統，以節省 人力、減少誤測並提高測試敫率。 〇 [0004] 還有必要提供一種應用於驅測試系統的休眠喚 醒測試方法。 [0005] 一種休眠喚醒測試系統，包括一測試治具及一安裝於一 待測主機板的測試軟體，該測試治具包括一計時模組、 一計數模組、一開關模組及一介面模組，該待測主機板 的作業系統中按下電源按鈕操作被設定為執行休眠/喚醒 操作，該開關模組與該電源按鈕的正、負電源引腳相連. ，該測試治具透過該介面模組與該待測主機板進行通訊 ，該測試軟體包括： 098131438 表單編號A0101 第3頁/共16頁 0982053938-0 201111979 [0006] 一初始化單元，用於設定測試次數及休眠與喚醒之間的 延時時間，並將該延時時間寫入該計時模組，且將該計 數模組清零； [0007] 一訊號發送單元，用於發送計時訊號給該計時模組，以 讓該計時模組在接收到該計時訊號後開始計時，並在到 達該延時時間後發送一計數訊號給該計數模組且發送一 閉合訊號給該開關模組，該開關模組接收到該閉合訊號 後，執行一次閉合操作，該正、負電源引腳瞬間短路， 該待測主機板進入休眠/喚醒狀態，該計數模組接收到該 計數訊號後，其數值加一，並輸出加一之後的結果；及 [0008] —比較單元，用於比較該計數模組輸出的結果除二取整 後所得的整數與該設定測試次數是否相等，若不相等， 該訊號發送單元再次向該計時模組發送計時訊號，若相 等*測試結束。 [0009] 一種休眠喚醒測試方法，包括以下步驟： [0010] 將待測主機板作業系統中按下電源按鈕的操作設定為執 行休眠/喚醒操作； [0011] 設定測試次數及休眠與喚醒之間的延時時間，將該延時 時間寫入一測試治具的計時模組，並將該測試治具的計 數模組清零； [0012] 發送一計時訊號給該計時模組，該計時模組開始計時， 並在到達該延時時間後向該計數模組發送一計數訊號， 且向該測試治具的一開關模組發送一閉合訊號； 098131438 表單編號A0101 第4頁/共16頁 0982053938-0 201111979 [0013] [0014] 該開關模組接收到該閉合訊號後，執行_次閉人也' 作 該電源按鈕的正、負電源引腳瞬間短路，該待測主機板 進入休眠/喚醒狀態； 該計數模組接收到該計數訊號後，其數值加一，並輸出 加一之後的結果；及 [0015]比較該計數模組輸出結果除二取整後所得的整數與該設 定賴次數是㈣等，若不相等，再次向該計時模S 送一計時訊號；若相等，測試結束。 〇 ^ [0016]上述休眠喚醒測試系統及方法透過該測試軟體來控制該 測試治具，以完成對該待測主機板休眠喚醒的自動化測 試’節省了人力，減少了誤測’並提高了測試效率。 【實施方式】 [0017]請一併參閱圖1及圖2，本發明休眠喚醒測試系統的較佳 實施方式包括一測試治具1 〇及一安裝於一待測主機板3 〇 中的測試軟體20。 〇 [〇〇18]該測試治具10包括一電路板11、一計時模組12、一計數 模組14、一開關模組丨5及一介面模組18。該計時模組12 、計數模組14、開關模組15及介面模組18均設於該電路 板11上，該計時模組12與該計數模組14、開關模組15及 介面模組18電氣相連，該計數模組14與該介面模組18電 氣相連◊該開關模組15透過兩連接線16、17分別與該待 測主機板30上電源按鈕的正電源引腳38及負電源引腳39 相連。該測試治具透過該介面模組18及一線纜19與該 待測主機板30上相應的介面模組32相連 ，以實現該測試 098131438 表單編號A0101 第5頁/共16頁 0982053938-0 201111979 治具10與該待測主機板30之間的通訊。在本實施方式中 ，該兩介面模組 18、32均為USB(Universal Serial Bus,通用串列匯流排）介面，該線纜19為一兩端設有 USB連接器的線纜。 [0019] 該計時模組12用於在接收到該測試軟體20發出的計時訊 號後開始計時，並在到達該測試軟體20設定的延時時間 時，發送一計數訊號給該計數模組14且發送一閉合訊號 給該開關模組15。該計數模組14接收到該計數訊號後， 其寄存器内的數值加一，並將加一之後的結果即時發送 給該待測主機板30的中央處理器34。該開關模組15接收 到該閉合訊號後執行一次閉合的操作，該正電源引腳38 與負電源引腳39之間瞬間短路，相當於該電源按鈕被按 下一次。 [0020] 該測試軟體20包括一初始化單元22、一訊號發送單元24 及一比較單元26。該初始化單元22用於設定測試次數及 休眠與喚醒之間的延時時間，並將該延時時間寫入該計 時模組12，且對該計數模組14進行清零。該訊號發送單 元24用於向該計時模組12發送計時訊號。該比較單元26 用於接收該計數模組14發送的記錄的結果，並將記錄的 結果除以二後取整，再用取整所得的整數與該設定測試 次數相比較，若取整所得的整數小於該設定測試次數， 則該訊號發送單元24再次向該計時模組12發送計時訊號 :若取整所得的整數等於該設定測試次數，則測試結束 。在本實施方式中，該測試軟體20存儲於該待測主機板 30的一記憶體（如硬碟）36中，該中央處理器34與該記 098131438 表單編號A0101 第6頁/共16頁 0982053938-0 201111979 [0021] [0022] ❹ [0023] [0024] ❹ [0025] 憶體36相連，並用於執行該測試軟體20的程式，以實現 該初始化單元22、訊號發送單元24及比較單元26的功能 〇 請繼續參閱圖3，本發明應用於該休眠喚醒測試系統的休 眠喚醒測試方法的較佳實施方式包括以下步驟： 測試開始前，用該連接線16、17將該電源按鈕的正電源 引腳38及負電源引腳39與該開關模組15相連，並用該線 纜19將該測試治具10的介面模組18與該待測主機板30的 介面模組32連接起來，以實現該測試治具10與該待測主 機板30之間的通訊。 步驟S1，開啟該待測主機板30，在該待測主機板30的作 業系統的電源管理中將按下電源按鈕操作設定為執行休 眠/喚醒操作。 步驟S2，執行該測試軟體20，根據實際需要在該初始化 單元22中設定測試次數及休眠與喚醒之間的延時時間， 該初始化單元22將該延時時間寫入該計時模組12，並發 送一清零訊號給該計數器14，以讓該計數模組14中的數 值清零。 步驟S3，該訊號發送單元24發送一計時訊號給該計時模 組12，該計時模組12接收到計時訊號後開始計時，並在 到達該延時時間後發送一計數訊號給該計數模組14且發 送一閉合訊號給該開關模組15。 步驟S4，該開關模組15接收到該閉合訊號後，執行一次 閉合操作後自動斷開，該電源按鈕的正電源引腳38與負 098131438 表單編號A0101 第7頁/共16頁 0982053938-0 [0026] 201111979 電源引腳39之間瞬間短路，相當於電源按鈕被按下一次 ，該作業系統接收到電源按鈕被按下的訊號後開始進入 休眠或喚醒狀態。在本實施方式中，該作業系統接收到 電源按鈕被按下的訊號後會自動在進入休眠狀態或喚醒 狀態之間切換。例如，當本次該作業系統接收到電源按 鈕被按下的訊號後進入休眠狀態，則當下次該作業系統 接收到電源按鈕被按下的訊號後進入喚醒狀態。該待測 主機板30從進入休眠狀態到完全被喚醒為完成一次測試 ，即在一次測試中，該開關模組15接收到該閉合訊號兩 次。 [0027] 步驟S5，該計數模組14接收到該計時訊號後，寄存器中 的數值加一，並將加一之後的結果發送給該比較單元26 〇 [0028] 步驟S6，該比較單元26接收到該計數模組14發送的結果 後，將該結果除以二後取整，再用取整所得的整數與該 設定測試次數比較，若取整所得的整數小於該設定測試 次數，則返回步驟S3 ;若取整所得的整數等於該設定測 試次數，則測試結束。 [0029] 上述休眠喚醒測試系統及方法透過該測試軟體20來控制 該測試治具10，以完成對該待測主機板30的休眠喚醒的 自動化測試，節省了人力，減少了誤測，並提高了測試 效率。 [0030] 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 098131438 表單編號A0101 第8頁/共16頁 0982053938-0 201111979 [0031] 熟悉本案技藝之人士 ’在麦依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明休眠喚醒測試系統的原理框圖。 [0032] 圖2係本發明休眠喚醒測試系統的示意圖。 [0033] 圖3係本發明休眠喚醒測試方法的流程圖。 [0034] ❹ [0035] 【主要元件符號說明】 測試治具：10 電路板：11 [0036] 計時模組：12 [0037] 計數模組：14 [0038] 開關模組：15 [0039] 連接線· 16、1 7 ! [0040] ❹ [0041] 介面模組：18、32 . ^ ... 線纜：19 、 [0042] 測試軟體：20 [0043] 初始化單元：2 2 [0044] 訊號發送單元：24 [0045] 比較單元：26 [0046] 待測主機板：30 098131438 表單編號A0101 第9頁/共16頁 0982053938-0 201111979 [0047] 中央處理器：34 [0048] 記憶體：36 [0049] 正電源引腳：38 [0050] 負電源引腳：39 0982053938-0 098131438 表單編號A0101 第10頁/共16頁201111979 VI. Description of the invention: [Technical field to which the invention pertains] '[Caf 1] The present invention relates to a test system and method, and more particularly to a sleep wake-up test system and method. [Prior Art] [0002] The sleep wake-up test is an indispensable project in computer testing. In order to ensure the quality of the computer, it is often necessary to adopt a variety of different methods for the sleep wake-up test. When the sleep wake-up test is performed by pressing the power button of the computer, the tester needs to repeatedly press the power button. This repetitive work is easy to make the tester fatigue, which may cause misoperation. Also, there is a delay between sleep and wake-up during the test, but the tester's delay may not be exactly the same each time, so the test false positive rate is higher. It can be seen that this test method is not only labor-intensive, but also has a high false positive rate and low efficiency. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to have a dormancy wake-up test to save manpower, reduce misdetection and increase test rate. 〇 [0004] It is also necessary to provide a sleep wake-up test method applied to a drive test system. [0005] A sleep wake-up test system includes a test fixture and a test software installed on a motherboard to be tested, the test fixture includes a timing module, a counting module, a switch module, and a interface module. The operation of pressing the power button in the operating system of the motherboard to be tested is set to perform a sleep/wake operation, and the switch module is connected to the positive and negative power pins of the power button. The test fixture passes through the interface. The module communicates with the motherboard to be tested. The test software includes: 098131438 Form No. A0101 Page 3 of 16 0982053938-0 201111979 [0006] An initialization unit for setting the number of tests and between sleep and wakeup Delay time, and writing the delay time to the timing module, and clearing the counting module; [0007] a signal sending unit, configured to send a timing signal to the timing module, so that the timing module is After receiving the timing signal, the timing starts, and after the delay time is reached, a counting signal is sent to the counting module and a closing signal is sent to the switching module, and the switching module receives After the signal is closed, a closing operation is performed, the positive and negative power supply pins are short-circuited instantaneously, and the motherboard to be tested enters a sleep/wake state, and after receiving the counting signal, the counting module adds one to the value, and outputs one plus one. And the result of the comparison; and [0008] a comparison unit, configured to compare the output of the counting module, except that the integer obtained by the second rounding is equal to the set number of test times, and if not equal, the signal sending unit again counts the time The module sends a timing signal, if equal* the test ends. [0009] A sleep wake-up test method includes the following steps: [0010] setting an operation of pressing a power button in a motherboard operating system to be tested to perform a sleep/wake operation; [0011] setting a test number and sleeping and awakening The delay time is written into the timing module of the test fixture, and the counting module of the test fixture is cleared; [0012] sending a timing signal to the timing module, the timing module starts Timing, and after the delay time is reached, send a counting signal to the counting module, and send a closing signal to a switch module of the test fixture; 098131438 Form No. A0101 Page 4 / Total 16 Page 0992053938-0 201111979 [0014] [0014] after receiving the closing signal, the switch module performs a short-circuit of the positive and negative power pins of the power button, and the motherboard to be tested enters a sleep/wake state; After receiving the counting signal, the counting module adds one value and outputs the result after adding one; and [0015] compares the integer obtained by the counting module output result with the second rounding and the setting The number is (4), etc. If they are not equal, a timing signal is sent to the timing module S again; if they are equal, the test ends. [0016] The sleep wake-up test system and method described above control the test fixture through the test software to complete an automated test of the sleep wake-up of the motherboard to be tested, which saves manpower, reduces misdetection, and improves testing. effectiveness. [Embodiment] [0017] Referring to FIG. 1 and FIG. 2 together, a preferred embodiment of the sleep wake-up test system of the present invention includes a test fixture 1 and a test software installed in a motherboard 3 to be tested. 20.测试 [〇〇18] The test fixture 10 includes a circuit board 11, a timing module 12, a counting module 14, a switch module 丨5, and an interface module 18. The timing module 12 , the counting module 14 , the switch module 15 , and the interface module 18 are all disposed on the circuit board 11 , the timing module 12 , the counting module 14 , the switch module 15 , and the interface module 18 . Electrically connected, the counting module 14 is electrically connected to the interface module 18, and the switch module 15 is respectively connected to the positive power supply pin 38 and the negative power supply of the power button on the motherboard 30 to be tested through the two connecting lines 16, 17. The feet 39 are connected. The test fixture is connected to the corresponding interface module 32 on the motherboard 30 to be tested through the interface module 18 and a cable 19 to implement the test 098131438 Form No. A0101 Page 5 / Total 16 Page 0992053938-0 201111979 Communication between the jig 10 and the motherboard 30 to be tested. In the embodiment, the two interface modules 18 and 32 are USB (Universal Serial Bus) interfaces, and the cable 19 is a cable with USB connectors at both ends. [0019] The timing module 12 is configured to start timing after receiving the timing signal sent by the testing software 20, and send a counting signal to the counting module 14 and send when the delay time set by the testing software 20 is reached. A closing signal is applied to the switch module 15. After receiving the counting signal, the counting module 14 adds one to the value in the register, and sends the result after adding one to the central processing unit 34 of the motherboard 30 to be tested. The switch module 15 performs a close operation after receiving the closing signal, and the short circuit between the positive power pin 38 and the negative power pin 39 is instantaneously equivalent to pressing the power button. [0020] The test software 20 includes an initialization unit 22, a signal transmission unit 24, and a comparison unit 26. The initialization unit 22 is configured to set the number of tests and the delay time between sleep and wake-up, and write the delay time to the timer module 12, and clear the counting module 14. The signal transmitting unit 24 is configured to send a timing signal to the timing module 12. The comparing unit 26 is configured to receive the result of the record sent by the counting module 14, and divide the result of the recording by two, and then use the integer obtained by rounding to compare with the set number of test times. If the integer is less than the set number of test times, the signal sending unit 24 sends a timing signal to the timing module 12 again: if the integer obtained by rounding is equal to the set number of test times, the test ends. In this embodiment, the test software 20 is stored in a memory (such as a hard disk) 36 of the motherboard 30 to be tested, the central processor 34 and the 098131438 form number A0101 page 6 / a total of 16 pages 0992053938 [0024] [0024] [0024] The memory 36 is connected and used to execute the program of the test software 20 to implement the initialization unit 22, the signal transmitting unit 24, and the comparing unit 26 Continuation Referring to FIG. 3, a preferred embodiment of the sleep wake-up test method applied to the sleep wake-up test system of the present invention includes the following steps: Before the test starts, the power supply of the power button is powered by the connection lines 16, 17. The pin 38 and the negative power pin 39 are connected to the switch module 15 , and the interface module 18 of the test fixture 10 is connected to the interface module 32 of the motherboard 30 to be tested by the cable 19 to realize The test fixture 10 communicates with the motherboard 30 to be tested. In step S1, the motherboard 30 to be tested is turned on, and the power button operation is set to perform a sleep/wake operation in the power management of the operating system of the motherboard 30 to be tested. In step S2, the test software 20 is executed, and the number of tests and the delay time between sleep and wake-up are set in the initialization unit 22 according to actual needs. The initialization unit 22 writes the delay time to the timing module 12, and sends a The counter signal is cleared to the counter 14 to clear the value in the counting module 14. In step S3, the signal sending unit 24 sends a timing signal to the timing module 12, and the timing module 12 starts timing after receiving the timing signal, and sends a counting signal to the counting module 14 after the delay time is reached. A closing signal is sent to the switch module 15. In step S4, after receiving the closing signal, the switch module 15 automatically disconnects after performing a closing operation, the positive power supply pin 38 of the power button and the negative 098131438 form number A0101 page 7 / total 16 pages 0982053938-0 [ 0026] 201111979 Instantaneous short circuit between power pins 39, equivalent to the power button being pressed once, the operating system receives the signal that the power button is pressed and then starts to enter the sleep or wake state. In this embodiment, the operating system automatically switches between entering a sleep state or a wake state after receiving a signal that the power button is pressed. For example, when the operating system receives the signal that the power button is pressed and enters the sleep state, the next time the operating system receives the signal that the power button is pressed, it enters the awake state. The test board 30 is in a sleep state from being in a sleep state to being completely awake to complete a test, that is, in one test, the switch module 15 receives the close signal twice. [0027] Step S5, after the counting module 14 receives the timing signal, the value in the register is incremented by one, and the result after the addition is sent to the comparing unit 26 [0028] Step S6, the comparing unit 26 receives After the result is sent by the counting module 14, the result is divided by two and then rounded, and the integer obtained by rounding is compared with the set test number. If the integer obtained by rounding is less than the set test number, the step is returned. S3; if the integer obtained by rounding is equal to the set number of tests, the test ends. [0029] The sleep wake-up test system and method control the test fixture 10 through the test software 20 to complete the automatic test of the sleep wake-up of the motherboard 30 to be tested, saving manpower, reducing misdetection, and improving Test efficiency. [0030] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, such as 098131438 Form No. A0101 Page 8 / Total 16 Page 0992053938-0 201111979 [0031] Those skilled in the art of the present invention are in the spirit of the invention of Mai Yi. Modifications or changes shall be covered by the following patents. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a sleep wake-up test system of the present invention. 2 is a schematic diagram of a sleep wake-up test system of the present invention. 3 is a flow chart of a sleep wake-up test method of the present invention. [0035] [Main component symbol description] Test fixture: 10 Circuit board: 11 [0036] Timing module: 12 [0037] Counting module: 14 [0038] Switch module: 15 [0039] Connection Line · 16, 1 7 ! [0040] ❹ [0041] Interface module: 18, 32 . ^ ... Cable: 19 , [0042] Test software: 20 [0043] Initialization unit: 2 2 [0044] Signal Transmitting unit: 24 [0045] Comparison unit: 26 [0046] Board to be tested: 30 098131438 Form number A0101 Page 9/16 pages 0992053938-0 201111979 [0047] Central processing unit: 34 [0048] Memory: 36 [0049] Positive Power Supply Pin: 38 [0050] Negative Power Supply Pin: 39 0982053938-0 098131438 Form Number A0101 Page 10 of 16