CN206532194U - Embedded type high speed mass memory system - Google Patents
Embedded type high speed mass memory system Download PDFInfo
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- CN206532194U CN206532194U CN201720214768.8U CN201720214768U CN206532194U CN 206532194 U CN206532194 U CN 206532194U CN 201720214768 U CN201720214768 U CN 201720214768U CN 206532194 U CN206532194 U CN 206532194U
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Abstract
Turn IDE boards and IDE hard disks the utility model discloses a kind of embedded type high speed mass memory system, including embedded type CPU, PCI slot, PCI；The PCI slot is electrically connected with embedded type CPU；Also include PCI switching boards；The PCI switchings board includes PCI connection-pegs, PCI plug sockets and detection circuit, and the detection circuit includes some detection paths, status display circuit；The detection path is used for the corresponding detection signal of output when being powered；Some pins of the PCI connection-pegs are electrically connected by the path with some pins of the PCI plug sockets respectively；The status display circuit is electrically connected with the detection path, and the detection signal for receiving and responding to the detection path output makes corresponding instruction.The utility model can avoid user that interface is inserted into bad when in use.
Description
Technical field
The utility model is related to computer hardware technology, more specifically, it relates to which a kind of embedded high-speed Large Copacity is deposited
Storage system.
Background technology
The sample rate of fault wave recording device is high in power system, and channel capacity is big, and the time is recorded with to failure wave-recording
It is required that more and more higher, normality record also becomes a reality requirement, therefore the capacity and speed of recording memory is proposed higher
It is required that, and the requirement to failure wave-recording high reliability make it that current fault wave recording device uses embedded hardware and software systems,
So it is accomplished by fault wave recording device faster, the bigger storage system of capacity.
In built-in field, mainly use nandflash as storage medium in terms of massive store at present, conclude
To have two than more typical scheme：
Scheme one, directly using embedded type CPU+large capacity single chip nandflash；
Scheme two, using embedded type CPU+interface chip+microcontroller+multi-disc nandflash；
Current SLC single-chip nandflash main flows capacity is 2Gbyte, 8 data and address interface, nominal writing speed
In 15MB/s, nominal reading speed is in 40MB/s.Scheme one occupies a large amount of cpu resources, and speed and capacity are by single-chip
Limitation, speed is also by I/O Interface limits, and the program can only be used in the occasion relatively low to speed and capacity requirement；Scheme two
Solve the limitation of single-chip, and can reduce the consumption to cpu resource by the dma operation of interface chip, but hardware design
Complexity, upgrading is complicated.
Notification number is CN201527642U Chinese patent, discloses a kind of embedded type high speed mass memory system, is wrapped
Include embedded type CPU, it is characterised in that：Also turn ATA100 interface chips and IDE storage dishes including PCI, embedded type CPU passes through PCI
Bus turns ATA100 interface chips with PCI and is connected, and PCI turns ATA100 interface chips and is connected by ide interface with IDE storage dishes.
Embedded type high speed mass memory system of the present utility model, the general ATA100 interfaces of use can connect conventional hard and also use
The SSD solid-state disks of high speed, upgrading is convenient, it is only necessary to change IDE storage dishes；Because IDE storage dishes are replaceable, memory capacity
It is scalable, failure wave-recording or other embedded equipments are met in demand of the different application occasion to different memory sizes；Due to driving
Dynamic to realize ATA100 interfaces, actual read or write speed is in more than 16MB/s, and memory capacity is met up to 2G-120G or more
The requirement of failure wave-recording or other embedded equipments to high-performance storage speed.
At present, PCI on the market turns ATA100 interface chips, has developed into PCI and turns IDE boards, both are functionally
Substantially identical, user only needs to PCI turning IDE boards to be inserted into the PCI slot of PC, and hard disk then is connected into PCI turns IDE
Can normally it be used on ide interface on board.In actual use, user is when slotting PCI turns IDE boards, may be because of
Misoperation or other reasons, cause interface to damage, influence is used.
Utility model content
In view of the deficienciess of the prior art, the purpose of this utility model is that providing a kind of embedded high-speed Large Copacity deposits
Storage system, can avoid user that interface is inserted into bad when in use.
To achieve the above object, the utility model provides following technical scheme：
A kind of embedded type high speed mass memory system, including embedded type CPU, PCI slot, PCI turn IDE boards and
IDE hard disks；The PCI slot is electrically connected with embedded type CPU；Also include PCI switching boards；The PCI switchings board includes PCI
Connection-peg, PCI plug sockets and detection circuit, the detection circuit include some detection paths, status display circuit；The inspection
Surveying path is used for the corresponding detection signal of output when being powered；Some pins of the PCI connection-pegs pass through the path respectively
Electrically connected with some pins of the PCI plug sockets；The status display circuit is electrically connected with the detection path, for receiving
And the detection signal exported in response to the detection path makes corresponding instruction.
Preferably, the detection path includes current detection circuit.
Preferably, the status display circuit includes the output end of some LEDs, the LED and current detection circuit
Electrical connection.
Preferably, in addition to auditory tone cues electric circuit, the auditory tone cues electric circuit is electrically connected with detection path, for receiving simultaneously
The detection signal exported in response to the detection path makes corresponding auditory tone cues.
Preferably, the auditory tone cues electric circuit includes：
Insertion detection circuit, is electrically connected with detection path, for detecting that PCI turns whether IDE boards are inserted into PCI plug sockets
On, and export corresponding first detection signal；
Abnormal detection circuit, is electrically connected with detection path, is not powered on all the way for detecting that the detection path whether there is,
And export corresponding second detection signal；
Output circuit, is electrically connected with insertion detection circuit, abnormal detection circuit, for believing in response to the described first detection
Number, second detection the corresponding cue of signal output.
Preferably, the output circuit includes the first not circuit, second and gate circuit, NPN triode, buzzer；Institute
The input for stating the first not circuit is electrically connected with abnormal detection circuit, output end and second one of input with gate circuit
End electrical connection；Described second electrically connects with another input of gate circuit with insertion detection circuit, output end and NPN triode
Base stage electrical connection；The grounded emitter of the NPN triode, colelctor electrode accesses VCC voltages after being connected with buzzer.
Compared with prior art, the utility model has the advantages that：By above technical scheme, PCI switching boards are advance
（Factory default is assembled）It has been inserted on PCI slot, i.e., PCI connection-pegs has been inserted on PCI slot.In this way, user is installing
During hard disk, PCI is first turned into IDE boards and is inserted on the PCI plug sockets of PCI switching boards；Finally the IDE lines of hard disk are inserted into
PCI turns on IDE boards.So, on the one hand, after powered up, PCI can be clearly observed by status display circuit and turns IDE plates
Whether card is plugged；On the other hand, user is it also avoid because misoperation causes PCI slot to be occurred by bad situation is inserted.
Brief description of the drawings
Fig. 1 is the overall structure figure of embedded type high speed mass memory system in embodiment；
Fig. 2 is the structure chart of PCI switching boards in embodiment；
Fig. 3 is the circuit diagram of current detection circuit in embodiment；
Fig. 4 is the circuit diagram of status display unit in embodiment；
Fig. 5 A are the circuit diagram of insertion detection circuit in embodiment；
Fig. 5 B are the circuit diagram of abnormal detection circuit in embodiment；
Fig. 6 is the circuit diagram of output circuit in embodiment.
Embodiment
With reference to embodiment and accompanying drawing, the utility model is described in further detail, but reality of the present utility model
The mode of applying is not limited only to this.
Reference picture 1, this implementation provides a kind of embedded type high speed mass memory system, including be sequentially connected electrically it is embedded
CPU, PCI slot, PCI switchings board, PCI turn IDE boards and IDE hard disks；Wherein, the embedded type CPU and PCI slot collect
Into on the mainboard of main frame, embedded type CPU can use the POWERPC8270 of Freescale company, it would however also be possible to employ Intel
The core series processors of company, or Advanced Micro Devices processor.PCI turns IDE boards and IDE hard disks pin on the market
Sell, user directly can buy and use.
Before use, PCI switching boards are inserted into PCI slot in advance.
Reference picture 2, PCI switching boards include PCI connection-pegs, PCI plug sockets（It is identical with PCI slot）And detection electricity
Road, detection circuit includes some detection paths, status display circuit.Wherein, detection path provides some signalling channels, and
When each signalling channel is powered, corresponding detection signal can be exported.In one embodiment, the detection path uses electric current
Circuit is detected, its circuit diagram reference picture 3 is made up of current distributing monitor, its model IN282, it gathers port and is parallel with
Sampling resistor Rx, in connection, the pin of PCI connection-pegs is connected to by sampling resistor Rx the pin of PCI plug sockets（One
One collection resistance Rx of pin correspondence）, i.e. PCI connection-pegs and the corresponding current detecting of each pin of PCI plug sockets
Circuit.In this way, when PCI is turned IDE boards be inserted on PCI plug sockets, the pin between PCI plugs and PCI plug sockets is powered,
So that passing through electric current Ix, current distributing monitor output sampled signal Vs on corresponding use resistance Rx.
Reference picture 2, Fig. 3, Fig. 4, status display circuit include some LEDs, LED and current detection circuit（That is electric current
Shunt monitor）Output end electrical connection, to receive sampled signal Vs.Thus, when sampled signal Vs is high level so that
LED electrified light emitting.
The present embodiment further comprises auditory tone cues electric circuit, and auditory tone cues electric circuit includes insertion detection circuit, abnormal inspection
Slowdown monitoring circuit and output circuit.
Reference picture 5A, insertion detection circuit includes the first OR circuit N1, and it has some inputs, each input
Electrically connected with the output end of a current detection circuit, to receive sampled signal Vs.Therefore, it is inserted into PCI when PCI turns IDE boards
When on plug socket, the sampled signal Vs of a high level can be at least produced so that the of the first OR circuit N1 output high level
One detection signal Vj1.
Reference picture 5B, abnormal detection circuit is using first and gate circuit N2, and it has some inputs, each input
Electrically connected with the output end of a current detection circuit, to receive sampled signal Vs.Therefore, it is inserted into PCI when PCI turns IDE boards
When on plug socket, if there is a pin not to be plugged, it is low level just to have sampled signal Vs all the way, and then causes first and door electricity
The low level second detection signal Vj2 of road N2 outputs.
Reference picture 6, output circuit includes the first not circuit N3, second and gate circuit N4, NPN triode Q1, buzzer
B1；First not circuit N3 input is electrically connected with abnormal detection circuit, to receive the second detection signal, output end and second
Electrically connected with gate circuit N4 one of input；Second and gate circuit N4 another input and insertion detection circuit electricity
Connection, to receive first detection signal, output end is electrically connected by resistance R1 with the base stage of NPN triode Q1；NPN triode Q1
Grounded emitter, colelctor electrode connected with buzzer B1 after access VCC voltages.Therefore, when first detection signal Vj1 is high electricity
Flat, when the second detection signal Vj2 is low level, second makes NPN triode with the gate circuit N4 control signal Vc for exporting high level
Q1 is turned on, and then buzzer B1 is powered and sends sound.
Claims (6)
1. a kind of embedded type high speed mass memory system, including embedded type CPU, PCI slot, PCI turn IDE boards and IDE
Hard disk；The PCI slot is electrically connected with embedded type CPU；It is characterized in that, in addition to PCI switching boards；The PCI switchings board
Including PCI connection-pegs, PCI plug sockets and detection circuit, the detection circuit includes some detection paths, status display electricity
Road；The detection path is used for the corresponding detection signal of output when being powered；Some pins of the PCI connection-pegs pass through respectively
The path is electrically connected with some pins of the PCI plug sockets；The status display circuit is electrically connected with the detection path,
Detection signal for receiving and responding to the detection path output makes corresponding instruction.
2. embedded type high speed mass memory system according to claim 1, it is characterized in that, the detection path includes electricity
Current detection circuit.
3. embedded type high speed mass memory system according to claim 2, it is characterized in that, the status display circuit bag
Some LEDs are included, the LED is electrically connected with the output end of current detection circuit.
4. embedded type high speed mass memory system according to claim 2, it is characterized in that, in addition to auditory tone cues electricity
Road, the auditory tone cues electric circuit is electrically connected with detection path, the detection letter for receiving and responding to the detection path output
Number make corresponding auditory tone cues.
5. embedded type high speed mass memory system according to claim 4, it is characterized in that, the auditory tone cues electric circuit bag
Include：
Insertion detection circuit, is electrically connected with detection path, for detecting that PCI turns whether IDE boards are inserted into PCI plug sockets, and
Export corresponding first detection signal；
Abnormal detection circuit, is electrically connected with detection path, is not powered on all the way for detecting that the detection path whether there is, and defeated
Go out corresponding second detection signal；
Output circuit, is electrically connected with insertion detection circuit, abnormal detection circuit, in response to the first detection signal,
The two detection corresponding cues of signal output.
6. embedded type high speed mass memory system according to claim 5, it is characterized in that, the output circuit includes the
One not circuit, second and gate circuit, NPN triode, buzzer；The input of first not circuit and abnormality detection electricity
Road is electrically connected, and output end is electrically connected with second with one of input of gate circuit；Described second with gate circuit another
Input is electrically connected with insertion detection circuit, and output end is electrically connected with the base stage of NPN triode；The transmitting of the NPN triode
Pole is grounded, and colelctor electrode accesses VCC voltages after being connected with buzzer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720214768.8U CN206532194U (en) | 2017-03-06 | 2017-03-06 | Embedded type high speed mass memory system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720214768.8U CN206532194U (en) | 2017-03-06 | 2017-03-06 | Embedded type high speed mass memory system |
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| Publication Number | Publication Date |
|---|---|
| CN206532194U true CN206532194U (en) | 2017-09-29 |
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ID=59918704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720214768.8U Expired - Fee Related CN206532194U (en) | 2017-03-06 | 2017-03-06 | Embedded type high speed mass memory system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108647167A (en) * | 2018-04-26 | 2018-10-12 | 安徽展航信息科技发展有限公司 | A kind of modularization mass-storage system |
-
2017
- 2017-03-06 CN CN201720214768.8U patent/CN206532194U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108647167A (en) * | 2018-04-26 | 2018-10-12 | 安徽展航信息科技发展有限公司 | A kind of modularization mass-storage system |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170929 Termination date: 20180306 |