201109670 六、發明說明： 【發明所屬之技術領域】 本發明係有酶針卡的製作方法，特別是指—麟針模組製作 的方法’利用才示準互補金氧半導體(CM〇s)製程技術設計探針晶片 與空間轉縣漁(spaee transfG_·)—體财，並結合微電鑄製 程、化學織程與研磨技術製作探針及探針頭結構，最後以微機 電蝕刻技術完成探針的懸浮與貫穿孔。 【先前技術】 在半導體製造技術日益精進並進入奈米時代之下，晶片體積縮 小’自鱗射抓謂之_、，探針設備與探針卡衫能快速且 準確的與#墊制，便成為晶圓檢測技術未來的重點發展方向。 #在降低測試成本的考量下，有效縮減測試時間，也是各業者所 持、，.貝追求的發展方向，因此增力口同時測試的晶粒數(刪Η_〇υτ)亦 疋探針卡廠商努力發展的目標。依據不同類型的產品，由於其▽〇 數的不同，可’進行晶_試的晶粒顆數也有所不同。 至於探針卡的結構設計方面，目前_外半導體^測試仍 有以壤減3旨_探財絲作城量測，其優點為探針可依電 極板位置進仃配置，以及探針可調變的垂直位移行程範圍較大， 201109670 可以確保每-探針與電極板之間有良好的電性接觸。另外，每— 根探針在垂直方向均可·定位的調整，方便運麟高低不一致 的_板上，因此可以適用於晶片系統化的測試。此外，若有探 針損壞時可以進行铜的探針更換，科需更換整個測試模組。 但其缺點為高頻元件在職_中產生的電性以及機械雜訊會影 響整個測試結果’並且對於微小間距之電極板無法進行針測。所 以利用微機電技術製作之微探針可以克服上述缺點，尤其是使用 #在通訊高頻晶片測試與針對具有小間距電極板之晶片測試，以及 考置批罝製造的成本縮減。 目前國内外參考文獻’姻微機電製程所製作的微探針卡， 無論是利用體型微加工、面型微加工或是光刻電鍍禱模模造成型 〇JC}A’ Uthogmphie Galvan0f0rmung Abf〇rmung)技術，已是下一個 半導體世代不可或缺的測試元件，而可以應用於高頻、晶圓級測 試以及批量製造的做法更是可以降低成本符合時勢所趨。但是這 ®些微機電技術製作的微探針卡基本上幾乎以懸臂式為主’不易實 現垂直探針卡的功能；另外基本上並非使用標準互補金氧半導體 (CMOS)製程來完成，不易内建被動元件與電路，被動元件仍需要 於印刷電路板上實現；再者小轉大的空間轉換器也不易實現；因 此本發明提出一種新的設計與製造技術，無論半導體技術如何演 進’以微機電製作的矩陣式微探針卡皆可以有效的進行搭配，尤 其以微機電製作的微結構可以與電路做整合，因此可以提高探針 201109670 卡的優點’諸如尺寸設計變小、訊號量測功能加大以及可靠度的 增加’這些實現系統與系統單晶片（SyStem 〇n咖卩)的技術，是一般 傳統組裝式探針所無法比擬的。 【發明内容】 有關本發明以下的說明其相關名詞定義如下：化學鍍與無電 鲁鍍(electroless plating)或無電解電鍍為同義辭。本發明導入有限元 ^軟體進行騎㈣設計，並且再使賴魏製程技術，透過微 影、電鑄與研磨技術進行高產量、高精度的凸塊探針，完成探針 卡製作。故本發明整個設計與製程所具有的特色與優點如下： a)利用標準標準互補金氧半導體(CM〇s购呈、電禱製程及化學 鍍製程製作探針，同時利用標準互補金氧半導體製程的多層内201109670 VI. Description of the Invention: [Technical Fields of the Invention] The present invention relates to a method for manufacturing an enzyme needle card, in particular to a method for manufacturing a lining needle module, which utilizes a process technology for quasi-complementary MOS (s). Design probe wafer and space to fishery (spaee transfG_·) - body wealth, combined with micro-electroforming process, chemical weaving and grinding technology to make probe and probe head structure, and finally complete the probe with micro-electromechanical etching technology Suspension and through holes. [Prior Art] As semiconductor manufacturing technology becomes more sophisticated and enters the nano-era era, the wafer size shrinks, and the probe device and the probe card can be quickly and accurately placed with the pad. Become the key development direction of wafer inspection technology in the future. # Under the consideration of reducing the cost of testing, effectively reducing the test time is also the development direction pursued by various industry players. Therefore, the number of crystal chips tested at the same time (deleted _ 〇υ τ) is also the probe card manufacturer. The goal of hard work. Depending on the type of product, the number of grains that can be crystallized varies depending on the number of turns. As for the structural design of the probe card, at present, the external semiconductor test is still measured by the soil reduction, and the advantage is that the probe can be placed according to the position of the electrode plate, and the probe can be adjusted. The variable vertical displacement range is large, and 201109670 ensures good electrical contact between each probe and the electrode plate. In addition, each probe can be adjusted in the vertical direction, which is convenient for the board to be inconsistent, so it can be applied to the system test of the wafer. In addition, if the probe of copper can be replaced when there is damage to the probe, the department needs to replace the entire test module. However, the disadvantage is that the electrical and mechanical noise generated by the high-frequency component in the job _ will affect the entire test result' and the needle plate cannot be pinched for the micro-pitch. Therefore, the micro-probes fabricated using MEMS technology can overcome the above disadvantages, especially the use of #in communication high-frequency wafer testing and wafer testing for electrodes with small pitch, and the cost reduction of the manufacturing process. At present, the microprobe card made by the domestic and foreign reference 'Medical Micro Electromechanical Process' is made by the use of bulk micromachining, surface micromachining or lithography electroplating model. JC}A' Uthogmphie Galvan0f0rmung Abf〇rmung) It is already an indispensable test component for the next semiconductor generation, and it can be applied to high-frequency, wafer-level testing and batch manufacturing to reduce costs. However, the micro-probe cards made by these MEMS technologies are almost almost cantilevered. It is not easy to implement the function of the vertical probe card. In addition, it is basically not completed by the standard complementary metal oxide semiconductor (CMOS) process, and it is not easy to be built in. Passive components and circuits, passive components still need to be implemented on printed circuit boards; and small space converters are also difficult to implement; therefore, the present invention proposes a new design and manufacturing technology, no matter how semiconductor technology evolves The matrix micro-probe cards can be effectively matched, especially the micro-electromechanical micro-structure can be integrated with the circuit, so the advantages of the probe 201109670 card can be improved, such as the size design is smaller and the signal measurement function is increased. And the increase in reliability 'these systems and system single-chip (SyStem 卩n curry) technology, is unmatched by the traditional traditional assembly probe. SUMMARY OF THE INVENTION The following description of the invention is defined as follows: electroless plating is synonymous with electroless plating or electroless plating. The invention introduces a finite element ^soft body for riding (four) design, and further enables the Lai Wei process technology to perform high-yield, high-precision bump probe through the lithography, electroforming and grinding technology to complete the probe card production. Therefore, the features and advantages of the overall design and process of the present invention are as follows: a) Using standard standard complementary MOS semiconductors (CM 〇s purchase, electro-pray process and electroless plating process to make probes while using standard complementary MOS process) Within multiple layers
terc_eetiGn)①成小轉大的佈線，甚朗含測試電路。 (2)互補金氧料體探_的鮮化：可藉由後製絲決定探針 的位置，提料同節距的_式標準互補金氧铸體探針晶 片，使用時可依照客戶需求。 I題 =研磨職作探針，爾傳麵式探 大幅縮小探針的間隙(pitch)。。 ⑷將探針與㈣均_(spaee Μ_)_體成形於標 201109670 準^補金氧半導體探針晶片，並以覆晶錫球(S。咖於晶 片月面直接與界接探測器(int〒_妾合，再與探針卡之印刷 電路板⑽)接合’大帽提升整個探針卡共面度至10微米以 下，領先國際水準之15-20微米。 (5)利用化學辦!程製條針結構，提升過去文獻伽凸塊或金屬 溥膜層為探針的受力能力無法達到數克以上的接觸力。必要時 可加上填入高分子材料到底部當支撐。 ⑹利用f難錄作撕結構，提升贴文獻伽凸塊或金屬薄 膜層為探針較力能力纽達驗克以上_觸力。必要時可 加上填入高分子材料到底部當支撐。 ⑺讓1C設計完成後’ IC設計人員可同步設計出測試用的標準互補 金氧半導義針U 標準錄半導雜針晶片測試 1C ’可主導測試的流程’並大幅縮短封裝測試的時間與步驟。 【實施方式】 本發明乃I種探針卡，如圖i與圖2所示，主要係由一^ 準互補金氧料體(CMOS)探針晶m (以下簡稱探針晶片）、力: 強板2、螺絲3、底座環4、彈簧探針式界接探測器$、内固定蓋 板6、鋼珠7、補強用界接探測器8、彈簧9、外固定蓋板1〇與連 接測試儀器用的印刷電路板1接合而成。 如圖3、圖4、圖5、圖6所示，探針晶片u主要特徵為使用 201109670 “準互補金氧半導體結合微機電(CMOS-MEMS)製程技術設計製 作懸以探針結構，使得探針卩㈣與㈣轉浦組(啊e t^anSf_ef；^i成型；該朗轉賴組具小轉大的魏，係利用 *準1金氧半導體製程的内連線佈局㈣erc_ecti〇n)納入探針 二間轉換,連接線路’該連接線路從懸臂式探針的固定端向外擴 政至探針曰曰片n的邊緣銲塾㈣％ ;於懸臂式探針的自由端設有 凸塊作為探針測試探頭，並突出於探針晶片u ;探針與外部小轉 大P刷電路板i的連接方式乃藉由石夕貫穿孔細响细⑽ =a)15其製程是由微機電後製程加工將晶片貫穿，並填入導電材 枓28’再使探針晶片丨丨背面的發貫穿孔15具有薛錫凸塊％以利 於覆晶封胁補_界雜· 8。請注意本發龍針晶片n實 施_如圖3、圖4、圖5、圖6所示，但並不以此為限，圖中 以更小、更密。圖3.為探針卡上的CM〇S探針晶片示意 西。、圖5為C聰探針晶片光罩佈局圖。圖6顯示探針卡 的單根懸臂探針底部可以有高分子材料 木針卡 晶片U上探針的各種佈局，可叹# 可以^可以是單排探針頭中間，可以是雙排探針頭對探針頭， 疋城式’可以是_式，可以是隨機式。基本上對於多曰 杻(喊1Ρ1，的測試，上述的CM〇s探針晶片可以是多塊电人: 與補強用界接細||8#由覆晶接合。 °再 本發明之整個新型標準互補金氧半導體探針卡的製造過程，是 201109670 由數個主要的奴結合而成，分狀標準 微影製程、微麵製程、化學難程 導體製程、 心_㈣_臟彳糊 ==半導體製程是利用台積電所提供 0.35微樣私(但不以此為限)，進行 不㈤使肋含電路進行補償，卿需鮮僅兩要 =供内連接金屬層之繼義即可，咖亦可簡化，不需要繁 〇s電晶細聽製程，大幅降低鮮與製程成本。 微影製程歧耻紐、貞紘、聚亞》(P〇lyimide)等旋塗 ^材的表面，並_光罩或網片加鱗光後顯影蚊義的凸塊 微電鑛製程是_具有電源供應H、躲槽 '加熱器、溫控 回饋裝置等f鍍設備組合而成，其可用來製造出多層探針及探針 頭的結構。 化學鍍製程是利用具有鍍液槽、加熱器、溫控回饋裝置、磁 石攪拌等電鍍設備組合而成，其可用來製造出多層探針及探針頭 的結構。 化學機械研磨製程是利用具有研磨墊、研磨液、晶圓載具、 201109670 研磨液櫈拌幫料研磨設備組合而成，其可絲平坦化電锻後均 勻度以及粗赌差的凸塊結構，使其具有共面度良好以及表面粗 糖度小的特性。有時亦可指機械研磨製程。 蝴製&係指將石夕貫穿孔15與多餘的石夕14基材，利用乾餘 刻方式來去除的製程。有時亦可指濕侧製程。 [製造程序] 如圖8所示。 乂 使用心準半導體製程，來設計探針與電路佈線以及石夕貫穿 孔15位置，如圖8(a)所示。 步驟2.將晶粒的正面密合上載板，將基材背面研磨㈣，如圖 8(b)所示。 ^ 將研磨几成後的晶粒之正面旋塗一層光阻2〇後，進行曝 光員K義出圖案，利用非等向性乾钱刻(如：哑)將氧 化夕勤刻疋，再利用非等向性乾軸(如：观E)將矽基材 餘刻至想要的深度，如圖8(c)所示。 乂驟4.去除光阻2〇後，將银刻後的晶粒之石夕貫穿孔Η周圍沉積 上-層絕緣層(例如：Pa咖ec、CF2聚合物等），如圖 8(d)所示。 步驟5.將晶粒密合上具有晶種層之載板，進行沉積製程將石夕貫穿 201109670 孔is填滿導電材料Μ且與1/〇焊塾％的金屬層η連接 起來’如圖8(e)所示。 步驟6:將晶粒之正面旋塗一 層先阻20後，進行曝光顯影，定義 錢探針的區域19，進行沉積金屬及研磨，如圖8(f) 所示。 步驟7:將晶粒之正面旋塗一声 疋文層光阻20後，進行曝光顯影定義出 圖案，定義出欲乾餘刻(如：RIE、DRIE)的區域後，進行 • _等向性乾敍刻，如圖8(g)所示。 乂私將曰曰粒泡入蝴液中(如：K〇H) ’將可讓探針變形之空間 侧出來，如圖8⑻所示；此步驟也可使用乾侧技術 (如：DRIE)。 乂驟9.在印刷電路板上製作銲錫凸塊π，细覆晶封裝技術， 將上述完成的探針^ U與印職路板丨結合後，如圖 8(0，το成CMOS探針晶片11的製作步驟。 φ Note .右基材太厚導致乾餘刻製造成本過高，可在製程中增加簡 易的化學機械研磨(CMP)製程將紐研磨變薄。探針晶片u 與印刷電路;fe 1接合前可以沉積一層或多層的高抗氧化、低 阻抗之金屬或金屬合金。以上製程在製程順序允許下可調換 其順序。 ' 上述所提出的新方法與技術，對於探針卡的測試積體電路晶 片，其設計可以根據功能積體電路(IC)設計而同步完成，目的在於 12 201109670 測試該功能積體電路’包括探針陣列的設計；空間轉換器細咖 transf_ef)的輯’具有小轉大的佈線，乃是_鮮標準互補 金氧半導體製程的多層内連線(interc〇nnecti〇n)完成。此測試積體 電路晶片’其設計所需要的佈局可以同時與功能積體電路的佈 局’設置於同-批次的光罩上，以同時下線取得，也可以與功能 積體電路的佈局分開下線取得。其理由是本發_枝是以標準 標準互補錄半導體製軸額方式設計，而且其探針的尺寸也 • 與功能積體電路的銲墊(pad)16尺寸相近。 有關本發撕賴鮮互補金氧半導體製程，料含電路需 求，而僅需具有内連接的多層金屬的話，也可以是僅能完成金^ 與絕緣層圖絲作的半導體或微機電製程，如此可以，大幅降低 製作電晶體所需的費用與光罩成本，另外也可使步進機—次曝光 面積較大，原狀不需多次對準、内連接多層金屬的線寬較電晶 體的通道寬度大。 有關探針尺寸的設計這一部份可由下列三個實施例得知。 [實施例-]垂直式探針結構（以化學鑛金屬為主結構） 以ic測試IC為目的，考慮IC的銲塾間距，採用探針所佔面 積為100微米X 100微米來模擬，探針懸臂寬度方面選取如微 米。然而，光憑IC薄膜來支樓是不狗的，在設計上利用電錢製程 使探針厚度增加(厚度分別為10微米、20微米及30微米），來加 13 201109670 強支揮懸臂的強度，如圖9(a)〜@。 =經m魏體的分析<τ，施加位織針能承受到最大 探.的位移量定及反作用力。探針厚度大於频 絲力，祕要求’且其最大應力也不麵過材料本身的降terc_eetiGn) 1 into a small turn large wiring, very long with test circuit. (2) Complementary gold oxide body exploration _ the freshness: the position of the probe can be determined by the post-spinning, and the _ standard complementary gold-oxygen casting probe wafer with the same pitch can be used, which can be used according to customer requirements. . I question = Grinding job probe, the face-to-face probe greatly reduces the pitch of the probe. . (4) The probe and (4) _ (spaee Μ _ _ _ body _ body formed on the standard 201109670 quasi-compensation MOS wafer probe, and the flip-chip solder ball (S. coffee on the wafer surface directly with the boundary detector (int 〒 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The structure of the needle bar can improve the contact force of the probes in the past literature galax bumps or metal ruthenium film layers, and can not reach the contact force of several grams or more. If necessary, the polymer material can be added to the bottom to support. (6) Using f It is difficult to record the tearing structure, and the lifting of the document gamma bump or metal film layer as the probe is more powerful than the New Zealand gram. The contact force can be added to the bottom when necessary. (7) Let the 1C design After the completion, IC designers can simultaneously design the standard complementary gold-oxide semi-conducting needle for testing. U standard recording semi-conducting needle test 1C 'the process that can lead the test' and greatly shorten the time and steps of the package test. Method] The present invention is a type of probe card, as shown in Figure i and Figure 2 It is mainly composed of a quasi-complementary gold oxide body (CMOS) probe crystal m (hereinafter referred to as a probe wafer), force: strong plate 2, screw 3, base ring 4, spring probe type interface detector $ The inner fixed cover 6, the steel ball 7, the reinforcing boundary detector 8, the spring 9, and the outer fixed cover 1 are joined with the printed circuit board 1 for connecting the test instrument. As shown in Fig. 3, Fig. 4, Fig. 5 As shown in FIG. 6, the probe chip u is mainly characterized by using the 201109670 "quasi-complementary MOS-integrated microelectromechanical (CMOS-MEMS) process technology to design and construct a suspended probe structure, so that the probe 卩(4) and (4) the pulsing group ( Ah et^anSf_ef;^i molding; the lang turn to the group with a small turn to the big Wei, the use of the * quasi 1 oxy-metal semiconductor process of the interconnect layout (four) erc_ecti〇n) into the probe two conversion, the connection line 'this The connecting line is extended outward from the fixed end of the cantilever probe to the edge of the probe cymbal n (4)%; the free end of the cantilever probe is provided with a bump as a probe test probe, and is highlighted Needle wafer u; the connection mode of the probe to the external small turn large P brush circuit board i is made by the fine-grained (10) = a) 15 The process is performed by the micro-electromechanical post-processing process, and the conductive material 枓 28' is filled in, and then the through-hole 15 of the back surface of the probe wafer has a Xuexi bump % to facilitate the flip-chip sealing compensation. 8. Please note that the hairpin wafer n implementation is shown in Figure 3, Figure 4, Figure 5, Figure 6, but not limited to this, the figure is smaller and denser. Figure 3. Probe The CM〇S probe wafer on the card is shown in the west. Figure 5 is the layout of the C-clamp probe wafer mask. Figure 6 shows that the single cantilever probe on the probe card can have a polymer material on the bottom of the chip. The various layouts of the probes can be sighed. # can be a single row of probe heads in the middle, can be a double row of probe heads to the probe head, and the 疋-style can be _-type, which can be random. Basically, for the test of 曰杻 曰杻 喊 喊 喊 上述 上述 上述 上述 上述 上述 上述 上述 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针 探针The manufacturing process of the standard complementary MOS probe card is 201109670. It is composed of several major slaves. The standard lithography process, micro-surface process, chemical process conductor process, heart _ (four) _ dirty paste == The semiconductor process is to use the 0.35 micro-sample private provided by TSMC (but not limited to this), to carry out the compensation of the rib-containing circuit without the (5), the need for the fresh two only = the continuity of the metal layer for the inner connection, the coffee also It can be simplified, does not require the shovel s electro-crystal fine-graining process, and greatly reduces the cost of fresh and process. The surface of the lithography process, such as 微 制 歧 纽 纽 纽 纽 贞纮 贞纮 聚 聚 聚 聚 聚 聚 聚 聚 聚 聚 , , , , , , The visor or mesh is scalded to develop the mosquito-like bump micro-electron process, which is composed of a power supply H, a gully heater, a temperature-controlled feedback device, etc., which can be used to manufacture a multilayer probe. The structure of the needle and the probe head. The electroless plating process utilizes a plating bath, a heater, and temperature control. A combination of electroplating equipment such as feedback device and magnet stirring, which can be used to fabricate a multilayer probe and a probe head. The chemical mechanical polishing process utilizes a polishing pad, a polishing liquid, a wafer carrier, and a 201109670 polishing slurry stool. The material grinding equipment is combined, which can flatten the uniformity after electric forging and the bump structure of the rough gambling, so that it has the characteristics of good coplanarity and small surface roughness. It can also be referred to as a mechanical grinding process. Butterfly & refers to the process of removing the stone eve through hole 15 and the excess Shi Xi 14 substrate by dry remnant method. Sometimes it can also refer to the wet side process. [Manufacturing procedure] As shown in Fig. 8.乂 Use the mind-precision semiconductor process to design the probe and circuit wiring and the position of the stone-like through-hole 15, as shown in Figure 8(a). Step 2. Close the front side of the die to the plate and grind the back surface of the substrate (4) , as shown in Fig. 8(b). ^ After the surface of the crystal grain after grinding for several times, a layer of photoresist is applied by a layer of 2 ,, and then the pattern of the exposure member K is used, and the non-isotropic dry money is used (eg, dumb). ) to oxidize the evening, then use the anisotropic dry axis (such as View E) Residually rub the substrate to the desired depth, as shown in Figure 8(c). Step 4. After removing the photoresist 2〇, the silver-etched grains are deposited around the hole. The upper-layer insulating layer (for example, Pacaec, CF2 polymer, etc.) is as shown in Fig. 8(d). Step 5. The crystal grains are adhered to the carrier plate having the seed layer, and the deposition process is carried out. Through 201109670, the hole is filled with conductive material and connected with the metal layer η of 1/〇 塾% as shown in Fig. 8(e). Step 6: After the surface of the die is spin-coated with a first resistance of 20, Exposure development, defining the area 19 of the money probe, depositing metal and grinding, as shown in Fig. 8(f). Step 7: After the front side of the crystal grain is spin-coated with a smectic layer photoresist 20, exposure development is defined. The pattern, after defining the area of the desired moment (eg, RIE, DRIE), performs the _ isotropic dry narration, as shown in Figure 8(g). The sputum granules are soaked into the liquid (eg, K〇H) ’ will allow the probe to deform laterally, as shown in Figure 8(8); this step can also use dry-side techniques (eg DRIE). Step 9. Make a solder bump π on the printed circuit board, fine-grained package technology, and combine the above-mentioned completed probe with the printed circuit board, as shown in Figure 8 (0, το CMOS probe wafer) Step 11: φ Note. The right substrate is too thick, resulting in excessive manufacturing cost, and a simple chemical mechanical polishing (CMP) process can be added to the process to thin the button. The probe wafer u and the printed circuit; One or more high-oxidation, low-impedance metals or metal alloys can be deposited before fe 1 bonding. The above process can be changed in order of process sequence. 'The new method and technology proposed above, for probe card testing The integrated circuit chip can be designed to be synchronized according to the functional integrated circuit (IC) design. The purpose is to test the functional integrated circuit 'including the design of the probe array; the space converter fine coffee transf_ef' has a set of 12 201109670 The small-to-large wiring is completed by the multi-layer interconnect (interc〇nnecti〇n) of the _ fresh standard complementary MOS process. The test integrated circuit chip 'the layout required for the design can be simultaneously set on the same-batch reticle with the layout of the functional integrated circuit to be taken offline at the same time, or can be separated from the layout of the functional integrated circuit. Acquired. The reason is that the hairpin is designed in the standard standard complementary recording semiconductor system, and the size of the probe is also similar to the size of the pad 16 of the functional integrated circuit. The semiconductor or micro-electromechanical process can only be completed by using only a plurality of interconnected metal layers, and the semiconductor or micro-electromechanical process can only be completed with gold and insulating layers. It can greatly reduce the cost and mask cost of making the transistor, and also can make the stepper-sub-exposure area larger, the original shape does not need to be aligned multiple times, and the line width of the interconnected multilayer metal is larger than that of the transistor. Large width. This part of the design of the probe size can be known from the following three embodiments. [Example-] Vertical probe structure (mainly composed of chemical mineral metal) For the purpose of ic test IC, considering the solder fill pitch of the IC, the probe is occupied by an area of 100 μm × 100 μm, and the probe is used. The cantilever width is selected as micrometers. However, the use of IC film to support the building is not a dog, the design of the use of the money process to increase the thickness of the probe (thickness of 10 microns, 20 microns and 30 microns, respectively) to add 13 201109670 strong support cantilever strength , as shown in Figure 9(a)~@. = Analysis by m-Wei body <τ, the position of the needle can be subjected to the maximum displacement and reaction force. The thickness of the probe is greater than the frequency of the filament, the secret requirement 'and its maximum stress does not face the drop of the material itself.
旦料挑圖10ί)〜(b)。但隨著IC製程線寬越小，其銲墊16數 二^小、越靠近及隨機出現，應用此製程方法可將每隻懸臂 的見度和間距任意的調整。當寬度變窄時，只需調整其長度或電 鐘的厚度，便很_達到量測應用端的需求。叫)為探針實 把例-之接觸力量與位移之相結果，其探臂增加25微米的 Z ’當接觸力量73.6亳牛頓時，其位移量約為32微米 針並未斷裂。 [實施例二]懸臂式探針一結構（以化學錢金屬為主結構） X 1C測„式1C為目的’考慮IC的銲塾間距採用探針長為鄕 •微米、750微米、1000微米，微米及_微米來模擬，探針 懸臂寬度方面 2G微米。細，絲IC _來支撐是不夠的， 在X十上利用化予鍍製程或電鑄製程使探針厚度增加(厚度分別為 3〇微米' 4_、5G絲、輕米及％微米），來加強支樓懸臂 的強度’如圖11與圖12⑻〜(b)。 在，-過減健的分析之下，施加轉舰針能承受到最大 應力時，紀錄探測點的位移量定及反作用力。以長度考量時，探 針越長所需求的位移量就越足夠但相對反作用力也越小，長度大 201109670 的需求 :麵微米加嶋、探針厚度大微米，較為符合 求’且其最大應力也不會超過獅本身崎伏應力、。要 程線寬越小，其物6數量將會削、、越紐及製 此製程方村喷細細咖㈣轉。用 ^需嶋長蝴_厚度，便_物^^ 着[實施例三]懸臂式探針二結構（以化學錄金屬為主結構） 以1C測41C為目的，考慮IC的銲塾間距，採用探針長為⑽ 微米、微米及300微米來模擬，探針懸臂寬度方面選取顯 米，而’光憑IC薄膜來支撐是不夠的，在設計上利用化學鑛製 程或電鑄製程使探針厚度增加(厚度分別為1〇微米、2〇微米、邓 微米及40微米），來加強支撐懸臂的強度，如圖u。 在經過模絲體的分析之下，施加位移使探針能承受到最大 鲁應力時’紀錄探測點的位移量定及反侧力。以長度考量時，探 針越長所需求的位移量就越足夠但相對反侧力也越小，長度大 於300微米寬度20微米、探針厚度大於4〇微米，較為符合規格 要求’且其最大應力也不會超過材料本身的降伏應力，如圖 14(a)〜(b) ” 1C製程線寬越小，其料16數量將會越小越 義近及Ik機出現’應用此製程方法可將每錢臂的寬度和間距任 意的調整。當寬度變窄時’只需調整其長度或滅的厚度，便很 輕易的達到量測應用端的需求。 201109670 進一步，對於上述三種實施例之探針結構可在其背面填入具 有彈性的材料如高分子材料20，增加探針耐衝擊力與強度。 [實施例四] 圖15⑻為TSMC2P4M0.35微米的製程一次所曝光的區域， 寬度A為22厘米，寬度B為11厘米，假使一次所曝光的區域可 以製作出四組探針晶>{11。圖15⑼是-組3組X 3組探針卡(依 照待測物多寡），其每一探針晶片有效量測區域為6厘卡χ 6厘米 (寬度C X寬度C) ’每一探針晶片可以先測第一區的晶粒(die)，再 位移測第2區的晶粒(依需求順序類推），如圖15⑹〜圖15(e)。假 使待測晶粒的量顺域超過6厘米χ 6厘米，此時可以將探針陣列 排至四鋪落再四她裝成為—個可量顺大區域（寬度Dx寬度 D ’12厘米X 12厘米）恤針晶片，如圖15 (f)。注意此實施例的 晶粒大小可大可小，並不限於上述所列。 [實施例五] .本發月之CMOS探針卡中，其分別在探針的固定端底部設置 壓阻材料（多晶石夕3卜為典型⑽S標準製程具有的材料層），使 探針具有力量哺機制，如圖16所示。實施舣以台積電〇 35 微米製程設計’以多砂31為壓阻材料，可以利用電阻的改變 量，進而求得所受的力量大小。_探針接觸力回饋，確實能達 到監測探針接觸的狀況。 由於力量回饋侧是用互補式金氧半㈣技術製作 ，因此對 16 201109670 於感測訊號的放大電路24，也可一併設計於探針旁，以收整合之 功效。當然力量回饋機制亦不僅限於壓阻式的感測方式，其他如 電容式、場效電晶體式等，也是熟悉此技藝者容絲之的方式。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本 發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當 可作各種之更動與潤飾，因此本發明之賴細當視後附之申請 專利範圍所界定者為準。 月 【圖式簡單說明】 優點與實施 為讓本發明之上述和其他目的、特徵、 例能更明顯易懂，所附圖式之詳細說明如下 圖1.為本發明之探針卡的爆炸視圖。 圖2.為本發明之探針卡的剖面側視圖。 φ圖3.為本發明之探針卡上的CM〇s探針晶片示意圖。 圖《為本發明之CMOS探針晶片光草佈局圖㈠。 圖5.為本發明之CM0S探針晶片光罩佈局圖㈡。 圖6.為本發明之探針卡的單根懸臂探針示意圖。 圖7.為本發明之探針卡的各種佈局方式。 圖8⑻至圖8(0為本發明之⑽探針晶片之製程步驟流程圖。 201109670 圖9(a)至圖9(b)為本發明之CM〇s探針實施例一的立體圖。 圖10 (a)至圖1〇 (b)為本發明之實施例一之垂直式探針的最大反 力值、最大位移量。 圖11為本發明之CMOS探針實施例二的立體圖。 圖12 (a)至圖12 (b)為本發明之實施例二之垂直式探針的最大反 力值、最大位移量。 圖13為本發明之CMOS探針實施例三的立體圖。 圖H (a)至圖H (b) &本發明之實施例三之垂直式探針的最大反 力值、最大位移量。 圖15(a)至圖i5(f)為本發曰月之實施例四的探針晶片佈局圖、不同 組裝方式之上視圖及量測順序圖。I picked up the figure 10 ί) ~ (b). However, as the IC process line width is smaller, the number of pads 16 is smaller, closer, and randomly appears. This process method can be used to adjust the visibility and spacing of each cantilever. When the width is narrowed, it is only necessary to adjust the length or the thickness of the clock to measure the demand of the application. For the probe, the result of the contact force and the displacement of the probe is increased by a 25 μm Z ′ when the contact force is 73.6 亳 Newton, and the displacement is about 32 μm. The needle is not broken. [Embodiment 2] Cantilever probe-structure (mainly based on chemical money metal) X 1C is measured for the purpose of formula 1C. Considering the distance between the pads of the IC, the length of the probe is 鄕•micron, 750 micron, 1000 micron. Micron and _micron to simulate, the probe cantilever width is 2G micron. Fine, silk IC _ to support is not enough, on the X ten using the pre-plating process or electroforming process to increase the thickness of the probe (thickness is 3〇 Micron '4_, 5G wire, light meter and % micron) to strengthen the strength of the cantilever of the branch' as shown in Fig. 11 and Fig. 12(8)~(b). Under the analysis of the over-reduction, the rotating needle can withstand When the maximum stress is reached, record the displacement and reaction force of the probe point. When considering the length, the longer the probe is, the more the displacement is required, but the smaller the relative reaction force, the larger the length of the 201109670: the surface micron twist, exploration The thickness of the needle is large, which is more in line with the requirements and the maximum stress will not exceed the singular stress of the lion itself. The smaller the line width, the smaller the number of the material will be cut, the more new and the process will be sprayed. Fine coffee (four) turn. Use ^ need long butterfly _ thickness, then _ matter ^^ [Embodiment 3] Cantilever probe two structure (mainly composed of chemical recording metal) For the purpose of 1C measurement of 41C, considering the soldering pitch of IC, the probe length is (10) micron, micron and 300 micron to simulate The width of the cantilever is selected in terms of the width of the cantilever, and it is not enough to support with the IC film. The thickness of the probe is increased by using a chemical or electroforming process (thickness: 1 〇 micron, 2 〇 micron, Deng micron, respectively). And 40 microns) to strengthen the strength of the supporting cantilever, as shown in Fig. u. Under the analysis of the filament body, the displacement is applied so that the probe can withstand the maximum Lu stress, and the displacement of the detection point and the opposite force are recorded. When considering the length, the longer the probe is, the more the displacement is required, but the smaller the relative side force is. The length is more than 300 micrometers and the width is 20 micrometers. The probe thickness is more than 4 micrometers, which is more in line with the specification' and the maximum stress is not. Will exceed the material's own lodging stress, as shown in Figure 14 (a) ~ (b) ” 1C process line width is smaller, the amount of material 16 will be smaller and more close to the Ik machine appears 'apply this method can be used for every money Arm width and space Adjust any meaning. When the width is narrowed, it is easy to measure the application end by simply adjusting its length or thickness. Further, for the probe structures of the above three embodiments, a resilient material such as a polymer material 20 may be filled on the back surface thereof to increase the impact resistance and strength of the probe. [Embodiment 4] Fig. 15 (8) shows the area where the TSMC2P4M 0.35 micron process is exposed once, the width A is 22 cm, and the width B is 11 cm. If one exposed area can be used to make four sets of probe crystals > {11 . Figure 15 (9) is a set of 3 sets of X 3 sets of probe cards (according to the amount of the test object), the effective measurement area of each probe wafer is 6 PCT χ 6 cm (width CX width C) 'per probe wafer The die of the first zone can be measured first, and then the grain of the second zone can be measured by displacement (as in the order of demand), as shown in Fig. 15(6) to Fig. 15(e). If the amount of the crystal to be tested is more than 6 cm χ 6 cm, the probe array can be discharged to four spreads and then she can be mounted as a large area (width Dx width D '12 cm X 12 Centimeter) needle wafer, as shown in Figure 15 (f). Note that the grain size of this embodiment can be large or small, and is not limited to the above list. [Embodiment 5] In the CMOS probe card of the present month, a piezoresistive material is provided at the bottom of the fixed end of the probe (the polycrystalline stone is a material layer of a typical (10) S standard process), so that the probe Has a power feeding mechanism, as shown in Figure 16. The implementation is based on TSMC's 35 micron process design. With the multi-sand 31 as a piezoresistive material, the amount of change in resistance can be utilized to determine the amount of force. _Probe contact force feedback can indeed reach the condition of monitoring probe contact. Since the power feedback side is fabricated by the complementary MOS technology, the amplifier circuit 24 for the sensing signal of 16 201109670 can also be designed next to the probe to integrate the effect. Of course, the power feedback mechanism is not limited to the piezoresistive sensing method. Others, such as capacitive and field-effect transistor, are also familiar with the way the craftsman fits. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The details of the patent application scope are subject to the provisions of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and examples of the present invention will become more apparent and understood. . Figure 2. A cross-sectional side view of the probe card of the present invention. φ Figure 3. Schematic diagram of the CM〇s probe wafer on the probe card of the present invention. Figure "is a layout diagram of the CMOS probe wafer light grass of the present invention (1). Figure 5 is a layout diagram of a CMOS sensor wafer mask of the present invention (2). Figure 6. Schematic illustration of a single cantilever probe of the probe card of the present invention. Figure 7. Various layouts of the probe card of the present invention. 8(8) to 8(0) are flowcharts showing the steps of the process of the (10) probe wafer of the present invention. 201109670 FIG. 9(a) to FIG. 9(b) are perspective views of the first embodiment of the CM〇s probe of the present invention. (a) to Fig. 1(b) is the maximum reaction force value and maximum displacement amount of the vertical probe of the first embodiment of the present invention. Fig. 11 is a perspective view of the second embodiment of the CMOS probe of the present invention. a) to Fig. 12(b) is the maximum reaction force value and the maximum displacement amount of the vertical probe according to the second embodiment of the present invention. Fig. 13 is a perspective view of the third embodiment of the CMOS probe of the present invention. The maximum reaction force value and the maximum displacement amount of the vertical probe of the third embodiment of the present invention are shown in Fig. 15(a) to Fig. 5(f). Probe wafer layout, top view of different assembly methods, and measurement sequence diagram.
圖16為本發明之實_五的具有力量回饋機制喊針“側 視圖。 13 J 【主要元件符號說明】 7. 鋼珠 8. 補強用界接探測器 9. 彈簧 10. 外固定蓋板 11. 探針晶片 12. 探針頭 1. 印刷電路板 2. 加強板 3. 螺絲 4. 底座環 5. 彈簧探針式界接探測器 6·内固定蓋板 201109670 13.金屬層 23.氧化矽 14.石夕 24.電路 15.矽貫穿孔(TSV) 25.支撐基材 16.銲墊 26.蝕刻後的貫穿孔 17.欲钱刻的矽貫穿孔 27.絕緣材料 18.欲蝕刻的區域 28.導電材料 19.欲鍍探針之區域 29.探針結構 20.高分子材料或光阻 30.録錫凸塊 21.薄膜層 31.多晶矽 22.純化層Figure 16 is a side view of the invention with the power feedback mechanism "Side view. 13 J [Description of the main components] 7. Steel ball 8. Reinforcement boundary detector 9. Spring 10. External fixed cover 11. Probe wafer 12. Probe head 1. Printed circuit board 2. Reinforcement plate 3. Screw 4. Base ring 5. Spring probe type interface detector 6. Internal fixed cover 201109670 13. Metal layer 23. Oxide 矽14熙夕24. Circuit 15. 矽 through-hole (TSV) 25. Support substrate 16. Pad 26. Through-hole after etching 17. 矽 through-hole 27. Insulating material 18. Area to be etched 28 Conductive material 19. Area where the probe is to be plated 29. Probe structure 20. Polymer material or photoresist 30. Tin bump 21. Thin film layer 31. Polycrystalline germanium 22. Purified layer
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