201106399 六、發明說明： 【發明所屬之技術領域】 一種使用 本發明係有關於一種電容器封装結構，尤指 表面黏著技術之電容器封裝結構。 曰 【先前技術】 電容器已廣泛地被使用於消費性家電用品 板及其周邊、電源供應器、通訊產品、及汽車等之=機 件’其主要的作用包括：滤波、旁路、整流、搞合、^疋 轉相等。是電子產品中不可缺少的元件之— 不同的材質及用途，有不同的型態。包括紹質電解電容: 鈕質電解電容、積層陶瓷電容、薄膜電容等。 &先行技術中，用於i呂電解電容器的料通常區分為正 伯與負羯’必須經過触、化成的步驟才可以用於電解 容。腐餘是指將高純度的魅於電兹液令利用電姓 除氯、水洗等-連串的製程，以增加料的表面積，才得 以大大地提高比電容。比容的提高是電解電容實現小型化 的重要技術。經過腐崎的㈣（正必須再經過化成 的處理’以在m形成氧化銘，作為電解電容的電介 質。電介質的厚度與__壓通f成―正比的線性關 係，這也是電解電容工作電壓的主要依據。至於負箱，通 常於f表面形成一 1〜3V的耐電壓層’也有不做化成處理 的負箔，不過若是將不做耐壓處理的腐蝕箔置於空氣中， 也會自然形成氧化铭。經過腐蝕、化成的鋁箔，根據設計 的規格尺寸裁切成-定的寬度，再將導針釘接於㈣上， 再以電解紙隔開經過釘接、捲繞製程形成—個圓柱體的結 構，其稱為怒子或素子。此時，怒子並不具備有電解電容 201106399 的電氣特性，必須經由將電解液完全浸潤於芯子，藉由電 解紙的吸水能力將電解液吸附其中並滲透入鋁箱的3腐蝕 結構中。將此完全浸潤的芯子裝入於底部有爆 狀容器t，於柱狀容器之開口端裝置橡膠之封口物，藉由 機械封口及封腰，形成一密閉的柱狀結構，再經由套^、 充電老化等製程而成。 g 實際上，在電解電容器的負極是藉由電解液中離子的 移動而形成一電子迴路，因此電解液的電導度 (conductivity)就直接影響電解電容器的電氣特性。因此二 ^提高電解液的電導度，以使電解電容器在高溫中仍能保 夺,電解液與料、電解紙的化學穩定性，特別是電解液盘 是電解液發展的趨勢。一般文獻中提到的 1 “解電奋态使用的電解液’特別是使用於 :二=是由水、有機溶劑、有機酸、無嫌 二特殊外、加劑依不同比例調配而成。 固態電解電容器係於電解電容器領 優異態電解電容器中，主= conver # ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (chemical ΐϊΐ 構造係諸如有一種構造，即：以隔離紙 為中介而將形成有介雷辦备儿 、、 及相對@豆化膑之％極鋁用化學轉化箔 Γ 轉化箱繞捲而成之電容器元件浸泡有 密‘之ϊ::?納在鋁製盒體或合成樹脂製盒體等予以 =之=。上述固態電解電容器係小型 口各、聚嗟吩、聚ί胺；:：又，電解質係使用諸如聚口比 專但為了降低ESR(等效串聯電阻） 201106399 之目的，因此主要使用電阻係數低之聚乙撐基二氧噻吩。 士述固態電解電容器小型且具有大電容，除了 ESR低外j 還具有易於晶片化且適用表面安裝等特性，因此便成為電 子機器之小型化、高功能化、低成本化時不可或缺者。 近年來，伴隨著電子機器的數位化，電解電容器也需 要大谷量化、小型化及在高頻率區域中使阻抗低下化，而 固體電解電容器具優異頻率特性的特點使其在電解電容 器中備受注目。又，固體電解電容器尹，有捲繞型固體電 解電容器、疊層型固體電解電容器等。習知疊層型固體電 解電容器設有具有閥作用之鋁箔，且設有由藉由化學聚合 法、電解聚合法等形成並由聚吼p各構成之電解質層。但 是，由聚吡咯構成之電解質層具有無法均勻地形成在鋁箔 表面上且谷易損壞的缺點。所以，前述叠層型固體電解電 各器具有漏電流增加、短路等問題。 因此’本發明人有感習知技術仍有可改善的空間，且 依據多年來從事此方面之相關經驗，悉心觀察且研究之， 並配合學理之運用，而提出一種設計合理且有效改善習知 缺失之本發明。 【發明内容】 本發明所要解決的技術問題，在於提供一種使用表面 黏著技術之電容器封裝結構，其主要目的在於： 1、 可達成大面積、大容量、低背化（LowProfile)、 低成本之使用表面黏著技術之電容器封裝結構。 2、 可大幅減低漏電流（Leakage Current，LC )及短 路問題。 201106399 3、 可降低焊接困難度，並大幅降低相同容量電容器 的等效串聯電阻（Equivalent Series Resistance，ESR)。 4、 本發明透過基板單元的使用，而不需另外設置導 線架。 、 為了解決上述技術問題’根據本發明之其中一種方 案’提供一種使用表面黏著技術之電容器封裝結構，其包 括ί一基板單元、一電容模組及一封裝單元Q其中，該基 板單元係具有一絕緣本體、至少兩個彼此分離且成形於該 絕緣本體上表面之第一上層導電層及第二上層導電層、至 =兩個彼此分離且成形於該絕緣本體下表面之第一曰下層 導電層及第二下層導電層、至少兩個穿透該絕緣本體之^ 孔、及至少兩個分別成形於上述至少兩個穿孔内之中間導 ，層並且其中-中間導電層係電性連接於該第—上 連ί二::ί 層ΐ電層之間，另外一中間導電層係電性 容模層導電層及該第二下層導電層之間。該電 ，係具有複數個設置於該絕緣本體上之 二;tr極及負極係分別電性接觸‘^ 緣本體上並且覆蓋該電容模組。 u於義 ^了解決上述技術問題’根據本發明之 面，啸器封裝結構，= 板單元係具;：絕緣::早二-封裝單元。其中，該基 絕緣本體上表面之第一上層導電：:且成:於該 Ϊ兩個彼此分離且成形於該絕緣本體下—表面之第電層、； 下層導電層、至少兩個穿透該絕緣本體之穿 201106399 =及至少兩個分別成形於上述至少兩個穿孔内之 電層’亚且其中-中間導電層係電性連接於該第—上 =及該第:下層導電層之間，另外—中間導電層係^性 ―於=第二上層導電層及該第二下層導電層之間。、該電 :早兀的正極及負極係分別電性接觸於該第一上 】及=，上層導電層。該封I單元餘置於該絕、i本體 上亚且覆盍該電容模組。 之技ί 了1\進Γ步瞭解本發明為達成預定目的所採取 ^支術、手&及功效’請參_下㈣本發明之詳細 f附圖，相信本發明之目的、特徵與特點，當可由此得一 味入且具體之瞭解，然而所附圖式僅提供參考與說， 並非用來對本發明加以限制者。 【實施方式】 請參閱第-A圖至第—C圖所示，本發明第—實施例 係提供一種使用表面黏著技術（SMT)之 其包括 > 基板單元13、—電容模組= 單元3 a。 、 其中，該基板單元1 a係具有一絕緣本體i 〇 a、至 少兩個彼此分離且成形於該絕緣本體1 〇 a上表面之第 ^上層導電層1 1 a及第二上層導電層丄2 a、至少兩個 彼此分離且成形於該絕緣本體i 〇 a下表面之第一下声 導電層1 3 a及第二下層導電層i 4 a、至少兩個穿透‘ 絕緣本體1 〇 a之穿孔1 5 a (例如半穿孔）、及至少兩 個分別成形於上述至少兩個穿孔丄5 a内之中間導電層 1 6 a，並且其中一中間導電層1 6 a係電性連接於該第 一上層導電層1 1 a及該第一下層導電層丄3 a之間了另 201106399 :卜：中間導電層i 6 a係電性連接於該 123及該第二下層導電層“a之間。再者層 放型開孔，並且上述至少兩個中 = 據不同的設計需求， 5a内。曰6 a亦可分別填充於上述至少兩個穿孔1 0 a H電^容1組2 3係具有一設置於該絕緣本體1 n 9及、€合早702 〇 a的正極2 0 1 a及負極2 匕性接觸於該第一上層導電層1 1 3及該 f 層冷電層1 2 a。另外，第-實施例更進一步包 板單元la與該電容模組2a之間之^ ,〇!, D^ — c圖所示），以避免外界的水氣透過基 电2 a的σ ^傳遞至㈣容模組2 a，而影響到該電容模 組Z a的品質。 技ΐΪϋ封1^單元3 a係設置於該絕緣本體1 〇 a上 二殼二3 St模組2 3。此外，該封裝單元3 3係具有 一 Λ!\及一位於該殼體3〇a内之固定膠體31 a ’ 5亥電谷模組2 a係被該固定膠體3 1 a所包覆。依據 =同0J設計需求’該殼體3 0 a係可為金屬或塑膠，並且 ^固定膠體3 1 a係可為㈣脂（仙議e)或環氧樹脂 (epoxy) ° π ί 凊參閱第一 D圖所示，本發明可同時製作多數 =谷&封|結構。該等電容器封裝結構係由複數個V型 日5 3所區分’當延著該等V型槽5 a而切割基板時，則 201106399 可形成複數個單一的電容器封裝結構，並且每一個電容器 封裝結構係包括：一基板單元丄a、複數個電容模組2 °a 及一封裝單元3 a。 請參閱第二圖所示，本發明第二實施例係提供一種使 用表面黏著技術（SMT)之電容器封裝結構，其包括：— 基板單元1 b、一電容模組2 b及一封裝單元3 b。其 中，第二實施例與第一實施例最大的差別在於：在第二^ 施例令，該電容模組2 b係具有複數個設置於該絕緣本體 10b上之電容單元2〇b，每一個電容單元2〇b的正 極2 01b及負極202b係分別電性接觸於該第一上 電層1 1 b及該第二上層導電層1 2b，並且該等電 容單元2 0 b係彼此並列在上述至少一第一上層導電層 1 1 b及上述至少一第二上層導電層i 2 b之間曰。 日 請參閱第三圖所示’本發明第三實施例係提供一種使 用表面黏著技術（SMT)之電容器封裝結構，其包括：一 基板單元1 c、一電容模組2 c及一封裝單元'3 c。其 中，第三實施例與第一實施例最大的差別在於：在第三^ 施例中，該電容模組2 c係具有複數個設置於 上之電容單Μ"，每—個電容單 極2 0 1 c及負極2 〇 2 c係分別電性接觸於該第一上 ^電層1 1 c及該第二上層導電層丄2 c，並且該等電 容單元2 0 c係彼此堆疊在上述至少一第一上層導電層 1 1 c及上述至少一第二上層導電層i 2 c之間。 θ ^ 由上述第一貫施例及第三實施例可知，該等電容單元 ，彼此可選擇性地（selectably)並列或堆疊在上述至少一 第一上層導電層及上述至少一第二上層導電層之間。換言 201106399 之，，等電容單元係可彼此並列（如第二圖所示）或叠堆 (如第三圖所示）在上述至少—第—上層導電層及上=至 =第二上層導電層之間，或者該等電容單元亦可同時彼 j列及疊堆在上述至少—第—上層導電層及上述至少 第一上層導電層之間（例如先堆疊後再並列）。 請參閱第四圖所示，本發明第四實施例係提供一種使 表面黏者技術（SMT)之電容器封褒結構，|包括一 基板單元1 d、一電容模組2行及一封 亓 二第二實施例與第-實施例最大的差別;於心實施 例的至少兩個穿孔1 5 d係為封閉型開孔。 請參閱第五A圖及第五b圖所 係提供—種使用表面黏著技術（=)五實施例 構，其包括:-基板單元/二二:^容器封叢結 3 e。其中，第五實施例與:二:裴 有-環形凹槽…，上述至少L第一1 e、上述至少一第二上層導 上層V電層1 1 孔1 5 e的位置皆被該環形曰6及上述至少兩個穿 裝單元3 e的底端係設置於該;二繞内並且該封 第五實施例更進—包括：_ 日1 7 e心另外’ 防水層5 e係設置於該環形 〜層5:，其中該環形 形凹槽17e與該封裴單元 内並且位於該環 凹槽1 7 e的使用，以使得e之^。因此’透過該環形 於該絕緣本體1 〇 e上 我旱兀3 e可穩固地卡固 用，以避免外界的水氣從該封^該，形防水層5 e的使 e之間的接合處跑進該封^早兀3 e與該基板單元工 ^早兀3 e内而影響到該電容 201106399 單元2 e的品質。 請參閱第六圖所示，本發明第六實施例係提供一種使 用表面黏著技術（SMT)之電容器封裝結構，i · ，單元η、-電容模組。及_封裝單 :，第六實施例與第五實施例最大的差別在於：在第六每 施例中，該環形防水層5 f係設置於該絕緣本體丄〇ϋ 形凹槽17f與該封裝單元3f之間（或該 、、巴、、彖本體1 〇 f與該封裝單元3 f之間）的外部接合處 如’一以使得第六實施例同樣能夠避免外界的水氣從該封裝 早凡3 f與該基板單元i丨之間的接合處跑進該封 兀3 ί内而影響到該電容單元2 f的品質。 、早 請參閱第七圖所示，本發明第七實施例係提供一種使 表面黏著技術（SMT)之電容器封裝結構，其包括.一 f板單元1 g、一電容模組2g及—封裝單元、3卜1 :’第七實施例與上述其它實施例最大的差別在於 ^ 貫把例的電谷模組2 g係為一捲繞型的電容單元 「因此，該電容單元20g的正極2〇lg及負極2〇 _ g係分別電性接觸於該第一上層導電層1 及 導電層1 2 g，進而使得該電容單元2 0 g的i極 及負極20 2 g係分別電性連接於該第声 導電層1 3 g及該第二下層導電層i 4 g。 曰 請參，第八圖所示’本發明第八實施例係提供一種使 表面黏著技術（SMT)之電容器封裝結構，i ^單元lh、-電容模組211及—封裝單元、3'括。·: ，第八實施例與第七實施例最大的差別在於：在 施例令，該電容單元2〇h的正極2〇1 h及負極2〇2 12 201106399 h係分別穿過兩個穿孔1 5 h而分別電性接觸於兩個 間導電層1 6 h，進而使得該電容單元2 〇 h的正極2 〇 1 h及負極2 〇 2 h係分別電性連接於該第一下層 層13h及該第二下層導電層i4h。 θ 請參閱第九圖所示，本發明第九實施例係提供一種使 用表面黏著技術（SMT)之電容器封裝結構，其包括：— 基板單元1 i、一電容模組2 i及一封裝單元3 i。其 中，第九實施例與第八實施例最大的差別在於：在第九^ 施例中’該絲模組2 i似有複數個設置於該絕緣本體 1 Ο 1上之電容單元20 i，每一個電容單元2〇丨的正 極2 0 1 i及負極2 〇 2 i係分別電性接觸於該第一上 電層1 1 i及該第二上層導電層i 2 i，並且該等電 容單元2 0 i係彼此並列在上述至少一第一上層導電層 1 1 i及上述至少一第二上層導電層丄2 i之間。 曰 上述實施例中，第一至第六實施例之電容模組，可採 用下列敘述之電容模組之任何一種，完成所需之固離 容。 ’ “請參閱第十圖所示，本發明第一種電容模組具有複數 =電容單元1 j，並且每兩個電容單元i j之間係塗佈有 電層S j母一個電谷單元1 j係依序由一負箱（負極） 土 0 0 j、一吸附有導電高分子之隔離紙丄i j、一正 箔（正極U 2 j、一吸附有導電高分子之隔離紙丄丄工j 及負箔（負極）1 〇 1 j堆疊而成，每一個正羯（正極）1 2 j的表面皆有氧化物層（圖中未標示），以做為介電層 來產生絕緣效果，每一個電容單元1 j之兩個隔離紙（1 1 〇 j、1 1 1 j )係一體成型而形成一呈11字型之隔離 13 201106399 Ί11j，以使得每-個電容單元工j之正箱（正極) 二丄白了分係_隔離紙層u j所包覆，並且每一 早兀1 J之兩個負落（負極）（1 00 j、i i J)係一體成型而形成一呈11字型之負箔声 得該隔離紙層11j被該負箱層10;所；覆使 再者，該等電容單元1彳# # @ τ β 1 數個谭接點P j而電性連接*二=2 j係透過複 該等負箱（“οΓΊ〜、起：亥等電容單元1 j之 並且該等正笛12j與該等負馆（100j、1 別設絕A °P另外，該電容模組係具有複數個分 成形在每-個相對應;^ 的方式 之口Ρ分外表面的上下兩 面及兩相反側邊），以限制該等負箔（工 紙（110j、⑴j)的長度，並做 '·、、母個電谷單701 j之正極與負極的絕緣線。 盤伽第十一圖所示，本發明第二種電容模組具有複 且每兩個電容單元1k之間係塗佈 有導電層S k。母-個電容單元i k#、依序由 極H〇〇k、-吸附有導電高分子之隔離紙U ^負 兩個負箔（1 0 0 k、1 0 1 k)之間，並且每 7=正極i12 k、—吸附有導電高分子之隔離紙1 一負泊（負極）1 0 i匕堆疊而成，每一個正箔 (正極）1 2 k的表面皆有氧化物層（圖中未標示），以做 為介電層來產生絕緣效果。另外，該電容模組係具有複數 個導電2 5 k ’其分別電性連接於每一個電容單元工u 個電容 201106399 單元1 k之兩個負箔（1〇〇k、 端長度係大於每一個電容單Si k :二目， 端長度’以避免該等正落12k朗末 數個==單元1 k該等‘複 數個坏接點Pk而電性連接在一起灵 該等負箔（1 0 0 k、1 0 i k )係^ “早兀1匕之 而電性連接在一起，並且該等導電層5 k ◦m…係彼此絕緣 =分:設严於該等…“的==; 且圍、兀成一圈之絕緣層4k(亦即每— 圍繞的方式成形在每-個相對應正fl i 2^^外= ，的3兩面及兩相反側邊)，以n ⑴及該等隔離紙（110k、m 、;度，並做為每-個電容單元Ik之正極與負極二 電4參^十二_示，本發明第三種模組具有一 ^早Γ’該電容單元lm係具純數個㈣（負極） 伽=、/ 吸附有導電高分子之隔離紙1 lm及複數 個正油（正極）丄2m彼此交替堆疊在一起，並 每一㈣(正極)1〜及每- :負/白（負極）1 〇m之間’每一値正箱（正201106399 VI. Description of the invention: [Technical field to which the invention pertains] One use The present invention relates to a capacitor package structure, particularly a capacitor package structure of a surface adhesion technique.曰[Prior Art] Capacitors have been widely used in consumer appliances and their peripherals, power supplies, communication products, and automobiles, etc. Their main functions include: filtering, bypassing, rectification, and Combine, ^ turn to be equal. It is an indispensable component in electronic products - different materials and uses, and different types. Including the electrolytic capacitor: button electrolytic capacitor, laminated ceramic capacitor, film capacitor and so on. In the prior art, the material used for the i-Lu electrolytic capacitor is usually divided into positive and negative 羯, which must be touched and formed to be used for electrolysis. The rot is to increase the specific capacitance by increasing the surface area of the material by using a series of processes such as dechlorination, water washing, etc. to increase the surface area of the high-purity enchantment. The increase in specific volume is an important technology for miniaturization of electrolytic capacitors. After the rot-akizaki (four) (the process must be processed again) to form the oxidation in m, as the dielectric of the electrolytic capacitor. The thickness of the dielectric is proportional to the __pressure-f, which is also the operating voltage of the electrolytic capacitor. Mainly. As for the negative box, a voltage layer of 1~3V is usually formed on the surface of f. There is also a negative foil which is not processed, but if the corrosion foil which is not subjected to pressure treatment is placed in the air, it will naturally form. Oxidation Ming. After corrosion and formation of aluminum foil, according to the size of the design cut to a certain width, then the needle is attached to (4), and then separated by electrolysis paper through the nailing, winding process to form a cylinder The structure of the body, which is called the anger or the element. At this time, the anger does not have the electrical characteristics of the electrolytic capacitor 201106399. It must be completely impregnated into the core by the electrolyte, and the electrolyte is adsorbed by the water absorption capacity of the electrolytic paper. It penetrates into the 3 corroded structure of the aluminum box. The fully infiltrated core is placed in the bottom of the explosion-shaped container t, and the rubber seal is placed at the open end of the column container by mechanical sealing. And sealing the waist to form a closed columnar structure, and then through the process of charging, charging and aging, etc. g In fact, the negative electrode of the electrolytic capacitor forms an electronic circuit by the movement of ions in the electrolyte, so electrolysis The conductivity of the liquid directly affects the electrical characteristics of the electrolytic capacitor. Therefore, the electrical conductivity of the electrolyte is increased so that the electrolytic capacitor can still be retained at high temperatures, and the chemical stability of the electrolyte and the material, electrolytic paper, In particular, the electrolyte disk is the development trend of the electrolyte. Generally mentioned in the literature 1 "The electrolyte used in the electrolysis" is especially used in: 2 = is composed of water, organic solvents, organic acids, no special two The external and additive are prepared according to different proportions. The solid electrolytic capacitor is in the electrolytic capacitor of the electrolytic capacitor, the main = conver # ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (chemical ΐϊΐ structural system such as a structure, That is to say, the capacitor element formed by the chemical conversion foil Γ conversion box formed by the medium-definition preparation, and the chemical conversion foil of the % aluminum with respect to @豆化膑 is immersed in the insulation paper. ϊ::?In the case of an aluminum case or a synthetic resin case, etc. = The above-mentioned solid electrolytic capacitors are small mouths, polybenzazole, poly-amine; Specifically, in order to reduce the ESR (equivalent series resistance) 201106399, it is mainly used to use polyethylene dioxythiophene with low resistivity. The solid electrolytic capacitor is small and has a large capacitance, and it has an easy chip in addition to the low ESR. In addition, it is indispensable for miniaturization, high functionality, and low cost of electronic equipment. In recent years, with the digitization of electronic equipment, electrolytic capacitors need to be quantified and miniaturized. And the impedance is lowered in the high frequency region, and the characteristics of the excellent electrolytic characteristics of the solid electrolytic capacitor make it attract attention in electrolytic capacitors. Further, the solid electrolytic capacitors include a wound solid electrolytic capacitor and a laminated solid electrolytic capacitor. The conventional laminated solid electrolytic capacitor is provided with an aluminum foil having a valve function, and is provided with an electrolyte layer formed of a chemical polymerization method, an electrolytic polymerization method, or the like and composed of each of the polyfluorenes. However, the electrolyte layer composed of polypyrrole has a drawback that it cannot be uniformly formed on the surface of the aluminum foil and the valley is easily damaged. Therefore, the above-mentioned laminated solid electrolytic cells have problems such as an increase in leakage current and a short circuit. Therefore, the inventor has a space for improvement in the perceived technology, and based on years of experience in this field, carefully observed and studied, and with the use of academics, proposes a reasonable design and effective improvement of the knowledge. The invention is missing. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a capacitor package structure using surface adhesion technology, the main purpose of which is to: 1. Can achieve large area, large capacity, low profile (LowProfile), low cost use Capacitor package structure for surface mount technology. 2. It can greatly reduce Leakage Current (LC) and short circuit problems. 201106399 3. It can reduce the difficulty of soldering and greatly reduce the Equivalent Series Resistance (ESR) of capacitors of the same capacity. 4. The present invention transmits through the use of the substrate unit without separately providing a wire guide. In order to solve the above technical problem, "one of the solutions according to the present invention" provides a capacitor package structure using a surface mount technology, which comprises a substrate unit, a capacitor module and a package unit Q, wherein the substrate unit has a An insulating body, at least two first upper conductive layers and a second upper conductive layer separated from each other and formed on an upper surface of the insulating body, and two first underlying conductive layers separated from each other and formed on a lower surface of the insulating body And a second lower conductive layer, at least two holes penetrating the insulating body, and at least two intermediate conductive layers respectively formed in the at least two through holes, and wherein the intermediate conductive layer is electrically connected to the first - 上 ί 2:: ί Between the layers of the electrical layer, another intermediate conductive layer is between the electrically conductive layer conductive layer and the second lower conductive layer. The electric system has a plurality of two disposed on the insulative housing; the tr pole and the negative pole are respectively electrically contacted to the body of the edge and cover the capacitor module. u Yuyi ^ solves the above technical problem'. According to the invention, the whistle package structure, = plate unit tie;: insulation:: early two-package unit. Wherein, the first upper layer of the upper surface of the base insulating body is electrically conductive: and: the second electrical layer separated from each other and formed under the insulating body, the lower conductive layer, at least two penetrates the The insulating body is worn by 201106399 = and at least two electrical layers are respectively formed in the at least two perforations, and wherein the intermediate conductive layer is electrically connected between the first upper layer and the first lower conductive layer, In addition, the intermediate conductive layer is between the second upper conductive layer and the second lower conductive layer. The electricity: the positive electrode and the negative electrode of the early ring are electrically contacted with the first upper layer and the upper conductive layer, respectively. The I unit is placed on the main body of the i-substrate and covers the capacitor module. The technique of the present invention is to understand the purpose, characteristics and features of the present invention. It is to be understood that the invention is not limited by the scope of the invention. [Embodiment] Referring to Figures -A through -C, the first embodiment of the present invention provides a surface adhesion technology (SMT) including > substrate unit 13, - capacitor module = unit 3 a. The substrate unit 1a has an insulative body i 〇a, at least two upper conductive layers 11 a and second upper conductive layers 分离 2 separated from each other and formed on the upper surface of the insulating body 1 〇a a, at least two first lower acoustic conductive layers 13 a and second lower conductive layers i 4 a separated from each other and formed on the lower surface of the insulating body i 〇a, at least two penetrating 'insulating bodies 1 〇 a a perforation 15 a (eg, a semi-perforated), and at least two intermediate conductive layers 16 a formed respectively in the at least two perforated turns 5 a, and wherein an intermediate conductive layer 16 6 is electrically connected to the first An upper conductive layer 11 a and the first lower conductive layer 丄 3 a are separated by another 201106399: the intermediate conductive layer i 6 a is electrically connected between the 123 and the second lower conductive layer “a” In addition, the layer-opening apertures, and at least two of the above = according to different design requirements, 5a. 曰6 a can also be filled in the above at least two perforations 1 0 a H electric capacity 1 group 2 3 series The positive electrode 2 0 1 a and the negative electrode 2 disposed on the insulating body 1 n 9 and the early 702 〇a are in contact with the first An upper conductive layer 1 1 3 and the f-layer cold current layer 12 2 a. In addition, the first embodiment further comprises a pattern between the cladding unit 1a and the capacitor module 2a, 〇!, D^-c In order to prevent the external water vapor from passing through the σ ^ of the base power 2 a to the (4) capacitive module 2 a, which affects the quality of the capacitive module Z a. The technical seal 1 ^ unit 3 a is set in the The insulative housing 1 〇a is a two-shell two 3 St module 2 3. In addition, the encapsulation unit 3 3 has a cymbal!\ and a fixed colloid 31 a' 5 in the housing 3〇a Group 2 a is covered by the fixed colloid 3 1 a. According to the design requirements of the same 0J, the shell 30 can be metal or plastic, and the fixed colloid 3 1 a can be (four) fat e) or epoxy (epoxy) ° π ί 凊 Referring to the first D figure, the present invention can simultaneously produce a majority = valley & seal | structure of the capacitor package is composed of a plurality of V-type days Differentiating 'When the substrate is cut by the V-grooves 5 a, 201106399 can form a plurality of single capacitor package structures, and each capacitor package structure includes: a substrate unit 丄a a plurality of capacitor modules 2 °a and a package unit 3 a. Referring to the second figure, a second embodiment of the present invention provides a capacitor package structure using surface mount technology (SMT), which includes: - a substrate The unit 1 b, a capacitor module 2 b and a package unit 3 b. The greatest difference between the second embodiment and the first embodiment is that, in the second embodiment, the capacitor module 2 b has a plurality The capacitor unit 2〇b disposed on the insulative housing 10b, the positive poles 201b and the cathodes 202b of each of the capacitor units 2〇b are electrically connected to the first power-on layer 1 1 b and the second upper layer respectively. The layer 1 2b, and the capacitor units 20b are juxtaposed between the at least one first upper conductive layer 11b and the at least one second upper conductive layer i2b. Referring to the third figure, a third embodiment of the present invention provides a capacitor package structure using surface mount technology (SMT), which includes: a substrate unit 1 c, a capacitor module 2 c and a package unit 3 c. The maximum difference between the third embodiment and the first embodiment is that, in the third embodiment, the capacitor module 2 c has a plurality of capacitors arranged on the upper side, each capacitor monopole 2 0 1 c and the negative electrode 2 〇 2 c are electrically connected to the first upper electrical layer 1 1 c and the second upper conductive layer 丄 2 c, respectively, and the capacitive units 20 c are stacked on each other at least A first upper conductive layer 1 1 c and the at least one second upper conductive layer i 2 c. θ ^ According to the first embodiment and the third embodiment, the capacitor units are selectively selectably juxtaposed or stacked on the at least one first upper conductive layer and the at least one second upper conductive layer. between. In other words, in 201106399, the equal capacitance units can be juxtaposed to each other (as shown in the second figure) or stacked (as shown in the third figure) in the at least-first-upper conductive layer and the upper=to=second upper conductive layer. Between these, or the capacitor units may be stacked and stacked between the at least first-first upper conductive layer and the at least first upper conductive layer (for example, stacked first and then juxtaposed). Referring to the fourth embodiment, a fourth embodiment of the present invention provides a capacitor sealing structure for surface adhesion technology (SMT), including a substrate unit 1 d, a capacitor module 2 row, and a second layer. The greatest difference between the second embodiment and the first embodiment is that the at least two perforations 15 5 of the embodiment of the heart are closed openings. Please refer to Figures 5A and 5B for a five-part embodiment using surface adhesion technology (=), which includes: - substrate unit / 22: container seal 3 e. Wherein, the fifth embodiment and the second: the annular groove ..., the at least L first 1 e, the at least one second upper layer of the upper layer V electrical layer 1 1 hole 1 5 e are all the ring 曰6 and the bottom end of the at least two wearing units 3 e are disposed in the two windings and the fifth embodiment is further advanced - including: _ day 1 7 e heart and another 'waterproof layer 5 e is disposed in the Ring ~ layer 5:, wherein the annular groove 17e is used in the sealing unit and is located in the ring groove 17 e to make e. Therefore, through the ring on the insulative body 1 〇e, the mite 3 e can be firmly secured to avoid the external moisture from the seal, the joint between the e-shaped waterproof layer 5 e and e Running into the seal ^ early 兀 3 e and the substrate unit ^ early 兀 3 e affect the quality of the capacitor 201106399 unit 2 e. Referring to the sixth embodiment, a sixth embodiment of the present invention provides a capacitor package structure using surface mount technology (SMT), i. , a unit η, a capacitor module. And the package list: the greatest difference between the sixth embodiment and the fifth embodiment is that, in the sixth embodiment, the annular waterproof layer 5f is disposed on the insulating body 凹槽-shaped recess 17f and the package. The external joint between the units 3f (or between the body, the bar, the body 1 〇f and the package unit 3 f) is such that the sixth embodiment can also avoid the external moisture from the package. The junction between the 3f and the substrate unit i丨 runs into the package 3 ί to affect the quality of the capacitor unit 2 f. As shown in the seventh figure, the seventh embodiment of the present invention provides a surface mount technology (SMT) capacitor package structure including a f-plate unit 1 g, a capacitor module 2g, and a package unit. 3b1: The biggest difference between the seventh embodiment and the other embodiments described above is that the electric valley module 2g of the example is a wound capacitor unit. Therefore, the positive pole of the capacitor unit 20g is Lg and the negative electrode 2〇_g are electrically connected to the first upper conductive layer 1 and the conductive layer 12 g, respectively, so that the i-pole and the negative electrode 20 2 g of the capacitor unit 20 g are electrically connected to the The first acoustic layer 1 3 g and the second lower conductive layer i 4 g. As shown in the eighth figure, the eighth embodiment of the present invention provides a surface mount technology (SMT) capacitor package structure, i ^ unit lh, -capacitor module 211 and - package unit, 3'..: The biggest difference between the eighth embodiment and the seventh embodiment is that, in the embodiment, the positive pole of the capacitor unit 2〇h〇 1 h and negative electrode 2〇2 12 201106399 h are respectively passed through two perforations for 15 h and respectively electrically contacted between two The electrical layer is 16 h, and the positive electrode 2 〇 1 h and the negative electrode 2 〇 2 h of the capacitor unit 2 〇h are electrically connected to the first lower layer 13h and the second lower conductive layer i4h, respectively. Referring to the ninth embodiment, a ninth embodiment of the present invention provides a capacitor package structure using a surface mount technology (SMT), comprising: a substrate unit 1 i, a capacitor module 2 i and a package unit 3 i. The maximum difference between the ninth embodiment and the eighth embodiment is that, in the ninth embodiment, the wire module 2 i seems to have a plurality of capacitor units 20 i disposed on the insulative housing 1 , 1 . A positive electrode 2 0 1 i and a negative electrode 2 〇 2 i of a capacitor unit 2 are electrically connected to the first power-on layer 1 1 i and the second upper conductive layer i 2 i, respectively, and the capacitor units 2 0 i is juxtaposed between the at least one first upper conductive layer 11 i and the at least one second upper conductive layer 丄 2 i. In the above embodiments, the capacitor modules of the first to sixth embodiments, Use any of the capacitor modules described below to achieve the required solid-state capacity. ' As shown in the tenth figure, the first capacitor module of the present invention has a complex number=capacitor unit 1 j, and each of the two capacitor units ij is coated with an electric layer S j and one electric valley unit 1 j is sequentially From a negative box (negative electrode) soil 0 0 j, an isolating paper 丄ij with a conductive polymer adsorbed, a positive foil (positive electrode U 2 j, a separator paper with a conductive polymer adsorbed j and a negative foil ( The negative electrode) 1 〇1 j is stacked, and each surface of the positive (positive) 1 2 j has an oxide layer (not shown) to serve as a dielectric layer to produce an insulating effect, and each capacitor unit 1 The two isolating papers of j (1 1 〇j, 1 1 1 j ) are integrally formed to form a 11-shaped isolation 13 201106399 Ί11j, so that each positive capacitor box (positive) The white separation _ is separated by the paper layer uj, and each of the two negative (negative) (1 00 j, ii J) of the early 1 J is integrally formed to form a negative-shaped foil of 11-shape. The isolating paper layer 11j is covered by the negative tank layer 10; and the capacitor unit 1 彳# # @ τ β 1 is connected to several tan junctions P j and electrically connected * 2 = 2 j series Through the recovery of the negative box ("οΓΊ~, 起: Hai and other capacitor units 1 j and the such flute 12j and the negative hall (100j, 1 do not set A °P, in addition, the capacitor module has a complex number The sub-sections are formed in each of the corresponding ones; the manner of the ^ is the upper and lower sides of the outer surface and the opposite sides) to limit the length of the negative foil (work paper (110j, (1) j), and do '· , the mother wire of the electric grid single 701 j of the positive and negative insulated wire. As shown in the eleventh figure of the disc, the second capacitor module of the present invention has a complex and a conductive layer S k is coated between each of the two capacitor units 1k. The mother-capacitor unit ik#, sequentially by the pole H〇〇k, - isolating the conductive paper U ^ negative between the two negative foils (1 0 0 k, 1 0 1 k), and every 7 = positive i12 k, - separator paper with adsorbed conductive polymer 1 - a negative (negative) 1 0 i 匕 stacked, each positive foil (positive) 1 2 k surface has an oxide layer (not shown) Marked) as a dielectric layer to create an insulating effect. In addition, the capacitor module has a plurality of conductive 2 5 k 's which are respectively electrically connected to each of the capacitor unit u capacitors 201106399 unit 1 k of two negative foils (1〇〇k, the end length is greater than each Capacitor single Si k : dim, end length 'to avoid the number of such a positive 12k suffix == unit 1 k these 'plural number of bad junctions Pk and electrically connected together such a negative foil (1 0 0 k, 1 0 ik ) system ^ "early and electrically connected together, and the conductive layers 5 k ◦ m ... are insulated from each other = points: set stricter than the ..." ==; The insulating layer 4k that surrounds and turns into a circle (that is, each of the surrounding sides is formed in each of the corresponding positive fl i 2^^ outside =, 3 sides and opposite sides), with n (1) and the isolation Paper (110k, m, ; degree, and as the positive and negative poles of each capacitor unit Ik), the third module of the present invention has a ^1" With a few (4) (negative) gamma =, / isolating paper with conductive polymer 1 lm and a plurality of positive oil (positive) 丄 2m alternately stacked together, and each (four) (positive) 1 ~ and each - : Negative / white (negative) 1 〇 m between each 値 positive box (positive
;:皆有氧化物層（圖中未標示)，以做為介電層來產L 透過複數個焊接點pm而電 、 一起，该等負箔1 〇 m係透過一導電層5 m而雷 '生連接在-起，最底端之負落 ^ 銀膠或銀膏)而電性連於一基板，並且該等正導 15 201106399 "亥等負1 〇 rn係彼此絕緣。再者，該電容模組係具有複 數個分別設置於該等正! 2㈣部分外表面上並且圍 ⑽成H緣層4 m(亦即每—個絕緣層4 以圍繞 的方式成形在每一個相對應正箔i 2m之部分外表面的 上下兩面及兩相反侧邊），以限制該等 隔離紙llm的長度，並做為每一個電容單元 〃負極的絕緣線。另外’該導電層5 m係電性連接於該等 二0m之末端’並且每一個負箱工〇m的末端長度係 大於母一個正箱1 2m的末端長度，以避免該等正猪i 2 m接觸到該導電層5 m。 、了，閱第十二圖所示，本發明第四種電容模組係包 ==元”，並且每兩個電容單元ln之間 于1怖有導電層S η，例如：銀膠或銀膏。 (逢^中—Ϊ —個電容單元1 η係依序由—碳膠1 0 η 極)、°一道:導電高分子1 1 Ω、一閥金屬箔片1 2 η(正 導,尚分子iiη及一碳膠丄〇η(負極）堆疊 母Τ個閥金屬f“12n的表面皆有氧化物層（圖 個導；；C電層來產生絕緣效果，其中上述兩 面，物層上。另外，此電容模組更屬進:片== 個導電層5 n，其 乂匕括‘歿數 該等碳膠10n之；連接於母一個電容單元h之 再者，該等電容單元工n之該等間金屬 電過複數個焊接點p n而電性連接在一起，該等 而電性連接：之：4碳膠1 〇 η係透過該等導電層5 η 連接在一起’並且該等閥金屬箱片1 2讀該等碳 16 201106399 膠1 〇 η係彼此絕緣。另外，此電容模組更進— . 複數個分別設置於該等闕金屬箱片i 2 η的部分 ί並二圍繞成一圈之絕緣層4 η(亦即每-個絕緣層In '、以圍繞的方式成形在每—個相對應間金屬荡片 外表面的上下兩面及兩相反側邊)，以限制該等 .以了等導電高分子11η的長度，並做為每2 電谷，兀1 η之正極與負極的絕緣線。 請參閱第十四圖所示’本發明第 C元1Ρ。其中，每-個 閥金屬落片12ρ(正極)、一導二lp、-膠ι〇ρ(負極）堆疊而成，每！二 物層(圖中未標示)，以做== 、、邑、，彖效果，其中上述兩個導電高分子 : 金屬鶴片1 2 P的表面之氧化物層上1 =形於該間 之間係透過碳膠1Gp而電性堆疊在母二個電二單 此電容模組更進一步包括：複數個導電層 盆^卜， 性連接於每一個電容單开 刀別電 再者，該等之間。 係透過複數個焊接點p p而電性連ί Ξίί二LP之該等碳膠1 °透過該等導電 膠ίο P係彼此絕緣。另外，此電與該料 複數個分別設置於該等閥金屬箔片 步包括. 土並且圍繞成-圈之絕緣層4 p(亦即每二面 係以圍繞的方式成形在每-個相對應閥金 17 201106399 之邛分外表面的上下兩面及兩相反側邊）w 膠ι〇Ρ及該等導電高分子上，，==等碳 電容單元“之正極與負極的絕緣線 為母-個 態樣另外，上述五種堆疊型電容係可採用下列不同的實施 各!t閱第十五圖所示（一正極引出與一負極引出）， 母-個電容單^之正η 2係具有—向 並且該等正極引腳120係分別電性地堆： :腳=組正極引腳單元12〇'，其令該等正極 腳12 〇係分別從該等正箱丄2的同一方向 ΐ性二圖未示)係透過該等導電㈣ 冤地隹f在一起（如第十圖至第十四圖所示）。 請參閱第十六圖及第十七圖所示（多正 丨出)，每一個電容單元1之正箱12係= 向外引出之正極引腳丄2 〇，並且該等正極引腳丄2 區分成複數組分別電性地堆疊在一起之正極引腳單元工 2 0 (第十六圖揭露兩組正極引腳單元1 2 〇,;第十七 圖顯露三Μ正極引腳單元工2 〇,)，其中該等正極引腳工 2 〇係分別從該等正箔1 2的同一方向向外引出。第十六 圖顯示可堆疊8層，但可維持4層焊接的高度，另外第= 七圖顯示可堆疊1 2層，但可維持4層焊接的高度。此 外，該等負箔（圖未示）係透過該等導電層而電性地堆疊 在一起（如第十圖至第十四圖所示）。 且 綜上所述，本發明使用表面黏著技術之電容器封裝結 構的優點在於：本發明透過表面黏著技術（Smt )的方式， 即可直接將電容模組設置於該基板單元上。換言之，本發 18 201106399 明透過基板單元的使用，而不需另外設置導線架 ::::器封裝結構比習知結構簡單，並且 封裝^的製作方法比習知的製作方法容易且快速⑽ 惟’本發明之所有範圍應以下述之中請專利 本發明巾請專利範圍之精神與其類似變化之實 包含於本發明之範嘴中，任何熟悉該項技2 之領域内，可輕易思及之變化或修飾皆 以下本案之專利範圍。 在 【圖式簡單說明】 第A圖係為本發明使用表面黏著技術之電容器封士 欠 構的第一實施例之立體分解示意圖； 、、、、°;: There are oxide layers (not shown), as a dielectric layer to produce L through a plurality of solder joints pm and electricity, together, the negative foil 1 〇 m through a conductive layer 5 m and 'The raw connection is at the bottom, the bottom of the negative ^ silver glue or silver paste) and is electrically connected to a substrate, and the positive guides 15 201106399 "Hai and other negative 1 〇rn are insulated from each other. Furthermore, the capacitor module has a plurality of outer surfaces respectively disposed on the positive portion 2 (four) portion and encircles (10) into a H-edge layer 4 m (ie, each of the insulating layers 4 is formed in a manner surrounding each phase). Corresponding to the upper and lower sides and opposite sides of a portion of the outer surface of the positive foil i 2m to limit the length of the spacer paper 11m, and as an insulated wire of the negative electrode of each capacitor unit. In addition, the conductive layer 5 m is electrically connected to the ends of the two 0 m and the end length of each negative box m is greater than the end length of the parent box of 1 2 m to avoid the pigs i 2 m is in contact with the conductive layer 5 m. According to the twelfth figure, the fourth capacitor module of the present invention is a package of == yuan, and there is a conductive layer S η between every two capacitor units ln, for example, silver glue or silver. Paste. (every ^ Ϊ - Ϊ - a capacitor unit 1 η series by - carbon glue 1 0 η pole), ° one: conductive polymer 1 1 Ω, one valve metal foil 1 2 η (positive guide, still Molecular ii η and a carbon 丄〇 ( η (negative electrode) stacked mother Τ a valve metal f "12n surface has an oxide layer (Figure; guide; C electric layer to produce insulation effect, which is the above two sides, on the layer. In addition, the capacitor module is more advanced: the film == a conductive layer 5 n, which includes 'the number of the carbon glue 10n; connected to the mother one capacitor unit h, the capacitor unit n The inter-metals are electrically connected to the plurality of solder joints pn, and are electrically connected: the 4 carbon pastes 1 〇 η are connected through the conductive layers 5 η ' and the valves The metal box piece 1 2 reads the carbon 16 201106399 glue 1 〇 系 is insulated from each other. In addition, the capacitor module is further advanced - a plurality of separate sets of the metal box i 2 η a portion of the insulating layer 4 η (that is, each of the insulating layers In ', formed in a surrounding manner on the upper and lower sides and opposite sides of the outer surface of each of the corresponding metal slabs), In order to limit the length of the conductive polymer 11n, it is an insulated wire of the positive electrode and the negative electrode of every 2 electric valleys, 兀1 η. Please refer to the fourth embodiment of the present invention. Among them, each valve metal piece 12p (positive electrode), one lead two lp, - glue ι〇ρ (negative electrode) are stacked, each of the two layers (not shown) to do ==, 邑, 彖 effect, wherein the above two conductive polymers: the metal oxide sheet 1 2 P on the surface of the oxide layer 1 = shape between the two through the carbon glue 1Gp and electrically stacked in the mother two electric two The capacitor module further includes: a plurality of conductive layer basins, and a plurality of capacitors connected to each of the capacitors, and the other ones are electrically connected to each other through a plurality of solder joints pp ί Ξ ί ί The carbon glues are insulated from each other by the conductive pastes ίο P. In addition, the plurality of electrodes and the materials are respectively disposed on the valves. The foil step comprises: a soil and surrounds the ring-shaped insulating layer 4p (ie, each of the two sides is formed in a surrounding manner on each of the upper and lower sides of the corresponding surface of the corresponding valve gold 17 201106399 and the opposite On the side) w ι 〇Ρ and the conductive polymer, == and other carbon capacitor units "the insulated wire of the positive and negative electrodes is the mother-in-one state. In addition, the above five stacked capacitors can adopt the following differences. The implementation of each of them is shown in the fifteenth figure (a positive lead is extracted from a negative lead), and the positive η 2 of the mother-capacitor has a pair and the positive poles 120 are electrically stacked: : foot = group positive pin unit 12 〇 ', which makes the positive electrode 12 〇 are respectively from the same direction of the positive box 丄 2 (not shown) through the conductive (four) 冤 隹 f Together (as shown in Figures 11 through 14). Please refer to the sixteenth and seventeenth diagrams (multiple positive output). The positive box 12 of each capacitor unit 1 = the positive pole 丄2 向外 that is led out, and the positive pins 丄2 The region is divided into a positive array of positive electrode units 2 that are electrically stacked together (the sixteenth figure discloses two sets of positive pin units 1 2 〇, and the seventeenth figure shows three positive electrodes of the positive unit 2 〇 ,), wherein the positive electrode pins are respectively led out from the same direction of the positive foils 1 2 . The sixteenth figure shows that 8 layers can be stacked, but the height of the four layers can be maintained. In addition, the figure VII shows that 12 layers can be stacked, but the height of the four layers can be maintained. In addition, the negative foils (not shown) are electrically stacked together through the conductive layers (as shown in Figures 11 through 14). In summary, the capacitor package structure using the surface mount technology of the present invention has the advantage that the capacitor module can be directly disposed on the substrate unit by means of surface mount technology (Smt). In other words, the present invention 18 201106399 discloses the use of the substrate unit without the need to additionally provide a lead frame: the ::: package structure is simpler than the conventional structure, and the manufacturing method of the package is easier and faster than the conventional fabrication method (10) 'All the scope of the present invention should be included in the scope of the present invention in the spirit of the patent scope of the present invention, and any similar changes therein can be easily considered in any field familiar with the technique 2 Changes or modifications are within the scope of the patent in this case. BRIEF DESCRIPTION OF THE DRAWINGS FIG. A is a perspective exploded view of a first embodiment of a capacitor sealer using a surface mount technique of the present invention; , , , , °
第B圖係為本發明使用表面黏著技術之電容器封震、妹 々 構的第一實施例之立體組合示意圖； 、、、D 第c圖係為本發明使用表面黏著技術之電容器封裝結 構的第一實施例之剖面示意圖； σ 第 第D圖係為本發明使用表面黏著技術之複數個電容器 封裝結構的第一實施例之立體示意圖； 第 圖係為本發明使用表面黏著技術之電容器封裝結構 的第二實施例之部分立體分解示意圖； 圖係為本發明使用表面黏著技術之電容器封裝結構 的第三實施例之部分立體分解示意圖； 第四圖係為本發明使用表面黏著技術之電容器封褽結構 的第四實施例之部分立體分解示意圖； 第五Α圖係為本發明使用表面黏著技術之電容器封裝钟 構的第五實施例之部分上視示意圖； 201106399 第五B圖係為本發明使用表面黏著技術之電容器士 構的第五實施例之剖面示意圖； 第六圖係為本發明使用表面黏著技術之電容器封裝結 的第六實施例之剖面示意圖； ι° 第七圖係為本發明使用表面黏著技術之電容器 的第七實施例之剖面示意圖； 一構 第八圖係為本發明使用表面黏著技術之電容器封裴結構 的第八實施例之剖面示意圖； 第九圖係為本發明使用表面黏著技術之電容器封裴結構Figure B is a perspective view of the first embodiment of the capacitor sealing and the first embodiment of the present invention using the surface adhesion technology; and, the second figure is the capacitor package structure using the surface adhesion technology of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a first embodiment of a plurality of capacitor package structures using surface mount technology according to the present invention; FIG. 1 is a capacitor package structure using surface mount technology of the present invention. 2 is a perspective exploded view of a third embodiment of a capacitor package structure using a surface mount technology according to the present invention; and the fourth figure is a capacitor seal structure using the surface mount technology of the present invention. A partially exploded perspective view of a fourth embodiment of the present invention; a fifth schematic view of a fifth embodiment of a capacitor package structure using a surface mount technique of the present invention; 201106399 A cross-sectional view of a fifth embodiment of a capacitor structure of an adhesive technique; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view showing a sixth embodiment of a capacitor package using a surface mount technique; FIG. 7 is a cross-sectional view showing a seventh embodiment of a capacitor using a surface mount technique according to the present invention; A cross-sectional view of an eighth embodiment of a capacitor sealing structure using a surface bonding technique; the ninth drawing is a capacitor sealing structure using a surface bonding technique of the present invention
々 的第九實施例之部分立體分解示意圖； D 第十圖係為本發明第一種堆疊型電容模組之側視示意圖； 第十一圖係為本發明第二種堆疊型電容模組之側視示竟 圖； ~ 第十一圖係為本發明第三種堆疊型電容模組之側視示咅 圖； ~ 第十二圖係為本發明第四種堆疊型電容模組之側視示意 圖； & 第十四圖係為本發明第五種堆疊型電容模組之侧視示意 圖； 第十五圖係為本發明使用表面黏著技術之電容器封装結 構之第一種引腳配合方式之示意圖； 第十六圖係為本發明使用表面黏著技術之電容器封裝結 — 構之第二種引腳配合方式之示意圖；以及 第十七圖係為本發明使用表面黏著技術之電容器封裝結 構之第三種引腳配合方式之示意圖。 20 201106399 【主要元件符號說明】 [第一實施例] 基板單元 1 a 絕緣本體 1 0 a 第一上層導電層 1 la 第二上層導電層 1 2 a 第一下層導電層 1 3 a 第二下層導電層 1 4 a 穿孔 1 5 a 中間導電層 1 6 a 電容模組 2 a 電容單元 2 0 a 正極 2 0 1 負極 2 0 2 封裝單元 3 a 殼體 3 0 a 固定膠體 3 la 防水層 4 a V型槽 5 a [第二實施例] φ 基板單元 lb 絕緣本體 10b 第一上層導電層 lib 第二上層導電層 12b 電容模組 2b 電容單元 2〇b 正極 201b 、 負極 202b . 封裝單元 3 b [第三實施例] 基板單元 1 c 絕緣本體 10c 21 201106399 第一上層導電層 11c 第二上層導電層 12c 電容模組 2 c 電容單元 2 0c 正極 2 0 1 負極 2 0 2 封裝單元 3 c [第四實施例] 基板單元 Id 穿孔 1 5 d 電容模組 2d 封裝單元 3d [第五實施例] 基板單元 1 e 絕緣本體 1 0 e 第一上層導電層 lie 第二上層導電層 1 2 e 穿孔 1 5 e 環形凹槽 1 7 e 電容模組 2 e 封裝單元 3 e 環形防水層 5 e [第六實施例] 基板單元 If 絕緣本體 1 0 f 環形凹槽 1 7 f 電容模組 2 f 封裝單元 3 f 環形防水層 5 fA partial exploded perspective view of a ninth embodiment of the present invention; D is a side view of the first stacked capacitor module of the present invention; and FIG. 11 is a second stacked capacitor module of the present invention. Side view shows the image; ~ The eleventh figure is a side view of the third stacked capacitor module of the present invention; ~ The twelfth figure is a side view of the fourth stacked capacitor module of the present invention The fourteenth figure is a side view of the fifth stacked capacitor module of the present invention; the fifteenth figure is the first pin matching mode of the capacitor package structure using the surface adhesion technology of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 16 is a schematic view showing a second pin-fitting manner of a capacitor package structure using a surface mount technology according to the present invention; and a seventeenth view showing a capacitor package structure using a surface mount technique of the present invention. Schematic diagram of three pin-fit methods. 20 201106399 [Description of main component symbols] [First Embodiment] Substrate unit 1 a Insulating body 1 0 a First upper conductive layer 1 la Second upper conductive layer 1 2 a First lower conductive layer 1 3 a Second lower layer Conductive layer 1 4 a perforated 1 5 a intermediate conductive layer 1 6 a capacitor module 2 a capacitor unit 2 0 a positive pole 2 0 1 negative pole 2 0 2 package unit 3 a housing 3 0 a fixed colloid 3 la waterproof layer 4 a V-shaped groove 5 a [Second embodiment] φ substrate unit lb insulating body 10b first upper conductive layer lib second upper conductive layer 12b capacitor module 2b capacitor unit 2〇b positive electrode 201b, negative electrode 202b. package unit 3 b [ Third Embodiment] Substrate Unit 1 c Insulating Body 10c 21 201106399 First Upper Conductive Layer 11c Second Upper Conductive Layer 12c Capacitor Module 2 c Capacitor Unit 2 0c Positive 2 0 1 Negative 2 0 2 Package Unit 3 c [Fourth Embodiment] Substrate Unit Id Perforation 1 5 d Capacitor Module 2d Package Unit 3d [Fifth Embodiment] Substrate Unit 1 e Insulating Body 1 0 e First Upper Conductive Layer lie Second Upper Layer Electrical layer 1 2 e perforated 1 5 e annular groove 1 7 e capacitor module 2 e package unit 3 e annular waterproof layer 5 e [sixth embodiment] substrate unit If insulating body 1 0 f annular groove 1 7 f capacitance Module 2 f package unit 3 f annular waterproof layer 5 f
22 201106399 [第七實施例] 基板單元 1 g 第 一上層 導 電 層 1 1 g 第 二上層 導 電 層 1 2 g 第 一下層 導 電 層 1 3 g 第 二下層 導 電 層 1 4 g 電容模組 2 g 電 容單元 2 0 g 正極 2 0 1 g 負 極 2 0 2 g 封裝單元 3 g [第八實施例] 基板單元 1 h 第 一下層 導 電 層 1 3 h 第二下層導電層 1 4 h 穿孔 1 5 h 中間導電層 1 6 h 穿孔 1 5 h 中間導電層 1 6 h 電容模組 2h 電容單元 20h 正極 2 0 1 h 負極 2 0 2 h φ 封裝單元 3 h [第九實施例] 基板單元 1 i 絕緣本體 1 0 i 第一上層導電層 1 1 i 第二上層導電層 1 2 i . 電容模組 2 i 電容單元 2 0 i 正極 2 0 1 i 負極 2 0 2 i 封裝單元 3 i 23 201106399 [第一種堆疊型電容] 電容單元 1j 負箔層 負箔 負箔 隔離紙層 隔離紙 隔離紙 正箔 1 0 j 1 0 0 j 1 0 1 j 1 1 j 1 1 0 j 1 1 1 j 1 2 j 絕緣層 4 j 導電層 S j 焊接點 P j [第二種堆疊型電容] 電容單元 lk22 201106399 [Seventh embodiment] substrate unit 1 g first upper conductive layer 1 1 g second upper conductive layer 1 2 g first lower conductive layer 1 3 g second lower conductive layer 1 4 g capacitance module 2 g Capacitor unit 2 0 g Positive electrode 2 0 1 g Negative electrode 2 0 2 g Package unit 3 g [Eighth embodiment] Substrate unit 1 h First lower conductive layer 1 3 h Second lower conductive layer 1 4 h Perforation 1 5 h Intermediate conductive layer 16 h Perforation 1 5 h Intermediate conductive layer 16 h Capacitor module 2h Capacitor unit 20h Positive pole 2 0 1 h Negative pole 2 0 2 h φ Package unit 3 h [Ninth embodiment] Substrate unit 1 i Insulating body 1 0 i first upper conductive layer 1 1 i second upper conductive layer 1 2 i . capacitor module 2 i capacitor unit 2 0 i positive pole 2 0 1 i negative pole 2 0 2 i package unit 3 i 23 201106399 [first type Stacked Capacitor] Capacitor Unit 1j Negative Foil Layer Negative Foil Negative Foil Isolation Paper Layer Isolation Paper Isolation Paper Positive Foil 1 0 j 1 0 0 j 1 0 1 j 1 1 j 1 1 0 j 1 1 1 j 1 2 j Insulation 4 j Conductive layer S j Solder joint P j [Second stacked capacitor] Capacitor Unit lk
負箔 負箔 隔離紙 隔離紙 正箔 10 0k 10 1k 110k 111k 12k 絕緣層 4 k 導電層 5 k 導電層 S k 焊接點 P k [第三種堆疊型電容] 電容單元 1mNegative foil Negative foil Isolation paper Isolation paper Positive foil 10 0k 10 1k 110k 111k 12k Insulation 4 k Conductive layer 5 k Conductive layer S k Solder joint P k [3rd stacked capacitor] Capacitor unit 1m
負箔 隔離紙 正箔 10m 11m 12m 絕緣層 4 m 24 201106399 導電層 5 m 焊接點 Pm [第四種堆疊型電容] 電容單元 In 碳膠 碳膠 導電高分子 導電高分子 閥金屬箔片 絕緣層 4 η • 導電層 5η 導電層 S η 焊接點 Ρ η [第五種堆疊型電容] 電容單元 Ip 絕緣層 4 ρ 導電層 5 ρ 焊接點 Ρ ρ [引腳導出實施例] 電容單元 1 正箔 1 正極引腳 1 正極引腳單元 1 碳膠 碳膠 導電高分子 導電高分子 閥金屬箔片 2 2 0 2 0Negative foil isolating paper positive foil 10m 11m 12m Insulation layer 4 m 24 201106399 Conductive layer 5 m Soldering point Pm [Fourth type of stacked capacitor] Capacitor unit In Carbon adhesive Carbon conductive polymer conductive polymer valve Metal foil insulation layer 4 η • Conductive layer 5η Conductive layer S η Solder joint Ρ η [Fifth stacked capacitor] Capacitor unit Ip Insulation layer 4 ρ Conductive layer 5 ρ Solder joint Ρ ρ [Pin-out example] Capacitor unit 1 Positive foil 1 Positive Pin 1 Positive Pin Unit 1 Carbon Glue Carbon Conductive Polymer Conductive Polymer Valve Metal Foil 2 2 0 2 0