TW201044480A - Method of characterizing a semiconductor device and semiconductor device - Google Patents

Abstract

A method of characterizing a semiconductor device includes providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a BT dummy device for measurement, respectively measuring tunneling currents (Igb) and scattering parameters (S-parameters) of the BT SOI device and the BT dummy device, subtracting Igb of the BT dummy device from that of the BT SOI device to obtain Igb of a floating body (FB) SOI device, filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device, and analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances of the FB SOI device.

Description

201044480 s. 6. Description of the Invention: The present invention relates to a method for characterizing a semiconductor device and a semiconductor device, particularly a floating body, a silicon-on-insulator (SOI). A method of characterizing a semiconductor element and a semiconductor element applied to the characterization method. [Prior Art] With the requirement of the performance circuit, the conventional bulk metal oxide semiconductor field-effect transistor (MOSFET) structure cannot be overcome due to the ultra-short channel effect and the area of the PN junction is large. Undesirable effects such as parasitic capacitance and leakage current have led to the continued attention of SOI technology. ❹ In the S〇I technology, the MOSFET component is formed on a thin film, and a buried oxide (buried) layer is provided between the tantalum film and the substrate, which provides many transcendences. The advantages of traditional bulk crystal M〇SFET components, such as SOI MOSFET components with small parasitic capacitance, therefore have better speed characteristics in circuit operation; s〇im〇sfet components have strong radiation resistance', thus reducing soft errors (s〇fterr〇r); due to the presence of buried oxide layer 'can prevent the latch_up effect; s〇I m〇SFET components are less affected by the short channel effect, making the component easier to scale (scaled , d〇Wn). Due to the advantages of 201044480 such as improved performance, high package density and low power consumption, in the field of semiconductor manufacturing, SOI MOSFET components are more predictive of the mainstream of components. According to the thickness of the germanium film on the BOX layer, SOI The technology can be further divided into partially depleted (PD SOI) or fully depleted ' FD SOI. Due to the high productivity advantages, the SOI technology is more commonly used. It is a PD SOI. Please refer to Fig. 1, which is a schematic diagram of a conventional PD SOI device. The PD SOI device 1 is disposed on an SOI substrate 110, and the SOI substrate 110 includes a substrate 112. a film 116, and a BOX layer 114 disposed between the substrate 112 and the germanium film 116. The PD SOI device 100 further includes a gate conductive layer 120, a gate dielectric layer 122, and a source/germanium The pole 124. The thickness of the PD SOI element 100 of the PD SOI element 100 is thicker than that of the depletion region, thus leaving a region of its substrate 110 undeted and ungrounded, so it is generally described as a floating body 126. Since the base 126 of the PD SOI component 100 is not grounded, the charge carriers generated by the impact ionization cannot be eliminated, and the substrate potential of the PD SOI component 100 may be related to static, dynamic or transient component operating conditions. The difference is floating, resulting in a change in the threshold voltage of the PD SOI element 100, a so-called hysteresis effect or a history effect. Briefly, the substrate potential and element characteristics of the PD SOI element 100 are deep. Switch state As mentioned above, since the base 126 of the PD SOI component 100 is not grounded; 5 201044480 and because the characteristics of the PD SOI component loo are greatly affected by the historical effect, it is still impossible to convert the PD SOI component. In particular, the floating body (FB) of the substrate is not grounded. The real characteristics of the SOI component are the gate-to-base (gate_t〇_b〇dy) capacitance (Cgb) and the gate-to-substrate through current (Igb). Chemical. In addition, since the gate resistance and the gate capacitance determine the input impedance of the MOSFET component in the radio frequency (RF) component, accurate measurement of the gate capacitance is the key to RF circuit simulation. Not only that, but the general knowledge in the a-Hai field should be aware that component characterization is extremely important for integrated circuit design: reliable component models must come from accurate measurement techniques' and can be extracted from measurement data. The actual characteristics of the component to be tested, in order to provide the component's process and the component designer's fast and detailed component characteristics, as a basis for further improvement. 〇 【Contents】

Accordingly, it is an object of the present invention to provide a characterization method that can effectively obtain FB SOI component characteristics and a semiconductor component applied to the characterization method. According to the scope of the invention provided by the present invention, a method for characterizing a semiconductor device is provided, which first provides an SOI substrate, and the SOI substrate is provided with at least one body-tied insulating material. (BT SOI) element 6 201044480 pieces and - body external (BT) parasitic element, wherein the parasitic element comprises a first type source/drain heavily doped region and a parasitic gate, and the parasitic = very And disposed on the first type source/drain heavily doped region, and then respectively measure the wear current (Igb) and scattering parameters (s parameters) of the BTS〇I element and the parasitic element, And correcting the tunneling current of the BT SOI component by using the tunneling current of the BT parasitic element 2 to obtain a pass-through current of a floating body IGBT (FB SOI) component, and then removing the current by a de-boiling technique The BTS0I component deducts the characteristics of the BT parasitic component to extract the S parameter of the fb SOI component, and finally calculates and analyzes the s parameter of the FB S0I component to obtain a gate-related capacitance value (Cgb) that truly belongs to the FB SOI component. According to the patent application scope provided by the present invention, there is further provided a semiconductor device comprising: a bottom portion including a second type well region; and a first type source/汲 disposed in the second type well region a heavily doped region heavily re-doped region, a first type heavily doped region disposed within the SOI substrate and isolated by the second type well region and the first type source/drain heavily doped region a parasitic gate disposed on the second well region and not crossing the source/drain heavily doped region, and a substrate electrically connected to a circuit.

According to the semiconductor device characterization method provided by the present invention, the concept of de-embedding technology and the setting of parasitic components are used to remove the parasitic effects caused by the BT SOI component, and the FD SOI component is correctly analyzed by the S-parameter calculation. Cgb. In addition, the Igb provided by the bt SOI 201044480 component can be corrected by the Igb provided by the parasitic element and the Igb of the FD SOI component is actually obtained. [Embodiment] The semiconductor component measuring method provided by the present invention and the semiconductor component applied to the method are applicable to a plurality of test key structures formed on a surface of a component wafer or a surface of a monitor sheet (4). That is, while performing various semiconductor processes of the RF components on the die, the same steps are used to fabricate the semiconductor components required for the test on the wafer scribe or the surface of the monitor to simulate the same process on the etch. Then, using the test device such as a probe (pr〇be), the test button is touched to measure the parameters of the test component to obtain the desired measurement and the material, and the actual measurement of the component to be tested is extracted from the measurement data. characteristic. πRefer to Fig. 2 and Fig. 3' Fig. 2 - Test body can be externally connected to one of the body-tied elements (hereinafter referred to as "βτ")

A schematic view of a preferred embodiment; and Fig. 3 is a schematic cross-sectional view of the BTS0I element of the second towel taken along a tangential line A-A. As described above, the BT s〇i component is fabricated on the semiconductor process of the RF component on the enamel, that is, the same step is performed on the scribe line of the wafer or on the surface of the monitor sheet, so that The steps are not described here. In addition, the BT SOI component in the first preferred embodiment is an N-type MOSFET component, but those skilled in the art should be aware that the BT SOI component is not limited to a P-type BT SOI component. When the BT ★ SOI component is a P-type, those skilled in the art should know that the following n, P 201044480 type doping is reversed, and therefore will not be described here. As shown in Figures 2 and 3, the first preferred embodiment first provides a BT SOI device 200 disposed on a substrate 21A. The substrate 〇 21 includes a substrate 212, a buried oxide layer 214 and a p-type doped layer 216. The BOX layer 214 is preferably a oxidized stone layer based on the excellent insulating properties of the yttrium oxide (Si) material and the high integration with the Shihwa wafer process, but is not limited thereto. The P-type doped layer 216 also has a shallow trench isolation (STI) 220 and a P-type well region 23, and a portion of the p-type well region 230 serves as a substrate for the BTS0I element 200. The BTS(R) I element 2 has a gate dielectric layer (shown in Fig. 3) composed of an oxide oxide, a nitride or other high dielectric constant material, and is formed on the surface of the substrate 210. On the gate dielectric layer 240, the BT SOI device 2 includes a τ-type gate structure 242. The gate structure 242 has a - portion 246 and a second portion 248 that is perpendicular to the first portion 246. And the second portion 248 extends and traverses the P-type well region 230 as shown in FIG. The p-type well region 23 〇 θ on both sides of the first portion 248 is set to - N-type source / secret 4 doped (four) domain ice, the value of hiding is due to the formation of the Ν-type source / immersion When the impurity of the miscellaneous region 2 is replayed, the second portion 248 above the p-plastic zone 230 and the portion of the first portion 246 serve as a 掺杂-type doped implant mask, thus completing the second part after implantation. 248 and the portion 246 of this portion have a Ν-type doping to form a Ν-type region 242a. In addition, a portion of the first portion of the other side of the Ν-type region, that is, away from the source (four) and the heavily doped region 244 is used as a ρ 9 201044480

0 2 (8) has contact plugs 250, 252, 2M (shown only in Figure 2). The contact plug 250 is electrically connected to the base under the gate structure 242, the contact plug 252 is electrically connected to the gate structure 242, and the contact plug 254 is electrically connected to the N-type source and the heavily heavily doped region 244. The sexual connection 'is easily measured and extracted by the component characteristics of the test BT SOI element 200 such as Cgb and Igb.

However, since the first portion 240 of the T-type gate structure 242 has both the N-type region 242a and the p-type region 242b, the characteristics of the second portion 248 that are actually effective, such as the amount of Cgb and Igb, are distorted. Test results. In other words, although the component characteristics to be obtained can be extracted by the measurement result of the BT SOI element 200, the first portion 246 of the T-type gate structure 242 has both the N-type region 242a and the P-type region 242b. On the contrary, it causes a parasite effect that is greatly affected by the measurement of the FB S0I component, and does not reflect the characteristics of the actual FB SOI component. 'Next, please refer to FIG. 4 and FIG. 5'. FIG. 4 is a schematic diagram of one of the test subject externally connectable (BT) dummy elements 3 提供 provided in the first preferred embodiment 201044480; FIG. Then, a cross-sectional view of the parasitic element in FIG. 4 is obtained along a tangential line. As described above, the BT parasitic element 300 provided in the first preferred embodiment is formed in synchronization with the scribe line of the wafer or the surface of the monitor sheet when the RF element on the die and the BT sII component 200 are formed. However, these steps are also omitted here. 〇 〇 As shown in FIG. 4, the bt parasitic element 300 is disposed on the SOI substrate 210, similarly to the BT SOI element 200. The BT parasitic element 300 further has a parasitic gate 342; unlike the BT SOI element 2, the BT parasitic element 300 is not like the BT SO [the element 200 has an active first portion 248 that spans the p-well 23 〇 That is, the parasitic gate 342 and the τ-type gate structure 242 have different layout patterns. However, the mistletoeium element 3〇〇 still maintains the implantation pattern of the same condition as the bts〇i element 2, and undergoes the implantation step of forming the N-type source/wave heavily doped region: 44, so the dopant will enter the original The p-type well region 230 and the dummy gate 342, and the eight-button 丨 丨 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他, RT ^ 匕 field * 244 and Ν type area 342a. Similarly, the BT parasitic element 300 also undergoes the p-p-type region 342b, while at the same time (four) comes to the doping process, forming

Form-P type heavily doped region 232, and the original wide:: one type well difference and N type source / _ heavy doping \ heavy push area 232 by P know BT parasitic element 3 00 send: = _ area _isolation. Thus, pa,. ^ ° thirst pole 342 is the same as the first portion 2 of the gate structure 242 of the BT S0I device 200. 'Value BT parasitic element 300 is sent 11 201044480 The gate 342 does not span the N-type source/汲Very heavily doped region 244. In addition, the BT parasitic element 300 has contact plugs 350 and 352, and the contact plug 350 is electrically connected to the base; and the contact plug 352 is electrically connected to the N-type source/drain heavily doped region 244. The BT parasitic element 300 can provide the relevant characteristics of the parasitic gate 342 to the substrate. Referring to Figure 6, Figure 6 is a flow chart showing a method of measuring a semiconductor element provided by the first preferred embodiment. As shown in FIG. 6, the measuring method of the semiconductor device comprises the following steps: 4: providing a BT SOI component 200 for testing and an external (BT) parasitic component 300; 402: measuring bt SOI component and BT, respectively The tunneling current and scattering parameter (S parameter) of the parasitic element; 404. Deducting the characteristics of the BT parasitic element from the BT SOI component by de-embedding technology to extract the floating body insulation (FB SOI) The S parameter of the component; 406: Calculating and analyzing the S parameter of the fb SOI component, and obtaining the gate related capacitance value Cgb of the FB SOI component. According to the measurement method provided by the present invention, the parasitic gate 342 of the BT parasitic element 300 is the same as the first portion 246 of the T-type gate structure 242 that causes the measurement result to be distorted in the BT SOI element 200, so the BT parasitic element 300 The correlation characteristic of the parasitic gate 342 to the substrate provided by 12 201044480 can be regarded as equivalent to the first portion 246. Therefore, the present invention further utilizes the de-embedding technique and the applicable software to remove the parasitic component of the device under test, that is, the BT parasitic element 3 is used to remove the head of the T-type gate structure 242 in the BT SOI element 200, that is, simultaneously The first portion 246 of the N-type region 242a and the P-type region 242b actually produces parasitic effects. Since the measurement method of the semiconductor device provided by the present invention can effectively remove the parasitic effect of the first portion 246, as is known to those skilled in the art, by the S parameter and the admittance parameter (Y- The parameter 'Y parameter) or the impedance parameter (impes (jance parameter) conversion method, etc., can calculate and calculate the correct capacitance value cgb of the gate of the FB SOI element to the base. In addition, by the BT parasitic element 300 The Igb is provided to correct the Igb measured by the BTSOI component 200, and to actually obtain the igb of the FB SOI component. Please refer to FIG. 7 and FIG. 8 , and FIG. 7 shows the N-type BT SOI component and the

Q Comparison of Cgb of N-type FB SOI elements obtained by the method; Figure 8 is a comparison of Cgb of P-type BT SOI elements and p-type FB SOI elements obtained by the method. As shown in FIG. 7, the Cgb provided by the N-type BT SOI element is often due to the head of the T-type gate structure as compared to a true N-type FB SOI element (as in the first portion of the first preferred embodiment 246). Parasitic effects lead to over-estimated situations. As shown in Figure 8, the p-type BT SOI component provides the under-estimated Cgb for the same reason as the true P-type FB SOI component. That is to say, according to the method provided in a preferred embodiment of the present invention, the transmission component of the device to be tested can be effectively removed, and the actual characteristics to be obtained can be obtained. Next, please refer to Fig. 9 to Fig. 12. Fig. 9 is a graph of Igb and gate voltage (Vgb) of the 1^ type BTS〇I element; Fig. 1 is the N obtained by the method. A plot of Igb and Vgb for a type FB SOI component. The nth figure is a graph of Igb and Vgb measured by the P-type BT SOI element; the 12th 〇 diagram is a plot of Igb and V of the P-type FB SOI element obtained by the method. From the above graph, it can be found that, via the measurement method provided by the present invention, it can be found that the Igb of either the N-type or p-type BTSOI element is different from the lgb of the actual FB SOI element. That is to say, by the lgb provided by the parasitic element 300, it is possible to correct the Lb' measured by the BTS 〇I element 2 and obtain the lgb of the true FB SOI. ❹ Please refer to FIG. 13 and FIG. 14 , FIG. 13 is a schematic diagram of one of the test BT SOI components provided by the second preferred embodiment; FIG. 14 is a test provided by the second preferred embodiment. The main body can be connected to a (BT) parasitic element. Since the linear body resistance (Rb) is determined by the function of the element width (W) and the gate length (l), a Η-type gate is also formed in the s〇I technique to reduce the linear matrix resistance and avoid resistance. The value is too large to cause an open circuit. And because the Η-type gate has lower resistance and better transconductance, it has a larger cutoff frequency and a lower minimum impurity than the Τ-type gate. Index 201044480 (minimum noise figure), and better RF performance. When the FB SOI element fabricated in the wafer has an H-type gate, the BT SOI element 500 provided by the second preferred embodiment is obtained by the same steps on the wafer dicing street or on the surface of the monitor sheet. In order to simulate the same process and components on the die, the BT SOI component 5〇〇 shown in Figure 13 also has a germanium gate. Furthermore, the BT SOI component 500 and the BT parasitic component 600 in the second preferred embodiment are also an N-type component, but those skilled in the art will recognize that such components are not limited to a P-type component. When the elements are of the P type, those skilled in the art should be aware that the use of the N and p type dopants described below is reversed and will not be further described herein. In addition, the materials of the components in the second preferred embodiment are the same as those in the first preferred embodiment. Therefore, reference may be made to the first preferred embodiment. As shown in FIG. 13, the BT SOI device 500 is disposed on an SOI substrate 510, which includes an n-type gate structure 542. The 闸-type gate structure 542 includes a pair of parallel first portions 546. The second portion 548' is perpendicular to the first portion 546 and the second portion 548 extends and traverses a p-type well region (not shown). A Ν-type source/no-heavy area 544 is formed in the 井-type well region on both sides of the second portion 548. The BTS0I device also includes a p-type re-doping region (not shown) which is isolated from the N-type source/drain heavily doped region 544 by the P-well region. The gate structure 542 of the gate structure 542 and the portion of the first portion 546 used as the implant mask have N-type doping to form an n-type region 542a; and further away from the N-type source / 汲 重 heavily doped area 5 material part 201044480 刀 邛 546 will form a p-type area 542b. Simply put, I am in the structure. The gate structure 542 has a pair of first portions 546 that are parallel to each other and a second portion 548 that is perpendicular to the first portion 546 and spans the P-type well region; in the doped form, the gate structure 542 has An N-type region 542a and a p-type region 542b. The BT S0I device 50 has a contact plug 55〇, 552, and the contact plug 550 is electrically connected to the base; and the contact plug 552 is electrically connected to the source/drain heavily doped region 544. The component characteristics such as Cgb and Igb of BT s〇I element 5 can be easily measured and extracted. Next, please refer to Figure 14. As previously mentioned, due to the presence of the N-disk region 542a and the P-type region 542b of the first portion 546, the characteristics of the substantially effective N-type region 542a such as the measurement of Cgb and Igb are distorted. Therefore, the second preferred embodiment further provides one of the BT parasitic elements 600. Like the BT SOI element 500, the BT parasitic element 600 is disposed on the SOI substrate 510. The BT parasitic element 600 has a parasitic gate 642; it is different from the BT SOI element 500.

The parasitic gate 642 is a pair of parallel gate structures; unlike the BT SOI element 500, it has an active second portion 548 that spans the P-well region. However, the BT dummy element 600 also has a N-source/no-heavy doped region 544 and a P-type heavily doped region, and the P-type heavily doped region is heavily weighted by the P-type well region and the N-type source/drain The doped region 544 is isolated. Similarly, the dummy gate 642 as the implant mask forms an N-type region 642a near the N-type source/drain heavily doped region 544; a P-type is formed on the side close to the P-type heavily doped region. Area, 642b. It can be seen that the dummy gate 642 of the BT dummy device is the same as the first portion 546 of the BT SOI 16 201044480 component 500. However, the dummy gate 642 of the BT SOI component 600 does not span the N-type source/no-heavy replacement region. 544. In addition, the BT parasitic element 600 has contact plugs 650, 652, and the contact plug 650 is electrically connected to the base; and the contact plug 652 is electrically connected to the N-type source/drain heavily doped region 544. The BT parasitic element 600 can provide the relevant characteristics of the parasitic gate 642 to the substrate. Please refer back to Fig. 6. Since the steps of the measuring method of the semiconductor component provided by the second preferred embodiment are the same as those of the first preferred embodiment, the steps are as shown in Fig. 6 and the above description. In addition, it is worth noting that, since the Igb and Cgb to be obtained are very small, in the measurement method provided by the present invention, the test BT SOI component 200/500 and the BT dummy component 300/600 are preferably RF test keys (radi 〇〇freqUency, RF test keW structure construction to increase the measurement accuracy of Igb and Cgb. See Figure 17, which is one of the RF test keys provided by the present invention. As shown in Figure 17, rf The test button 7 is disposed on the substrate 21〇/51〇 at its central position to set the device to be tested 71 such as BTS〇I element 2〇〇/5〇〇 or BT dummy element 3〇〇/6〇〇 The device to be tested has a gate connection end 712, a source connection end 714, a drain connection end 716 and a base connection end 718, and the connection ends of the 5th and the other are sequentially electrically connected to the device under test 71. The gate, the source, the drain and the substrate of the crucible. The RF test key 7〇〇 includes a bottom gold layer, and the bottom metal layer has a front block 722, a right block 724, and a 17 201044480 rear block. 726 and a left block 728 are circumferentially disposed around the device under test 71, and sequentially connected to the gate terminal 712, The front connection block 714 and the rear end block 726 respectively have a front signal pad 742 and a rear signal pad 746 for connecting with the probe. The RF test key structure 700 further has a top metal layer above the bottom metal layer, and a dielectric layer not shown in the second layer between the top metal layer and the bottom metal layer. A right metal piece and a left metal piece are included, respectively, and a via plug is used to pass through the dielectric layer to electrically connect to the right block 724 and the left block 728 of the bottom metal layer, respectively. The right metal piece 764 and the left side The metal sheets 768 are each an elongated metal piece and are parallel to each other. A ground pad 764a is defined at the front end of the right metal piece 764, and another ground pad 76 is defined at the rear end. A ground pad is defined at the front end of the left metal piece 768. ❹ a 'After % also has another ground pad 768b. Also as shown in Figure 17, the ground pad 768a, the front signal pad 742 and the ground pad 76 are arranged in a front row connection area; and the ground pad 768b, rear The signal pad 746 and the ground pad 76 are arranged in a row - The row connection area', that is, the front and rear row connection areas are the grounding area, the signal pad area, and the grounding area (GSG) from left to right. Thus, the probe card's slave needle can be respectively contacted with the RF test key 7 (8). The front row connection area and the rear row connection area are tested by the device under test 710. 4 As described above, the present invention first discloses the concept of using de-embedding technology and the setting of the dummy 18 201044480 component to remove the BT SOI component. Parasitic effect, and the correct Cgb of the floating transistor component is analyzed by the conversion of the Y parameter and the Ζ parameter. In addition, the Igb provided by the BT parasitic element corrects the Igb measured by the BTSOI element and actually obtains the Igb of the floating body transistor. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. Ο [Simple description of the diagram] Figure 1 is a schematic diagram of a conventional PD SOI component. Figure 2 is a schematic illustration of a first preferred embodiment of a test body externally connectable (BT) SOI component. Fig. 3 is a schematic cross-sectional view of the BT SOI element taken along line A-A' in Fig. 2. Figure 4 is a BT parasitic element for testing in the first preferred embodiment. ❹ Fig. 5 is a layout view of a cross-sectional view of the BT parasitic element along the tangential line B-B' in Fig. 4. Fig. 6 is a flow chart showing a method of measuring a semiconductor device provided in the first preferred embodiment. Figure 7 is a Cgb comparison of the N-type BT SOI element and the N-type FB SOI element obtained by the method. Figure 8 is a comparison of Cgb of a P-type BT SOI element and a P-type FB SOI element obtained by the method. 19 201044480 Figure 9 is a plot of tunneling current (Igb) and gate voltage (Vgb) for an N-type BT SOI component. Figure 10 is a graph of Igb and Vgb of an N-type FB SOI element obtained by the method. Figure 11 is a plot of Igb and Vgb measured by a P-type BT SOI component. Figure 12 is a graph of Igb 0 and Vgb of a P-type FB SOI element obtained by the method. Figure 13 is a schematic view showing a second preferred embodiment of a test BT SOI element. Fig. 14 is a view showing a test BT parasitic element provided in the second preferred embodiment. Figure 15 is a schematic diagram of one of the RF test keys provided by the present invention. [Main component symbol description] 100 partially depleted insulating member 110 112 substrate 114 116 germanium film 120 122 gate dielectric layer 124 126 substrate SOI substrate buried oxide gate conductive layer source/drain 200, 500 body An externally-clad insulating member 210 can be used. SOI substrate 20 201044480 212 214 216 220 230 232 240 q 242 > 542 242a, 542a 242b > 542b 244, 544 246, 546 248, 548 250, 252, 254, 550, 552 300, 600 342 ' 642 342a, 642a 342b, 642b 350 , 352 , 650 , 652 400 for testing 402 separately measured 基材 基材 substrate buried oxide layer 矽 type doped 矽 layer shallow trench isolation Ρ type well area Ρ type heavy doping Area gate dielectric layer gate structure Ν type region Ρ type region Ν type source/drain heavily doped region first part second contact plug body can be connected with parasitic element dummy gate Ν type region Ρ type region contact Plug BT SOI component and tunneling electrical component of the ΒΤ parasitic component 01 component and BT parasitic component 21 201044480 Flow and s parameter 404 Deducting the characteristics of the BT parasitic component from the BT SOI component by de-embedding technology A silicon on insulator (FB SOI) S parameter calculation element 406 of the S-parameter analysis FB SOI element, the gate of the obtained extreme FB SOI element capacitance value of a floating body of the base body Cgb

700 RF test button 710 DUT 712 Gate connection 714 Source connection 716 Drawer connection 718 Base connection 722 Front block 724 Right block 726 Rear block 728 Left block 742 Front signal pad 746 Rear signal Pad 764 Right metal piece 764a, 764b Ground pad 768 Left metal piece 22 201044480 768a, 768b Ground pad

Claims (1)

201044480 VII. Patent application scope: 1. A method for measuring a semiconductor component, comprising the following steps: knowing that a silicon-on-insulator (SOI) substrate is provided, and at least one body is externally connected on the SOI substrate ( B〇£jy_tied) a BT SOI component and a body externally connectable (BT) parasitic component, wherein the bt parasitic component comprises a first type source/drain heavily doped region and a parasitic gate, And the parasitic gate is not disposed on the first source/drain heavily doped region; and the tunneling current (Igb) and the scattering parameter (scattering parameter) of the BT SOI component and the BT parasitic component are respectively measured. S parameter); correcting the tunneling current of the BT SOI element by using the tunneling current of the BT parasitic element to obtain a tunneling current of a floating body (BT SOI) component; by de-embedding technology Deducting the characteristics of the BT parasitic element from the BT SOI component to extract the S parameter of the FB SOI component; and ◎ calculating and analyzing the S parameter of the FB SOI component to obtain the gate related capacitance value (Cgb) of the fb SOI component . 2. The measuring method according to claim 1, wherein the bt SOI element and the BT parasitic element are simultaneously formed on the SOI substrate by the same steps. 3. The measuring method according to claim 1, wherein the SOI base 24 201044480 . . . bottom comprises a plurality of second type well regions. 4. The measuring method according to claim 3, wherein the b s 〇 element comprises: a question mark structure disposed on the second type well region; at least one first type source/ a heavily doped region of the drain is formed in the second well region; a second heavily doped region is formed in the base of the s〇I, and the first well region and the first type The source/no-heavy area is isolated; the body is electrically connected to a circuit. A please refer to the measurement of the fourth paragraph of the scope of the patent scope of the right-wing 1 丨 # w 歹凊 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中Cross the second type of well area.邛❹第一邛❹6· The first part of the structure described in the fifth paragraph of the patent application; ^ g r 万 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 近 近 近 近 近 近 近 近 近 近 近 近 近 近 近The region, while the second type of heavily doped region. ° A regional crime is close to the gate. The measurement method described in the application for the hometown (4) is a τ-type gate structure. 25 201044480 8 The measuring method component of claim 7, further comprising: a mistletium-type second type heavily doped region; and a substrate, wherein the base system is electrically connected to a circuit; wherein the parasitic The gate system is disposed in the upper region of the second type well region and a second type region, the first type region/, the first type is replaced by #, the crime is close to the first type source/drainage impurity region and the first The type II region is adjacent to the second type heavily doped region. The material is a (four)-shaped (four) material, wherein the closed-pole structure is a Η-type gate structure, and the first pair of the Η-type gate structure is parallel to each other and disposed at both ends of the second portion. The method of claim 10, wherein the measuring element according to claim 9 further comprises: a second type heavily doped region; and a substrate, wherein the base system is electrically connected to a circuit, The parasitic gate is a parasitic gate that is parallel to each other and disposed on the second well region, and the parasitic gate has a “first-type region” and a second region: the first-(fourth) region is close to The first type source/secret heavily doped region, and the second type region is adjacent to the second type heavily doped region. U. The method of measuring according to claim 1, wherein the Βτ s〇i element and the BT parasitic element are constructed by using a radio frequency test key. 26 201044480 <w test key). 12. The method of measuring according to claim 1, wherein the SOI substrate is a substrate of a component wafer or a monitor wafer. 13. A semiconductor device comprising: a germanium-insulated insulating (SOI) substrate, the SOI substrate comprising a second type well region; ❹ a first type source/drain heavily doped region disposed in the second a second type heavily doped region disposed in the s〇I substrate and isolated from the first type source/drain heavily doped region by the second type well region; a gate electrode disposed on the first type well region and not crossing the first type source/difficult heavily doped region; and the body may be externally connected to the (BT) substrate, and the bt base system is electrically connected to a circuit . The semiconductor device according to claim 13, wherein the coffee substrate comprises a substrate, a buried oxide layer and a first-type doped layer in sequence. 15. If the patent application is smothered and ancient, the junction (four) and the flat (four) component, wherein the dummy B and the gate have a first type region and a second region, the first type: 3 = bungee heavily doped And the second type region is adjacent to the second 27 201044480. The semiconductor device according to claim 15 is a pair of mutually parallel gate structures. 17. The construction of a semiconductor component conductor component as described in claim 13 of the patent specification. ❹I8. The semiconductor component of claim 13, wherein the substrate is a substrate of a component wafer. 19. The semiconductor component conductor component of claim 18, wherein the conductor component is disposed in a scribe line of the component wafer. 20. The semiconductor component according to claim 13, wherein the substrate is a substrate of a monitor wafer. Where is the virtual 'the half of the SOI' where the half of the SOI ❹ eight, the pattern: 28