TWI484573B - Method of characterizing a semiconductor device and semiconductor device - Google Patents

Method of characterizing a semiconductor device and semiconductor device Download PDF

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TWI484573B
TWI484573B TW098118689A TW98118689A TWI484573B TW I484573 B TWI484573 B TW I484573B TW 098118689 A TW098118689 A TW 098118689A TW 98118689 A TW98118689 A TW 98118689A TW I484573 B TWI484573 B TW I484573B
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soi
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component
heavily doped
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TW201044480A (en
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Yue Shiun Lee
Yuan Chang Liu
Cheng Hsiung Chen
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United Microelectronics Corp
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半導體元件特徵化方法及半導體元件Semiconductor component characterization method and semiconductor component

本發明係關於一種半導體元件之特徵化方法以及半導體元件,尤指一種浮體(floating body)矽覆絕緣(silicon-on-insulator,SOI)半導體元件之特徵化方法以及應用於該特徵化方法之半導體元件。The present invention relates to a method for characterizing a semiconductor device and a semiconductor device, and more particularly to a method for characterizing a floating body silicon-on-insulator (SOI) semiconductor device and a method for applying the same Semiconductor component.

隨著對高性能電路的要求,傳統塊晶(bulk)金屬氧化物半導體場化電晶體(MOSFET)結構因無法克服超短通道效應,以及因PN接面面積較多而產生的寄生電容與漏電流等不理想的效應,使得矽覆絕緣(SOI)技術持續受到矚目。With the demand for high-performance circuits, the traditional bulk metal oxide semiconductor field-effect transistor (MOSFET) structure cannot overcome the ultra-short channel effect, and the parasitic capacitance and leakage due to the large PN junction area. Undesirable effects such as currents make SOI technology continue to attract attention.

在SOI技術中,MOSFET元件係形成於一矽薄膜上,矽薄膜與基材之間則設置有一埋置氧化(buried oxide,以下簡稱為BOX)層,其提供了許多超越傳統塊晶MOSFET元件的優點,例如SOI MOSFET元件具有較小的寄生電容,因此在電路操作中具有較佳的速度特性;SOI MOSFET元件的抗輻射能力強,因此可減少軟式錯誤(soft error);由於埋置氧化層的存在,可防止栓鎖(latch-up)效應;SOI MOSFET元件更因受短通道效應的影響較小,使得元件較易微縮(scaled down)。由於具有上述提高性能、高封裝密度以及低功耗等優點,在半導體製程領域中,SOI MOSFET元件更有成為元件主流的預見。In the SOI technology, the MOSFET component is formed on a thin film, and a buried oxide (hereinafter referred to as BOX) layer is disposed between the germanium film and the substrate, which provides many advantages over the conventional bulk crystal MOSFET component. Advantages, such as SOI MOSFET components with small parasitic capacitance, therefore have better speed characteristics in circuit operation; SOI MOSFET components have strong radiation resistance, thus reducing soft errors; due to buried oxide layer Exist, it can prevent the latch-up effect; SOI MOSFET components are less affected by the short channel effect, making the components easier to scaled down. Due to the above-mentioned advantages of improved performance, high package density, and low power consumption, SOI MOSFET components are expected to become mainstream components in the semiconductor manufacturing field.

根據BOX層上矽薄膜的厚度,SOI技術又可分為部分空乏矽覆絕緣(partially depleted,PD SOI)或完全空乏矽覆絕緣(fully depleted,FD SOI)。而由於高度生產性的優勢,目前較常使用的SOI技術乃為PD SOI。請參閱第1圖,第1圖係為一習知PD SOI元件之示意圖。PD SOI元件100係設置於一SOI基底110上,SOI基底110則包含有一基材112、一矽薄膜116、與一設置於基材112與矽薄膜116之間的BOX層114。PD SOI元件100更包含一閘極導電層120、一閘極介電層122與一源極/汲極124。PD SOI元件100的矽薄膜116厚度比空乏區要厚,因此使得其基底110的一區域未遭空乏且未接地,故一般將其描述為一浮動基體(floating body)126。且由於PD SOI元件100的基體126並未接地,因此元件因衝擊離子化而產生的電荷載子無法排除,並使得PD SOI元件100的基體電位可能隨著靜態、動態或暫態元件操作條件的不同而浮動,從而導致PD SOI元件100的臨界電壓的變化,即所謂的遲滯效應(hysteresis effect)或稱歷史效應(history effect)。簡單地說,PD SOI元件100的基體電位與元件特性深受開關狀態歷史之影響。According to the thickness of the germanium film on the BOX layer, the SOI technology can be further divided into partially depleted (PD SOI) or fully depleted (FD SOI). Due to the high productivity advantage, the more commonly used SOI technology is PD SOI. Please refer to FIG. 1 , which is a schematic diagram of a conventional PD SOI component. The PD SOI component 100 is disposed on an SOI substrate 110. The SOI substrate 110 includes a substrate 112, a germanium film 116, and a BOX layer 114 disposed between the substrate 112 and the germanium film 116. The PD SOI device 100 further includes a gate conductive layer 120, a gate dielectric layer 122, and a source/drain 124. The germanium film 116 of the PD SOI element 100 is thicker than the depletion region, thus leaving a region of its substrate 110 undeted and ungrounded, so it is generally described as a floating body 126. And since the base 126 of the PD SOI component 100 is not grounded, the charge carriers generated by the impact ionization of the component cannot be eliminated, and the base potential of the PD SOI component 100 may be related to static, dynamic or transient component operating conditions. It varies differently, resulting in a change in the threshold voltage of the PD SOI element 100, a so-called hysteresis effect or a history effect. Briefly, the base potential and component characteristics of the PD SOI component 100 are heavily affected by the state of the switch state.

如前所述,由於PD SOI元件100的基體126並未接地;且因PD SOI元件100的特性受到歷史效應影響甚鉅,因此目前仍無法將PD SOI元件100,尤其是基體未接地之浮體(FB)SOI元件,真實的特性如閘極對基體(gate-to-body)電容(Cgb )與閘極對基體穿隧電流(tunneling current,Igb )等特徵化。As described above, since the base 126 of the PD SOI element 100 is not grounded; and since the characteristics of the PD SOI element 100 are greatly affected by historical effects, the PD SOI element 100, especially the ungrounded floating body of the substrate, is still not available at present. (FB) SOI components, real characteristics such as gate-to-body capacitance (C gb ) and gate-to-substrate tunneling current (I gb ).

此外,由於在射頻(radio frequency,RF)元件中,閘極阻抗與閘極電容決定了MOSFET元件的輸入阻抗,因此能夠精確的量測閘極電容乃為RF電路模擬的關鍵。不僅如此,該領域中具通常知識者應知元件特性分析對於積體電路設計而言極為重要:可靠的元件模型必需來自精確的量測技術,且能從量測資料中萃取(extract)出待測元件的實際特性,以提供元件的製程與元件設計者快速而詳實的元件特性,作為進一步改良的依據。In addition, since the gate impedance and the gate capacitance determine the input impedance of the MOSFET component in a radio frequency (RF) component, accurate measurement of the gate capacitance is the key to RF circuit simulation. Moreover, those with ordinary knowledge in the field should be aware that component characterization is extremely important for integrated circuit design: reliable component models must come from accurate measurement techniques and can be extracted from measurement data. The actual characteristics of the component are measured to provide the component's process and the component designer's fast and detailed component characteristics as a basis for further improvement.

因此,本發明之一目的係在於提供一種可有效獲得FB SOI元件特性的特徵化方法以及應用於該特徵化方法的半導體元件。Accordingly, it is an object of the present invention to provide a characterization method that can effectively obtain the characteristics of an FB SOI element and a semiconductor element that is applied to the characterization method.

根據本發明所提供之申請專利範圍,係提供一種半導體元件特徵化方法,該方法首先提供一SOI基底,該SOI基底上設置有至少一主體可外接(body-tied)矽覆絕緣(BT SOI)元件與一主體可外接(BT)寄生元件,其中該BT寄生元件包含有一第一型源極/汲極重摻雜區域與一寄生閘極,且該寄生閘極不設置於該第一型源極/汲極重摻雜區域之上,隨後分別測量該BT SOI元件與該BT寄生元件的穿隧電流(Igb )與散射參數(scattering parameters,S參數),並利用該BT寄生元件之穿隧電流校正該BT SOI元件之穿隧電流,以獲得一浮體矽覆絕緣(FB SOI)元件之穿隧電流,再藉由一去嵌化技術從該BT SOI元件扣除該BT寄生元件之特性,以萃取出該FB SOI元件之S參數,最後計算分析該FB SOI元件之S參數而得到真正屬於該FB SOI元件之閘極相關電容值(Cgb )。According to the scope of the invention provided by the present invention, a semiconductor device characterization method is provided, which first provides an SOI substrate having at least one body-tied overlying insulation (BT SOI) disposed on the SOI substrate. The component and a body may be externally connected (BT) parasitic components, wherein the BT parasitic component comprises a first type source/drain heavily doped region and a parasitic gate, and the parasitic gate is not disposed on the first type source Above the pole/thin pole heavily doped region, the tunneling current (I gb ) and scattering parameters (S parameters) of the BT SOI element and the BT parasitic element are respectively measured and utilized by the BT parasitic element The tunneling current corrects the tunneling current of the BT SOI component to obtain a tunneling current of a floating body overlying insulation (FB SOI) component, and then deducts the characteristics of the BT parasitic component from the BT SOI component by a de-embedding technique To extract the S parameter of the FB SOI component, and finally calculate and analyze the S parameter of the FB SOI component to obtain the gate related capacitance value (C gb ) that truly belongs to the FB SOI component.

根據本發明所提供之申請專利範圍,更提供一種半導體元件,該半導體元件包含有一包含有一第二型井區之SOI基底、一設置於該第二型井區內之第一型源極/汲極重摻雜區域重摻雜區域、一設置於該SOI基底內且藉由該第二型井區與該第一型源極/汲極重摻雜區域隔離之第一型重摻雜區域、一設置於該第二型井區上且不跨越該源極/汲極重摻雜區域之寄生閘極、以及一與一電路電性連接之基體。According to the patent application scope provided by the present invention, there is further provided a semiconductor device comprising: an SOI substrate including a second type well region; and a first type source/汲 disposed in the second type well region a heavily doped region heavily doped region, a first type heavily doped region disposed within the SOI substrate and separated from the first type source/drain heavily doped region by the second type well region, a parasitic gate disposed on the second well region and not crossing the source/drain heavily doped region, and a substrate electrically connected to a circuit.

根據本發明所提供之半導體元件特徵化方法,係首揭利用去嵌化技術的觀念與寄生元件之設置去除BT SOI元件所帶來的寄生效應,並藉由S參數計算分析出FD SOI元件正確的Cgb 。另外,藉由寄生元件所提供的Igb ,係可校正BT SOI元件所量得之Igb ,並真正獲得該FD SOI元件的IgbAccording to the semiconductor device characterization method provided by the present invention, the concept of de-embedding technology and the setting of parasitic components are used to remove the parasitic effects caused by the BT SOI component, and the FD SOI component is correctly analyzed by the S-parameter calculation. C gb . Further, by I gb parasitic element is provided, based BT SOI element may be corrected to give an amount of I gb, and really get the FD SOI element I gb.

本發明所提供之半導體元件測量方法與應用於該方法之半導體元件適用於元件晶圓之切割道或於監控片(monitor wafer)表面製作之複數個測試鍵(test key)結構,亦即在進行晶粒上射頻元件之各項半導體製程的同時,便採用相同的步驟於晶圓切割道或監控片表面製作測試所需的半導體元件,來模擬晶粒上之相同製程。然後再利用探針(probe)等測試裝置接觸測試鍵,量測測試元件的各項參數,以獲得所需的測量資料,進而從測量資料中萃取出待測元件的實際特性。The semiconductor component measuring method provided by the present invention and the semiconductor component applied to the method are applicable to a dicing die of a component wafer or a plurality of test key structures fabricated on a surface of a monitor wafer, that is, in progress At the same time as the semiconductor process of the RF components on the die, the same steps are used to fabricate the semiconductor components required for the test on the wafer scribe or the surface of the monitor to simulate the same process on the die. Then, using a test device such as a probe to contact the test button, the parameters of the test component are measured to obtain the required measurement data, and the actual characteristics of the component to be tested are extracted from the measurement data.

請參閱第2圖與第3圖,第2圖係一測試用主體可外接(body-tied)矽覆絕緣元件(以下簡稱為BT SOI元件)之一第一較佳實施例之示意圖;第3圖為第2圖中BT SOI元件沿切線A-A’所獲得的一剖面示意圖。如前所述,BT SOI元件係於晶粒上RF元件之各項半導體製程的同時,即採用相同的步驟於晶圓之切割道或於監控片表面所製作而得,因此該等步驟係不再於此贅述。另外,本第一較佳實施例中之BT SOI元件係為一N型MOSFET元件,但熟習該項技藝之人士應知BT SOI元件亦不限為一P型BT SOI元件。而當BT SOI元件為P型時,熟習該項技藝之人士應知下述的N、P型摻雜質之利用即相反,故於此亦不再贅述。Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a schematic diagram of a first preferred embodiment of a body-tied overlying insulating component (hereinafter abbreviated as BT SOI component); The figure is a schematic cross-sectional view of the BT SOI element taken along the tangential line A-A' in Fig. 2. As described above, the BT SOI component is fabricated on the semiconductor process of the RF component on the die, that is, the same step is performed on the scribe line of the wafer or on the surface of the monitor sheet, so the steps are not I will repeat this. In addition, the BT SOI component in the first preferred embodiment is an N-type MOSFET component, but those skilled in the art should be aware that the BT SOI component is not limited to a P-type BT SOI component. When the BT SOI component is a P-type, those skilled in the art should be aware that the use of the N and P-type dopants described below is reversed and will not be described herein.

如第2圖與第3圖所示,本第一較佳實施例首先提供一BT SOI元件200,設置於一SOI基底210上。SOI基底210包含有一基材212、一埋置氧化(BOX)層214與一P型摻雜矽層216。基於氧化矽(SiO)材料優良的絕緣特性,以及易與矽晶圓製程的高整合性,BOX層214較佳為氧化矽層,但不限於此。P型摻雜矽層216內尚有一淺溝隔離(shallow trench isolation,STI)220與一P型井區230,且部分的P型井區230係作為BT SOI元件200之基體。BT SOI元件200具有一由氧化矽、氮化矽或其他高介電係數材料構成之閘極介電層240(示於第3圖),形成於基材210的表面上。而在閘極介電層240上,BT SOI元件200尚包含一T型的閘極結構242,閘極結構242具有一第一部246與一垂直於第一部246的第二部248,且第二部248係如第2圖所示,延伸並橫越P型井區230。第二部248兩側之P型井區230內,係設置一N型源極/汲極重摻雜區域244,值得注意的是,由於在佈植用以形成N型源極/汲極重摻雜區域244的摻雜質時,P型井區230上方的第二部248與部分的第一部246係作為一N型摻雜質的佈植遮罩,因此完成佈植之後第二部248與此部分的第一部246係具有N型摻雜質而形成一N型區域242a。另外,相對於N型區域242a之另一側,即遠離N型源極/汲極重摻雜區域244的部分第一部246則用以作為一P型摻雜質的佈植遮罩,因此該部分的第一部246便具有P型摻雜質而形成如第2圖與第3圖所示之P型區域242b。簡單地說,就結構型態而言,閘極結構242具有一第一部246以及一垂直於第一部246且橫跨P型井區230的第二部248;就摻雜型態而言,閘極結構242則具有一N型區域242a與一P型區域242b。另外,前述P型摻雜質佈植製程係於P型摻雜矽層216內形成一P型重摻雜區域232。BT SOI元件200更具有接觸插塞250、252、254(僅示於第2圖)。接觸插塞250係與閘極結構242下方的基體電性連接,接觸插塞252與閘極結構242電性連接,而接觸插塞254則與N型源極/汲極重摻雜區域244電性連接,是以測試用BT SOI元件200之元件特性如Cgb 以及Igb 可輕易量測並萃取獲得。As shown in FIG. 2 and FIG. 3, the first preferred embodiment first provides a BT SOI device 200 disposed on an SOI substrate 210. The SOI substrate 210 includes a substrate 212, a buried oxide (BOX) layer 214, and a P-type doped germanium layer 216. The BOX layer 214 is preferably a ruthenium oxide layer based on excellent insulating properties of yttrium oxide (SiO) material and high integration with the ruthenium wafer process, but is not limited thereto. There is a shallow trench isolation (STI) 220 and a P-type well region 230 in the P-type doped germanium layer 216, and a portion of the P-type well region 230 serves as a substrate for the BT SOI element 200. The BT SOI device 200 has a gate dielectric layer 240 (shown in FIG. 3) made of tantalum oxide, tantalum nitride or other high dielectric constant material formed on the surface of the substrate 210. On the gate dielectric layer 240, the BT SOI device 200 further includes a T-type gate structure 242 having a first portion 246 and a second portion 248 perpendicular to the first portion 246, and The second portion 248 extends and traverses the P-well region 230 as shown in FIG. An N-type source/drain heavily doped region 244 is disposed in the P-type well region 230 on both sides of the second portion 248. It is worth noting that the implant is used to form an N-type source/drain When doping the doping region 244, the second portion 248 above the P-well region 230 and a portion of the first portion 246 serve as an N-type doped implant mask, thus completing the second portion after implantation. 248 and the first portion 246 of this portion have an N-type dopant to form an N-type region 242a. In addition, a portion of the first portion 246 that is away from the N-type source/drain heavily doped region 244 is used as a P-type dopant implant mask on the other side of the N-type region 242a. The first portion 246 of the portion has a P-type dopant and forms a P-type region 242b as shown in FIGS. 2 and 3. Briefly, in terms of configuration, the gate structure 242 has a first portion 246 and a second portion 248 that is perpendicular to the first portion 246 and spans the P-well region 230; The gate structure 242 has an N-type region 242a and a P-type region 242b. In addition, the P-type dopant implantation process is formed in the P-type doped germanium layer 216 to form a P-type heavily doped region 232. The BT SOI element 200 further has contact plugs 250, 252, 254 (shown only in Figure 2). The contact plug 250 is electrically connected to the base under the gate structure 242, the contact plug 252 is electrically connected to the gate structure 242, and the contact plug 254 is electrically connected to the N-type source/drain heavily doped region 244. The sexual connection is obtained by measuring and extracting the component characteristics of the test BT SOI element 200 such as C gb and I gb .

然而,由於T型閘極結構242之第一部246同時具有N型區域242a與P型區域242b,因此會扭曲(distort)實際上有效用的第二部248的特性如Cgb 與Igb 的量測結果。換句話說,雖然藉由BT SOI元件200的量測結果可萃取出所欲獲得的元件特性,但實際上T型閘極結構242之第一部246因同時具有N型區域242a與P型區域242b反而造成FB SOI元件測量時之一影響甚鉅的寄生(parasite)效應,而無法反映實際FB SOI元件之特性。However, since the first portion 246 of the T-type gate structure 242 has both the N-type region 242a and the P-type region 242b, it can distort the characteristics of the second portion 248 that are actually effective, such as C gb and I gb Measurement results. In other words, although the characteristics of the element to be obtained can be extracted by the measurement result of the BT SOI element 200, the first portion 246 of the T-type gate structure 242 has both the N-type region 242a and the P-type region 242b. On the contrary, it causes a parasite effect that is greatly affected by the measurement of the FB SOI component, and does not reflect the characteristics of the actual FB SOI component.

接下來請參閱第4圖與第5圖,第4圖係第一較佳實施 例所提供之一測試用主體可外接(BT)寄生(dummy)元件300之示意圖;第5圖則為第4圖中寄生元件沿切線B-B’所獲得的一剖面示意圖。如前所述,本第一較佳實施例所提供之BT寄生元件300係與晶粒上RF元件以及前述BT SOI元件200形成時同步於晶圓之切割道或於監控片表面所製作而得,故該等步驟亦於此省略。Next, please refer to FIG. 4 and FIG. 5, and FIG. 4 is a first preferred embodiment. For example, one of the test subjects can be externally connected to the (BT) dummy element 300; and the fifth figure is a schematic cross-sectional view of the parasitic element taken along the tangential line B-B' in FIG. As described above, the BT parasitic element 300 provided in the first preferred embodiment is formed when the RF element on the die and the BT SOI component 200 are formed in synchronization with the scribe line of the wafer or on the surface of the monitor sheet. Therefore, these steps are also omitted here.

如第4圖所示,與BT SOI元件200相同,BT寄生元件300係設置於SOI基底210上。BT寄生元件300更具有一虛設閘極342;與BT SOI元件200不同的是,BT寄生元件300並不像BT SOI元件200具有跨越P型井區230的有效的第二部248,亦即虛設閘極342與T型閘極結構242具有不同之佈局圖案。然而BT寄生元件300仍然維持與BT SOI元件200相同條件的佈植圖案,且經歷形成N型源極/汲極重摻雜區域244的佈植步驟,故摻雜質會進入原來的P型井區230與虛設閘極342,而分別形成如第5圖所示的N型源極/汲極重摻雜區域重摻雜區域244與N型區域342a。同樣地,BT寄生元件300亦經歷P型摻雜質佈植製程,而形成一P型區域342b,而同時於原來的P型摻雜矽層216內形成一P型重摻雜區域232,且P型重摻雜區域232係藉由P型井區230與N型源極/汲極重摻雜區域244隔離。由此可知BT寄生元件300之虛設閘極342與BT SOI元件200之閘極結構242的第一部246相同,但BT寄生元件300之虛 設閘極342並不跨越N型源極/汲極重摻雜區域244。此外,BT寄生元件300具有接觸插塞350、352,接觸插塞350係與基體電性連接;而接觸插塞352則與N型源極/汲極重摻雜區域244電性連接,是以BT寄生元件300可提供虛設閘極342對基體的相關特性。As shown in FIG. 4, the BT parasitic element 300 is disposed on the SOI substrate 210, like the BT SOI element 200. The BT parasitic element 300 further has a dummy gate 342; unlike the BT SOI element 200, the BT parasitic element 300 does not have an effective second portion 248 across the P-well region 230, as is the BT SOI element 200. Gate 342 and T-type gate structure 242 have different layout patterns. However, the BT parasitic element 300 still maintains the implant pattern of the same conditions as the BT SOI element 200, and undergoes the implantation step of forming the N-type source/drain heavily doped region 244, so that the dopant enters the original P-well. The region 230 and the dummy gate 342 form an N-type source/drain heavily doped region heavily doped region 244 and an N-type region 342a as shown in FIG. 5, respectively. Similarly, the BT parasitic element 300 also undergoes a P-type dopant implantation process to form a P-type region 342b while simultaneously forming a P-type heavily doped region 232 in the original P-type doped germanium layer 216, and The P-type heavily doped region 232 is isolated from the N-type source/drain heavily doped region 244 by a P-type well region 230. It can be seen that the dummy gate 342 of the BT parasitic element 300 is the same as the first portion 246 of the gate structure 242 of the BT SOI element 200, but the BT parasitic element 300 is virtual. It is assumed that the gate 342 does not span the N-type source/drain heavily doped region 244. In addition, the BT parasitic element 300 has contact plugs 350 and 352, and the contact plug 350 is electrically connected to the base; and the contact plug 352 is electrically connected to the N-type source/drain heavily doped region 244. The BT parasitic element 300 can provide the relevant characteristics of the dummy gate 342 to the substrate.

請參閱第6圖,第6圖係本第一較佳實施例所提供之半導體元件之測量方法之一流程示意圖。如第6圖所示,本半導體元件之測量方法包含有以下步驟:400:提供測試用的BT SOI元件200與主體可外接(BT)寄生元件300;402:分別測量BT SOI元件與BT寄生元件的穿隧電流與散射參數(scattering parameter,S參數);404:藉由去嵌化(de-embedding)技術從BT SOI元件扣除BT寄生元件之特性,以萃取出浮體矽覆絕緣(FB SOI)元件之S參數;406:計算分析該FB SOI元件之S參數,而得到該FB SOI元件之閘極相關電容值CgbPlease refer to FIG. 6. FIG. 6 is a schematic flow chart of a method for measuring a semiconductor device according to the first preferred embodiment. As shown in FIG. 6, the measuring method of the semiconductor device includes the following steps: 400: providing a BT SOI component 200 for testing and a BT external parasitic component 300; 402: measuring a BT SOI component and a BT parasitic component, respectively. Tunneling current and scattering parameter (S parameter); 404: deducting the characteristics of the BT parasitic element from the BT SOI component by de-embedding technique to extract the floating body insulation (FB SOI) The S parameter of the component; 406: Calculating and analyzing the S parameter of the FB SOI component, and obtaining the gate related capacitance value C gb of the FB SOI component.

根據本發明所提供之測量方法,BT寄生元件300之虛設閘極342係與BT SOI元件200中造成量測結果扭曲的T型閘極結構242之第一部246相同,故BT寄生元件300所提 供的虛設閘極342對基體的相關特性可視為相當於第一部246。因此本發明更利用去嵌化技術輔以適用的軟體去除待測元件的寄生成分,即利用BT寄生元件300之設置去除BT SOI元件200中T型閘極結構242頭部,即同時具有N型區域242a與P型區域242b之第一部246,實際上所產生的寄生效應。由於本發明所提供之半導體元件之測量方法係可有效地去除第一部246之寄生效應,輔以如熟習該領域之人士所知,藉由S參數與導納參數(admittance parameter,Y-parameter,Y參數)或阻抗參數(impedance parameter,Z參數)之轉換等方法,係可計算分析得到FB SOI元件之閘極對基體正確的之電容值Cgb 。另外,藉由BT寄生元件300所提供的Igb ,係可校正BT SOI元件200所量得之Igb ,並真正獲得FB SOI元件的IgbAccording to the measurement method provided by the present invention, the dummy gate 342 of the BT parasitic element 300 is the same as the first portion 246 of the T-type gate structure 242 which causes the measurement result to be distorted in the BT SOI element 200, so the BT parasitic element 300 The associated characteristics of the dummy gate 342 provided to the substrate can be considered equivalent to the first portion 246. Therefore, the present invention further utilizes the de-embedding technique to supplement the parasitic component of the device under test with the applicable software, that is, the head of the T-type gate structure 242 in the BT SOI device 200 is removed by the setting of the BT parasitic element 300, that is, the N-type is simultaneously provided. The first portion 246 of the region 242a and the P-type region 242b actually produces parasitic effects. Since the measurement method of the semiconductor device provided by the present invention can effectively remove the parasitic effect of the first portion 246, supplemented by an S parameter and an admittance parameter (Y-parameter), as known to those skilled in the art. , Y parameter) or impedance parameter (Z parameter) conversion method, etc., can be calculated and analyzed to obtain the correct capacitance value C gb of the gate of the FB SOI component to the substrate. Further, by I gb BT parasitic element 300 is provided, based BT SOI element may be corrected to give an amount of 200 I gb, and really get FB SOI element I gb.

請參閱第7圖與第8圖,第7圖為N型BT SOI元件與經由本方法所獲得的N型FB SOI元件之Cgb 比較圖;第8圖則為P型BT SOI元件與經由本方法所獲得的P型FB SOI元件之Cgb 比較圖。如第7圖所示,與真正的N型FB SOI元件相較,N型BT SOI元件所提供的Cgb 常因T型閘極結構之頭部(如第一較佳實施例之第一部246)的寄生效應導致高估(over-estimated)的情形。而如第8圖所示,與真正的P型FB SOI元件相較,P型BT SOI元件則因相同的原因導致所提供的Cgb 低估(under-estimated)。也就是說,根據本第 一較佳實施例所提供之方法,便可有效地去除待測元件的寄生成分,而得到所欲取得的實際特性。Please refer to FIG. 7 and FIG. 8. FIG. 7 is a comparison diagram of C gb of the N-type BT SOI element and the N-type FB SOI element obtained by the method; FIG. 8 is a P-type BT SOI element and the same The C gb comparison chart of the P-type FB SOI element obtained by the method. As shown in Figure 7, the C gb provided by the N-type BT SOI element is often due to the head of the T-type gate structure as compared to a true N-type FB SOI element (as in the first part of the first preferred embodiment) The parasitic effect of 246) leads to an over-estimated situation. As shown in FIG. 8 and, compared with the P-type real FB SOI element, P-type BT SOI elements due to the same cause underestimation C gb provided (under-estimated). That is to say, according to the method provided by the first preferred embodiment, the parasitic component of the device to be tested can be effectively removed to obtain the actual characteristics to be obtained.

接下來請參閱第9圖至第12圖,第9圖為N型BT SOI元件的Igb 與閘極電壓(Vgb )之曲線圖;第10圖則為經由本方法所獲得的N型FB SOI元件之Igb 與Vgb 之曲線圖。而第11圖為P型BT SOI元件所量測的Igb 與Vgb 之曲線圖;第12圖則為經由本方法所獲得的P型FB SOI元件之Igb 與Vgb 之曲線圖。根據上述曲線圖所示,可發現經由本發明所提供之測量方法,可發現不論是N型或P型的BT SOI元件,其Igb 的確與實際FB SOI元件的Igb 不同。也就是說,藉由寄生元件300所提供的Igb ,的確可校正BT SOI元件200所量得之Igb ,並獲得真正的FB SOI的IgbNext, please refer to FIG. 9 to FIG. 12, FIG. 9 is a graph of I gb and gate voltage (V gb ) of the N-type BT SOI element; and FIG. 10 is an N-type FB obtained by the method. A plot of I gb and V gb of the SOI element. Figure 11 is a graph of I gb and V gb measured by a P-type BT SOI element; and Figure 12 is a graph of I gb and V gb of a P-type FB SOI element obtained by the method. According to the graph, it can be found by the measurement method of the present invention to provide, whether it is found to be N-type or P-type BT SOI element, which indeed I gb I gb actual FB SOI with different elements. That is, by I gb parasitic element 300 is provided, can indeed correct amount BT SOI element 200 of I gb obtained, and the obtained real FB SOI I gb.

請參閱第13圖與第14圖,第13圖係第二較佳實施例所提供之一測試用BT SOI元件之一示意圖;第14圖則為第二較佳實施例所提供之一測試用主體可外接(BT)寄生元件600之示意圖。由於線性基體電阻(linear body resistance,RB )係由元件寬度(W)與閘極長度(L)的函數決定,因此SOI技術中亦有形成H型閘極以降低線性基體電阻,避免阻值過大造成斷路的作法。且由於H型閘極具有較低的電阻以及較佳的跨導(transconductance),因此與T型閘極相比,H型閘極具有較大截止頻率(cutoff frequency)、較低最小雜訊指數 (minimum noise figure)、以及較佳的射頻性能(RF performance)。當晶圓內製作的FB SOI元件具有H型閘極時,即於晶圓切割道或於監控片表面採用相同的步驟製作而得到本第二較佳實施例所提供之一BT SOI元件500,以模擬晶粒上之相同製程及元件,故第13圖所示之BT SOI元件500亦具有一H型閘極。此外第二較佳實施例中之BT SOI元件500與BT寄生元件600亦為一N型元件,但熟習該項技藝之人士應知該等元件亦不限為一P型元件。而當該等元件為P型時,熟習該項技藝之人士應知下述的N、P型摻雜質之利用即相反,故於此亦不再贅述。另外,第二較佳實施例中各元件之材料係同於第一較佳實施例,故亦可參閱前述第一較佳實施例所揭露者。Please refer to FIG. 13 and FIG. 14 , FIG. 13 is a schematic diagram of one of the test BT SOI components provided by the second preferred embodiment; and FIG. 14 is a test for the second preferred embodiment. The body can be externally connected to the (BT) parasitic element 600. Since the linear body resistance (R B ) is determined by the function of the element width (W) and the gate length (L), an H-type gate is also formed in the SOI technique to reduce the linear matrix resistance and avoid the resistance. Too big to cause an open circuit. And because the H-type gate has lower resistance and better transconductance, the H-type gate has a larger cutoff frequency and a lower minimum noise index than the T-type gate. (minimum noise figure), and better RF performance. When the FB SOI element fabricated in the wafer has an H-type gate, the BT SOI element 500 provided by the second preferred embodiment is obtained by the same steps on the wafer dicing street or on the surface of the monitor sheet. In order to simulate the same process and components on the die, the BT SOI component 500 shown in FIG. 13 also has an H-type gate. In addition, the BT SOI component 500 and the BT parasitic component 600 in the second preferred embodiment are also an N-type component, but those skilled in the art will recognize that such components are not limited to a P-type component. When the components are of the P type, those skilled in the art should be aware that the use of the N and P type dopants described below is reversed and will not be described herein. In addition, the materials of the components in the second preferred embodiment are the same as those in the first preferred embodiment. Therefore, reference may also be made to the first preferred embodiment.

如第13圖所示,BT SOI元件500係設置於一SOI基底510上,其包含一H型的閘極結構542;H型閘極結構542包含一對平行之第一部546以及一垂直於第一部546之第二部548,且第二部548係延伸並橫越一P型井區(圖未示)。在第二部548兩側之P型井區內形成有一N型源極/汲極重摻雜區域544。BT SOI元件亦包含有一P型重摻雜區域(圖未示),其藉由P型井區與N型源極/汲極重摻雜區域544隔離。而用以作為佈植遮罩的閘極結構542第二部548與部分第一部546的閘極結構542係具有N型摻雜質而形成一N型區域542a;另外遠離N型源極/汲極重摻雜區域544之部 分第一部546則會形成一P型區域542b。簡單地說,就結構型態而言,閘極結構542具有一對互相平行的第一部546以及一垂直於第一部546且橫跨P型井區的第二部548;就摻雜型態而言,閘極結構542則具有一N型區域542a與一P型區域542b。BT SOI元件500更具有接觸插塞550、552,接觸插塞550係與基體電性連接;而接觸插塞552則與源極/汲極重摻雜區域544電性連接,是以測試用BT SOI元件500之元件特性如Cgb 以及Igb 可輕易量測並萃取獲得。As shown in FIG. 13, the BT SOI device 500 is disposed on an SOI substrate 510 and includes an H-type gate structure 542. The H-type gate structure 542 includes a pair of parallel first portions 546 and a vertical The second portion 548 of the first portion 546 extends and traverses a P-type well region (not shown). An N-type source/drain heavily doped region 544 is formed in the P-type well region on both sides of the second portion 548. The BT SOI device also includes a P-type heavily doped region (not shown) that is isolated from the N-type source/drain heavily doped region 544 by a P-type well region. The gate structure 542 of the gate structure 542 and the portion of the first portion 546 of the gate structure 542 used as the implant mask have an N-type doping to form an N-type region 542a; and further away from the N-type source/ A portion of the first portion 546 of the heavily doped region 544 will form a P-type region 542b. Briefly, in terms of structural form, the gate structure 542 has a pair of first portions 546 that are parallel to each other and a second portion 548 that is perpendicular to the first portion 546 and spans the P-type well region; In other words, the gate structure 542 has an N-type region 542a and a P-type region 542b. The BT SOI component 500 further has contact plugs 550, 552, and the contact plug 550 is electrically connected to the base; and the contact plug 552 is electrically connected to the source/drain heavily doped region 544, which is a test BT. The component characteristics of the SOI element 500 such as C gb and I gb can be easily measured and extracted.

接下來請參閱第14圖。如前所述,由於第一部546的N型區域542a與P型區域542b的存在,會扭曲實際上有效用的N型區域542a的特性如Cgb 與Igb 的量測。因此,第二較佳實施例更提供之一BT寄生元件600。與BT SOI元件500相同,BT寄生元件600係設置於SOI基底510上。BT寄生元件600更具有一虛設閘極642;與BT SOI元件500不同的是,虛設閘極642係為一對平行的閘極結構;而不像BT SOI元件500具有跨越P型井區的有效的第二部548。然而BT虛設元件600亦具有N型源極/汲極重摻雜區域544與P型重摻雜區域,且P型重摻雜區域係藉由P型井區與N型源極/汲極重摻雜區域544隔離。同理,作為佈植遮罩的虛設閘極642在靠近N型源極/汲極重摻雜區域544形成一N型區域642a;在靠近P型重摻雜區域的一側會形成一P型區域642b。由此可知BT虛設元件600之虛設閘極642係與BT SOI 元件500之第一部546相同,但BT SOI元件600之虛設閘極642並不跨越N型源極/汲極重摻雜區域544。此外,BT寄生元件600具有接觸插塞650、652,接觸插塞650係與基體電性連接;而接觸插塞652則與N型源極/汲極重摻雜區域544電性連接,是以BT寄生元件600可提供虛設閘極642對基體的相關特性。Next, please refer to Figure 14. As previously mentioned, due to the presence of the N-type region 542a and the P-type region 542b of the first portion 546, the characteristics of the substantially effective N-type region 542a such as C gb and I gb can be distorted. Therefore, the second preferred embodiment further provides a BT parasitic element 600. Like the BT SOI element 500, the BT parasitic element 600 is disposed on the SOI substrate 510. The BT parasitic element 600 further has a dummy gate 642; unlike the BT SOI element 500, the dummy gate 642 is a pair of parallel gate structures; unlike the BT SOI element 500, which has an effective span across the P-type well region. The second part of 548. However, the BT dummy device 600 also has an N-type source/drain heavily doped region 544 and a P-type heavily doped region, and the P-type heavily doped region is heavily weighted by the P-type well region and the N-type source/drain The doped region 544 is isolated. Similarly, the dummy gate 642 as the implant mask forms an N-type region 642a near the N-type source/drain heavily doped region 544; a P-type is formed on the side near the P-type heavily doped region. Area 642b. It can be seen that the dummy gate 642 of the BT dummy device 600 is the same as the first portion 546 of the BT SOI device 500, but the dummy gate 642 of the BT SOI device 600 does not span the N-type source/drain heavily doped region 544. . In addition, the BT parasitic element 600 has contact plugs 650, 652, and the contact plug 650 is electrically connected to the base; and the contact plug 652 is electrically connected to the N-type source/drain heavily doped region 544. The BT parasitic element 600 can provide the relevant characteristics of the dummy gate 642 to the substrate.

請重新參閱第6圖,由於第二較佳實施例所提供之半導體元件之測量方法各步驟係與第一較佳實施例相同,因此該等步驟係可參閱第6圖及上述說明。Please refer to FIG. 6 again. Since the steps of the measurement method of the semiconductor device provided by the second preferred embodiment are the same as those of the first preferred embodiment, the steps can be referred to FIG. 6 and the above description.

此外值得注意的是,由於所欲獲得的Igb 與Cgb 非常微小,因此本發明所提供之測量方法中,測試用BT SOI元件200/500與BT虛設元件300/600較佳可以射頻測試鍵(radio frequency,RF test key)結構建構,以增加Igb 與Cgb 的測量精準度。請參閱第17圖,其為本發明所提供之一RF測試鍵之示意圖。如第17圖所示,RF測試鍵700係設置於基材210/510上,其中央位置係設置待測元件710如BT SOI元件200/500或BT虛設元件300/600,且待測元件710具有一閘極連接端712、一源極連接端714、一汲極連接端716與一基體連接端718,而該等連接端則依序分別電性連接至待測元件710之閘極、源極、汲極與基體。RF測試鍵700包含有一底部金屬層,底部金屬層則具有一前區塊722、一右區塊724、一 後區塊726與一左區塊728環繞設置於待測元件710四周,且依序與閘極連接端712、源極連接端714、汲極連接端716基體連接端718電性連接。另外,前區塊722與後區塊726更分別具有一前訊號墊742與一後訊號墊746,用以與探針連接。It is also worth noting that, since the desired and obtained I gb C gb very small, the measurement method of the present invention is provided in the test dummy BT BT 200/500 and the SOI elements as RF test key may be preferred 300/600 (radio frequency, RF test key) structure construction to increase the measurement accuracy of I gb and C gb . Please refer to FIG. 17, which is a schematic diagram of an RF test key provided by the present invention. As shown in FIG. 17, the RF test button 700 is disposed on the substrate 210/510, and the central position thereof is a device 710 such as a BT SOI device 200/500 or a BT dummy device 300/600, and the device to be tested 710 is disposed. The device has a gate connection end 712, a source connection end 714, a drain connection end 716 and a base connection end 718, and the connection ends are electrically connected to the gate and source of the device under test 710. Pole, bungee and substrate. The RF test button 700 includes a bottom metal layer, and the bottom metal layer has a front block 722, a right block 724, a rear block 726, and a left block 728 disposed around the device to be tested 710, and sequentially. The base connection end 712, the source connection end 714, and the drain connection end 716 are connected to the base connection end 718. In addition, the front block 722 and the rear block 726 further have a front signal pad 742 and a rear signal pad 746 for connecting with the probe.

RF測試鍵結構700更具有一位於底部金屬層上方之頂部金屬層,且頂部金屬層與底部金屬層之間則另設有一未示於第17圖中之介電層。頂部金屬層包含有右金屬片764與左金屬片768,分別利用導電插塞(via plug)穿過介電層以分別電性連接至底部金屬層之右區塊724與左區塊728。右金屬片764與左金屬片768各為一狹長之金屬片,且互相平行。在右金屬片764之前端定義有一接地墊764a;後端則定義有另一接地墊764b。左金屬片768之前端定義有一接地墊768a;後端亦定義有另一接地墊768b。另外如第17圖所示,接地墊768a、前訊號墊742與接地墊764a係排列成一前排連接區域;而接地墊768b、後訊號墊746與接地墊764b則排列成一後排連接區域,即前後排連接區域由左至右依序為接地墊區域、訊號墊區域、接地墊區域(G-S-G)。如此一來,探針卡之探針就可分別接觸於射頻測試鍵700之前排連接區域與後排連接區域,進行待測元件710之測試。The RF test key structure 700 further has a top metal layer above the bottom metal layer, and a dielectric layer not shown in FIG. 17 is further disposed between the top metal layer and the bottom metal layer. The top metal layer includes a right metal piece 764 and a left metal piece 768, respectively, through a dielectric layer through a via plug to electrically connect to the right block 724 and the left block 728 of the bottom metal layer, respectively. The right metal piece 764 and the left metal piece 768 are each an elongated metal piece and are parallel to each other. A ground pad 764a is defined at the front end of the right metal piece 764; another ground pad 764b is defined at the rear end. A ground pad 768a is defined at the front end of the left metal piece 768; another ground pad 768b is defined at the rear end. In addition, as shown in FIG. 17, the ground pad 768a, the front signal pad 742 and the ground pad 764a are arranged in a front row connection region; and the ground pad 768b, the rear signal pad 746 and the ground pad 764b are arranged in a rear row connection region, that is, The front and rear row connection areas are the ground pad area, the signal pad area, and the ground pad area (GSG) from left to right. In this way, the probe of the probe card can respectively contact the connection area of the front row and the connection area of the rear row of the RF test button 700 to perform the test of the device to be tested 710.

綜上所述,本發明係首揭利用去嵌化技術的觀念與虛設 元件之設置去除BT SOI元件所帶來的寄生效應,並藉由Y參數、Z參數的轉換分析出浮體電晶體元件正確的Cgb 。另外,藉由BT寄生元件所提供的Igb ,係可校正BT SOI元件所量得之Igb ,並真正獲得浮體電晶體的IgbIn summary, the present invention firstly utilizes the concept of de-embedding technology and the setting of dummy components to remove parasitic effects caused by BT SOI components, and analyzes floating-body transistor components by conversion of Y-parameters and Z-parameters. The correct C gb . In addition, the I gb provided by the BT parasitic element can correct the I gb measured by the BT SOI element and truly obtain the I gb of the floating body transistor.

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧部分空乏矽覆絕緣元件100‧‧‧Some dry and covered insulation components

110‧‧‧SOI基底110‧‧‧SOI substrate

112‧‧‧基材112‧‧‧Substrate

114‧‧‧埋置氧化層114‧‧‧Embedded oxide layer

116‧‧‧矽薄膜116‧‧‧矽film

120‧‧‧閘極導電層120‧‧‧ gate conductive layer

122‧‧‧閘極介電層122‧‧‧ gate dielectric layer

124‧‧‧源極/汲極124‧‧‧Source/Bungee

126‧‧‧基體126‧‧‧ base

200、500‧‧‧主體可外接矽覆絕緣元件200, 500‧‧‧ body can be externally covered with insulating elements

210‧‧‧SOI基底210‧‧‧SOI substrate

212‧‧‧基材212‧‧‧Substrate

214‧‧‧埋置氧化層214‧‧‧ buried oxide layer

216‧‧‧P型摻雜矽層216‧‧‧P-type doped layer

220‧‧‧淺溝隔離220‧‧‧Shallow trench isolation

230‧‧‧P型井區230‧‧‧P type well area

232‧‧‧P型重摻雜區域232‧‧‧P type heavily doped area

240‧‧‧閘極介電層240‧‧‧ gate dielectric layer

242、542‧‧‧閘極結構242, 542‧‧ ‧ gate structure

242a、542a‧‧‧N型區域242a, 542a‧‧‧N-type area

242b、542b‧‧‧P型區域242b, 542b‧‧‧P type area

244、544‧‧‧N型源極/汲極重摻雜區域244, 544‧‧‧N type source/drain heavily doped regions

246、546‧‧‧第一部246, 546‧‧‧ first

248、548‧‧‧第二部248, 548‧‧‧ second

250、252、254、550、552‧‧‧接觸插塞250, 252, 254, 550, 552‧‧‧ contact plugs

300、600‧‧‧主體可外接寄生元件300, 600‧‧‧ body can be connected to parasitic components

342、642‧‧‧虛設閘極342, 642‧‧‧Dummy gate

342a、642a‧‧‧N型區域342a, 642a‧‧‧N-type area

342b、642b‧‧‧P型區域342b, 642b‧‧‧P type area

350、352、650、652‧‧‧接觸插塞350, 352, 650, 652‧‧‧ contact plugs

400‧‧‧提供測試用的BT SOI元件與BT寄生元件400‧‧‧Providing BT SOI components and BT parasitic components for testing

402‧‧‧分別測量BT SOI元件與BT寄生元件的穿隧電 流與S參數402‧‧‧Measure the tunneling power of BT SOI components and BT parasitic components respectively Flow and S parameters

404‧‧‧藉由去嵌化技術從BT SOI元件扣除該BT寄生元件之特性,以萃取出一浮體矽覆絕緣(FB SOI)元件之S參數404‧‧‧Deducting the characteristics of the BT parasitic element from the BT SOI component by de-embedding technology to extract the S-parameter of a floating body-covered insulation (FB SOI) component

406‧‧‧計算分析該FB SOI元件之S參數,而得到該FB SOI元件之閘極對基體之電容值Cgb 406‧‧‧ Calculate and analyze the S-parameter of the FB SOI component, and obtain the capacitance value C gb of the gate-to-base of the FB SOI component

700‧‧‧射頻測試鍵700‧‧‧RF test button

710‧‧‧待測元件710‧‧‧Device under test

712‧‧‧閘極連接端712‧‧‧ gate connection

714‧‧‧源極連接端714‧‧‧Source connection

716‧‧‧汲極連接端716‧‧‧汲 connection

718‧‧‧基體連接端718‧‧‧ base connection

722‧‧‧前區塊722‧‧‧前 block

724‧‧‧右區塊724‧‧‧Right block

726‧‧‧後區塊726‧‧‧After block

728‧‧‧左區塊728‧‧‧Left block

742‧‧‧前訊號墊742‧‧‧Pre-signal pad

746‧‧‧後訊號墊746‧‧‧ After signal pad

764‧‧‧右金屬片764‧‧‧right metal piece

764a、764b‧‧‧接地墊764a, 764b‧‧‧ grounding mat

768‧‧‧左金屬片768‧‧‧left metal piece

768a、768b‧‧‧接地墊768a, 768b‧‧‧ grounding mat

第1圖為一習知PD SOI元件之示意圖。Figure 1 is a schematic diagram of a conventional PD SOI component.

第2圖為一測試用主體可外接(BT)SOI元件之一第一較佳實施例之示意圖。Figure 2 is a schematic illustration of a first preferred embodiment of a test body externally connectable (BT) SOI component.

第3圖為第2圖中BT SOI元件沿切線A-A’所或的的一剖面示意圖。Fig. 3 is a schematic cross-sectional view of the BT SOI element taken along line A-A' in Fig. 2.

第4圖為第一較佳實施例中一測試用BT寄生元件。Figure 4 is a BT parasitic element for testing in the first preferred embodiment.

第5圖為第4圖中BT寄生元件沿切線B-B’所或的的一剖面示意圖之佈局圖。Fig. 5 is a plan view showing a cross-sectional view of the BT parasitic element along the tangential line B-B' in Fig. 4.

第6圖為本第一較佳實施例所提供之半導體元件之測量方法之一流程示意圖。FIG. 6 is a schematic flow chart showing a method of measuring a semiconductor device according to the first preferred embodiment.

第7圖為N型BT SOI元件與經由本方法所獲得的N型FB SOI元件之Cgb 比較圖。Figure 7 is a comparison of the C gb of the N-type BT SOI element and the N-type FB SOI element obtained by the method.

第8圖為P型BT SOI元件與經由本方法所獲得的P型FB SOI元件之Cgb 比較圖。Figure 8 is a comparison of the C gb of the P-type BT SOI element and the P-type FB SOI element obtained by the method.

第9圖為一N型BT SOI元件的穿隧電流(Igb )與閘極電壓(Vgb )之曲線圖。Figure 9 is a graph of tunneling current (I gb ) and gate voltage (V gb ) for an N-type BT SOI device.

第10圖為經由本方法所獲得的一N型FB SOI元件之Igb 與Vgb 之曲線圖。Figure 10 is a graph of I gb and V gb of an N-type FB SOI element obtained by the method.

第11圖為一P型BT SOI元件所量測的Igb 與Vgb 之曲線圖。Figure 11 is a graph of I gb and V gb measured by a P-type BT SOI device.

第12圖為經由本方法所獲得的一P型FB SOI元件之Igb 與Vgb 之曲線圖。Figure 12 is a graph of I gb and V gb of a P-type FB SOI element obtained by the method.

第13圖為一測試用BT SOI元件之一第二較佳實施例之示意圖。Figure 13 is a schematic illustration of a second preferred embodiment of a test BT SOI component.

第14圖為第二較佳實施例所提供之一測試用BT寄生元件之示意圖。Figure 14 is a schematic illustration of one of the test BT parasitic elements provided in the second preferred embodiment.

第15圖為本發明所提供之一RF測試鍵之示意圖。Figure 15 is a schematic diagram of one of the RF test keys provided by the present invention.

400...提供測試用的BT SOI元件與BT寄生元件400. . . Provides BT SOI components and BT parasitic components for testing

402...分別測量BT SOI元件與BT寄生元件的穿隧電流與S參數402. . . Measuring the tunneling current and S-parameters of BT SOI components and BT parasitic components, respectively

404...藉由去嵌化技術從BT SOI元件扣除該BT寄生元件之特性,以萃取出一浮體矽覆絕緣(FB SOI)元件之S參數404. . . Deducting the characteristics of the BT parasitic element from the BT SOI component by de-embedding technology to extract the S-parameter of a floating body-covered insulating (FB SOI) component

406...計算分析該FB SOI元件之S參數,而得到該FB SOI元件之閘極相關電容值Cgb 406. . . Calculating and analyzing the S parameter of the FB SOI component, and obtaining the gate related capacitance value C gb of the FB SOI component

Claims (20)

一種半導體元件測量方法,包含有以下步驟:提供一矽覆絕緣(silicon-on-insulator,SOI)基底,該SOI基底上設置有至少一主體可外接(body-tied)矽覆絕緣(BT SOI)元件與一主體可外接(BT)寄生元件,其中該BT寄生元件包含有一第一型源極/汲極重摻雜區域與一寄生閘極,且該寄生閘極不設置於該第一型源極/汲極重摻雜區域之上;分別測量該BT SOI元件與該BT寄生元件的穿隧電流(Igb )與散射參數(scattering parameter,S參數);利用該BT寄生元件之穿隧電流校正該BT SOI元件之穿隧電流,以獲得一浮體矽覆絕緣(floating body,BT SOI)元件之穿隧電流;藉由去嵌化技術從該BT SOI元件扣除該BT寄生元件之特性,以萃取出該FB SOI元件之S參數;以及計算分析該FB SOI元件之S參數而得到該FB SOI元件之閘極相關電容值(Cgb )。A semiconductor component measuring method comprising the steps of: providing a silicon-on-insulator (SOI) substrate having at least one body-tied overlying insulation (BT SOI) disposed on the SOI substrate The component and a body may be externally connected (BT) parasitic components, wherein the BT parasitic component comprises a first type source/drain heavily doped region and a parasitic gate, and the parasitic gate is not disposed on the first type source Above the pole/thin pole heavily doped region; measuring tunneling current (I gb ) and scattering parameter (S parameter) of the BT SOI element and the BT parasitic element, respectively; using tunneling current of the BT parasitic element Correcting a tunneling current of the BT SOI component to obtain a tunneling current of a floating body (BT SOI) component; deducting a characteristic of the BT parasitic component from the BT SOI component by a de-embedding technique, Extracting the S parameter of the FB SOI component; and calculating and analyzing the S parameter of the FB SOI component to obtain a gate related capacitance value (C gb ) of the FB SOI component. 如申請專利範圍第1項所述之測量方法,其中該BT SOI元件與該BT寄生元件係利用相同的步驟同時形成於該SOI基底上。 The measuring method according to claim 1, wherein the BT SOI element and the BT parasitic element are simultaneously formed on the SOI substrate by the same steps. 如申請專利範圍第1項所述之測量方法,其中該SOI基 底包含有複數個第二型井區。 The measuring method according to claim 1, wherein the SOI group The bottom contains a plurality of second well zones. 如申請專利範圍第3項所述之測量方法,其中該BT SOI元件包含有:一閘極結構,設置於該第二型井區上;至少一第一型源極/汲極重摻雜區域,形成於該第二型井區內;一第二型重摻雜區域,形成於該SOI基底內,且藉由該第二型井區與該第一型源極/汲極重摻雜區域隔離;以及一基體(body),且該基體係與一電路電性連接。 The measuring method of claim 3, wherein the BT SOI component comprises: a gate structure disposed on the second well region; and at least one first source/drain heavily doped region Formed in the second type well region; a second type heavily doped region formed in the SOI substrate, and the second type well region and the first type source/drain heavily doped region Isolating; and a body, and the base system is electrically connected to a circuit. 如申請專利範圍第4項所述之測量方法,其中該閘極結構具有一第一部與一垂直於該第一部之第二部,且該第二部係跨越該第二型井區。 The measuring method of claim 4, wherein the gate structure has a first portion and a second portion perpendicular to the first portion, and the second portion spans the second type well region. 如申請專利範圍第5項所述之測量方法,其中該閘極結構之第一部具有一第一型區域與一第二型區域,該第一型區域靠近該第一型源極/汲極重摻雜區域,而該第二型區域靠近該第二型重摻雜區域。 The measuring method of claim 5, wherein the first portion of the gate structure has a first type region and a second type region, the first type region being adjacent to the first type source/drain The heavily doped region is adjacent to the second type heavily doped region. 如申請專利範圍第6項所述之測量方法,其中該閘極結構係為一T型閘極結構。 The measuring method of claim 6, wherein the gate structure is a T-type gate structure. 如申請專利範圍第7項所述之測量方法,其中該BT寄生元件更包含有:一第二型重摻雜區域;以及一基體,且該基體係與一電路電性連接;其中該寄生閘極係設置於該第二型井區上,且具有一第一型區域與一第二型區域,該第一型區域靠近該第一型源極/汲極重摻雜區域,而該第二型區域靠近該第二型重摻雜區域。 The measuring method of claim 7, wherein the BT parasitic element further comprises: a second type heavily doped region; and a substrate, wherein the base system is electrically connected to a circuit; wherein the parasitic gate The pole system is disposed on the second type well region and has a first type region and a second type region, the first type region is adjacent to the first type source/drain heavily doped region, and the second portion The type region is adjacent to the second type heavily doped region. 如申請專利範圍第6項所述之測量方法,其中該閘極結構係為一H型閘極結構,該H型閘極結構之該第一部係為一對互相平行且設置於該第二部兩端之結構。 The measuring method of claim 6, wherein the gate structure is an H-type gate structure, and the first portion of the H-type gate structure is a pair of mutually parallel and disposed on the second The structure of the two ends. 如申請專利範圍第9項所述之測量方法,其中該BT寄生元件更包含有:一第二型重摻雜區域;以及一基體,且該基體係與一電路電性連接;其中該寄生閘極係為一對互相平行,且設置於該第二型井區上之寄生閘極;且該寄生閘極具有一第一型區域與一第二區域,該第一型區域靠近該第一型源極/汲極重摻雜區域,而該第二型區域靠近該第二型重摻雜區域。 The measurement method of claim 9, wherein the BT parasitic element further comprises: a second type heavily doped region; and a substrate, wherein the base system is electrically connected to a circuit; wherein the parasitic gate The pole is a pair of parasitic gates that are parallel to each other and disposed on the second well region; and the parasitic gate has a first type region and a second region, the first type region is adjacent to the first type The source/drain is heavily doped, and the second region is adjacent to the second heavily doped region. 如申請專利範圍第1項所述之測量方法,其中該BT SOI元件與該BT寄生元件皆以射頻測試鍵(radio frequency,RF test key)結構建構。 The measurement method according to claim 1, wherein the BT SOI component and the BT parasitic component are both radio frequency test keys (radio frequency, RF) Test key) Structure construction. 如申請專利範圍第1項所述之測量方法,其中該SOI基底係為一元件晶圓或一監控片(monitor wafer)之基底。 The measuring method of claim 1, wherein the SOI substrate is a substrate of a component wafer or a monitor wafer. 一種半導體元件,包含有:一矽覆絕緣(SOI)基底,該SOI基底包含有一第二型井區;一第一型源極/汲極重摻雜區域,設置於該第二型井區內,且該第一型源極/汲極重摻雜區域彼此接觸;一第二型重摻雜區域,設置於該SOI基底內,且藉由該第二型井區與該第一型源極/汲極重摻雜區域隔離;一虛設閘極,設置於該第二型井區上,且不跨越該第一型源極/汲極重摻雜區域;以及一主體可外接(BT)基體,且該BT基體係與一電路電性連接。 A semiconductor device comprising: a silicon-on-insulator (SOI) substrate, the SOI substrate includes a second type well region; and a first type source/drain heavily doped region disposed in the second type well region And the first type source/drain heavily doped regions are in contact with each other; a second type heavily doped region is disposed in the SOI substrate, and the second type well region and the first type source /汲 very heavily doped region isolation; a dummy gate disposed on the second well region and not crossing the first source/drain heavily doped region; and a body externally connectable (BT) substrate And the BT base system is electrically connected to a circuit. 如申請專利範圍第13項所述之半導體元件,其中該SOI基底依序包含有一基材、一埋置氧化層與一第二型摻雜矽層。 The semiconductor device of claim 13, wherein the SOI substrate comprises a substrate, a buried oxide layer and a second type doped germanium layer in sequence. 如申請專利範圍第13項所述之半導體元件,其中該虛設閘極具有一第一型區域與一第二區域,該第一型區域靠近該第一型源極/汲極重摻雜區域,而該第二型區域靠近該第二 型重摻雜區域。 The semiconductor device of claim 13, wherein the dummy gate has a first type region and a second region, the first type region being adjacent to the first type source/drain heavily doped region, And the second type region is adjacent to the second Type heavily doped area. 如申請專利範圍第15項所述之半導體元件,其中該虛設閘極係為一對互相平行之閘極結構。 The semiconductor device of claim 15, wherein the dummy gate is a pair of mutually parallel gate structures. 如申請專利範圍第13項所述之半導體元件,其中該半導體元件係以射頻測試鍵結構建構。 The semiconductor component of claim 13, wherein the semiconductor component is constructed by a radio frequency test key structure. 如申請專利範圍第13項所述之半導體元件,其中該SOI基底係為一元件晶圓之基底。 The semiconductor component of claim 13, wherein the SOI substrate is a substrate of a component wafer. 如申請專利範圍第18項所述之半導體元件,其中該半導體元件係設置於該元件晶圓之切割道內。 The semiconductor component of claim 18, wherein the semiconductor component is disposed in a scribe line of the component wafer. 如申請專利範圍第13項所述之半導體元件,其中該SOI基底係為一監控片(monitor wafer)之基底。The semiconductor component of claim 13, wherein the SOI substrate is a substrate of a monitor wafer.
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