201044133 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種無橋式功率因數校正電路，尤指一 種將交流接地和直流接地端相連，且適當選擇電流路徑’ 從而有效地降低電磁干擾（EM1)與導通損耗之無橋式功率因 數校正電路。 【先前技術】 傳統升壓式功率因數校正電路（Boost PFC)由具有一 輸入橋式整流電路，因此具有顯著的導通損失（conduction l〇ss) ’為克服此缺點，遂提出無橋式功率因數校正電路 (Bridgeless PFC)。 如第六圖所示，為美國第7215560號專利案所揭示之 無橋式功率因數校正電路其中一實施例，其包含有： Q 一輸出端，另一端連接一第 一第-電感（lpfg1)，其-端連接_交流電源（Vac)之第 該第一串聯電路（61)以第一二 聯組成，其串聯中點指第—二 (S1)之連接節點； 一串聯電路（61)之串聯中點， —極體（D1)與第一開關（S1)串 —極體（D1)之陽極與第一開關 —端連接該交流電源（Vac)之第 串聯電路（62)之串聯中點，201044133 VI. Description of the Invention: [Technical Field] The present invention relates to a bridgeless power factor correction circuit, in particular to an AC ground and a DC ground terminal, and appropriately selecting a current path 'to effectively reduce electromagnetic interference (EM1) and conduction loss bridgeless power factor correction circuit. [Prior Art] The conventional boost power factor correction circuit (Boost PFC) has an input bridge rectifier circuit and therefore has a significant conduction loss (conduction l〇ss). To overcome this disadvantage, a bridgeless power factor is proposed. Calibration circuit (Bridgeless PFC). As shown in the sixth figure, an embodiment of the bridgeless power factor correction circuit disclosed in U.S. Patent No. 7,215,560 includes: Q an output terminal connected to a first first inductance (lpfg1) The first series circuit (61) of the -terminal connection_AC power supply (Vac) is composed of a first two-way, the midpoint of the series refers to the connection node of the second (S1); a series circuit (61) The midpoint of the series, the pole body (D1) and the first switch (S1), the anode of the pole body (D1) and the first switch terminal are connected to the series midpoint of the series circuit (62) of the alternating current power source (Vac) ,
輪出電容（Co)與— 一第二電感（LPFC2)，其— 二輸出端，另一端連接一 該第二串聯電路（62)以第 聯組成，其串聯中點指第 (S2)之連接節點； 一負載電路（63)，由一 一輪出負載（RL) 3 201044133 並聯構成，該負載電路（63)之兩端分別定義為一直流輸出 端（曰64)與-直流接地端（65)，其中，前述兩串聯電路（叫_ 亦疋連接於直流輸出端（64)與直流接地端（65)之間且與負 載電路（63)構成並聯。 、' ，前述實施例之特點在於交流電源（VaG)之第—輸入端與 直流接地端（65)之間設有第一輸入二極體⑴…，而第二輸 入端與直流接地端（65)之間設有第二輸入二極體（Db)。兩 ❹輸入m(Da)(Db)均是慢恢復二極體，其作用類似橋式 整流器中的二極體，當交流電源（Vac)為正半週時，可通過 第二輸入二極體（Db)使交流接地與直流接地端（65)彼此連 接，以抑制由第二電感（LpFC2)上的電壓波動所帶來的em| 干擾，當交流電源（Vac)為負半週時，將通過第一輸入二極 體（Da)使交流接地與直流接地端（65)連接，以抑制由第一 電感（LPFC1)上的電壓波動帶來的EMI干擾；高頻紋波電流 (High-frequency ripp|e current)和部分工頻電流（市頻電流 ◎ /低頻電流）通過第一輸入二極體（Da)或者第二輸入二極體 (Db)回到輸入端，部分工頻電流通過第一開關（si)/第二開 關(S2)流過第-電感(LpfC1V第二電感(LPFC2)回到輸入端。 惟上述電路中的第一輸入二極體（Da)與第二輸入二極 體（Db)必須選用具備較大導通壓降之二極體，其導通損耗 大，且需要額外加設散熱器，整體的體積相對增加。 清參考第七圖所示，為美國第72彳556〇號專利案所揭 示之無橋式功率因數校正電路之另一實施例，與其第一實 施例之差異在於原第一輸入二極體（Da)與第二輸入二極體 (Db)以一第—輪入電容（Ca)與一第二輸入電容（〇b)加以取 201044133 =兩輸入電容(Ca)(Cb)均為高電容量的電容，亦具備高 其電路動作原理么· 、為.因兩輪入電容（Ca)(Cb)具備高容 …頻雜訊通過電容時，其阻抗較小，相當於短路。 虽交>瓜電源（Vac)之輸出為正半週時，可通過第二電容（⑽ 而使交流接地與直流接地端（65)連接，以抑制由第二電感 (PFC2)《電[波動所帶來的EMI干擾；反之，當交流電 〇源（vac)為負半週時’可通過第一輸入電容㈣而使交流接 地與直流接地端（65)連接，藉此抑制由第-電感（LPFC1)上 的電壓波動所帶來的EMI干後。其中，高頻紋波電流可通 、第冑入電令(Ca)/第二輸入電容回到交流電源 (Μ)，工頻電流則可通過第一開關（S1)之寄生二極體 (Dsd1)/第二開關（S2)之寄生二極體（Dsd2)而流過第一電感 (Lpfc1)/第一電感（LPFC2)回到交流電源（Vac)。 -惟上述電路中的兩輸入電容（Ca)(Cb)須採用高品質的 〇 A件’以確保低等效電阻；然而在低壓重载的情況下，其 導通損耗仍很大。 請參考第八圖所示，為中國大陸CN 2〇〇62〇124692】 專利案所揭示之「無橋並聯的單級功率因數校正電路」·， 其電路結可說是同時結合前述第六、七圖電路之特徵即 同時存在第一輸入二極體（Da)、第二輸入二極體_、第 一輸入電容（Ca)與第二輸入電容（Cb)，其中第—輪入二極 體（Da)與第一輸入電容（Ca)並聯，第二輸入二極體 第二輸入電容（Cb)並聯。此電路之動作原理前述兩實施例 相同，故不另贅述，然而可明顯看出此電路使用相對較多 201044133 數里的f子7L件僅製造成本提高，且低壓重載時導通 損耗亦大。 【發明内容】 由前述說明心口，習帛無橋式功#因數校正電路因部 分工頻電流從開關之寄生二極體和電感流過，導致導通損 耗增加，不利於應用在低壓重載的情況。有鐘於此，本發 〇日月之主要目的係提供-種低導通損耗、低電磁干擾之益橋 式功:因數校正電路，為達成前述目的，本發明係具有、 -第-電感’其一端連接一交流電源之第一輸出端， 另一端連接-第-串聯電路，該第一串聯電路以第一二極 開關串聯構成’該第-二極體其陽極與第-開關 之連接即點係連接該第一電感之該另—端； =電感，其一端連接該交流電源之第二輸出端， 2 L第二串聯電路，該第二串聯電路以第二二極 ❹ ϋ與第二開關串聯構成，該第二二極體 一一和 之連接節點係連接該第二電感之該另-端； 開關 -負载電路’由—輸出電容與一輸出 =負载電路之兩端分別作為__直流輸出端與’ &，f中，前述兩串聯電路與負載電路係並聯連接;机地 一第一輪入開關，係連接至交流電 ’ 該直流接地端之間； 之第一輸入端與 :第二輪入開關，係連接於交流電 該直流接地端之間。 步一輸入為與 當該交流輸入電源輸出正半週„時，係控制第二輸 6 201044133 入開關為常導通狀態輸人開關與第二開關處於 止狀態’ f 一開關控制為交替i也導通,載止；由於第 -直維持為低電壓準位（戴止狀態），電流可經由；：輪 入開關回到交流電源’而不須經過第二開關之寄生二極： 和第二電感，故損耗降低。 反之，當該交流輸入電源輪出負半週電壓時，係控制 第-輸入開關為常導通狀態，第二輸入開關與第一 ❹ 〇 於恆截止狀態，第二開關控制為交替地導通/截止；由於第 -開關在輸人電壓為負半週時—直維持為低電㈣位，' 流可經由第一輸入開關回到交流電源，而沒有經過 關之寄生二極體和第-電感，故損耗降低，從而提高效/ 【實施方式】 請參閱第一圖所示，為本發明坌 圖，其包含有： …第-貧施例之詳細電路 :第-電感(lpfc1)，其一端連接一交流電源 =出端，另-端連接一第一串聯電路⑴)之 弟 聯组虫 體（D1)與第1關（叫串 聯;且成，其串聯中點指第一二極體(D”之陽極與二 (S1)之連接節點； 野’關 二輸出:二=:二其第::連接該交流電源(V，* i^連接第一串聯電路（12)之由脾士 該第二串聨電路⑽《第二二極心第):=點， 聯組成’其串聨中點指第二二極_2)==關（S2)串 (叫相連之連接節點； 〶極與第二開關 7 201044133 -負載電路(13)，由一輸出電容(c〇)與一輸出負載(RL) 並聯構成，該負載電路（13)之兩端分別定義為一直流輸出 端（14)與-直流接地端（15)，其中，前述兩串聯電路⑴）（】2) 亦是連接於直流輸出端（14)與直流接地端（15)之間且與負 載電路（13)構成並聯； 一第一輸入開關（Sa)，其一端連接至第一電感（LpFci) 與父流電源（Vac)相連之節點，另一端連接至一檢測電阻（Rs) 〇的第一端，該檢測電阻（Rs)的第二端連接該直流接地端 (15)，其中§亥第一輸入開關（Sa)可為μ〇s電晶體； 一第二輸入開關（Sb)，其一端連接至第二電感（LpFC2) 與交流電源（Vac)相連之節點，另一端連接該檢測電阻（Rs) 的第一端，其中該第二輸入開關（Sb)可為M〇s電晶體。 此外，在交流輸入電源（Vac)之輸出端與兩電感（LpFci) (lPFC2)之間可連接一電磁干擾濾波器（EM| f丨丨ter)(2〇)，將 欲輸出之電流先行濾波再提供至兩電感（LpFci) (“π」。 ❹ 清同時參閱第二、三圖所示，當交流輸入電源（Vac)為 正半週時，第二輸入開關（Sb)處於常導通狀態，第一輸入 開關（Sa)與第二開關（S2)處於恆截止狀態，第一開關 控制為交替地導通/截止。由於第二輸入開關（Sb)之導通電 阻極小’故全部電流（包含工頻電流和高頻紋波電流）均 可通過第二輸入開關（Sb)經過該電磁干擾濾波器（2〇)回到 交流電源（Vac)。 另一方面，當第一開關（S1)導通時，電流通過第—電 感（LPFCi)流經第一開關（S1)，並通過檢測電阻（Rs)和第二 輸入開關（Sb) ’經電磁干擾濾波器（20)回到交流電源 8 201044133 (Vac)，輸入電流線性上升；反之，當第一開關（S1)關閉時， 電机通過第一電感（lPFC1)流經第一二極體（D1)，對輸出電 谷（C〇)進行充電並提供輸出負載（RL)電流，最後通過該檢 測電阻（Rs)和第二輸入開關（Sb)，經電磁干擾遽波器㈣ 回到交流電源（Vac)端，輸入電流線性下降。 由於第二開關（S2)在輸入電壓正半週時一直維持為低 電壓準位，電流經由檢測電阻（Rs)、第二輸入開關（Sb)和 〇 電磁干擾濾波器（20)回到交流電源（Vac)，而沒有經過第二 開關（S2)之寄生二極體（Dsd2)和第二電感（Lpfc2)，故損耗 降低’從而提高效率。 印參考第二、四圖所示，當交流輸入電源（Vac)為負半 週時，第一輸入開關（Sa)處於常導通狀態，第二輪入開關（Sb) 與第—開關（S1)處於恆截止狀態，第二開關（S2)控制為交 替地導通/截止。由於第一輸入開關（Sa)之導通電阻極小， 故全部電流（包含工頻電流和高頻紋波電流）均可通過第 Ο 一輸入開關（Sa)經過該電磁干擾濾波器（20)回到交流電源 (Vac) 〇 另一方面，當第二開關（S2)導通時，電流通過第二電 感（LPFC2)流經第二開關（S2)，並通過檢測電阻（Rs)和第一 輸入開關（Sa) ’經電磁干擾濾波器（20)回到交流電源 (vac) ’輸入電流線性上升；反之，當第二開關（S2)關閉時， 電流通過第二電感（LpFC2)流經第二二極體（D2)，對輸出電 容（c〇)進行充電並提供輸出負載（rL)電流，最後通過該檢 測電阻（Rs)和第一輸入開關（Sa)，經電磁干擾濾波器（2〇) 回到交流電源（Vac)端，輸入電流線性下降。 9 201044133 由於第一開關（S1)在輸入電壓為負半週時—直維持為 低電壓準位，電流經由檢測電阻（Rs)、第_輸人開關㈣ 和電磁干擾濾波器（20)回到交流電源（Vac)，而沒有經過第 一開關（S1)之寄生二極體（Dsd1)和第一電感，故損 耗降低，從而提高效率。 本發明以兩輸入開關（Sa)(Sb〉提供電流迴路，使輸入 正/負半週時能將交流接地和直流接地端（15)直接相連，從 〇 而有效地降低EMI干擾。同時’由於工頻電流基本上皆經 由兩輸入開關（Sa)(Sb)回流到交流電源（Vac)，可避免流經 第一開關（si)之寄生二極體（DscM)和第一電感（LpF或第 二開關（S2)之寄生二極體（Dsd2)和第二電感（LpFc2),故亦 可降低導通損耗。此外，本發明亦具有以下數點特徵 1 _採用單一檢測電阻（RS),可簡化無橋式功率因數校 正電路的電流檢測線路。 2.對於低壓大電流場合應用，效率提升明顯。 Q 3·兩電感（Lpfci)(LPFC2)交替工作，可降低電感的發熱 程度。 … 4.通過兩輸入開關（sa)(Sb)組成的續流支路，將交流 接地與直流接地端（15)直接連接起來，有效降低因無橋拓 撲自身缺陷導致的E Μ丨干擾和損耗問題。 凊參考第五圖所示，為本發明之第二實施例，係將原 檢測電阻（Rs)以三個電流互感器（3〇a)~(3〇c)取代，第一電 流互感器（30a)係與第一串聯電路（1 j)串聯以偵測流過第— 串聯電路（11)上的電流’第二電流互感器（3〇b)與第二串聯 電路（12)串聯’以偵測流過第二串聯電路（12)上的電流， 201044133 第三電流互感器(30c)連接在第二二極體(D2)之陰極盘輸出 電谷(c〇)之間’偵測二者之間的電流。該三個電流互感琴 (30a)〜(3〇C)係共同輪出—電流感測信號（cs)。 “ 圖式簡單說明】 第一圖 第二圖 第三圖 第四圖 第五圖 第六圖 :本發明第一實施例之詳細電路。 本發明之主要工作波形圖 Ο 〇 本發明第-實施例於正半週之電路動作圖。 本發明第-實施例於負半週之電路動作圖。 本發明第二實施例之詳細電路圖。 美國第7215560號專利案所揭示之無橋式功 率因數校正電路之一實施例。 第七圖：美國第721556〇號專利案所揭示之無橋式功 率因數校正電路之另一實施例。 第八圖：中國大陸CN200620U4692」專利案所揭示 之無橋並聯的單級功率因數校正電路之電路圖。 【主要元件符號說明】 (11) (61)第一串聯電路 (12) (62)第二串聯電路 (13) (63)負載電路 (14) (64)直流輸出端 (1 5)(65)直流接地端 (20)電磁干擾濾波器 11 201044133 (30a)第一電流互感器 (30b)第二電流互感器 (30c)第三電流互感器 (LPFC1〉第一電感 (LpFX2)苐-一電感 (Vac)交流電源 (D1)第一二極體 (D2)第二二極體 (Da)第一輸入二極體 (Db)第二輸入二極體 (Ca)第一輸入電容 (Cb)第二輸入電容 (51) 第一開關 (52) 第二開關 (Sa)第一輸入開關 (Sb)第二輸入開關 (Co)輸出電容 (RL)輸出負載 (Rs)檢測電阻 12The turn-off capacitor (Co) and - a second inductor (LPFC2), the second output terminal, the other end connected to the second series circuit (62) is composed of a combination, and the midpoint of the series refers to the connection of the (S2) A load circuit (63) is formed by parallel connection of one-to-one load (RL) 3 201044133, and two ends of the load circuit (63) are respectively defined as a DC output (曰64) and a DC ground (65). The two series circuits (called _ 疋 are connected between the DC output terminal (64) and the DC ground terminal (65) and are connected in parallel with the load circuit (63). , ', the foregoing embodiment is characterized by communication A first input diode (1) is disposed between the first input terminal and the DC ground terminal (65) of the power supply (VaG), and a second input diode is disposed between the second input terminal and the DC ground terminal (65). Body (Db). Both input m(Da)(Db) are slow recovery diodes, which function like diodes in bridge rectifiers. When AC power supply (Vac) is positive half cycle, it can pass The two-input diode (Db) connects the AC ground and the DC ground (65) to each other to suppress the second inductor (LpFC2) The em| interference caused by the voltage fluctuation on the upper side, when the AC power supply (Vac) is negative half cycle, the AC ground is connected to the DC ground (65) through the first input diode (Da) to suppress EMI interference caused by voltage fluctuations on the first inductor (LPFC1); high-frequency ripple current (High-frequency ripp|e current) and partial power-frequency current (commercial current ◎ / low-frequency current) pass through the first input diode The body (Da) or the second input diode (Db) returns to the input terminal, and part of the power frequency current flows through the first switch (si) / the second switch (S2) through the first inductor (LpfC1V second inductor (LPFC2) Return to the input. However, the first input diode (Da) and the second input diode (Db) in the above circuit must use a diode with a large turn-on voltage drop, which has a large conduction loss and requires additional Adding a heat sink, the overall volume is relatively increased. Referring to the seventh figure, another embodiment of the bridgeless power factor correction circuit disclosed in U.S. Patent No. 72,556, the first embodiment thereof The difference is that the original first input diode (Da) and the second input diode (Db) are one - The round-in capacitor (Ca) and a second input capacitor (〇b) are taken. 201044133 = Both input capacitors (Ca) (Cb) are high-capacitance capacitors, and also have high circuit operation principles. Because the two-wheel capacitor (Ca) (Cb) has high capacitance... When the frequency noise passes through the capacitor, its impedance is small, which is equivalent to a short circuit. Although the output of the melon power supply (Vac) is positive half cycle, it can pass. The second capacitor ((10) connects the AC ground to the DC ground (65) to suppress the EMI interference caused by the second inductance (PFC2) "Electric [fluctuation; otherwise, when the AC source (vac) is negative half In the circumferential direction, the AC ground can be connected to the DC ground (65) through the first input capacitor (4), thereby suppressing the EMI after the voltage fluctuation caused by the first inductance (LPFC1). Among them, the high-frequency ripple current can pass, the first input power (Ca) / the second input capacitance returns to the AC power supply (Μ), and the power frequency current can pass through the parasitic diode (Dsd1) of the first switch (S1) / The parasitic diode (Dsd2) of the second switch (S2) flows through the first inductor (Lpfc1) / the first inductor (LPFC2) back to the alternating current source (Vac). - Only the two input capacitors (Ca) (Cb) in the above circuit must use a high quality 〇 A piece ' to ensure low equivalent resistance; however, in the case of low voltage and heavy load, the conduction loss is still large. Please refer to the eighth figure, which is the "bridgeless parallel single-stage power factor correction circuit" disclosed in the Chinese patent CN 2〇〇62〇124692]. The circuit junction can be said to be combined with the sixth. The seven-chart circuit is characterized by a first input diode (Da), a second input diode _, a first input capacitor (Ca) and a second input capacitor (Cb), wherein the first wheel-in diode (Da) is connected in parallel with the first input capacitor (Ca), and the second input diode second input capacitor (Cb) is connected in parallel. The operation principle of the circuit is the same as the above two embodiments, so it will not be further described. However, it can be clearly seen that the circuit uses a relatively large number of sub-segments of the 20104133, and the manufacturing cost is increased, and the conduction loss is also large at low voltage and heavy load. SUMMARY OF THE INVENTION From the foregoing description, the Xiqiao bridgeless power factor correction circuit flows due to the partial power frequency current flowing from the parasitic diode and the inductor of the switch, resulting in an increase in conduction loss, which is disadvantageous for the application in the case of low voltage and heavy load. . In this case, the main purpose of the present invention is to provide a low-conduction loss, low-electromagnetic interference benefit bridge-type work: a factor correction circuit, in order to achieve the aforementioned purpose, the present invention has, - the first inductance One end is connected to a first output end of an AC power source, and the other end is connected to a - series-series circuit, wherein the first series circuit is connected in series with a first two-pole switch, and the anode and the first switch are connected to each other. Connecting the other end of the first inductor; = inductor, one end of which is connected to the second output end of the AC power source, 2 L of the second series circuit, and the second series circuit with the second diode and the second switch Connected in series, the second diode and the connection node are connected to the other end of the second inductor; the switch-load circuit 'from the output capacitor and an output = the two ends of the load circuit respectively as __DC The output terminal and '&, f, the two series circuits are connected in parallel with the load circuit; the first wheel switch of the machine ground is connected to the alternating current 'between the DC ground; the first input end: Two-wheel switch, connected to the intersection The DC electrical ground between the ends. Step 1 is input and when the AC input power output is positive for half a cycle „, the second output is controlled. 6 201044133 The input switch is normally-on state, the input switch is in the stop state, and the second switch is in the stop state. , because the first-right is maintained at a low voltage level (wearing state), the current can pass; the wheel switch back to the AC power supply' without passing through the parasitic diode of the second switch: and the second inductance, Therefore, when the AC input power supply rotates a negative half-cycle voltage, the first-input switch is normally-on, the second input switch is in a constant-off state, and the second switch is alternately controlled. Ground conduction/cutoff; since the first switch is in the negative half cycle when the input voltage is negative, the flow can be returned to the AC power supply via the first input switch without passing through the parasitic diode and The first inductance, so the loss is reduced, thereby improving the efficiency / [Embodiment] Please refer to the first figure, which is a schematic diagram of the present invention, which includes: ... detailed circuit of the first-lean embodiment: the first inductance (lpfc1) One end connected to one Stream power = output, the other end is connected to a first series circuit (1)), the brother group (D1) and the first level (called series; and, the series midpoint refers to the first diode (D) The connection between the anode and the second (S1); the wild 'off two output: two =: two of its:: connect the AC power (V, * i ^ connected to the first series circuit (12) by the spleen the second聨 聨 circuit (10) "second two-pole center": = point, combined into 'the middle point of the string refers to the second two poles_2) == off (S2) string (called the connected connection node; bungee and the first The second switch 7 201044133 - the load circuit (13) is composed of an output capacitor (c〇) connected in parallel with an output load (RL), and the two ends of the load circuit (13) are respectively defined as a DC output terminal (14) and - a DC ground terminal (15), wherein the two series circuits (1)) (2) are also connected between the DC output terminal (14) and the DC ground terminal (15) and connected in parallel with the load circuit (13); An input switch (Sa) having one end connected to a node connected to the first inductor (LpFci) and a parent current source (Vac), and the other end connected to a first end of a sense resistor (Rs) ,, the sense resistor The second end of the Rs) is connected to the DC ground (15), wherein the first input switch (Sa) can be a μ〇s transistor; and the second input switch (Sb) has one end connected to the second inductor ( LpFC2) The node connected to the AC power supply (Vac), the other end is connected to the first end of the sense resistor (Rs), wherein the second input switch (Sb) can be an M〇s transistor. An electromagnetic interference filter (EM|f丨丨ter) (2〇) can be connected between the output of the Vac) and the two inductors (LpFci) (lPFC2), and the current to be output is first filtered and then supplied to the two inductors (LpFci). ) ("π". ❹ At the same time, as shown in the second and third figures, when the AC input power (Vac) is positive half cycle, the second input switch (Sb) is in the normally conducting state, the first input switch (Sa) and the second switch (S2) In the constant off state, the first switch is controlled to be alternately turned on/off. Since the on-resistance of the second input switch (Sb) is extremely small, all currents (including the power frequency current and the high-frequency ripple current) can be returned through the second input switch (Sb) through the electromagnetic interference filter (2〇). AC power supply (Vac). On the other hand, when the first switch (S1) is turned on, current flows through the first switch (S1) through the first inductance (LPFCi), and is electromagnetically disturbed through the sense resistor (Rs) and the second input switch (Sb). The filter (20) returns to the AC power supply 8 201044133 (Vac), and the input current rises linearly; conversely, when the first switch (S1) is turned off, the motor flows through the first diode (1P1) through the first inductor (1PFC1) (D1) ), charging the output voltage valley (C〇) and providing an output load (RL) current, and finally passing the detection resistor (Rs) and the second input switch (Sb) to the AC power source via the electromagnetic interference chopper (4) ( At the Vac) end, the input current drops linearly. Since the second switch (S2) is maintained at a low voltage level for the positive half cycle of the input voltage, the current is returned to the AC power source via the sense resistor (Rs), the second input switch (Sb), and the 〇 electromagnetic interference filter (20). (Vac) without passing through the parasitic diode (Dsd2) and the second inductance (Lpfc2) of the second switch (S2), so the loss is reduced, thereby improving efficiency. Referring to the second and fourth figures, when the AC input power (Vac) is negative half cycle, the first input switch (Sa) is in a normally conducting state, and the second wheel switch (Sb) and the first switch (S1) In the constant off state, the second switch (S2) is controlled to be alternately turned on/off. Since the on-resistance of the first input switch (Sa) is extremely small, all currents (including the power frequency current and the high-frequency ripple current) can be returned through the electromagnetic interference filter (20) through the first input switch (Sa). AC power supply (Vac) 〇 On the other hand, when the second switch (S2) is turned on, current flows through the second switch (S2) through the second inductor (LPFC2), and passes through the sense resistor (Rs) and the first input switch ( Sa) 'Return to the AC power supply (vac) via the EMI filter (20) 'The input current rises linearly; conversely, when the second switch (S2) is off, the current flows through the second diode through the second inductor (LpFC2) Body (D2), charging the output capacitor (c〇) and providing an output load (rL) current, and finally passing the detection resistor (Rs) and the first input switch (Sa), via the electromagnetic interference filter (2〇) At the AC power supply (Vac) end, the input current drops linearly. 9 201044133 Since the first switch (S1) is maintained at a low voltage level when the input voltage is negative half cycle, the current is returned via the sense resistor (Rs), the _input switch (4) and the EMI filter (20). The AC power supply (Vac) does not pass through the parasitic diode (Dsd1) of the first switch (S1) and the first inductance, so the loss is reduced, thereby improving efficiency. The invention provides a current loop by a two-input switch (Sa) (Sb>, which can directly connect the AC ground and the DC ground (15) when inputting positive/negative half cycles, thereby effectively reducing EMI interference. The power frequency current is basically returned to the AC power supply (Vac) via the two-input switch (Sa) (Sb) to avoid the parasitic diode (DscM) and the first inductor (LpF or the first inductor) flowing through the first switch (si) The parasitic diode (Dsd2) and the second inductor (LpFc2) of the second switch (S2) can also reduce the conduction loss. In addition, the present invention also has the following characteristics: 1 using a single sense resistor (RS), which simplifies The current detection circuit of the bridgeless power factor correction circuit 2. For the application of low voltage and large current, the efficiency is obviously improved. Q 3·The two inductors (Lpfci) (LPFC2) work alternately to reduce the heat generation of the inductor. A freewheeling branch composed of two input switches (sa) (Sb) directly connects the AC ground to the DC ground (15), effectively reducing the E Μ丨 interference and loss caused by the defect of the bridgeless topology itself. The fifth figure shows the present invention In the second embodiment, the original sense resistor (Rs) is replaced by three current transformers (3〇a)~(3〇c), and the first current transformer (30a) is connected to the first series circuit (1 j). Connecting in series to detect a current flowing through the first series circuit (11) 'the second current transformer (3〇b) is connected in series with the second series circuit (12) to detect flowing through the second series circuit (12) Current, 201044133 The third current transformer (30c) is connected between the cathode disk output electric valley (c〇) of the second diode (D2) to detect the current between the two. (30a) ~ (3〇C) is a common rotation - current sensing signal (cs). "Simple diagram of the diagram" First figure Second figure Third figure Fourth figure Fifth figure Sixth figure: The present invention DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The main operation waveform of the present invention is a circuit operation diagram of the first embodiment of the present invention in the positive half cycle. The circuit operation diagram of the first embodiment of the present invention in the negative half cycle. Detailed circuit diagram of an embodiment. One embodiment of a bridgeless power factor correction circuit disclosed in U.S. Patent No. 7,215,560. Another embodiment of the bridgeless power factor correction circuit disclosed in the Patent No. 721,556. The eighth diagram: a circuit diagram of a single-stage power factor correction circuit without bridges and parallels disclosed in the CN200620U4692 patent of the Chinese mainland. Component Symbol Description] (11) (61) First series circuit (12) (62) Second series circuit (13) (63) Load circuit (14) (64) DC output terminal (1 5) (65) DC grounding Terminal (20) EMI filter 11 201044133 (30a) First current transformer (30b) Second current transformer (30c) Third current transformer (LPFC1 > First inductance (LpFX2) 苐 - One inductor (Vac) AC power supply (D1) first diode (D2) second diode (Da) first input diode (Db) second input diode (Ca) first input capacitance (Cb) second input capacitance (51) First switch (52) Second switch (Sa) First input switch (Sb) Second input switch (Co) Output capacitance (RL) Output load (Rs) Detection resistor 12