201042737 六、發明說明： . 【發明所屬之技術領域】 . 本發明係有關一種封裝基板及其製法，尤指一種防止 同層線路電性連接短路之封裝基板及其製法。 【先前技術】 . 目前封裝基板製程中，係於基板本體上堆疊複數介電 . 層，且於各介電層之間佈設所需之圖案化線路，以形成封 裝基板結構；由於一般封裝基板係為疊層結構，因而各層 〇 間之結合力相當重要，為確保各層之線路電性連接，故習 知技術係於介電層表面形成粗糖面，以增加介電層與線路 間之結合強度，且由於封裝基板之佈線趨勢係往高密度、 細線路間距發展，故製作封裝基板線路之方式以電鑛圖案 化線路為主流，請參閱第1A至1E圖，係提供一種習知封 裝基板製作線路之製法示意圖。 如第1A圖所示，提供一表面具有内層線路層100之 ^ 基板本體10，且於該基板本體10之至少一表面上形成介 電層11，以覆蓋該内層線路層100。 如第1B圖所示，於該介電層11之全部表面上形成粗 糙面11a，再於該介電層11之粗糙面11a上全面形成導電 層12 ;其中，該導電層12 —般係為無電電鍍銅。 如第1C圖所示，於該導電層12上形成阻層13，且 該阻層13經曝光與顯影製程以形成複數開口區130，令該 導電層12之部分表面外露於該些開口區130。 如第1D圖所示，藉由該導電層12作為電鍍金屬所需 201042737 之電流傳導路徑’於該些開口區13G中之導電層12上電參 形成圖案化線路層14，且該線路層14具有複數條線路^ 與複數個電性連接墊141。 &如第1E圖所示，移除該阻層13及其覆蓋之導電層 Μ 術係於該介^ U之全部表面上形成粗 奴面，以夕除該阻層13所覆蓋之導電層12之 粗韃面lla上之導電層U不易完全清除乾淨 ς s，導致該相鄰之線路二二匕山上殘存有導電材 現象，因而降低產品之可&成短路 罪度将別疋，當於細間距if〗ne 應用時，由於線距窄小，因此短路現象更容易發生 故不利於供細間距封裝基板使用。 CM生’ 口此，如何避免習知技術中之短 成目前歪欲解決的課題。 足象之問喊，貫已 【發明内容】 鑑於上述習知技術之種種缺失，本發明之主要 提供一種防止同層線路電性連 々係 法。 书改運接紐路之封裝基板及其製 本發明之另—目的係提供一種可 層附著力之封裝基板及其製法。 勺括㈣’本發㈣露—種封裝基板，係 ^ ，丨电層，以及第一線路層，传設於入 層之部分表面上；1中，^ ^ 一介電 ^中心一介電層部分表面係具有報 4 ί】】2】ΐ 201042737 糙面’該祕㈣設於該第—線路層與第—介電 且該粗糖面之粗輪度大於該未具有第-線路層之 層表面。 W電 :述=封裝基板復可包括基板本體，係具有 二二::：☆電層設於該基板本體上且覆蓋該二路 層弟一線路層並電性連接至該内層線路層。以路 刖迟之封裝基板復可包括+ Ο 第-線路層之間。 电層，係設於該㈣造面與 別述之封裝基板， 接墊及線跋 線路層係可包括複叙+ 該線路;又可於該第—介雷::二連接至部份或對應各 二：而該防焊層具有複數二路層上幾有防谭 外路於各該開孔。 7 “亥電性接觸备對應 構，係設於^第施^ ’前述之封裝基板復可包 〇 , 苐—介電層及第一續玖思 包秸i曾声好 有至少1二介電屏一 路層上，颉i曾腐 層、及設於該第二介電層^結構具 層之複數導電=電層中养電性連接讀第心第二線路 面’該粗糙面係設於介電層部分表面係:二線路 :凝面之粗键度大於該與第二介電層^粗麵 表面，·又該增層結構最外声;^二線路層之第/曰1，且 觸墊，且於該增声 曰之弟二線路層具有、介電層 數開孔，令各心=有防焊層，々電性接 本發明復揭露—種封二:外露於〜:*有複 4板之製法’係包拓. ._供一 5 201042737 第一介電層；於該第一介電層上形成第一阻層，且該第一 阻層中形成複數圖案化之第一開口區，令該第一介電層之 部分表面外露於該些第一開口區；於各該第一開口區中之 第一介電層上進行粗縫化，令該第一介電層之部分表面上 形成有粗链面；移除該第一阻層丨於該第一介電層及其粗 糙面上形成導電層；於該導電層上形成第二阻層，且該第 二阻層形成有複數圖案化之第二開口區，令該粗糙面上之 導電層外露於該些第二開口區；於該粗糙面之導電層上電 鍍形成第一線路層，且該粗糖面之粗鍵度大於該未具有第 一線路層之第一介電層表面；以及移除該第二阻層及其覆 蓋之導電層，以外露出該第一線路及第一介電層。 前述之封裝基板之製法復可包括提供一基板本體，且 該基板本體上具有内層線路層，令該第一介電層形成於該 基板本體之至少一表面上，以覆蓋該内層線路層，而該第 一線路層並電性連接至該内層線路層。 前述之封裝基板之製法復可包括於該外露之第一介 電層及第一線路層上形成增層結構，該增層結構具有至少 一第二介電層、設於該第二介電層上之第二線路層、及設 於該第二介電層中並電性連接該第一及第二線路層之複數 導電盲孔，而該第二介電層部分表面係具有粗链面，該粗 糙面係設於該第二線路層與第二介電層之間，且該粗糙面 之粗糙度大於該未具有第二線路層之第二介電層表面；又 該增層結構最外層之第二線路層具有複數電性接觸墊，且 於該增層結構上設有防焊層，而該防焊層具有複數開孔， ]]]21] 201042737 令各該電性接觸墊對應外％ 前述之封裴基板、，露於各該開孔。 電性連接墊及線路，，該第一線路層係 對應各該線路，並::電性連接墊電性連接 上形成防焊層，而該 卜露之第-介電層及第二或 觸塾對應外露於各該開^財複數開孔，令各該電性: 由上可知’本發明辑1 Ο Ο 緩路層之表面上形c該第-介電層僅於結合讀第— 平整，使該第—線路層及^餘之第-介電層表面保持 有效完全移除該第二限爲电性賴塾之周圍呈平整面，以 層與各該電性連接墊之二所覆蓋之導電層’俾該第一線路 強線路層與介電層之結人不胃發生紐路現象，此外亦可增 <目的。 H而相提升電性連接品質 【實施方式】 :下藉由特定的具體實施 武，熟悉此技藝之人士订丄丄 不I明之貫施方 瞭解本發明之其他優點及功=說明書所揭示之内容輕易地 請參閱第2Α至2Η 於& 敦基板之製法。 圖’ W本發明所揭露之-種封 如第2A圖所示，提供一其 ) 、土板本肢20 ,且該基板本體 2〇上具有内層線路層2〇〇 力、通暴板本體20之至少一表面 上形成第-介電層21，以覆蓋該内層線路層·。缺，於 其他實施射，該基板讀2G可為承載板，而於後續製程 中移除該承載板，以形成無核心板（em.dess )之封裝基板。 1312]] 7 201042737 22 :二W圖所示，於該第-介電層21上輪 22，且_ —阻層22_形成有複 /“1且層 220，令該第-介電層21之部分表：=之弟-開口區 區220。 、面卜路於該些第—開口 帝如第2C圖所示’於各該第—開口區 a 電層2】上進行粗越化製程，令該第—八^、巾之第一介 面形成粗趟面21〇。 — 电層之部4表 如第2D圖所不，移除該 介電層2】及其表面之粗#面2】〇/層22，以露出該第-如第2E圖所示，於該第—介 形成導電層23,且該導電層 曰=粗链面210上 該導電層23上形成第二阻層24^電鍍銅材；再於 複數圖案化之第二開口區240，令該且層24中形成 層23外露於該些第二開口區24〇。210上之導電 如第2F圖所不，藉由該導電層a作 導路徑’以於該粗糖面21〇之 4 $鑛之氣流傳 路層25,且該第一嗖路# "上電鍍形成第一線 性連接塾⑸且各=具有複數線路⑽與複數電 斟座Γ 電性連聽251電性連接至m =應各該線路250,又該第一線路層25並 =或 電性連接至該内層線路層2〇〇，而” W盲孔 係為成熟之技術，於此不再為文笔盲孔之製法 =性連接塾Μ1為植球墊、或覆晶焊塾；又該第 运5下之该粗糙面2]〇之粗糙度大於 > 25之第-介電層2]表面。 未-有弟-線路層 8 ⑴21] 201042737 如第2G圖所示，移除該第二阻層24及其覆蓋之導電 - 層23，以露出該第一介電層21及第一線路層25。 . 相較於習知技術之介電層全面形成粗糙面，本發明之 第一介電層21僅於結合該第一線路層2 5之表面上形成粗 糙面210，以確保該第一介電層21與第一線路層25之間 的結合強度，且該第一介電層21之其餘表面仍保持平整， - 以令該第一線路層25之周圍係為平整面，而能有效完全移 除該第二阻層24及其所覆蓋之導電層23。 〇 因此，當移除該第二阻層24及其所覆蓋之導電層23 之後，該導電層23不會殘留於該第一介電層21之平整面 上，令該線路250或電性連接墊251周圍不會殘存有導電 層23，以避免該線路250或各該電性連接墊251之間發生 橋接之短路現象，亦可增強線路層與介電層之接合強度。 如第2H圖所示，又於另一後續製程之實施例中，該 電性連接墊251非供用以連接外部電子元件（如焊錫凸塊） 之用，而當作為後續線路增層製程用於電性連接導電盲孔 之用，以構成線路增層結構；係於該第一介電層21及第一 線路層25上形成增層結構26,該增層結構26具有至少一 第二介電層260、設於該第二介電層260上之第二線路層 261、及設於該第二介電層260中並電性連接該第一及第二 線路層25,261之複數導電盲孔262，而該第二介電層260 部分表面係具有粗糙面210’，該粗糙面210’係設於該第二 線路層261與第二介電層260之間，且該粗糙面21 (T之粗 糙度大於該未具有第二線路層26]之第二介電層260表 9 111211 201042737 面。又該增層結構26最外層之第二線路層加 性接觸墊263，並於該增層結構26 ^有複數電防焊層27具有複數開孔27〇，令各該冑 =27,而該 外露於各該開孔27〇。 蜀上263對應 綜前所述，本發明復揭露—種 一介電層21;f—線路層25，係設於該土第—介1 包括：第 部分表面上，其中，該第一介電層21部分表面：層21之 面210，該粗链面21〇係設於兮 ’、具有粗糙 、以罘一綠路層25幽妨 層21之間，且該粗键面2104糙度大於該未介電 路層25之第一介電層21表面n ”有第一線 再者，㈣敦絲可為核心板堆疊 所示，該封裝基板復包括基板本體2〇，係夏如⑦2G圖 ?nn，a妓穿—八^—— 内層線路層 2 〇 〇，令該第—介電層21設於縣板本體如、 層線路層200;然，於其他實施例中， ^覆蓋該内 核心板(G_ess)式（並未以圖式表示），即^板可為無 本體20。\該封裳基板復 Ί具有該基板 請與第'線路層25之間广層23,係設於該 另外 έ亥第~線路層25係句赵诘叙& 及線路250， “括稷數電性連接墊2S1 251，又各^ 该線路25G電性連接51 又各该電性連接墊 该電性連接墊 路25。’而讀第-綠路…:=:份或對應各‘ 該内層線路層2〇。;二亚二導電盲孔電性迷4 »笙一# 〇α 、为 戶、知恶樣中，今咏 变至 Λ乐一介電層 及第線路層25上τν …，％弟一） 防焊層具有可設杨焊層（未以圖式表 楚數開孔（未以…飞表 開孔（未以圖式表 不 電烛 2] ，磅 10 201042737 墊251對應外露於各讀開孔 電子裝置之電性接觸聲。，而成為用以電性連接至其它 該封裏基板復可包括増 層21及第-線路層25上，26 ’係設於該第—介命 介電層260、設於該第二介：：層結構％具有至少_第： 及设於έ亥第二介電層26〇中命 之第—線路層26ι、 層25,261之複數導電| '…电性連接讀第一及第_ 仅双♦电盲孔2幻， 夂罘—線路 Ο Ο 表面係具有粗糙面21 〇,，今 人〜介電層260部分 層261與第二介電層、之;^面210係設於該第二線路 大於該未具有第二線袼層〕^之且該=糙面210,之粗糙度 該增層結構26最外層之窜_之第一’丨電層260表面。又 墊263，並於該增層結構2 '、桌^層261具有複數電性接觸 27具有複數開孔270，a夂 '有防焊層27，而該防焊層 各該開孔270。 々各該電性接觸墊如對應外露於 綜上所述，本發明之封 第-次係於該第-介電声上：：：係稭由兩次阻層製程’ 电層上定義出粗糙面及 次則令該第-線路層形成於該粗韃面上，以二 二阻層所覆蓋之導電層，即平敕 &王移除该第 电層即千整面上之導電層，使該第— 線路層與各該電性連接墊之間不會殘存有該導電層，而有 效避免發生短路現象，不僅有效達到提升電性連接良率之 目的’且當於細間距（finepitch)設計時，因不易發生短 路現象，亦可增強線路層與介電層之結合強度，而有利於 細間距之產品設計。 上述實施例係用以例示性說明本發明之原理及其功 1Π2Π 201042737 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違月本發明之精神及範_下，對上述實施例進行修 此切明之權卿㈣圍，應如後叙申請專利範 及 圖式簡單説明】 弟1A至1£圖係為習知封裝基板之製法之示意圖；以 …土么XI圑 【主要元件符號說明】…、褒基板之 10 ' 20 100 、 200 11 基板本體 内層線路層 介電層 ]]a、2]0、210’ 粗越面 12、23 導電層 13 阻層 130 開口區 14 線路層 140 、 250 線路 141 、 251 電性連接墊 21 第一介電層 22 第一阻層 220 第一開D區 24 第二阻層 240 第二開D區 25 第一線路層 J2 ⑴21] 201042737 26 增層結構 260 第二介電層 261 第二線路層 262 導電盲孔 263 電性接觸墊 27 防焊層 270 開孔 S 導電材201042737 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate for preventing short-circuiting of electrical interconnections of the same layer and a method of fabricating the same. [Prior Art] In the current package substrate process, a plurality of dielectric layers are stacked on the substrate body, and a desired patterned circuit is disposed between the dielectric layers to form a package substrate structure; For the laminated structure, the bonding force between the layers is very important. In order to ensure the electrical connection of the layers, the conventional technique forms a rough sugar surface on the surface of the dielectric layer to increase the bonding strength between the dielectric layer and the line. Moreover, since the wiring trend of the package substrate is toward high-density and fine-line pitch, the method of fabricating the package substrate line is mainly the electric ore patterned circuit. Please refer to FIGS. 1A to 1E to provide a conventional package substrate fabrication circuit. Schematic diagram of the system. As shown in Fig. 1A, a substrate body 10 having an inner wiring layer 100 is provided, and a dielectric layer 11 is formed on at least one surface of the substrate body 10 to cover the inner wiring layer 100. As shown in FIG. 1B, a rough surface 11a is formed on the entire surface of the dielectric layer 11, and a conductive layer 12 is formed on the rough surface 11a of the dielectric layer 11; wherein the conductive layer 12 is generally Electroless copper plating. As shown in FIG. 1C, a resist layer 13 is formed on the conductive layer 12, and the resist layer 13 is exposed and developed to form a plurality of open regions 130, and a portion of the surface of the conductive layer 12 is exposed to the open regions 130. . As shown in FIG. 1D, the current conducting path of the 201042737 required for the conductive layer 12 as a plating metal is electrically formed on the conductive layer 12 in the open regions 13G to form a patterned wiring layer 14, and the wiring layer 14 is formed. There are a plurality of lines ^ and a plurality of electrical connection pads 141. & As shown in FIG. 1E, removing the resist layer 13 and the conductive layer covering it form a rough surface on the entire surface of the dielectric layer, and removing the conductive layer covered by the resist layer 13 The conductive layer U on the rough surface 11a of the 12 is not easy to be completely cleaned, resulting in the existence of a conductive material remaining on the adjacent line of the second and second mountain, thus reducing the product's ability to be short-circuited. In the case of fine pitch if〗, since the line pitch is narrow, the short circuit phenomenon is more likely to occur, which is disadvantageous for the use of the fine pitch package substrate. CM Health is how to avoid the shortcomings of the prior art. In view of the above-mentioned various deficiencies of the prior art, the present invention mainly provides a method for preventing electrical interconnection of the same layer. The invention relates to a package substrate capable of layer adhesion and a method for manufacturing the same. The spoon includes (4) 'this hair (four) exposed-type package substrate, the system ^, the electric layer, and the first circuit layer, which is transmitted on a part of the surface of the inflow layer; 1 , ^ ^ a dielectric ^ center a dielectric layer Part of the surface has a report of 4 】] 】 2] ΐ 201042737 matte surface 'The secret (4) is set in the first - circuit layer and the first - dielectric and the coarse round of the coarse sugar surface is larger than the surface of the layer without the first - circuit layer . W = Description: The package substrate may comprise a substrate body having a 22::: ☆ electrical layer disposed on the substrate body and covering the two-layer layer and electrically connected to the inner layer. The package substrate can be included between the + Ο first-circuit layers. The electrical layer is disposed on the (four) surface and the package substrate, and the pad and the wire layer layer may include a re-enactment + the line; and the first connection may be connected to the part or corresponding Each of the two: and the solder resist layer has a plurality of anti-Tan external roads on the plurality of two-way layers. 7 “Hui electric contact preparation structure, which is set in the above-mentioned package substrate.” 苐-dielectric layer and the first continuation of the 包 包 秸 曾 i Zengsheng has at least 1 2 dielectric On the first layer of the screen, the ruthenium layer and the plurality of conductive layers in the second dielectric layer are electrically connected to the second layer of the second core surface. Part of the surface of the electric layer: two lines: the thickness of the surface of the surface is greater than the surface of the second dielectric layer, the outermost sound of the layered structure; the second layer of the second layer, and the touch Pad, and in the second layer of the sound-increasing cymbal, the number of dielectric layers is open, so that each core = has a solder mask layer, and the electric contact is re-exposed to the invention - the type 2: exposed in ~: * The method of making a four-plate is a package of the first dielectric layer; a first barrier layer is formed on the first dielectric layer, and a first pattern is formed in the first barrier layer. Opening a region, exposing a portion of the surface of the first dielectric layer to the first opening regions; roughing the first dielectric layer in each of the first opening regions to cause the first dielectric layer section Forming a thick chain surface on the surface; removing the first resist layer and forming a conductive layer on the first dielectric layer and the rough surface thereof; forming a second resist layer on the conductive layer, and forming the second resist layer a plurality of patterned second opening regions, wherein the conductive layer on the rough surface is exposed to the second opening regions; a first circuit layer is formed on the conductive layer of the rough surface, and the coarse bond of the coarse sugar surface is formed Larger than the surface of the first dielectric layer not having the first circuit layer; and removing the second resist layer and the conductive layer covering the same, exposing the first line and the first dielectric layer. The method for manufacturing the package substrate The method further includes providing a substrate body, and the substrate body has an inner circuit layer, wherein the first dielectric layer is formed on at least one surface of the substrate body to cover the inner circuit layer, and the first circuit layer Electrically connecting to the inner circuit layer. The method for fabricating the package substrate includes forming a build-up structure on the exposed first dielectric layer and the first circuit layer, the build-up structure having at least one second dielectric layer Provided on the second dielectric layer a second circuit layer, and a plurality of conductive blind holes disposed in the second dielectric layer and electrically connected to the first and second circuit layers, wherein the surface of the second dielectric layer has a thick chain surface, the rough surface Is disposed between the second circuit layer and the second dielectric layer, and the roughness of the rough surface is greater than the surface of the second dielectric layer having no second circuit layer; and the second outermost layer of the buildup structure The circuit layer has a plurality of electrical contact pads, and the soldering layer is provided with a solder resist layer, and the solder resist layer has a plurality of openings,]]] 21] 201042737 so that each of the electrical contact pads corresponds to the outer % The substrate is sealed and exposed to each of the openings. The electrical connection pad and the line, the first circuit layer corresponds to each of the lines, and: the electrical connection pad is electrically connected to form a solder resist layer, and the The exposed first-dielectric layer and the second or touched contact are exposed to each of the opening and opening openings, so that the electrical properties are as follows: From the above, the invention can be found on the surface of the slow-moving layer. The first dielectric layer is only removed in conjunction with the read-leveling, so that the surface of the first circuit layer and the surface of the first dielectric layer remain effectively removed. The second limit is a flat surface around the electric enamel, and the conductive layer covered by the layer and the two electrical connection pads 俾 the first line strong circuit layer and the dielectric layer are not stomachic The New Road phenomenon can also increase the purpose. H and phase to improve the quality of electrical connection [Embodiment]: Under the specific implementation of the specifics, those who are familiar with the art will understand the other advantages and work of the present invention. For easy reference, please refer to the 2nd to 2nd && FIG. 2 is a cover of the present invention, as shown in FIG. 2A, and a soil plate body 20 is provided, and the substrate body 2 has an inner layer 2 layer and a turbulence plate body 20 A first dielectric layer 21 is formed on at least one surface to cover the inner wiring layer. In other implementations, the substrate read 2G can be a carrier board, and the carrier board is removed in a subsequent process to form a package substrate without a core board (em.dess). 1312]] 7 201042737 22: shown in FIG. 2B, on the first dielectric layer 21, the wheel 22, and the _-resist layer 22_ is formed with a complex/"1 and a layer 220, such that the first dielectric layer 21 Part of the table: = brother - open area 220., face Bu Road in the first - opening emperor as shown in Figure 2C 'in each of the first - open area a electrical layer 2" to carry out the roughening process, so The first interface of the first-eighth, the towel forms a rough surface 21〇. - the portion 4 of the electric layer is as shown in the 2D figure, and the dielectric layer 2] and the surface thereof are removed. /layer 22, to expose the first - as shown in Figure 2E, forming a conductive layer 23 on the first dielectric layer, and forming a second resistive layer 24 on the conductive layer 23 on the conductive layer 曰 = thick chain surface 210 The second opening region 240 of the plurality of patterns is formed, and the layer 23 formed in the layer 24 is exposed to the second opening regions 24 〇. The conductivity on the 210 is not shown in FIG. 2F. The layer a serves as a guide path 'for the flow path layer 25 of the 4 $ mineral of the rough sugar surface 21, and the first first road # " is plated to form a first linear connection 塾 (5) and each = has a plurality of lines (10) With multiple electric Γ Γ 连 251 Sexually connected to m = should be each of the lines 250, and the first circuit layer 25 and = or electrically connected to the inner layer of the circuit layer 2, and "W blind hole is a mature technology, no longer a writing The method of manufacturing the blind hole=sexual connection 塾Μ1 is a ball-forming pad or a flip chip; and the roughness of the rough surface 2] is higher than the surface of the first-dielectric layer 2]. No-there is a circuit layer 8 (1) 21] 201042737 As shown in FIG. 2G, the second resist layer 24 and its covered conductive layer 23 are removed to expose the first dielectric layer 21 and the first wiring layer 25 . Compared with the conventional dielectric layer, the first dielectric layer 21 forms a rough surface 210 only on the surface of the first circuit layer 25 to ensure the first dielectric. The bonding strength between the layer 21 and the first circuit layer 25, and the remaining surface of the first dielectric layer 21 remains flat, so that the periphery of the first circuit layer 25 is a flat surface, and can be effectively moved completely In addition to the second resist layer 24 and the conductive layer 23 covered thereby. Therefore, after removing the second resist layer 24 and the conductive layer 23 covered by the second resist layer 24, the conductive layer 23 does not remain on the flat surface of the first dielectric layer 21, so that the line 250 or the electrical connection The conductive layer 23 does not remain around the pad 251 to avoid bridging between the line 250 or each of the electrical connection pads 251, and the bonding strength between the circuit layer and the dielectric layer can be enhanced. As shown in FIG. 2H, in another embodiment of the subsequent process, the electrical connection pad 251 is not used for connecting external electronic components (such as solder bumps), but is used as a subsequent line build-up process. Electrically connecting the conductive via holes to form a line build-up structure; forming a build-up structure 26 on the first dielectric layer 21 and the first circuit layer 25, the build-up structure 26 having at least a second dielectric The layer 260, the second circuit layer 261 disposed on the second dielectric layer 260, and the plurality of conductive vias 262 disposed in the second dielectric layer 260 and electrically connected to the first and second circuit layers 25, 261 And the surface of the second dielectric layer 260 has a rough surface 210 ′, the rough surface 210 ′ is disposed between the second circuit layer 261 and the second dielectric layer 260 , and the rough surface 21 (T The roughness is greater than the surface of the second dielectric layer 260 having no second wiring layer 26], the surface of the second dielectric layer 260, and the second wiring layer of the additional layer structure 26, the additive contact pad 263, and the layered structure 26 ^ The plurality of electric solder mask layers 27 have a plurality of openings 27 〇 such that each 胄 = 27, and the exposed portions are respectively 27 The above-mentioned 263 is corresponding to the foregoing, and the present invention discloses a dielectric layer 21; the f-circuit layer 25 is disposed on the first surface of the soil, wherein: the first medium Part of the surface of the electrical layer 21: the surface 210 of the layer 21, the thick chain surface 21 is disposed between the 兮', has a roughness, and is between the green layer 25 of the green layer 25, and the roughness of the thick interface 2104 is greater than The surface of the first dielectric layer 21 of the unintercalated circuit layer 25 has a first line. (4) The wire can be shown as a core board stack. The package substrate includes a substrate body 2〇, which is a 72G diagram. Nn, a 妓 穿 穿 八 —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— The core board (G_ess) type (not shown in the figure), that is, the board can be no body 20. The cover board has a wide layer 23 between the board and the 'circuit layer 25, The other έ海第~线路层25 is a sentence of Zhao Yuxu & and line 250, "the number of electrical connection pads 2S1 251, and each ^ the line 25G electrical connection 51 and each of the electrical connection pads The electrical connection pad 25. 'And read the first - green road ...: =: copies or corresponding to the 'inner wiring layer 2 〇.; two Asian two conductive blind hole electrical fans 4 » 笙一# 〇α, In the case of households and knowing evil, this is the time to change to the dielectric layer and the second layer of the circuit layer 25, τν ..., % brother a) The solder resist layer can be provided with a solder layer (not shown in the figure) The hole is not opened by the flying watch (not shown in the figure as the electric candle 2), and the pound 10 201042737 pad 251 corresponds to the electrical contact sound exposed to the electronic device of each reading opening. And the electrical connection to the other of the sealed substrate may include a germanium layer 21 and a first wiring layer 25, 26' is disposed on the first dielectric layer 260, and is disposed in the second dielectric layer: : The layer structure % has at least _: and a plurality of conductive layers disposed on the second dielectric layer 26 of the έ — - line layer 26 ι, layer 25, 261 | '... electrically connected to read the first and the first _ only double ♦ The electric blind hole 2 phantom, the 夂罘-line Ο Ο surface has a rough surface 21 〇, the present person ~ dielectric layer 260 part of the layer 261 and the second dielectric layer, the ^ surface 210 is set in the second line It is larger than the surface of the first 'tantalum layer 260' which is not the second layer of the second layer and the roughness of the surface layer of the layered structure 26. The pad 263, and the layered structure 2', the table layer 261 has a plurality of electrical contacts 27 having a plurality of openings 270, a 'with a solder resist layer 27, and the solder resist layer each of the openings 270. The electrical contact pads of the present invention are correspondingly exposed to the above, and the first-stage of the present invention is on the first-dielectric sound::: the straw is defined by the two-layer process, the electrical layer defines roughness. The surface layer and the second layer are formed on the rough surface, and the conductive layer covered by the two-layer resist layer, that is, the flat layer & the king removes the conductive layer of the first electrical layer, that is, the entire surface of the thousand layers. The conductive layer is not left between the first circuit layer and each of the electrical connection pads, and the short circuit phenomenon is effectively avoided, which not only effectively achieves the purpose of improving the electrical connection yield, but also serves as a fine pitch (finepitch). During design, the short-circuit phenomenon is not easy to occur, and the bonding strength between the circuit layer and the dielectric layer can be enhanced, which is advantageous for product design with fine pitch. The above embodiments are intended to exemplify the principles of the invention and its advantages, and are not intended to limit the invention. Anyone who is familiar with this skill can use the spirit and scope of the invention without departing from the scope of the invention. The right to modify the above-mentioned embodiments, the right (4), should be as follows, the application of the patent and the simple description of the drawings] 1A to 1 is a schematic diagram of a conventional method for manufacturing a package substrate; for [...] 圑 圑 圑 [main component symbol description], 褒 substrate 10 ' 20 100 , 200 11 substrate inner layer wiring layer dielectric layer]] a, 2] 0, 210' coarse facet 12, 23 conductive layer 13 resist layer 130 open area 14 circuit layer 140, 250 line 141, 251 electrical connection pad 21 first dielectric layer 22 first resistance layer 220 first Open D zone 24 Second resistive layer 240 Second open D zone 25 First circuit layer J2 (1) 21] 201042737 26 Additive structure 260 Second dielectric layer 261 Second circuit layer 262 Conductive blind hole 263 Electrical contact pad 27 Anti-welding Layer 270 opening S conductive material
ΟΟ