,201037432 六、發明說明： 【發明所屬之技術領域】 特別是關於一種高顯示品質之畫素 本發明係有關一種電極結構， 電極結構。 【先前技術】 清參閱第1圖，在傳統絲矩陣式晶顯示器（LCD)令其 單閘極電路娜之每個4素具有-薄輯晶體（TFT) 1Q，其問極連 接至水平方向的掃瞒線12 ’源極連接至垂直方向的資料線14，汲極則 連接至晝素電極，鄰行的薄膜電晶體1〇有各自連接的資料線14。 〇 ⑵下介紹此傳統電㈣構的基本操作方式，在水平方向上的同一 條掃瞒線12上，所有細電晶體1Q的閘極都連接在ϋ以施加 電壓疋連動的’若在某-條触線12上施加足夠大的正電壓，則此條 掃瞎線上所有的薄膜電晶體12都會被打開，此時該條掃猫線12上的 畫素電極’會與垂直方向的資料線14連接，而經由垂直f料線14送 入對應的概健’以將畫素電極充電至適當的電壓。接著施加足夠 =的負广壓’酬薄膜電晶體i。’直到下次再重新寫人信號，其間使 得電射保存在液晶電容上；此時再啟動—條水平掃猫線12，送入其對 應的視訊信號。如此依序將整個畫面的視訊資料寫入，再重新自第一 ^ 條重新寫入信號。 上述之單閘極電路架構由於資料線14的數量過多，因此其消耗在 源極晶片上的成本相當向’而為了減少此成本的消耗，後來的技術提 出了 -種雙閘極電路架構，也就是如第2圖所示，相鄰兩行的薄膜電 晶體16共用同一條資料線18，這樣一來，就可以減少資料線18的使 用數夏’進而降低源極晶片的製造成本^另外為了解決面板顯示的串 音(crosstalk)現象，在相鄰的資料線18之間，更設有一虛擬線2〇，並 在虛擬線20上提供與資料線彳8極性相反的訊號，如此便能使面板呈 現更好顯示效果。 3 201037432 但是對於上述所提供的技術而言，其從電路佈局來觀察，如第3 圖所示’因為共通電極線22佔有面積過大’使電極層24扣掉形成共 通電極線22之金屬層的透光區域變少，進而讓整個面板的開口率有所 損失。 因此，本發明係在針對上述之困擾，提出一種高顯示品質之畫素 電極結構，以解決習知所產生的問題。 【發明内容】 本發明之主要目的，在於提供一種高顯示品質之畫素電極結構， 其係將共通電極線設置在相鄰之掃瞄線之間，以減少共通電極線之數 量’如此可提升面板之畫素開口率。 本發明之另一目的，在於提供一種高顯示品質之晝素電極結構， 其係將共通電極線與虛擬線做短路連接，以擁有較佳的共同訊號之穩 疋性，並於資料線斷線時，可利用雷射修補的方式再與虛擬線連接， 藉此提升良率。 為達上述目的，本發明提供一種高顯示品質之畫素電極結構，包 含一透明基板，此基板上設有一資料線、一共通電極線與一第一、第 -陣列畫素’第-卩車列畫素係形成一第—薄膜電晶體、—第一畫素電 極與一第一掃瞄線，且使共通電極線設置於第一掃瞄線侧方，第二陣 列畫素係形成-第二薄膜電晶體、—第二畫素電極、—第二掃猫線， 且亦使共通電極線設置於第二掃瞄線側方，另在共通電極線上設有一 第一、第二通孔，其分別與第一、第二薄膜電晶體延伸端接觸，在資 料線之側邊設有一虛擬線，且又有一第三通孔位於虛擬線與共通電極 線上。 兹為使貴審查委員對本發明之結構特徵及所達成之功效更有進 一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明 如後： 【實施方式】 201037432 本發明所製作之㈣顯柯板主㈣_先紐術已 線與和與薄膜電晶體端之共通電極連接的共通電極線進行短路 請同時參閲第4圖與第5圖之電路佈局的第—實施例，第5圖為第* 圖中虛線雜巾的4素電姆構之放，此虛財框中所有的 疋件包含H：極層50形成的畫素電極、二顆薄膜電频％、28及 ❹ 其周圍的佈線，薄膜電晶體26、28為N型，而第4圖則是以此虛線 方框中的4素雜賴料it，彼此_軸線(Gate丨丨η_、資料 線(Data Hne)32、虛擬線34及共通電極線邡相互連接而構成的陣列 液晶顯示面板。且’由於晝素電極結構在顯示面板上是以矩陣方式排 列’因此同-行的晝素電極、结構會共用同一條資料線32、虛擬線34， 同-列的畫素電極、结構會共用同一條掃瞎線3〇與共通電極線36。每 -個畫素電極結射的元件之連制雜㈣_都朗，兹以一個 畫素電極結構為例，陳述如下。 為了清楚說明實施方式，以下請同時參閱第5圖與第6圖，第6 圖為第5圖之電路佈局(|ay0Ut)結構中沿A_A’切線之剖視圖，可表達出 第5圖中所包含的元件之上下堆疊關係。第5圖為一畫素_結構， 其主要包含一透明基板38、一第一陣列畫素與一第二陣列晝素，第 一、第二陣列晝素係分別形成第一、第二薄膜電晶體26、28、第—、 © 第二畫素電極33、35，以及第一、第二掃瞄線6〇、62。第一、第二 陣列晝素係由一第一金屬層40、一絕緣層42、一半導體層44、一第 —金屬層46、一保護層48、一電極層50所形成，而液晶層係設在電 極層上50。保護層48係為一絕緣材質，其與絕緣層42之材質皆為氮 化矽，電極層50的材質為氧化銦錫（IT0)，且此電極層50係形成與 第一、第二薄膜電晶體26、28分別連接之第一、第二畫素電極33、' 35 〇 第一金屬層40係設於透明基板38上，以形成一第一薄臈電晶體 26之閘極56、一第二薄膜電晶體28之閘極58、一第一掃瞄線6〇、 —第二掃瞄線62與在第一掃瞄線60下方與第二掃瞄線62上方之兩 5 201037432 者中間的一共通電極線64，然在第一金屬層40形成時，同時分別將 第一、第二掃描線60、62與第一、第二薄膜電晶體26、28之閘極 56、58形成為相連之線路，第一金屬層4〇形成後其上係形成有一絕 緣層42 ’絕緣層42係於第一、二薄膜電晶體26、28上作為閘極絕緣 層。絕緣層42上係設有半導體層44，此半導體層44分為上下二層結 構，其下層為一非晶矽層(a-Si)52，係直接設於絕緣層42上，其上層 為一n+摻雜非晶矽(η+a-Si)之歐姆接觸層54，歐姆接觸層54與絕緣層 42上係設有一第二金屬層46,以形成第一、第二薄膜電晶體26、28 之源極66、68與汲極70、72、一虛擬線74與在該虛擬線74側邊的 一資料線78，資料線78係連接第一、第二薄膜電晶體26、28之源極 66、68 ’又第一、第二薄膜電晶體26、28係位於資料線78的相異兩 側，第一、第二薄膜電晶體26、28係分別位於第一、第二掃瞄線6〇、 62的相異兩侧’第一、第二薄膜電晶體26、28 n 68、汲極 70、72係分別位於第一、第二薄膜電晶體26、28之開極％、邱上 方，且非晶矽層52與歐姆接觸層54皆位於第一、第二薄膜電晶體26、 28之源極66、68與汲極7〇、72下方，虛擬線74與資料線78互相 平行設置，並與共通電極線64及第一、第二掃猫線6〇、62垂直交會。 另從圖中可以發現，第一畫素電極33設於第一掃瞒線6〇下方且 掃極線64及第二掃猫線位，其中第一畫素電極33與第二 品f重疊面積小於第一晝素電極33與共通電極線64重疊面積。 及第二二素，極35設於第二掃晦線62上方且重叠於共通電極線64 其中第二畫素電極35與第一掃晦線60重疊面積小 ;第一畫素電極35與共通電極線64重疊面積。 電路參閱第5圖、第6圖及第7圖，第7圖為第5圖之 妨上’切線之剖視圖。歐姆接觸層54與第二金屬層 電晶=2—8 此保護層48具有分別位於第一、第二薄膜 極70、72和半導體層44上方的-第-、第二通 0、81，與位於虛擬線74和共通電極線64之交界處的—第三通孔 .201037432 82，且虛擬線74上之保護層48僅有部份覆蓋其線寬，第三通孔82 係同時貫穿下方之絕緣層42，另在保護層48蝕刻出第一、一第二通孔 80、81時，因無法透過半導體層44並繼續往絕緣層42餘刻，^以第 〜、第二通孔80、81的深度係僅能到達半導體層44。第"―通孔8〇 為第6圖之剖視圖中的保護層48沒有連接的部分，第三通孔82為第 7圖之剖視圖中的保護層48與絕緣層42沒有連接的部分。 在保護層48上係設有-電極層50，此電極層5〇二但可藉由第 一、第二通孔80、81與對應的第一、第二薄膜電晶體26、功之沒極 7〇、72和半導體層44相接觸，又可藉由第三通孔82與虛擬線μ和 〇 共通電極線64相接觸。如第6圖所示，由於通孔的緣故，作為沒極 的第二金屬層46和半導體層44暴露在外，因此可與電極層5〇相 接觸；亦如第7圖所示’由於通孔的緣故，作為虛擬線74之第二金屬 層46和作為共通電極線64之第一金屬層4〇也暴露在外因此可與 電極層50相接觸，此處的電極層50為獨立電極層區塊，可將虛擬^ 74與共通電極線64相連接並令其導通。 ' 另外，與薄膜電晶體之汲極相接觸的電極層5〇和第—金屬層4〇、 第二金屬層46重疊的部分，可形成該薄膜電晶體之儲存電容。如第一 相電晶體26找極70有-部分係往共通電極線μ延伸，並與此 〇共，電極線64和電極層50重疊之部分為第一薄膜電晶體26之儲存 電容；第二薄膜電晶體28之汲極72有-部分係往共通電極線64延 伸’並與此共通電極線64和電極層50重疊之部分為第二薄膜電晶體 28之儲存電容。 還有，此實施例之電極層50並沒有與第一、第二薄膜電晶體26、 之沒極、72側的第一、第二掃晦線6〇、62重疊，所以在連接 每個細f晶體之電極層邊緣處，賴於彩色就片情應設置遮光 ，，如黑色矩陣（BM )。如此一來，當顯示面板製作成液晶顯示器時， 母個畫素邊緣才不會出現漏光’而影響液晶分子排列，且鄰接畫素 才不會出現混色的現象。 7 201037432 利用上述電路佈局所製造出來的液晶顯示面板如第4圖所示，可 與先則技術之第3圖同時比較，在相鄰掃瞄線3〇與相鄰資料線32的 一個電極層50為分別二個畫素的畫素顯示區，在本發明之設計下，共 通電極線36*會侵佔到電極層50之透光區域的面積，另外在相同的 電晶體的數量下’第4圖所使用朗共通電極線36的數量比第3圖 少，如八顆電晶體本發明僅用到二條共通電極線，而先前技術卻用到 四條，換句話說，如此設計便能提升畫素的開口率。 接著請同時參閲第8圖與第9圖之電路佈局的第二實施例，其與 第一實施例的差異在於電極層50係與第一、第二薄膜電晶體26、28 之汲極70、72侧的第一、第二掃瞄線60、62部份重疊，所以在連接 每個薄膜電晶體之電極層與第一、第二掃瞄線6〇'62重疊區域的邊緣 處，不必於彩色濾光片中對應設置遮光物，此種設計可同時增加了儲 存電谷的分佈面積，進而減少面板閃爍率，且增加其開口率。 參閱完本發明之電路佈局，請繼續參閱其等效電路圖，如第1〇圖 所示。本發明之液晶顯示面板的等效電路包含複數條平行之掃描線86 與複數條平行之資料線84 ,掃描線86包含有一第一掃描線862與一 第二掃描線864 ’資料線84係與掃描線86互相垂直，且資料線84 中包含一第一資料線842，掃描線86係與複數共通電極線88互相平 行’且共通電極線88包含一第一共通電極線882。 本發明之液晶顯示面板還包含以矩陣方式排列的複數雙閘極畫素 單元92,並以資料線84、掃瞄線86與共通電極線88彼此連接而成， 每一個雙閘極畫素單元92係連接一條資料線84、二條掃瞄線86與一 條共通電極線88。同一行的雙閘極畫素單元92會共用同一條資料線 84，同一列的雙閘極畫素單元92會共用同一條掃瞄線86與共通電極 線88。每一個雙閘極晝素單元92中的元件之連接關係與位置關係都 相同，茲以一個雙閘極畫素單元92為例，並將第一、第二掃瞄線862、 864、第一資料線842、第一共通電極線882與一雙閘極畫素單元 彼此之間的連接與位置關係介紹如下。 201037432 請同時參閱第圖，每一個雙閘極畫素單元92包含一第一薄膜 電晶體922及其對應連接之一第一液晶電容925、一第一儲存電容 926 ’與一第二薄臈電晶體924及其對應連接之一第二液晶電容927、 一第二儲存電容928，且第一掃瞄線862與第二掃瞄線864之相異兩 側係分別設有一薄膜電晶體及其對應連接之液晶電容、儲存電容，第 一資料線842之相異兩側亦分別設有一薄膜電晶體及其對應連接之液 晶電容、儲存電容’第一掃瞄線862及第二掃瞄線864係設於第一共 通電極線882的相異兩側。, 201037432 VI. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to an electrode structure and an electrode structure. [Prior Art] Referring to Fig. 1, in a conventional silk matrix crystal display (LCD), each of its single-gate circuits has a thin-crystal (TFT) 1Q, and its polarity is connected to the horizontal direction. The broom line 12' source is connected to the vertical data line 14, the drain is connected to the halogen electrode, and the adjacent thin film transistor 1 has the respective connected data line 14. Under 〇(2), the basic operation mode of this conventional electric (four) structure is introduced. On the same broom line 12 in the horizontal direction, all the gates of the fine transistor 1Q are connected to the ϋ 施加 施加 施加 施加 施加 施加When a sufficiently large positive voltage is applied to the strip 12, all of the thin film transistors 12 on the sweep line are opened, and the pixel electrode ' on the sweeping cat line 12 and the vertical data line 14 Connected, while the corresponding fringe is fed via the vertical f-feed line 14 to charge the pixel electrodes to the appropriate voltage. Then apply a negative and wide pressure of the negative film transistor i. ’ Until the next time the person signal is rewritten, the electric radiation is saved on the liquid crystal capacitor; at this time, the horizontal sweeping cat line 12 is sent to send its corresponding video signal. In this way, the video data of the entire screen is sequentially written, and the signal is rewritten from the first ^ strip. The single gate circuit architecture described above has a large amount of data lines 14, so the cost of consuming it on the source wafer is quite 'to reduce the cost. The latter technology proposes a double gate circuit architecture. As shown in Fig. 2, the adjacent two rows of thin film transistors 16 share the same data line 18, so that the number of data lines 18 can be reduced, thereby reducing the manufacturing cost of the source wafer. To solve the crosstalk phenomenon displayed on the panel, between the adjacent data lines 18, a virtual line 2 is further provided, and a signal opposite to the polarity of the data line 8 is provided on the virtual line 20, so that The panel presents a better display. 3 201037432 However, for the technique provided above, it is observed from the circuit layout, as shown in FIG. 3 'Because the common electrode line 22 occupies an excessive area', the electrode layer 24 is buckled off to form the metal layer of the common electrode line 22. The light-transmissive area is reduced, which in turn causes a loss in the aperture ratio of the entire panel. Accordingly, the present invention has been made in view of the above-mentioned problems, and has proposed a pixel structure of high display quality to solve the problems caused by the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a pixel display structure with high display quality, which is to set a common electrode line between adjacent scan lines to reduce the number of common electrode lines. The aperture ratio of the panel. Another object of the present invention is to provide a high display quality pixel electrode structure, which is to short-circuit the common electrode line and the virtual line to have better stability of the common signal and disconnect the data line. At the same time, you can use the laser patching method to connect with the virtual line to improve the yield. In order to achieve the above object, the present invention provides a pixel display structure with high display quality, comprising a transparent substrate, wherein the substrate is provided with a data line, a common electrode line and a first, first-array pixel 'di-car The column elements form a first-thin film transistor, a first pixel electrode and a first scan line, and the common electrode line is disposed on the side of the first scan line, and the second array of pixels is formed - a thin film transistor, a second pixel electrode, a second mouse line, and a common electrode line is disposed on a side of the second scan line, and a first and a second through hole are disposed on the common electrode line. They are respectively in contact with the extending ends of the first and second thin film transistors, and a dummy line is disposed on a side of the data line, and a third through hole is located on the virtual line and the common electrode line. In order to provide a better understanding and understanding of the structural features and the achievable effects of the present invention, the preferred embodiments and the detailed description are as follows: [Embodiment] 201037432 The present invention (4) The main board of the board (4) _ first button has been short-circuited with the common electrode line connected to the common electrode of the thin film transistor. Please refer to the first embodiment of the circuit layout of FIGS. 4 and 5. Figure 5 is a diagram of the four-dimensional electric structure of the dotted scarf in the figure *, all the components in the virtual frame contain H: the pixel electrode formed by the pole layer 50, two thin film frequency %, 28 And ❹ the wiring around it, the thin film transistors 26, 28 are N-type, and the fourth picture is the four-dimensional miscellaneous it in the dotted box, each other_axis (Gate丨丨η_, data line (Data An array liquid crystal display panel formed by interconnecting HX) 32, imaginary line 34 and common electrode line 。. And 'since the pixel structure is arranged in a matrix on the display panel, the same-line pixel electrode and structure will be Share the same data line 32, virtual line 34, same-column The pixel electrode and structure share the same broom line 3〇 and the common electrode line 36. The components of each of the pixel electrodes are connected to each other (4)_Dulang, and a pixel element structure is taken as an example. In order to clarify the embodiment, please refer to Fig. 5 and Fig. 6 at the same time. Fig. 6 is a cross-sectional view along the line A_A' in the circuit layout (|ay0Ut) of Fig. 5, which can be expressed in Fig. 5. The included components are stacked on top of each other. Figure 5 is a pixel structure, which mainly includes a transparent substrate 38, a first array of pixels and a second array of pixels, and the first and second arrays of elements. Forming the first and second thin film transistors 26, 28, the first, the second second pixel electrodes 33, 35, and the first and second scan lines 6A, 62, respectively. The first metal layer 40, an insulating layer 42, a semiconductor layer 44, a first metal layer 46, a protective layer 48, and an electrode layer 50 are formed, and the liquid crystal layer is disposed on the electrode layer 50. The 48 series is an insulating material, and the material of the insulating layer 42 is tantalum nitride, and the material of the electrode layer 50 is oxidized. Tin (IT0), and the electrode layer 50 is formed by first and second pixel electrodes 33 connected to the first and second thin film transistors 26 and 28, and the first metal layer 40 is disposed on the transparent substrate. 38, to form a gate 56 of a first thin germanium transistor 26, a gate 58 of a second thin film transistor 28, a first scan line 6〇, a second scan line 62 and a first A common electrode line 64 between the lower portion of the scan line 60 and the two 5 201037432 above the second scan line 62. However, when the first metal layer 40 is formed, the first and second scan lines 60 and 62 are respectively The gates 56, 58 of the first and second thin film transistors 26, 28 are formed as connected lines, and the first metal layer 4 is formed with an insulating layer 42 formed thereon. The insulating layer 42 is attached to the first and second films. The transistors 26, 28 serve as a gate insulating layer. A semiconductor layer 44 is disposed on the insulating layer 42. The semiconductor layer 44 is divided into upper and lower layers. The lower layer is an amorphous germanium layer (a-Si) 52, which is directly disposed on the insulating layer 42 and has an upper layer. An ohmic contact layer 54 of n+ doped amorphous germanium (η+a-Si), a second metal layer 46 is disposed on the ohmic contact layer 54 and the insulating layer 42 to form first and second thin film transistors 26, 28 The source 66, 68 and the drain 70, 72, a virtual line 74 and a data line 78 on the side of the virtual line 74, the data line 78 is connected to the source of the first and second thin film transistors 26, 28. 66, 68 'the first and second thin film transistors 26, 28 are located on opposite sides of the data line 78, and the first and second thin film transistors 26, 28 are respectively located on the first and second scan lines 6 The first and second thin film transistors 26, 28 n 68 and the drain electrodes 70 and 72 of the first and second thin film transistors 26 and 28 are located at the upper and lower sides of the first and second thin film transistors 26 and 28, respectively. The amorphous germanium layer 52 and the ohmic contact layer 54 are both located under the sources 66, 68 and the drains 7 and 72 of the first and second thin film transistors 26 and 28, and the dummy lines 74 and the data lines 78 are arranged in parallel with each other. And the common electrode line 64 and the first and second scan lines 6〇 cat, 62 perpendicular intersection. It can be seen from the figure that the first pixel electrode 33 is disposed under the first broom line 6〇 and the sweep line 64 and the second sweeping cat line position, wherein the area of the first pixel electrode 33 and the second product f overlap. It is smaller than the overlapping area of the first halogen electrode 33 and the common electrode line 64. And the second element, the pole 35 is disposed above the second broom line 62 and overlaps the common electrode line 64, wherein the second pixel electrode 35 overlaps with the first broom line 60; the first pixel electrode 35 is common to The electrode lines 64 overlap the area. Refer to Figures 5, 6, and 7 for the circuit. Figure 7 is a cross-sectional view of the tangential line of Figure 5. The ohmic contact layer 54 and the second metal layer are electromorphized = 2-8. The protective layer 48 has -- and second-passes 0, 81 located above the first and second thin film electrodes 70, 72 and the semiconductor layer 44, respectively. The third via hole is located at the intersection of the imaginary line 74 and the common electrode line 64. 201037432 82, and the protective layer 48 on the imaginary line 74 only partially covers the line width thereof, and the third through hole 82 is simultaneously penetrated below. In the insulating layer 42, when the first and second via holes 80, 81 are etched by the protective layer 48, the first and second via holes 80 are not able to pass through the semiconductor layer 44 and continue to the insulating layer 42. The depth of 81 can only reach the semiconductor layer 44. The "through hole 8' is a portion where the protective layer 48 in the cross-sectional view of Fig. 6 is not connected, and the third through hole 82 is a portion where the protective layer 48 and the insulating layer 42 are not connected in the cross-sectional view of Fig. 7. An electrode layer 50 is disposed on the protective layer 48, and the electrode layer 5 is formed by the first and second via holes 80, 81 and the corresponding first and second thin film transistors 26 The semiconductor layer 44 is in contact with the semiconductor layer 44, and is further contacted with the dummy line μ and the common electrode line 64 via the third via 82. As shown in FIG. 6, due to the via hole, the second metal layer 46 and the semiconductor layer 44, which are infinite, are exposed, so that they can be in contact with the electrode layer 5; as shown in Fig. 7, due to the through hole For this reason, the second metal layer 46 as the dummy line 74 and the first metal layer 4 as the common electrode line 64 are also exposed and thus can be in contact with the electrode layer 50, where the electrode layer 50 is an independent electrode layer block. The dummy ^ 74 can be connected to the common electrode line 64 and turned on. Further, a portion of the electrode layer 5A which is in contact with the drain of the thin film transistor and the portion where the first metal layer 4A and the second metal layer 46 overlap may form a storage capacitor of the thin film transistor. For example, the first phase transistor 26 has a portion 70 extending toward the common electrode line μ, and in common with this, the portion where the electrode line 64 and the electrode layer 50 overlap is the storage capacitance of the first thin film transistor 26; The drain portion 72 of the thin film transistor 28 has a portion extending toward the common electrode line 64 and a portion overlapping the common electrode line 64 and the electrode layer 50 is a storage capacitor of the second thin film transistor 28. Further, the electrode layer 50 of this embodiment does not overlap with the first and second thin film transistors 26, the second and second broom lines 6〇, 62 on the 72 side, so that each thin connection is connected. At the edge of the electrode layer of the f crystal, depending on the color, the shading should be set, such as the black matrix (BM). In this way, when the display panel is fabricated into a liquid crystal display, the edge of the mother pixel does not appear to leak light, which affects the alignment of the liquid crystal molecules, and the adjacent pixels do not appear to be mixed. 7 201037432 The liquid crystal display panel manufactured by using the above circuit layout is as shown in FIG. 4, and can be compared with the third image of the prior art, in an adjacent electrode line 3 and an electrode layer of the adjacent data line 32. 50 is a pixel display area of two pixels respectively. Under the design of the present invention, the common electrode line 36* will occupy the area of the light-transmitting area of the electrode layer 50, and in the same number of transistors, the fourth The number of Lang common electrode lines 36 used in the figure is less than that of the third figure. For example, eight transistors use only two common electrode lines in the present invention, but the prior art uses four, in other words, the design can enhance the pixels. The aperture ratio. Next, please refer to the second embodiment of the circuit layout of FIGS. 8 and 9 simultaneously, which differs from the first embodiment in that the electrode layer 50 is connected to the drains 70 of the first and second thin film transistors 26, 28. The first and second scan lines 60, 62 on the 72 side overlap partially, so at the edge of the region where the electrode layer connecting each of the thin film transistors overlaps the first and second scan lines 6 〇 '62, it is not necessary Corresponding to the setting of the shade in the color filter, this design can simultaneously increase the distribution area of the storage valley, thereby reducing the panel flicker rate and increasing the aperture ratio. Having completed the circuit layout of the present invention, please continue to refer to its equivalent circuit diagram, as shown in Figure 1. The equivalent circuit of the liquid crystal display panel of the present invention comprises a plurality of parallel scan lines 86 and a plurality of parallel data lines 84. The scan lines 86 include a first scan line 862 and a second scan line 864 'data line 84. The scan lines 86 are perpendicular to each other, and the data line 84 includes a first data line 842, the scan line 86 is parallel to the plurality of common electrode lines 88, and the common electrode line 88 includes a first common electrode line 882. The liquid crystal display panel of the present invention further comprises a plurality of double gate pixel units 92 arranged in a matrix, and is formed by connecting the data line 84, the scan line 86 and the common electrode line 88 to each other, and each double gate pixel unit The 92 series connects one data line 84, two scanning lines 86, and one common electrode line 88. The double gate pixel unit 92 of the same row shares the same data line 84, and the double gate pixel unit 92 of the same column shares the same scanning line 86 and the common electrode line 88. The connection relationship and positional relationship of the components in each of the double-gate micro-element units 92 are the same. For example, a double-gate pixel unit 92 is taken as an example, and the first and second scan lines 862, 864 and the first data are used. The connection and positional relationship between the line 842, the first common electrode line 882 and a double gate pixel unit are described below. 201037432 Please also refer to the figure. Each double gate pixel unit 92 includes a first thin film transistor 922 and a corresponding one of the first liquid crystal capacitor 925, a first storage capacitor 926' and a second thin capacitor. The crystal 924 and its corresponding connection are a second liquid crystal capacitor 927 and a second storage capacitor 928, and the opposite sides of the first scan line 862 and the second scan line 864 are respectively provided with a thin film transistor and corresponding The connected liquid crystal capacitor and the storage capacitor are respectively provided with a thin film transistor and a correspondingly connected liquid crystal capacitor and a storage capacitor 'the first scan line 862 and the second scan line 864 on the opposite sides of the first data line 842. They are disposed on opposite sides of the first common electrode line 882.
❹ 第一薄膜電晶體922之閘極連接第一掃瞄線862，其源極連接第 一資料線842，其汲極連接第一液晶電容925與第一儲存電容926之 一端，第一液晶電容925之另一端連接一彩色濾光片（CF)端之共通電 極，以接收一第一共通電極訊號，第一儲存電容926之另一端連接第 一共通電極線882，第一資料線842與第一共通電極線882分別傳輸 一資料訊號與一第二共通電極訊號至第一薄膜電晶體922中，且第一 掃猫線862控制第一薄膜電晶體922接收該資料訊號，進而控制第一 液晶電容925之充放電’而第—儲存電容926侧來維持第一液晶電 容925兩端的電位差，以防第—液晶電容925漏電的情況發生。 同樣地，第二薄膜電晶體924之閘極連接第二掃瞄線864，其源 極連接第-資料線842，其沒極連接第二液晶電容927與第二儲存電 容928之-端’第二液晶電容927之另___端連接彩色渡光片端之共通 電極’以接收第-共通電極訊號，第二儲存電容928之另-端連 ^共通電極線882 ’第-資料線842與第—共通電極線882分別 資料訊號與第二共通電極訊號至第二薄膜電晶體924中，: 線864控制第二薄膜電晶體924接收該資料訊號，進而控制第曰 電容927之充放電，而第二儲存電容9功係用來維持第二液晶電= 兩端的電位差，以防第二液晶電容927漏電的情況發生。 液晶顯示®㈣包含複數虛擬線9Q，每—條虛 於相鄰兩行德_料㈣Μ，並娜雜紐紐=叹 9 201037432 由於在第一共通電極訊號在共通電極線88傳輸的過程中，會因為伟線 的長度過長而造成面板中央處的訊號不穩定，因此將共通電極線88藉 由與該些虛擬線90短路，以穩定第二共通電極訊號。 第10圖可與先則技術之第2圖同時比較，如同電路佈局比較的結 果’在相同的電晶艘的數量下，第8圖所使用到的共通電極線的數量 比第2圖少，換句話說，如此便能提升畫素的開口率，且此電路設計 可應用於垂直配向式（VA type)、扭轉向列式（tn type)、平面棘換 式卿之液晶或是有有機緣膜之畫素設計。ΥΡ )千面轉換 請繼續參’ 1G @，本發明之液晶顯示面板的作動描述如下首 先每-條共通電極線88與資料線84係分別傳輸一第二共通電極訊號 與一資料訊號至連接的儲存電容98與薄膜電晶體94中，且每一個液 晶電容96係接收-第-共通電極訊號，同時由於每一條共通電極線 88彼此藉由虛擬線90短路連接的緣故，因此在每一條共通電極線册 中的第二共通電極訊號是相當穩定的。接著利用掃故線86由上而下依 序控制每-行的細電晶體94接收該資料纖，麵控制液晶電容 96之充放電’啊連接液晶電容96的鱗電容98卿來轉液晶電 容96兩端的電位差。 最後請參閱第12圖，本發明之液晶顯示面板的電路設計還有一項 優點’即疋當資料線842斷線時，可在虛線方框所在位置處利用雷射 將其斷線後’在虛線圈所在位置處，再綱雷射將第-資料線842與 共通電極線88連接，即可利用第一虛擬線902來代替以斷線之資料 線842而修補完成，同時提昇產品良率。 综上所述’本發明不但可提升面板之畫素開口率，又將共通電極 線與虛擬義轉連接，_魏佳的共_狀穩纽，是 當實用的發明。 以上所述者’僅為本發明—健實闕而已，麟絲限定本發 明實施之制，轉凡依本發”請專職騎述之形狀、構造 徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍 201037432 内。 【圖式簡單說明】 第1圖與第2圖為先前技術之顯示面板的電路示意圖。 第3圖為先前技術之顯示面板的電路佈局(丨ayout)結構示意圖。 第4圖為本發明之液晶顯示面板的第一實施例之電路饰局結構示奄囷。 放大示意圖 第5圖為本發明之液晶顯示面板的第一實施例之電路佈局結構:局部 备6圖為第5圖之電路佈局結構中沿A-A’切線之結構剖視圖。 馬7圖為第5圖之電路佈局結構中沿b七’切線之結構剖視圖。The gate of the first thin film transistor 922 is connected to the first scan line 862, the source thereof is connected to the first data line 842, and the drain is connected to one end of the first liquid crystal capacitor 925 and the first storage capacitor 926, and the first liquid crystal capacitor The other end of the 925 is connected to a common electrode of a color filter (CF) end to receive a first common electrode signal, and the other end of the first storage capacitor 926 is connected to the first common electrode line 882, the first data line 842 and the first A common electrode line 882 transmits a data signal and a second common electrode signal to the first thin film transistor 922, respectively, and the first scan line 862 controls the first thin film transistor 922 to receive the data signal, thereby controlling the first liquid crystal. The charge and discharge of the capacitor 925 and the storage capacitor 926 side maintain the potential difference across the first liquid crystal capacitor 925 to prevent leakage of the first liquid crystal capacitor 925. Similarly, the gate of the second thin film transistor 924 is connected to the second scan line 864, and the source thereof is connected to the first data line 842, and the pole is connected to the end of the second liquid crystal capacitor 927 and the second storage capacitor 928. The other ___ terminal of the liquid crystal capacitor 927 is connected to the common electrode of the color faucet end to receive the first common electrode signal, and the other end of the second storage capacitor 928 is connected to the common electrode line 882 'the first data line 842 and the first The common electrode line 882 respectively receives the data signal and the second common electrode signal into the second thin film transistor 924. The line 864 controls the second thin film transistor 924 to receive the data signal, thereby controlling the charge and discharge of the second capacitor 927. The second storage capacitor 9 is used to maintain the potential difference between the two liquid crystals at both ends to prevent the second liquid crystal capacitor 927 from leaking. The liquid crystal display (4) contains a plurality of virtual lines 9Q, each of which is imaginary in the adjacent two rows of German materials (four) Μ, and 娜杂纽纽 = sigh 9 201037432 in the process of transmitting the first common electrode signal in the common electrode line 88, Because the length of the wire is too long, the signal at the center of the panel is unstable, so the common electrode wire 88 is short-circuited with the virtual wires 90 to stabilize the second common electrode signal. Figure 10 can be compared with Figure 2 of the prior art, as the result of the circuit layout comparison. 'The number of common electrode lines used in Figure 8 is less than that of Figure 2 under the same number of cells. In other words, this can increase the aperture ratio of the pixel, and the circuit design can be applied to the vertical alignment type (VA type), the twisted nematic (tn type), the plane ratchet type clear liquid crystal or the organic edge. Membrane design of the membrane. ΥΡ) Thousand-sided conversion, please continue to refer to '1G @, the operation of the liquid crystal display panel of the present invention is as follows. First, each of the common electrode lines 88 and the data line 84 respectively transmit a second common electrode signal and a data signal to the connection. The storage capacitor 98 and the thin film transistor 94, and each of the liquid crystal capacitors 96 receives the -first-common electrode signal, and at the same time, since each common electrode line 88 is short-circuited by the virtual line 90, each common electrode The second common electrode signal in the book is quite stable. Then, using the sweep line 86, the fine crystal 94 of each row is sequentially controlled from top to bottom to receive the data fiber, and the surface control liquid crystal capacitor 96 is charged and discharged. ah, the scale capacitor of the liquid crystal capacitor 96 is connected to the liquid crystal capacitor 96. The potential difference between the two ends. Finally, referring to Fig. 12, the circuit design of the liquid crystal display panel of the present invention has an advantage that, when the data line 842 is disconnected, it can be broken by a laser at the position of the dotted square box. At the position of the circle, the further laser connects the first data line 842 with the common electrode line 88, and the first virtual line 902 can be used instead of the broken data line 842 to complete the repair, and the product yield is improved. In summary, the invention not only can increase the aperture ratio of the panel of the panel, but also connects the common electrode line with the virtual positive rotation, which is a practical invention. The above-mentioned ones are only the present invention---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- It is included in the patent application scope 201037432 of the present invention. [Simplified description of the drawings] Figs. 1 and 2 are circuit diagrams of a display panel of the prior art. Fig. 3 is a circuit layout of a display panel of the prior art (丨ayout) 4 is a schematic diagram of a circuit decoration structure of a first embodiment of a liquid crystal display panel of the present invention. FIG. 5 is a circuit layout structure of a first embodiment of a liquid crystal display panel of the present invention: Figure 6 is a cross-sectional view of the structure along the line A-A' in the circuit layout structure of Figure 5. Figure 7 is a cross-sectional view of the circuit layout structure of Figure 5 along the line B7.
备8圖為本發明之液晶顯示面板的第二實施例之電路佈 P圖為本發狀液_涵_第二實關之极柄1構2部 故夬而奩β ° 第10圖為本發明之液晶顯示面板的電路示意圖。 第11圖為本發明之雙閘極畫素單元的電路示意圖。 第12圖為本發明之液晶顯示面板進行雷射侧後的電路示意圖 【主要元件符號說明】 μμ ❹ 10薄膜電晶體 14資料線 18資料線 22共通電極線 26第一薄膜電晶體 30掃瞄線 33第一畫素電極 34虛擬線 36共通電極線 38透明基板 42絕緣層 12掃瞄線 16薄膜電晶體 20虛擬線 24電極層 28第二薄膜電晶體 32資料線 35第二畫素電極 40第一金屬層 44半導體層 11 201037432 46 第二金屬層 48 50 電極層 52 54 歐姆接觸層 56 58 閘極 60 62 第二掃瞄線 64 66 源極 68 70 汲極 72 74 虛擬線 78 80 第一通孔 81 82 第三通孔 84 資料線 842第一資料線 86 掃猫線 862 第一掃瞄線 864 88 共通電極線 882 90 虛擬線 902 92 雙閘極畫素單元 922第一薄膜電晶體 924 925 第一液晶電容 926 927 第二液晶電容 928 94 薄膜電晶體 96 98 儲存電容 保護層 非晶矽層 閘極 第一掃瞒線 共通電極線 源極 汲極 資料線 第二通孔 第二掃猫線 第一共通電極線 第一虛擬線 第二薄膜電晶體 第一儲存電容 第二儲存電容 液晶電容 12BRIEF DESCRIPTION OF THE DRAWINGS FIG. 8 is a circuit diagram of a second embodiment of a liquid crystal display panel of the present invention. The figure P is a hair _ _ _ second real off pole shank 1 structure 2 夬 ° β ° Figure 10 A schematic circuit diagram of a liquid crystal display panel of the invention. Figure 11 is a circuit diagram of the dual gate pixel unit of the present invention. Figure 12 is a schematic diagram of the circuit after the laser side of the liquid crystal display panel of the present invention [main component symbol description] μμ ❹ 10 thin film transistor 14 data line 18 data line 22 common electrode line 26 first thin film transistor 30 scan line 33 first pixel electrode 34 virtual line 36 common electrode line 38 transparent substrate 42 insulating layer 12 scan line 16 thin film transistor 20 virtual line 24 electrode layer 28 second thin film transistor 32 data line 35 second pixel electrode 40 A metal layer 44 semiconductor layer 11 201037432 46 second metal layer 48 50 electrode layer 52 54 ohmic contact layer 56 58 gate 60 62 second scan line 64 66 source 68 70 drain 72 74 virtual line 78 80 first pass Hole 81 82 Third through hole 84 Data line 842 First data line 86 Sweeping cat line 862 First scanning line 864 88 Common electrode line 882 90 Virtual line 902 92 Double gate pixel unit 922 First film transistor 924 925 First Liquid Crystal Capacitor 926 927 Second Liquid Crystal Capacitor 928 94 Thin Film Transistor 96 98 Storage Capacitor Protective Layer Amorphous Layer Gate Gate First Broom Line Common Electrode Line Source Drainage Data Line Second Through Hole Second sweeping cat line first common electrode line first virtual line second thin film transistor first storage capacitor second storage capacitor liquid crystal capacitor 12