TWI709794B - Display apparatus - Google Patents

Abstract

A display apparatus includes a first substrate, first pixels disposed on the first substrate, a second substrate disposed opposite the first substrate, second pixels disposed on the second substrate and a display medium disposed between the first substrate and the second substrate. Each of the first pixels has a first signal line, a second signal line, a first thin film transistor and a first pixel electrode. Each of the second pixels has a third signal line, a fourth signal line, a second thin film transistor and a second pixel electrode. A vertical projection of the first thin film transistor of one of the first pixels on the first substrate and a vertical projection of the second thin film transistor of one of the second pixels on the first substrate are arranged in mirror symmetry.

Description

Display device

The present invention relates to an electronic device, and more particularly to a display device.

Improving the resolution of display devices has always been one of the important goals of developing display technology. Generally speaking, the resolution of the display device can be improved by increasing the pixel per inch (PPI) method. Increasing the pixel density is accompanied by an increase in the number of active elements in the active array, which will shorten the spacing between adjacent active elements and the spacing between adjacent components in the active element. As a result, for a display device in which the active array is disposed on the same substrate, increasing the pixel density will make it difficult to accurately control the spacing between adjacent active elements or between adjacent components of the active elements.

The invention provides a display device with good performance and low manufacturing cost.

The display device of the present invention includes a first substrate, a plurality of first pixels disposed on the first substrate, a second substrate disposed opposite to the first substrate, and a plurality of second pixels disposed on the second substrate And a display medium arranged between the first substrate and the second substrate. Each first pixel has a first signal line, a second signal line interleaved with the first signal line, a first thin film transistor electrically connected to the first signal line and the second signal line, and a first thin film transistor electrically connected to the first signal line The first pixel electrode of a thin film transistor. Each second pixel has a third signal line, a fourth signal line interleaved with the third signal line, a second thin film transistor electrically connected to the third signal line and the fourth signal line, and electrically connected to the first signal line. Two second pixel electrodes of thin film transistors. In particular, the vertical projection of the first thin film transistor of the first pixel on the first substrate and the vertical projection of the second thin film transistor of the second pixel on the first substrate are mirror-symmetrical.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can be based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, instead of one standard deviation for all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

1A to 1D are schematic top views of a manufacturing process of a display device according to an embodiment of the invention.

2A to 2D are schematic cross-sectional views of a manufacturing process of a display device according to an embodiment of the invention. Figures 2A to 2D respectively correspond to the section line A-A' of Figures 1A to 1D.

FIG. 3A is an enlarged schematic diagram of the region R1 in FIG. 1A. FIG. 1A omits the illustration of the plurality of first pixels PX1 and the first light shielding pattern BM1 in FIG. 3A.

FIG. 3B is an enlarged schematic diagram of the area R2 in FIG. 1B. FIG. 1B omits the illustration of the plurality of second pixels PX2 and the second light shielding pattern BM2 in FIG. 2B.

FIG. 3C is an enlarged schematic view of the area R in FIG. 1C and FIG. 1D. 1C and FIG. 1D omit the illustration of the plurality of first pixels PX1, the plurality of second pixels PX2, the first light shielding pattern BM1, and the second light shielding pattern BM2 of FIG. 3C.

FIGS. 1C and 1D omit the illustration of the display medium 300 and the sealant 400 of FIGS. 2C and 2D.

1A to 1D, 2A to 2D, and 3A to 3C illustrate the manufacturing process and structure of the display device 10 according to an embodiment of the present invention.

1A, 2A and 3A, first, a first pixel array substrate 100 is provided. The first pixel array substrate 100 includes a first substrate 110 and a plurality of first pixels PX1. The bearing surface 112 of the first substrate 110 has a first active area 112a. The plurality of first pixels PX1 are disposed on the first active area 112 a of the supporting surface 112 of the first substrate 110.

Referring to FIG. 3A, each first pixel PX1 has a first signal line SL1, a second signal line SL2 interleaved with the first signal line SL1, and a second signal line SL2 electrically connected to the first signal line SL1 and the second signal line SL2 The first thin film transistor T1 and the first pixel electrode E1 electrically connected to the first thin film transistor T1.

Specifically, in this embodiment, the first thin film transistor T1 includes a first terminal T1a, a second terminal T1b, a control terminal T1c, and a first semiconductor pattern T1d, wherein the first terminal T1a and the second terminal T1b are connected to the Two different regions of a semiconductor pattern T1d are electrically connected, and the second terminal T1b is electrically connected to the first pixel electrode E1.

In this embodiment, the first terminal T1a of the first thin film transistor T1 is electrically connected to the first signal line SL1, and the first signal line SL1 is, for example, the first data line; the control terminal T1c of the first thin film transistor T1 It is electrically connected to the second signal line SL2, and the second signal line SL2 is, for example, the first scan line, but the invention is not limited to this.

In this embodiment, the first pixel array substrate 100 may optionally have a first light shielding pattern BM1, which is disposed on the first substrate 110. The first light shielding pattern BM1 includes a plurality of first light shielding bars 121 and a plurality of second light shielding bars 122. The plurality of vertical projections of the plurality of first shading bars 121 on the first substrate 110 and the plurality of vertical projections of the first signal line SL1 on the first substrate 110 are alternately arranged. That is, the vertical projection of each first light shielding strip 121 on the first substrate 110 is located between the multiple vertical projections of two adjacent first signal lines SL1, and the first light shielding strip 121 is not connected to the first signal line SL1. SL1 overlaps. The plurality of second light-shielding bars 122 and the plurality of first light-shielding bars 121 are arranged to cross each other, and the plurality of second light-shielding bars 122 overlap with the plurality of second signal lines SL2 respectively.

In this embodiment, the first light shielding pattern BM1 may further include a plurality of third light shielding bars 123. The plurality of third light shielding bars 123 are arranged in parallel with the plurality of first light shielding bars 121. The plurality of third light-shielding bars 123 and the plurality of first light-shielding bars 121 are alternately arranged, and the plurality of third light-shielding bars 123 respectively overlap the plurality of first signal lines SL1. However, the present invention is not limited to this, and according to other embodiments, the arrangement of the third light shielding strip 123 may also be omitted.

1A, 2A, and 3A, in this embodiment, the first pixel array substrate 100 may also optionally include a first multiplexer MUX1 and a second multiplexer MUX2. In addition to the carrying surface 112 of the first substrate 110 having the first active area 112a, the carrying surface 112 of the first substrate 110 also has a first peripheral area 112b and a second peripheral area 112c located on opposite sides of the first active area 112a. . The first multiplexer MUX1 is disposed on the first peripheral region 112b, and is electrically connected to a plurality of first data lines of the plurality of first pixels PX1 (for example, but not limited to: the first signal line SL1). The second multiplexer MUX2 is disposed on the second peripheral area 112c, and is electrically connected to a plurality of first data lines of the plurality of first pixels PX1 (for example, but not limited to: the first signal line SL1).

In particular, in this embodiment, the vertical projection of the first multiplexer MUX1 on the first substrate 110 and the vertical projection of the second multiplexer MUX2 on the first substrate 110 are mirror-symmetrical. More precisely, a first reference line L1 passes through the center of the first active area 112a and is interleaved with the first data line (for example, but not limited to: the first signal line SL1), and the first multiplexer MUX1 is in the first The vertical projection on the substrate 110 and the vertical projection of the second multiplexer MUX2 on the first substrate 110 are mirror-symmetrical with respect to the first reference line L1.

In this embodiment, the first pixel array substrate 100 further includes a plurality of first fan-out traces FL1 and a plurality of second fan-out traces FL2, which are electrically connected to the first multiplexer MUX1 and the second multiplexer, respectively MUX2. In particular, in this embodiment, the vertical projections of the plurality of first fan-out traces FL1 on the first substrate 110 and the vertical projections of the plurality of second fan-out traces FL2 on the first substrate 110 are relative to the first reference line. L1 is mirror symmetry.

Please refer to FIG. 1B, FIG. 2B and FIG. 3B, and then, a second pixel array substrate 200 is provided. The first pixel array substrate 100 and the second pixel array substrate 200 are manufactured using the same set of photomasks, so the structure of the first pixel array substrate 100 is the same as the structure of the second pixel array substrate 200. A detailed description of the structure of the second pixel array substrate 200 is as follows.

The second pixel array substrate 200 includes a second substrate 210 and a plurality of second pixels PX2. The bearing surface 212 of the second substrate 210 has a second active area 212a. A plurality of second pixels PX2 are disposed on the second active area 212a of the supporting surface 212 of the second substrate 210.

Referring to FIG. 3B, each second pixel PX2 has a third signal line SL3, a fourth signal line SL4 interleaved with the third signal line SL3, and electrical connection to the third signal line SL3 and the fourth signal line SL4 The second thin film transistor T2 and the second pixel electrode E2 electrically connected to the second thin film transistor T2.

Specifically, in this embodiment, the second thin film transistor T2 includes a first terminal T2a, a second terminal T2b, a control terminal T2c, and a second semiconductor pattern T2d. The first terminal T2a and the second terminal T2b are connected to the Two different regions of the two semiconductor patterns T2d are electrically connected, and the second end T2b is electrically connected to the second pixel electrode E2.

In this embodiment, the first terminal T2a of the second thin film transistor T2 is electrically connected to the third signal line SL3, and the third signal line SL3 is, for example, the second data line; the control terminal T1c of the second thin film transistor T2 It is electrically connected to the fourth signal line SL4, and the fourth signal line SL4 is, for example, the second scan line, but the invention is not limited to this.

In this embodiment, the second pixel array substrate 200 may optionally have a second light shielding pattern BM2, which is disposed on the second substrate 210. The second light shielding pattern BM2 includes a plurality of fourth light shielding bars 221 and a plurality of fifth light shielding bars 222. The vertical projections of the fourth light shielding bars 221 on the second substrate 210 and the vertical projections of the third signal line SL3 on the second substrate 210 are alternately arranged. That is, the vertical projection of each fourth light-shielding strip 221 on the second substrate 210 is located between the multiple vertical projections of two adjacent third signal lines SL3 on the second substrate 210, and the fourth light-shielding strip 221 Does not overlap with the third signal line SL3. The plurality of fifth light shielding strips 222 and the plurality of fourth light shielding strips 221 are intersectedly arranged. The plurality of fifth light shielding strips 222 respectively overlap with the plurality of fourth signal lines SL4.

In this embodiment, the second light shielding pattern BM2 may further include a plurality of sixth light shielding bars 223. The plurality of sixth light shielding bars 223 and the plurality of fourth light shielding bars 221 are arranged in parallel. The plurality of sixth light shielding strips 223 and the plurality of fourth light shielding strips 221 are alternately arranged, and the plurality of sixth light shielding strips 223 overlap with the plurality of third signal lines SL3 respectively. However, the present invention is not limited to this. According to other embodiments, the arrangement of the sixth light shielding strip 223 may also be omitted.

In this embodiment, the first pixel array substrate 100 and the second pixel array substrate 200d may both have light shielding patterns (ie, the first light shielding pattern BM1 and the second light shielding pattern BM2). However, the present invention is not limited to this. According to other embodiments, one of the first light shielding pattern BM1 and the second light shielding pattern BM2 may also be omitted.

Referring to FIGS. 1B, 2B and 3B, in this embodiment, the second pixel array substrate 200 may also optionally include a third multiplexer MUX3 and a fourth multiplexer MUX4. In addition to the second active area 212a on the carrying surface 212 of the second substrate 210, the carrying surface 212 of the second substrate 210 also has a third peripheral area 212b and a fourth peripheral area 212c located on opposite sides of the second active area 212a. . The third multiplexer MUX3 is disposed on the third peripheral area 212b, and is electrically connected to a plurality of second data lines of the plurality of second pixels PX2 (for example, but not limited to: the third signal line SL3). The fourth multiplexer MUX4 is disposed on the fourth peripheral area 212c of the supporting surface 212 of the second substrate 210, and is electrically connected to the plurality of second data lines of the plurality of second pixels PX2 (for example, but not limited to: the third Signal line SL3).

In particular, in this embodiment, the vertical projection of the third multiplexer MUX3 on the second substrate 210 and the vertical projection of the fourth multiplexer MUX4 on the second substrate 210 are mirror-symmetrical. More precisely, a second reference line L2 passes through the center of the second active area 212a and is interleaved with the second data line (for example, but not limited to: the third signal line SL3), and the third multiplexer MUX3 is in the second The vertical projection on the substrate 210 and the vertical projection of the fourth multiplexer MUX4 on the second substrate 210 are mirror-symmetrical with respect to the second reference line L2.

In this embodiment, the second pixel array substrate 200 further includes a plurality of third fan-out traces FL3 and a plurality of fourth fan-out traces FL4, which are respectively electrically connected to the third multiplexer MUX3 and the fourth multiplexer MUX4. In particular, in this embodiment, the vertical projection of the plurality of third fan-out traces FL3 on the second substrate 210 and the vertical projection of the plurality of fourth fan-out traces FL4 on the second substrate 210 are relative to the second reference line. L2 can be mirror symmetry.

1C, 2C and 3C, then, assembling the first pixel array substrate 100 and the second pixel array substrate 200, and form a display medium 300 on the first pixel array substrate 100 and the second pixel array substrate Between 200.

For example, in this embodiment, the carrying surface 112 of the first substrate 110 of the first pixel array substrate 100 may be facing upward, and the sealant 400 may be coated on the carrying surface 112 of the first substrate 110; then, Fill the display medium 300 (for example: liquid crystal) into the space enclosed by the first pixel array substrate 100 and the sealant 400; then, make the bearing surface 212 of the second substrate 210 of the second pixel array substrate 200 face down, and The second pixel array substrate 200 is brought into contact with the sealant 400 on the first pixel array substrate 100 under conditions close to vacuum, thereby connecting the second pixel array substrate 200 to the first pixel array substrate 100 and connecting the display medium 300 is enclosed in the space enclosed by the first pixel array substrate 100, the second pixel array substrate 200 and the sealant 400.

Please refer to Figure 1C, Figure 2C, Figure 3C, Figure 1D and Figure 2D, then, cut the first pixel array substrate 100 along the first dicing lane C1, and cut the second pixel array substrate along the second dicing lane C2 200. In this embodiment, a part of each second fan-out wiring FL2 is located between the first cutting track C1 and the sealant 400, and a part of each third fan-out wiring FL3 is located between the second cutting track C2 and the sealant 400 between. After cutting the first pixel array substrate 100 and the second pixel array substrate 200 along the first scribe lane C1 and the second scribe lane C2, the multiple end points FL2a of the multiple second fan-out traces FL2 and the first substrate 110 The edges 110d of the second substrate 210 are substantially aligned with each other, and the multiple end points FL3a of the plurality of third fan-out traces FL3 are substantially aligned with an edge 210d of the second substrate 210.

1D, 2D and 3C, then, the first driving circuit IC1 is electrically connected to the plurality of first fan-out wiring FL1 on the first substrate 110, and the second driving circuit IC2 is electrically connected to the first A plurality of fourth fan-out traces FL4 on the second substrate 210. At this point, the display device 10 of this embodiment is completed. The first driving circuit IC1 is electrically connected to the first multiplexer MUX1 through a plurality of first fan-out wires FL1. The first multiplexer MUX1 is electrically connected between the first driving circuit IC1 and the plurality of first pixels PX1, and the plurality of first pixels PX1 are electrically connected to the first multiplexer MUX1 and the second multiplexer Between MUX2. The second driving circuit IC2 is electrically connected to the fourth multiplexer MUX4 through a plurality of fourth fan-out wires FL4. The fourth multiplexer MUX4 is electrically connected between the second driving circuit IC2 and the plurality of second pixels PX2, and the plurality of second pixels PX2 are electrically connected to the third multiplexer MUX3 and the fourth multiplexer Between MUX4.

1D, 2D, and 3C, the display device 10 includes a first substrate 110, a plurality of first pixels PX1 disposed on the first substrate 110, and a second substrate 210 disposed opposite to the first substrate 110 , A plurality of second pixels PX2 disposed on the second substrate 210, and a display medium 300 disposed between the first substrate 110 and the second substrate 210. In particular, as shown in FIG. 3C, the vertical projection of a first pixel PX1 on the first substrate 110 and the vertical projection of a corresponding second pixel PX2 on the first substrate 110 are mirror-symmetrical.

Specifically, the vertical projection of the first thin film transistor T1 of a first pixel PX1 on the first substrate 110 is perpendicular to the vertical projection of the second thin film transistor T2 of a second pixel PX2 on the first substrate 110 The projection is mirror symmetry.

In this embodiment, the first pixel array substrate 100 and the second pixel array substrate 200 have substantially no assembly offset (that is, the vertical projection of the first signal line SL1 of the first pixel PX1 on the first substrate 110 and The vertical projection of the third signal line SL3 corresponding to the second pixel PX2 on the first substrate 110 substantially overlaps), and the vertical projection of the first thin film transistor T1 on the first substrate 110 is the same as that of the second thin film transistor T2 The vertical projection on the first substrate 110 may be mirror-symmetrical with respect to the vertical projection of the first signal line SL1 on the first substrate 110, but the invention is not limited thereto.

For example, in this embodiment, the vertical projection of the first semiconductor pattern T1d of the first thin film transistor T1 on the first substrate 110 and the second semiconductor pattern T2d of the second thin film transistor T2 on the first substrate 110 The vertical projection of the first signal line SL1 is mirror-symmetrical to the vertical projection of the first signal line SL1 on the first substrate 110; the vertical projection of the second end T1b of the first thin film transistor T1 on the first substrate 110 is the same as that of the second thin film transistor T2 The vertical projection of the second end T2b on the first substrate 110 is mirror-symmetrical to the vertical projection of the first signal line SL1 on the first substrate 110.

The vertical projection of the first pixel electrode E1 of the first pixel PX1 on the first substrate 110 and the vertical projection of the second pixel electrode E2 of the second pixel PX2 on the first substrate 110 are mirror-symmetrical.

In this embodiment, the first pixel array substrate 100 and the second pixel array substrate 200 have substantially no assembly offset (that is, the vertical projection of the first signal line SL1 of the first pixel PX1 on the first substrate 110 and The vertical projection of the third signal line SL3 corresponding to the second pixel PX2 on the first substrate 110 substantially overlaps), and the vertical projection of the first pixel electrode E1 of the first pixel PX1 on the first substrate 110 is the same as The vertical projection of the second pixel electrode E2 of the second pixel PX2 on the first substrate 110 may be mirror-symmetrical with respect to the vertical projection of the first signal line SL1 on the first substrate 110, but the invention is not limited to this .

In this embodiment, the display device 10 includes a plurality of pixel groups GP, and each pixel group GP includes a first pixel PX1 and a second pixel PX2 whose vertical projections are mirror-symmetric to each other. The plurality of pixel groups GP includes a first pixel group GP1 and a second pixel group GP2 adjacent to each other. The first light-shielding strip 121 of the first light-shielding pattern BM1 shields the second pixel electrode E2 of the second pixel PX2 of the first pixel group GP1 and the first pixel electrode of the first pixel PX1 of the second pixel group GP2 The gap g between E1 is to prevent the display panel 10 from leaking light. Similarly, in this embodiment, the fourth light-shielding strip 221 of the second light-shielding pattern BM2 will also shield the second pixel electrode E2 of the first pixel group GP1 and the first pixel electrode E1 of the second pixel group GP2. There is a gap g between them to prevent the display panel 10 from leaking light.

In this embodiment, the first pixel PX1 and the second pixel PX2 are respectively fabricated on the first substrate 110 and the second substrate 210 to form the first pixel array substrate 100 and the second pixel array substrate 200; then Then, the first pixel array substrate 100 and the second pixel array substrate 200 are assembled to form the display device 10. Therefore, the distance between the first signal line SL1 of the first pixel PX1 and the third signal line SL3 of the second pixel PX2 and the first semiconductor pattern T1d of the first pixel PX1 and the second semiconductor pattern of the second pixel PX2 The distance of T2d is not limited by the capability of the patterning process. The first signal line SL1 of the first pixel PX1 and the third signal line SL3 of the second pixel PX2 can be very close or even overlapped. The first semiconductor of the first pixel PX1 The pattern T1d and the second semiconductor pattern T2d of the second pixel PX2 may be very close or even overlapped. In this way, the first pixel PX1 and the second pixel PX2 can be very close or even partially overlapped, so that a high-resolution display device 10 can be realized.

More importantly, the vertical projection of a first pixel PX1 on the first substrate 110 and the vertical projection of a corresponding second pixel PX2 on the first substrate 110 are mirror-symmetrical; that is, the first pixel The PX1 and the second pixel PX2 are manufactured using the same set of photomasks. Therefore, the display device 10 not only has a high resolution, but also has the advantage of low manufacturing cost.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

4A to 4D are schematic top views of a manufacturing process of a display device according to another embodiment of the invention.

5A to 5D are schematic cross-sectional views of a manufacturing process of a display device according to another embodiment of the invention. Figures 5A to 5D correspond to the section line A-A' of Figures 4A to 4D, respectively.

FIG. 6A is an enlarged schematic diagram of the area R1 in FIG. 4A. FIG. 4A omits the illustration of the plurality of first pixels PX1 and the first light shielding pattern BM1 in FIG. 6A.

FIG. 6B is an enlarged schematic diagram of the area R2 in FIG. 4B. FIG. 4B omits the illustration of the plurality of second pixels PX2 and the second light shielding pattern BM2 in FIG. 6B.

Fig. 6C is an enlarged schematic view of the area R in Fig. 4C and Fig. 4D. FIG. 6C omits the illustration of the plurality of first pixels PX1, the plurality of second pixels PX2, the first light-shielding pattern BM1, and the second light-shielding pattern BM2 of FIGS. 4C and 4D.

4C and 4D omit the illustration of the display medium 300 and the sealant 400 of FIGS. 5C and 5D.

Referring to FIGS. 4A, 5A and 6A, first, a first pixel array substrate 100 is provided. The first pixel array substrate 100 includes a first substrate 110 and a plurality of first pixels PX1. The bearing surface 112 of the first substrate 110 has a first active area 112a. The plurality of first pixels PX1 are disposed on the first active area 112 a of the supporting surface 112 of the first substrate 110. Each first pixel PX1 has a first signal line SL1, a second signal line SL2 interleaved with the first signal line SL1, and a first thin film transistor electrically connected to the first signal line SL1 and the second signal line SL2 T1 is electrically connected to the first pixel electrode E1 of the first thin film transistor T1.

Different from the previous embodiment, in this embodiment, the control terminal T1c of the first thin film transistor T1 is electrically connected to the first signal line SL1, and the first signal line SL1 is, for example, a first scan line; The first terminal T1a of the transistor T1 is electrically connected to the second signal line SL2, and the second signal line SL2 is, for example, the first data line.

Referring to FIG. 4A, FIG. 5A and FIG. 6A, in this embodiment, the first pixel array substrate 100 may also optionally include a first multiplexer MUX1. In addition to the carrying surface 112 of the first substrate 110 having the first active area 112a, the carrying surface 112 of the first substrate 110 also has first peripheral areas 112b respectively located on one side of the first active area 112a. The first multiplexer MUX1 is disposed on the first peripheral area 112b of the carrying surface 112 of the first substrate 110, and is electrically connected to the first data lines of the first pixels PX1 (for example, but not limited to: the second Signal line SL2). The difference from the foregoing embodiment is that in this embodiment, the first pixel array substrate 100 may not include the foregoing second multiplexer MUX2.

In this embodiment, the first pixel array substrate 100 further includes a plurality of first fan-out traces FL1, which are electrically connected to the first multiplexer MUX1. The difference from the foregoing embodiment is that in this embodiment, the first pixel array substrate 100 may not include the foregoing multiple second fan-out wirings FL2.

Please refer to FIG. 4B, FIG. 5B and FIG. 6B, and then, a second pixel array substrate 200 is provided. The first pixel array substrate 100 and the second pixel array substrate 200 are manufactured using the same set of photomasks, so the structure of the first pixel array substrate 100 is the same as the structure of the second pixel array substrate 200. A detailed description of the structure of the second pixel array substrate 200 is as follows.

The second pixel array substrate 200 includes a second substrate 210 and a plurality of second pixels PX2. The bearing surface 212 of the second substrate 210 has a second active area 212a. A plurality of second pixels PX2 are disposed on the second active area 212a of the supporting surface 212 of the second substrate 210. Each second pixel PX2 has a third signal line SL3, a fourth signal line SL4 interleaved with the third signal line SL3, and a second thin film transistor electrically connected to the third signal line SL3 and the fourth signal line SL4 T2 is electrically connected to the second pixel electrode E2 of the second thin film transistor T21.

The difference from the previous embodiment is that in this embodiment, the control terminal T2c of the second thin film transistor T2 is electrically connected to the third signal line SL3, and the third signal line SL3 is, for example, the second scan line; The first terminal T1a of the transistor T2 is electrically connected to the fourth signal line SL4, and the fourth signal line SL4 is, for example, the second data line.

Referring to FIG. 4B, FIG. 5B and FIG. 6B, in this embodiment, the second pixel array substrate 200 may also optionally include a third multiplexer MUX3. In addition to the second active area 212a on the supporting surface 212 of the second substrate 210, the supporting surface 212 of the second substrate 210 also has third peripheral areas 212b located on one side of the second active area 212a. The third multiplexer MUX3 is disposed on the third peripheral area 212b of the carrying surface 212 of the second substrate 210, and is electrically connected to the plurality of second data lines of the plurality of second pixels PX2 (for example, but not limited to: the fourth Signal line SL4). Different from the foregoing embodiment, in this embodiment, the second pixel array substrate 200 may not include the foregoing fourth multiplexer MUX4.

In this embodiment, the second pixel array substrate 200 further includes a plurality of third fan-out wiring FL3, which are electrically connected to the third multiplexer MUX3. The difference from the foregoing embodiment is that, in this embodiment, the second pixel array substrate 200 may not include the foregoing multiple fourth fan-out wirings FL4.

4C, 5C and 6C, then, the first pixel array substrate 100 and the second pixel array substrate 200 are assembled, and a display medium 300 is formed on the first pixel array substrate 100 and the second pixel array substrate Between 200.

4C, FIG. 5C, FIG. 6C, FIG. 4D and FIG. 5D, then, cut the first pixel array substrate 100 along the first dicing path C1, and cut the second pixel array substrate along the second dicing path C2 200.

Please refer to FIGS. 4D, 5D, and 6C. Then, the first driving circuit IC1 is electrically connected to the plurality of first fan-out traces FL1 on the first substrate 110, and the second driving circuit IC2 is electrically connected to the first A plurality of third fan-out traces FL3 on the second substrate 210. The first driving circuit IC1 is electrically connected to the first multiplexer MUX1 through a plurality of first fan-out wires FL1. The second driving circuit IC2 is electrically connected to the third multiplexer MUX3 through a plurality of third fan-out wires FL3. Hereby, the display device 10A of this embodiment is completed.

Referring to FIGS. 4D, 5D and 6C, the display device 10A includes a first substrate 110, a plurality of first pixels PX1 disposed on the first substrate 110, and a second substrate 210 disposed on the opposite side of the first substrate 110 , A plurality of second pixels PX2 disposed on the second substrate 210, and a display medium 300 disposed between the first substrate 110 and the second substrate 210. In particular, as shown in FIG. 6C, the vertical projection of a first pixel PX1 on the first substrate 110 and the vertical projection of a corresponding second pixel PX2 on the first substrate 110 are mirror-symmetrical.

The difference from the previous embodiment is that in this embodiment, the vertical projection of a first pixel PX1 on the first substrate 110 and the vertical projection of a corresponding second pixel PX2 on the first substrate 110 are relative to The second scan line (ie, the first signal line SL1 in this embodiment) is mirror-symmetrical.

Specifically, in this embodiment, in this embodiment, the vertical projection of the first semiconductor pattern T1d of the first thin film transistor T1 on the first substrate 110 and the second semiconductor pattern T2d of the second thin film transistor T2 The vertical projection on the first substrate 110 is mirror-symmetrical with respect to the vertical projection of the second scan line (that is, the first signal line SL1 in this embodiment) on the first substrate 110; the second end of the first thin film transistor T1 The vertical projection of T1b on the first substrate 110 and the vertical projection of the second end T2b of the second thin film transistor T2 on the first substrate 110 are relative to the second scan line (ie, the first signal line SL1 of this embodiment) The vertical projection on the first substrate 110 is mirror-symmetrical. The vertical projection of the first pixel electrode E1 of the first pixel PX1 on the first substrate 110 and the vertical projection of the second pixel electrode E2 of the second pixel PX2 on the first substrate 110 are relative to the second scan line ( That is, the vertical projection of the first signal line SL1) on the first substrate 110 in this embodiment is mirror-symmetrical.

In this embodiment, the first pixel PX1 and the second pixel PX2 are respectively fabricated on the first substrate 110 and the second substrate 210 to form the first pixel array substrate 100 and the second pixel array substrate 200; After that, the first pixel array substrate 100 and the second pixel array substrate 200 are assembled to form the display device 10A. The first data signal and the first scan signal are used for input to a plurality of first pixels PX1, the second data signal and the second scan signal are used for input to a plurality of second pixels PX2, among which the first data signal and the first scan signal , The first data signal and the second scan signal can be simultaneously input to a plurality of first pixels PX1 on the first substrate 110 and a plurality of second pixels PX2 on the second substrate 210. Thereby, the display device 10A can increase the frame rate while maintaining sufficient charging time.

More importantly, the vertical projection of a first pixel PX1 on the first substrate 110 and the vertical projection of a corresponding second pixel PX2 on the first substrate 110 are mirror-symmetrical; that is, the first pixel The PX1 and the second pixel PX2 are manufactured using the same set of photomasks. Therefore, the display device 10A not only has a high frame rate, but also has the advantage of low manufacturing cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10.10A: Display device

100: The first pixel array substrate

110: first substrate

112: bearing surface

112a: first active zone

112b: The first peripheral area

112c: second peripheral zone

121: The first shading strip

122: second shading strip

123: The third shading strip

200: The second pixel array substrate

210: second substrate

212: bearing surface

212a: second active zone

212b: The third peripheral zone

212c: the fourth peripheral area

221: The fourth shading strip

222: Fifth shading strip

223: The sixth shading strip

300: display medium

400: frame glue

A-A’: Cut line

BM1: The first shading pattern

BM2: second shading pattern

C1: The first cutting pass

C2: Second cutting pass

E1: The first pixel electrode

E2: second pixel electrode

FL1: The first fan-out wiring

FL2: The second fan-out wiring

FL2a, FL3a: Endpoint

FL3: The third fan-out wiring

FL4: The fourth fan-out wiring

GP: Pixel Group

GP1: The first pixel group

GP2: The second pixel group

g: gap

L1: The first reference line

L2: Second reference line

MUX1: the first multiplexer

MUX2: second multiplexer

MUX3: third multiplexer

MUX4: the fourth multiplexer

SL1: The first signal line

SL2: second signal line

SL3: The third signal line

SL4: The fourth signal line

T1: The first thin film transistor

T1a, T2a: first end

T1b, T2b: second end

T1c, T2c: control terminal

T1d: The first semiconductor pattern

T2: The second thin film transistor

T2d: second semiconductor pattern

PX1: the first pixel

PX2: second pixel

IC1: the first drive circuit

IC2: second drive circuit

R, R1, R2: area

1A to 1D are schematic top views of a manufacturing process of a display device according to an embodiment of the invention. 2A to 2D are schematic cross-sectional views of a manufacturing process of a display device according to an embodiment of the invention. FIG. 3A is an enlarged schematic diagram of the region R1 in FIG. 1A. FIG. 3B is an enlarged schematic diagram of the area R2 in FIG. 1B. FIG. 3C is an enlarged schematic view of the area R in FIG. 1C and FIG. 1D. 4A to 4D are schematic top views of a manufacturing process of a display device according to another embodiment of the invention. 5A to 5D are schematic cross-sectional views of a manufacturing process of a display device according to another embodiment of the invention. FIG. 6A is an enlarged schematic diagram of the area R1 in FIG. 4A. FIG. 6B is an enlarged schematic diagram of the area R2 in FIG. 4B. Fig. 6C is an enlarged schematic view of the area R in Fig. 4C and Fig. 4D.

10: Display device

100: The first pixel array substrate

110: first substrate

121: The first shading strip

122: second shading strip

123: The third shading strip

200: The second pixel array substrate

210: second substrate

221: The fourth shading strip

222: Fifth shading strip

223: The sixth shading strip

BM1: The first shading pattern

BM2: second shading pattern

E1: The first pixel electrode

E2: second pixel electrode

GP: Pixel Group

GP1: The first pixel group

GP2: The second pixel group

g: gap

SL1: The first signal line

SL2: second signal line

SL3: The third signal line

SL4: The fourth signal line

T1: The first thin film transistor

T1a, T2a: first end

T1b, T2b: second end

T1c, T2c: control terminal

T1d: The first semiconductor pattern

T2: The second thin film transistor

T2d: second semiconductor pattern

PX1: the first pixel

PX2: second pixel

R: area

Claims (11)

A display device, comprising: a first substrate; a plurality of first pixels arranged on the first substrate, wherein each of the first pixels has a first signal line interleaved with the first signal line A second signal line, a first thin film transistor electrically connected to the first signal line and the second signal line, and a first pixel electrode electrically connected to the first thin film transistor; a second The substrate is arranged opposite to the first substrate; a plurality of second pixels are arranged on the second substrate, wherein each of the second pixels has a third signal line, which is arranged alternately with the third signal line A fourth signal line, a second thin film transistor electrically connected to the third signal line and the fourth signal line, and a second pixel electrode electrically connected to the second thin film transistor; and The display medium is arranged between the first substrate and the second substrate, wherein the vertical projection of the first thin film transistor of a first pixel on the first substrate and the second pixel of the second pixel The vertical projection of the two thin film transistors on the first substrate is mirror-symmetrical, and the vertical projection of the first signal line of the first pixel on the first substrate and the third signal line of the second pixel are in The vertical projection on the first substrate substantially overlaps, and the vertical projection of the first thin film transistor on the first substrate and the vertical projection of the second thin film transistor on the first substrate are relative to the first signal The vertical projection of the line on the first substrate is mirror-symmetrical. The display device according to claim 1, wherein the vertical projection of the first pixel electrode of the first pixel on the first substrate and the second pixel electrode of the second pixel are on the The vertical projection on the first substrate is mirror-symmetrical to the vertical projection of the first signal line on the first substrate. For the display device described in the first item of the scope of patent application, the first signal line is a first data line, and the third signal line is a second data line. As for the display device described in claim 1, wherein the first signal line is a first scan line, and the third signal line is a second scan line. A display device, comprising: a first substrate; a plurality of first pixels arranged on the first substrate, wherein each of the first pixels has a first signal line interleaved with the first signal line A second signal line, a first thin film transistor electrically connected to the first signal line and the second signal line, and a first pixel electrode electrically connected to the first thin film transistor; a second The substrate is arranged opposite to the first substrate; a plurality of second pixels are arranged on the second substrate, wherein each of the second pixels has a third signal line, which is arranged alternately with the third signal line A fourth signal line, a second thin film transistor electrically connected to the third signal line and the fourth signal line, and a second pixel electrode electrically connected to the second thin film transistor; and The display medium is arranged between the first substrate and the second substrate, and a vertical projection of the first thin-film transistor of the first pixel on the first substrate and a The vertical projection of the second thin film transistor of the second pixel on the first substrate is mirror-symmetrical; wherein the first substrate has a first active area, a first peripheral area, and a second peripheral area, the The first pixels are arranged in the first active area, the first peripheral area and the second peripheral area are respectively located on opposite sides of the first active area, and the display device further includes: a first multiplexer, Is disposed on the first peripheral area of the first substrate and is electrically connected to the first pixels; a second multiplexer is disposed on the second peripheral area of the first substrate and is electrically connected Connected to the first pixels; and a first driving circuit electrically connected to the first multiplexer, wherein the first multiplexer is electrically connected to the first driving circuit and the first pixels And the first pixels are electrically connected between the first multiplexer and the second multiplexer. According to the display device described in claim 5, the vertical projection of the first multiplexer on the first substrate and the vertical projection of the second multiplexer on the first substrate are mirror-symmetrical. The display device described in item 5 of the scope of patent application further includes: a plurality of first fan-out wires electrically connected to the first multiplexer, wherein the first driving circuit is electrically connected to the first fans Outgoing traces; and a plurality of second fan-out traces are electrically connected to the second multiplexer, and a plurality of end points of the second fan-out traces are substantially aligned with an edge of the first substrate. The display device according to claim 5, wherein the second substrate has a second active area, a third peripheral area, and a fourth peripheral area, and the second pixels are disposed in the second active area , The third peripheral area and the fourth peripheral area are respectively located on opposite sides of the second active area, and the display device further includes: a third multiplexer disposed on the third peripheral area of the second substrate And electrically connected to the second pixels; a fourth multiplexer disposed on the fourth peripheral area of the second substrate and electrically connected to the second pixels; and a first Two driving circuits, electrically connected to the third multiplexer, wherein the fourth multiplexer is electrically connected between the second driving circuit and the second pixels, and the second pixels are electrically connected Connected between the third multiplexer and the fourth multiplexer. According to the display device described in claim 8, wherein the vertical projection of the third multiplexer on the second substrate and the vertical projection of the fourth multiplexer on the second substrate are mirror-symmetrical. For example, the display device described in item 8 of the scope of patent application further includes: a plurality of third fan-out wires electrically connected to the third multiplexer; and a plurality of fourth fan-out wires electrically connected to the first A quad multiplexer, wherein the second driving circuit is electrically connected to the fourth fan-out traces, and the ends of the third fan-out traces are substantially aligned with an edge of the second substrate. For example, the display device described in item 1 or item 5 of the scope of patent application includes: A plurality of first shading bars are arranged on the first substrate, wherein the vertical projections of the first shading bars on the first substrate and the first signal lines of the first pixels are on the first substrate A plurality of vertical projections on a substrate are arranged alternately, and the vertical projection of each of the first shading strips on the first substrate is located on the first signal lines. Two adjacent first signal lines are on the first substrate Between multiple vertical projections.

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