201036172 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種接面電晶體(JFET，Junction Field Effect Transistor)與蕭特基二極體(Schottky Diode)之整合元件。 【先前技術】 電源控制電路中經常需要使用到由獨立的NM〇s電晶 體與獨立的蕭特基二極體構成之功率開關元件。請參閱第j 0 圖，NMOS電晶體14與蕭特基二極體12串連作為功率開關 元件，NMOS電晶體14中包含寄生二極體14D。控制電路 10控制NMOS電晶體14的閘極，以將輸入電壓Vin轉換成 輸出電壓Vo。蕭特基二極體12的作用是在輸出電壓v〇高於 輸入電壓Vin的情況下，防止電流經寄生二極體14D逆流， 損及輸入電壓Vin。第2圖示出另一種先前技術，其係以耗 乏型NMOS電晶體16與蕭特基二極體12串連作為功率開關 元件，其中蕭特基二極體12的作用仍是防止電流經寄生二極 體16D逆流。 0 請參閱第3A與3B圖，以第i圖之先前技術為例，其控 • 制電路10中包括電流源18與曾納二極體19,此種功率開關 元件所欲達成的輸入一輸出電壓轉換曲線舉例而言如第3B圖 所示，當輸入電壓Vin大於NMOS電晶體14的臨界電壓vth 和蕭特基二極體12的前向偏壓Vf時，電能即可由輸入端vin 傳遞至輸出端Vo，但NMOS電晶體14的閘極受控於曾納二 極體19，當輸入電壓vin高於曾納二極體19的崩潰電壓5V 時，因曾納二極體19逆向導通，因此NM〇s電晶體14的閘 極電壓將維持為5V，而輸出電壓v〇也將維持為約5V。 3 201036172 *上述先前技術的缺點;％，獨立的丽〇8電晶體與獨立的 蕭特基二極體相當佔據面積，且控制電路1〇中必須使用曾納 二極體19，增加整體電路的成本。 有鑑於此，本發明即針對上述先前技術之*足，提出一種 接面電晶體與蕭特基二極體之整合元件，以減少功率開關元件 的面積並簡化控制電路1〇的電路結構。 【發明内容】 本發明目的之一在提供一種接面電晶體與蕭特基二極體 〇 之整合元件。 為達上述之目的，就其中一個觀點言，本發明提供了一 種接面電晶體與蕭特基二極體之整合S件’包含—個耗乏型 接面電晶體’其包括源極、沒極與閘極，該祕未設置歐姆接 觸而構成蕭特基二極體。 上述接面電晶體與蕭特基二極體之整合元件可為平面式 或垂直式。 就其中一個半導體結構觀點言，本發明所提出之一種接 〇 面電晶體與蕭特基二極體之整合元件包含：-個第一傳導型 態的基體；位於該基咖之具有第二傳導鶴的第一井區； 位於該第-井區内之具有第—傳導型態的第二井區；位於該 第一井區内之具有第二傳導型態的第一高濃度摻雜區；以及 ⑽該第二井區内之具有第—傳導型態的第二高濃度推雜 區’其中該基體、第—井區、第二井區構絲乏型接面電晶 體’該第-高濃度摻籠作為絲乏型接面電晶體源極之歐 姆接觸’該第二高濃度摻雜區作為該耗乏型接面電晶體閘極 之歐姆接觸，且該耗乏型接面電晶體之沒極不具有第一傳導 4 201036172 型態之歐姆接觸，以構成蕭特基二極體。 以上所述整合元件’在蕭特基二極體位置處，可 2個第-傳導型態的第三摻雜區，以控制蕭 反向漏電流。 胃扪 就另-辨導體結構觀點言，本發明所提出之—種接面 電晶體與蕭特基二極體之整合元件包含：—個第—傳導型態 =體；以及位於該基體内之具有第二傳導型態的兩個第二 品’其中該基體與該兩個第—井區構成垂直型耗乏型接面 Ο 〇 縣:體’絲體正面作為該耗乏型接面電日日日體之汲極，該基 f方面作為該耗乏型接面電晶體之源極，該兩個第-井區作 二該耗乏型接面電晶體之閉極，且該耗乏型接面電晶體之汲 不?有帛傳導型態之歐姆接觸，以構成蕭特基二極體。 以上所述整合元件’在蕭特基二極體位置處，可更包含至 =個第二傳導型態的摻雜區，以控制蕭特基二極體的反向 漏電流。 底下藉由具體實施例詳加說明，當更容g瞭解本發明之 目的、技抽容、特點及其所達成之功效。 【實施方式】 _本說明書之ΙΙτ均屬示意，其維度並未完全按照比例繪 不0 明參考第4Α與4Β圖’其中以電路圖形式顯示本發明的 ，實關。如騎不，本實酬中，係由齡基二極體22 面NMOS電晶體24整合構成功率開關元件2〇。此接面 〇S電晶體24為乾乏型，其閘極接地，因此並不需要複雜 控制電路10。輸人電壓與輸出電壓％的_如第4Β 5 201036172 圖所示’當輸入電壓Vin大於蕭特基二極體22的前向偏壓vf 時，電能即可由輸入端Vin傳遞至輸出端v〇 ,但由於耗乏型 接面電晶體24本身的限流特性，輸出電壓v〇將維持為約 4〜6vut錄僅是糊，可·級電路的需求來設計改變）。 以上電路以半導體製作時，其實施型態之一例請參閱第 5圖。如圖所示，在P型基體2〇1上製作N型井區2〇2，並 在N型井區202内設置p型摻雜區2〇3，如此即構成了第4a 目中的耗乏型接面電晶體24。P型摻雜區2〇3中宜設置高濃 ❹ 度P+摻雜區204 ’且N型井區202内宜設置高濃度N+掺雜 區205，以提供歐姆接觸(ohmic contact)，分別作為耗彡刑接 面電晶體的閘極和源極。但N型井區2〇2右方作為汲極的區 域’則不設置高濃度N+摻雜區。由於不提供歐姆接觸之故， 此處之導通障礙較高設置了-個蕭特基二極體，與接 ^電晶體24的汲極串連。在較佳實施方式中，更可在N型井 區2〇2内蕭特基二極體的位置設置高濃度p+摻雜區2〇6，以 控制蕭特基二極體的反向漏電流。 ❹ 由第5圖可知，本發明所佔面積僅相當於單一耗乏型接 面電晶體24的面積而已’且對照第3B和第4B圖可知，本 發明可直接剌於先前技術的應㈣合中需要複雜的控 制電路，故遠較先前技術為優。 第6圖顯示本發明的另一個實施例，本實施例中之耗乏 型接面電晶體係為垂直型。如圖所示，在N型基 作兩p型井區213，如此即構成了垂直型的耗乏:接面= 體’以兩P型井區213為閘極，而以基體的正面與背面分別 為没極與源極。在較佳實施方式中，為提供較佳之源極接觸 阻值’ N型基體210宜包含較高濃度的N+型本體211和n 6 201036172 型磊晶生長區212。與前一實施例相似地，作為汲極的區域 不双置尚》農度N+摻雜區，造成較高之導通障礙，以構成蕭特 基一極體’與垂直型接面電晶體的沒極串連。.相似地，為押 制蕭特基二極體的反向漏電流，可進一步在]Si型基體210表 面蕭特基二極體的位置設置高濃度的P+摻雜區214;此P+摻 雜區214同時也作為閘極的歐姆接觸。若未設置p+捧雜區 214，則圖示閘極端應與p型井區213連接。 以上已針對較佳實施例來說明本發明，唯以上所述者， ❹ 僅係為使熟悉本技術者易於了解本發明的内容而已，並非用 來限定本發明之權利範圍。在本發明之相同精神下，熟悉本 技術者可以思及各種等效變化，均應包含在本發明的之 内。 【圖式簡單說明】 第1圖與第2圖示出先前技術之功率開關元件，其中包含 獨立的NMOS電晶體與獨立的蕭特基二極體。 第3A與3B圖說明先前技術的一種應用實例。 〇 第4A與4B圖示出本發明的一個實施例及其應用。 帛5®示出本發明以半導體來實現時之其中_個實施例。 第6圖示出本發明以半導體來實現時之另一個實施例。 【主要元件符號說明】 10控制電路 12蕭特基二極體 14 NMOS電晶體 14D寄生二極體 16耗乏型NMOS電晶體 16D寄生二極體 20整合功率開關元件 22蕭特基二極體 7 201036172 24耗乏型接面電晶體 201 P型基體 202 N型井區 203 P型摻雜區 204 P+摻雜區 205 N+摻雜區 206 P+摻雜區 210 N型基體 211 N+型本體 212 N型磊晶生長區 213 P型井區 214 P+摻雜區201036172 VI. Description of the Invention: [Technical Field] The present invention relates to an integrated component of a JFET (Junction Field Effect Transistor) and a Schottky Diode. [Prior Art] It is often necessary to use a power switching element composed of an independent NM 〇s electromorph and a separate Schottky diode in a power supply control circuit. Referring to Fig. 0, the NMOS transistor 14 is connected in series with the Schottky diode 12 as a power switching element, and the NMOS transistor 14 includes a parasitic diode 14D. The control circuit 10 controls the gate of the NMOS transistor 14 to convert the input voltage Vin into an output voltage Vo. The function of the Schottky diode 12 is to prevent current from flowing back through the parasitic diode 14D and to the input voltage Vin, in the case where the output voltage v 〇 is higher than the input voltage Vin. Fig. 2 shows another prior art in which a NMOS transistor 16 and a Schottky diode 12 are connected in series as a power switching element, wherein the function of the Schottky diode 12 is to prevent current flow. Parasitic diode 16D countercurrent. 0 Refer to Figures 3A and 3B. Taking the prior art of Figure i as an example, the control circuit 10 includes a current source 18 and a Zener diode 19, and the input-output of the power switching element is desired. The voltage conversion curve is, for example, as shown in FIG. 3B. When the input voltage Vin is greater than the threshold voltage vth of the NMOS transistor 14 and the forward bias voltage Vf of the Schottky diode 12, the electric energy can be transmitted from the input terminal vin to The output terminal Vo, but the gate of the NMOS transistor 14 is controlled by the Zener diode 19, and when the input voltage vin is higher than the breakdown voltage of the Zener diode 19 by 5V, the Zener diode 19 is reverse-conducted. Therefore, the gate voltage of the NM〇s transistor 14 will remain at 5V, and the output voltage v〇 will also remain at approximately 5V. 3 201036172 *The shortcomings of the above prior art; %, the independent Radisson 8 transistor and the independent Schottky diode occupy a considerable area, and the control circuit 1 must use the Zener diode 19 to increase the overall circuit cost. In view of the above, the present invention is directed to the above-described prior art, and proposes an integrated component of a junction transistor and a Schottky diode to reduce the area of the power switching element and simplify the circuit structure of the control circuit. SUMMARY OF THE INVENTION One object of the present invention is to provide an integrated component of a junction transistor and a Schottky diode. In order to achieve the above object, in one aspect, the present invention provides an integrated interface between a junction transistor and a Schottky diode, including a depleted junction transistor, which includes a source, The pole and the gate, the secret does not provide ohmic contact to form a Schottky diode. The integrated components of the junction transistor and the Schottky diode may be planar or vertical. In view of one of the semiconductor structures, the integrated component of the interface transistor and the Schottky diode of the present invention comprises: a substrate of a first conductivity type; and a second conduction at the base a first well region of the crane; a second well region having a first conductivity type in the first well region; and a first high concentration doped region having a second conductivity type in the first well region; And (10) a second high-concentration doping region having a first-conducting type in the second well region, wherein the substrate, the first well region, and the second well region have a wire-connected junction transistor The concentration doping cage serves as an ohmic contact of the source of the wire-deficient junction transistor. The second high concentration doped region serves as an ohmic contact of the depleted junction transistor gate, and the depleted junction transistor is There is no ohmic contact with the first conduction 4 201036172 type to form the Schottky diode. The integrated component described above can have two third-doped regions of the first-conducting type at the Schottky diode position to control the reverse leakage current. In view of the fact that the gastric sputum is different from the conductor structure, the integrated element of the junction transistor and the Schottky diode of the present invention comprises: - a first conductivity type = body; and is located in the matrix Two second products having a second conductivity type, wherein the substrate and the two first well regions constitute a vertical type of wear junction Ο 〇 county: body 'silk body front as the depleted junction electric day The base of the Japanese body is the source of the depleted junction transistor, and the two first well regions are the closed poles of the depleted junction transistor, and the depletion type The junction transistor does not have an ohmic contact in the conduction mode to form the Schottky diode. The integrated component' described above may further include a doped region to the second conductivity type at the Schottky diode position to control the reverse leakage current of the Schottky diode. The details of the present invention, the technical pumping capacity, the characteristics, and the effects achieved by the present invention are described in detail below by way of specific examples. [Embodiment] _ τ of the present specification is a schematic, and its dimensions are not completely drawn to scale. The reference to the fourth and fourth diagrams is shown in the form of a circuit diagram. If the ride is not, the actual payback is formed by the integration of the 22-sided NMOS transistor 24 of the age-based diode to form the power switching element 2〇. The junction 〇S transistor 24 is dry and its gate is grounded, so that no complicated control circuit 10 is required. The input voltage and the output voltage % are as shown in Fig. 4, 2010. The current input voltage Vin is greater than the forward bias voltage vf of the Schottky diode 22, and the electric energy can be transmitted from the input terminal Vin to the output terminal. However, due to the current limiting characteristics of the depleted junction transistor 24 itself, the output voltage v〇 will remain at about 4 to 6 vut, which is only a paste, and the design of the circuit can be changed. When the above circuit is fabricated in a semiconductor, please refer to Figure 5 for an example of its implementation. As shown in the figure, an N-type well region 2〇2 is formed on the P-type substrate 2〇1, and a p-type doped region 2〇3 is disposed in the N-type well region 202, thus constituting the consumption in the 4th item. Lacked junction transistor 24. A high-concentration P+ doped region 204' should be disposed in the P-type doped region 2〇3 and a high-concentration N+ doped region 205 should be disposed in the N-type well region 202 to provide an ohmic contact, respectively. The gate and source of the junction transistor. However, the N-type well region 2〇2 is the region of the drain as the region of the drain, and no high-concentration N+ doped region is provided. Since no ohmic contact is provided, the conduction barrier here is higher than that of a Schottky diode, which is connected in series with the drain of the transistor 24. In a preferred embodiment, a high concentration p+ doping region 2〇6 can be disposed at the position of the Schottky diode in the N-well region 2〇2 to control the reverse leakage current of the Schottky diode. . As can be seen from Fig. 5, the area occupied by the present invention is only equivalent to the area of the single-depleted junction transistor 24, and it can be seen from the comparison of the 3B and 4B drawings that the present invention can be directly applied to the prior art. A complex control circuit is required, which is far superior to the prior art. Fig. 6 shows another embodiment of the present invention, in which the depleted junction cell crystal system is of a vertical type. As shown in the figure, the N-type base is used as the two p-type well regions 213, thus constituting the vertical type of consumption: the junction = body 'with the two P-type well regions 213 as the gate, and the front and back of the substrate They are immersed in the pole and source. In a preferred embodiment, to provide a preferred source contact resistance, the N-type substrate 210 preferably comprises a relatively high concentration of N+-type body 211 and n 6 201036172-type epitaxial growth region 212. Similar to the previous embodiment, the region as the drain is not double-mounted, and the N+ doped region is high, which causes a high conduction barrier to constitute the Schottky's one-pole and the vertical junction transistor. Extremely connected. Similarly, in order to suppress the reverse leakage current of the Schottky diode, a high concentration P+ doping region 214 may be further disposed at the position of the Schottky diode on the surface of the Si-type substrate 210; this P+ doping Zone 214 also serves as an ohmic contact for the gate. If the p+ holding region 214 is not provided, the illustrated gate terminal should be connected to the p-type well region 213. The present invention has been described above with reference to the preferred embodiments, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be considered within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 and 2 show prior art power switching elements including a separate NMOS transistor and a separate Schottky diode. Figures 3A and 3B illustrate an application example of the prior art. 〇 4A and 4B illustrate an embodiment of the present invention and its application.帛5® shows one of the embodiments when the present invention is implemented in a semiconductor. Fig. 6 shows another embodiment of the present invention when implemented in a semiconductor. [Main component symbol description] 10 control circuit 12 Schottky diode 14 NMOS transistor 14D parasitic diode 16 consuming NMOS transistor 16D parasitic diode 20 integrated power switching element 22 Schottky diode 7 201036172 24 Depleted junction transistor 201 P-type substrate 202 N-type well region 203 P-doped region 204 P+ doped region 205 N+ doped region 206 P+ doped region 210 N-type substrate 211 N+-type body 212 N-type Epitaxial growth zone 213 P-type well zone 214 P+ doped zone