TW201035656A - Pixel element of liquid crystal display and method for producing the same - Google Patents

Pixel element of liquid crystal display and method for producing the same Download PDF

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Publication number
TW201035656A
TW201035656A TW098109533A TW98109533A TW201035656A TW 201035656 A TW201035656 A TW 201035656A TW 098109533 A TW098109533 A TW 098109533A TW 98109533 A TW98109533 A TW 98109533A TW 201035656 A TW201035656 A TW 201035656A
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Taiwan
Prior art keywords
layer
semiconductor layer
electrode
halogen
voltage
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TW098109533A
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Chinese (zh)
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TWI413839B (en
Inventor
Tsu-Chiang Chang
Po-Yang Chen
Chao-Hui Wu
Po-Sheng Shih
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Hannstar Display Corp
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Priority to TW098109533A priority Critical patent/TWI413839B/en
Priority to US12/580,919 priority patent/US8264629B2/en
Publication of TW201035656A publication Critical patent/TW201035656A/en
Priority to US13/354,161 priority patent/US8854566B2/en
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Publication of TWI413839B publication Critical patent/TWI413839B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/139—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent
    • G02F1/1393—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells
    • G02F1/1395—Optically compensated birefringence [OCB]- cells or PI- cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Abstract

The present invention provides a method for forming a pixel element. The method comprises: forming a patterned first electrode layer within the pixel area; forming an insulation layer on the patterned first electrode layer; forming a semiconductor layer on the insulation layer; pattering the semiconductor layer to form bend seed generation portion; and forming a patterned second electrode layer to connect the semiconductor layer.

Description

201035656 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶顯示器的晝素結構，特別是關於 一種可快速完成熱機程序的液晶顯示器的晝素結構。 【先前技術】 液晶顯示器根據使用的液晶種類、驅動方式與光源配 〇置等不同而區分成許多種類。其中，光學補償雙折射液晶 顯示态（optically compensated birefringence liquid crystal display 或 optically compensated bend liquid crystal display, OCB LCD)具有快速的應答速度，可提供更加流暢的晝面 表現。 而光學補償雙折射液晶顯示器必須先讓液晶分子由展 延態(splay state)轉換成彎曲態(bend state)後，才能進入正 常顯示狀fe。第一 A圖與第一 b圖顯示光學補償雙折射液 晶顯示器10中，液晶分子處於展延態與彎曲態的示意圖， 其中第一 A圖顯示展延態，而第一 b圖顯示彎曲態。 如圖所示，在光學補償雙折射液晶顯示器1〇中，液晶 層11被設置於一薄膜電晶體陣列基板13與—彩色濾光片 基板I2之間，當液晶層11未受到電場作用時，液晶分子 以展延態（splay state)方式排列，當兩基板施加一電場於液 201035656 f * * ,201035656 VI. Description of the Invention: [Technical Field] The present invention relates to a halogen structure of a liquid crystal display, and more particularly to a pixel structure of a liquid crystal display capable of quickly completing a heat engine program. [Prior Art] The liquid crystal display is classified into many types depending on the type of liquid crystal used, the driving method, and the light source arrangement. Among them, the optically compensated birefringence liquid crystal display or optically compensated bend liquid crystal display (OCB LCD) has a fast response speed and provides a smoother surface performance. The optically compensated birefringent liquid crystal display must first convert the liquid crystal molecules from the splay state to the bend state before entering the normal display. The first A diagram and the first b diagram show a schematic diagram of the liquid crystal molecules in the extended state and the curved state in the optically compensated birefringent liquid crystal display 10, wherein the first A diagram shows the extended state, and the first b diagram shows the curved state. As shown in the figure, in the optically compensated birefringent liquid crystal display device, the liquid crystal layer 11 is disposed between a thin film transistor array substrate 13 and a color filter substrate I2. When the liquid crystal layer 11 is not subjected to an electric field, The liquid crystal molecules are arranged in a splay state manner, and when an electric field is applied to the two substrates in the liquid 201035656 f * * ,

PP

V b曰層’液晶分子才會轉換成彎曲態列(ben(j state)，此—轉 換過程亦稱為熱機(start up)。習知的光學補償雙折射液晶 顯示器需要數分鐘的時間進行熱機過程，才能進行正常軀 動，消費者恐不耐夂等。 丨為了減少熱機所需時間，美國專利公告號6597424揭 露一種光學補償雙折射液晶顯示器的晝素結構，如第二圖 所示。在資料線21與掃描線22所定義的晝素結構，包含 一晝素電極24與驅動晝素電極24的開關電晶體23。此外， 在晝素電極24邊緣靠近中央的部分具有凹陷部分25a與凸 出部分25b，而在掃描線22與資料線21的對應位置，具 有互補的凸出部分26a/27a與凹陷部分26b/27b。此晝素結 ..乂 構再搭配晝素電極24與資料線21之間，以及晝素電極24 與掃描線22之間的電位差，形成橫向電場，用以產生幫助 液晶分子轉換的轉態種子(bend seed)，使得轉換時間得以 縮短。The V b 曰 layer 'liquid crystal molecules will be converted into a bend state column (ben (j state), this - the conversion process is also called the start up. The conventional optically compensated birefringence liquid crystal display takes several minutes to heat the machine In order to perform normal body movements, consumers are not afraid of sputum, etc. 丨 In order to reduce the time required for the heat engine, US Patent Publication No. 6597424 discloses a halogen structure of an optically compensated birefringent liquid crystal display, as shown in the second figure. The halogen structure defined by the data line 21 and the scanning line 22 includes a halogen electrode 24 and a switching transistor 23 that drives the halogen electrode 24. Further, a portion near the center of the edge of the pixel electrode 24 has a concave portion 25a and a convex portion. The portion 25b is provided, and at the corresponding position of the scanning line 22 and the data line 21, there are complementary convex portions 26a/27a and concave portions 26b/27b. This bismuth junction is further coupled with the halogen electrode 24 and the data line. Between 21, and the potential difference between the halogen electrode 24 and the scanning line 22, a transverse electric field is formed to generate a bend seed that assists in the conversion of liquid crystal molecules, so that the switching time is shortened.

i'L 上述結構雖然縮短了熱機時間，但卻由於晝素結構具 有不規則的突出部分25b/26a/27a或凹陷部貪 25a/26b/27b ’需要同樣是不規則形狀、且更大面積的黑矩 陣遮蔽以避免漏光，導致開口率降低。 因此’亟需提供一種晝素結構與形成晝素結構的方 法，不僅可以縮短熱機時間，亦能保持良好的開口率。 201035656 【發明内容】 本發明的目的在於提供一種新的晝素結構與形成晝素 結構的方法，不僅可以縮短熱機時間，亦能保持良好的開 口率。 根據上述目的，本發明提供一種液晶顯示器:芝晝秦I#構 的形成方法，包含：在畫素區域形成一圖案化的第一電極 層；形成一絕緣層於第一電極層上；形成一半導體層於絕 0緣層上；及圖案化半導體層使形成多個轉態種子產生區 域；以及形成圖案化的一第二電極層連接半導體層。 根據本發明提供的晝素結構，第一電極層為一掃描線或 一共用線，第二電極層為一資料線、電容電極或晝素電極。 第一電極層具有一第一電壓，第二電極層具有一第二電 壓，該第一電壓與該第二電壓的電位差產生一橫向電場， ^使半導體層的轉態種子產生區域產生轉態種子。 【實施方式】 習知技術藉由改變晝素結構，以產生轉態種子使加速完 成熱機程序，都必須大幅改變晝素結構，犧牲了開口率， 或者使製程變複雜。本發明提供一種晝素結構與其形成方 法，以及應用此晝素結構的液晶顯示器，可在不影響晝素 結構、與原先製程相容、影響開口率小的條件下完成此目 201035656 的。 貝根據本發明實施例的形成晝素結構的方 法0於步驟31，+ * 在畫素區域形成圖案化的（patterned)第一 電極層第—電極層與掃描線位於同—層，並且可連接掃 描線或者’第一電極較佳係掃描線或共用線（亦稱為偏 壓線）。此處晝夸F 0 3 1 、 意京^域疋指由掃描線與資料線所定義的區 〆、匕3邊界區域’通常兩條掃描線與兩條資料線定義- 立（或個以上的）畫素，而第一電極層可以形成在晝素内 品+或者邊界區域。步驟32 ’形成絕緣層於第一電極層 上v驟33，形成半導體層於絕緣層上，此半導體層的材 質可為夕晶石夕、微晶石夕、非晶石夕的其中之一或其組合。步 驟34圖案化半導體層使形成多個轉態種子產生區域。步 ^ $成圖案化的第二電極層連接半導體層《在-實施 例中’第二電極層與㈣線位於同—層，並且可連接資料 或者’第二電極層較佳為資料線或電容電極。而在另 一實施例中，第二電極層係、晝素電極(㈣丨咖咖岭且 在畫素電極與半導體層之間尚具有—保護層，畫素電極透 過接觸窗（⑺福h。⑷連接半導體層。在本發明的各實施例 中’半導體層至少部分，或全部，位於第1極層的正上 方。 第四圖顯示-種在熱機期間，可快速完成轉態的方法， 201035656 應用於第三圖的製程所形成的晝素結構。步驟41，給予一 第一正電壓於第一電極層。步驟42，該半導體層感應到該 第一電極層的正電壓，因而在該半導體的底部聚集極性相 反的電子層。步驟43，給予一第二電壓於第二電極層，其 中第一正電壓大於第二正電壓。步驟44，此時層 ;與該第二電極層的電位會連結，該第二金屬層的導 入該半導體層。步驟45，利用該第一電極層與該第二電極 0層之間的電位差產生橫向電場，使該半導體層的轉態種子 產生區域產生轉態種子。 在上述的方法中，為了改變性質，半導體層可進行一摻 雜製程以形成一摻雜區域，例如N正型離子重摻雜區域， 使得半導體層與第二電極層之間為歐姆接觸。另外，正電 壓可以改成負電壓，只要保持足夠的電位差產生轉態種子 即可。另外，由於熱機程序與正常操作程序不同，因此在 ® 熱機程序給予第一電極層與第二電極層的電壓值，可能不 同於在正常操作程序給予第一電極層與第二電極層的電壓 值。例如，若第一電極層為掃描線，第二電極層為資料線， 在正常操作時掃瞄線的電壓可能為10V至15V，資料線的 電壓可能為0至10V，但熱機程序可能供應電壓給掃描線 40V，給資料線0至IV。 第五A圖至第五C圖顯示根據本發明實施例的晝素結 201035656 構，其中第五B圖是第五A圖的局部放大圖，第五C圖是 第五A圖在X-X’方向的剖面圖。 在第五A圖的實施例中，一晝素結構50由兩掃描線51 與兩資料線52所定義，但不限於此。如前所述，具有轉態 種子產生區域的半導體層54/55可形成菸晝素結構50的邊— i ··' 界區域，例如半導體層54被形成在共用線53與資料線52 之間，或者，半導體層55被形成在掃描線51與資料線52 之間。此外，晝素結構50包含一晝素電極56用於驅動液 晶分子，一薄膜電晶體57用於控制畫素電極56。薄膜電 晶體57的結構如同習知技術，包含一閘極、一汲極、一源 極，或者薄膜電晶體57也可以是其他種類的開關元件。此 外，畫素結構50包含一電容電極58，與共用線53構成一 種形成在共用線上的儲存電容結構(Cst on common)，但儲 存電容的結構也可以是形成在掃描線上的儲存電容結構 (Cst on gate)。 第五B圖顯示了半導體層可能的幾何構造。為了形成轉 態種子產生區域，半導體層54被挖空形成一多邊形 (polygon)的開口，其輪廓包含直角，而圖中以雙箭頭顯示 的8個區域即為轉態種子產生區域。值得注意的是，多邊 形的輪廓亦可包含鈍角、銳角、或其他不不規則輪廓等等。 並且，不同的半導體層可以有相同或不同形狀的轉態種子 201035656 產生£域’例如，半導am, 干导體層55的形狀，可與半導體層54 的形狀相同或者不同。 第五C圖疋第五八圖在χ—X，方向的剖面圖。如圖，共 用線53被形纽基板59上，絕緣層⑹被形成於共用線 53上，具有轉態種子產生區域的半導體過54被形成於絕: 緣層60上’其中半導體層S4至少部分位於共用㈣的正 上方，以及資料線52被形成於半導體層54上。 0帛六®與第七圖顯示另外兩種具有#_子產生區域 之半導體層的形狀。為了方便說明，以下實施例與之前實 施例的相同元件以相同符號表示，僅說明與前實施例的不 同處，相同處不再贅述。在第六圖中，半導體層54具有凸 出部分61作為轉態種子產生區域。在第七圖中，半導體層 54被挖空形成一多邊形（或一個以上的多邊形）的開口，其 ❹輪廓包含直角、鈍角或銳角，以及半導體層54的外輪廓具 有凸出部分61可作為轉態種子產生區域。 第八A圖至第八D圖說明本發明具有轉態種子產生區 域的半導體層也可形成在畫素結構的儲存電容結構中。其 中第八B圖是第八A圖的局部放大圖，第八c圖是第八八 圖在Y_Y’方向的剖面圖。 如第八Α圖與第八Β圖所示，半導體層62設置於電容 201035656 電極58的下方，且具有凸出部分〇作為轉態種子產生區 域，而電容電極58的電位係連接到畫素電極％的電位， 晝素電極56透過接觸窗63與電容電極％連接。 第八C圖是第八A圖在γ—γ，方向的剖面圖。如圖，共 用線53被形成於基板“上，絕緣層6〇被形成於共用“ 53上，具有轉態種子產生區域的半導體層62被形成於絕 緣層60上，電容電極58被形成在半導體層62上，保護層 63覆蓋電容電極58,以及晝素電極56藉由接觸窗63與半 導體層62連接。 如第八C圖具有轉態種子產生區域的半導體層62是被 ^/成在種金屬層/絕緣層/金屬層（MIM ; Metal/Insulation/i'L The above structure shortens the heat engine time, but the irregular structure 25b/26a/27a or the recessed portion 25a/26b/27b' of the halogen structure requires the same irregular shape and a larger area. The black matrix is shielded to avoid light leakage, resulting in a decrease in aperture ratio. Therefore, there is a need to provide a structure of a halogen and a method of forming a halogen structure, which not only shortens the heat engine time but also maintains a good aperture ratio. SUMMARY OF THE INVENTION The object of the present invention is to provide a novel halogen structure and a method for forming a halogen structure, which can not only shorten the heat engine time but also maintain a good opening ratio. According to the above objective, the present invention provides a liquid crystal display: a method for forming a zhixi Qin I# structure, comprising: forming a patterned first electrode layer in a pixel region; forming an insulating layer on the first electrode layer; forming a The semiconductor layer is on the rim layer; and the patterned semiconductor layer is formed to form a plurality of transition seed generation regions; and a patterned second electrode layer is formed to connect the semiconductor layer. According to the halogen structure provided by the present invention, the first electrode layer is a scan line or a common line, and the second electrode layer is a data line, a capacitor electrode or a halogen electrode. The first electrode layer has a first voltage, the second electrode layer has a second voltage, and the potential difference between the first voltage and the second voltage generates a transverse electric field, so that the transition seed generation region of the semiconductor layer generates the transition seed. . [Embodiment] Conventional techniques have to significantly change the structure of a halogen, by sacrificing the aperture ratio, or by making the process complicated by changing the structure of the halogen to generate a transition seed to accelerate the completion of the heat engine program. The present invention provides a halogen structure and a method for forming the same, and a liquid crystal display using the same, which can be completed without affecting the structure of the halogen, being compatible with the original process, and affecting the aperture ratio of 201035656. According to the method for forming a halogen structure of the embodiment of the present invention, in step 31, +* forms a patterned first electrode layer in the pixel region, and the first electrode layer is in the same layer as the scan line, and is connectable The scan line or 'first electrode is preferably a scan line or a common line (also known as a bias line). Here, FF 0 3 1 , Yi Jing ^ domain refers to the boundary area defined by the scan line and the data line 匕, 匕 3 boundary area 'usually two scan lines and two data lines defined - vertical (or more The pixel, and the first electrode layer may be formed in the halogen inner product + or the boundary region. Step 32: forming an insulating layer on the first electrode layer v 33, forming a semiconductor layer on the insulating layer, the material of the semiconductor layer may be one of the cerevisiae, the microcrystalline stone, the amorphous stone eve or Its combination. Step 34 patterning the semiconductor layer to form a plurality of transition seed generation regions. Step 2: patterning the second electrode layer to connect the semiconductor layer. In the embodiment, the second electrode layer and the (four) line are in the same layer, and the data or the second electrode layer is preferably a data line or a capacitor. electrode. In another embodiment, the second electrode layer, the halogen electrode ((4) 丨 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖 咖(4) Connecting the semiconductor layer. In each of the embodiments of the present invention, the semiconductor layer is at least partially or entirely located directly above the first electrode layer. The fourth figure shows a method for rapidly completing the transition state during the heat engine, 201035656 Applying to the halogen structure formed by the process of the third figure, step 41, applying a first positive voltage to the first electrode layer. In step 42, the semiconductor layer senses a positive voltage of the first electrode layer, and thus the semiconductor The bottom of the bottom gathers the opposite polarity electron layer. In step 43, a second voltage is applied to the second electrode layer, wherein the first positive voltage is greater than the second positive voltage. Step 44, at this time, the potential of the second electrode layer Connecting, the second metal layer is introduced into the semiconductor layer. In step 45, a potential electric field is generated by using a potential difference between the first electrode layer and the second electrode 0 layer to cause a transition of the transition seed generation region of the semiconductor layer. In the above method, in order to change the properties, the semiconductor layer may be subjected to a doping process to form a doped region, such as an N-type ion heavily doped region, such that the semiconductor layer is in ohmic contact with the second electrode layer. In addition, the positive voltage can be changed to a negative voltage, as long as sufficient potential difference is maintained to generate the transition seed. In addition, since the heat engine program is different from the normal operation procedure, the first electrode layer and the second electrode layer are given in the ® heat engine program. The voltage value may be different from the voltage value given to the first electrode layer and the second electrode layer in a normal operation procedure. For example, if the first electrode layer is a scan line and the second electrode layer is a data line, the scan line is in normal operation. The voltage may be 10V to 15V, the voltage of the data line may be 0 to 10V, but the heat engine program may supply voltage to the scan line 40V, to the data line 0 to IV. Figures 5A through 5C show implementation according to the present invention Example of a bismuth junction 201035656, wherein the fifth B is a partial enlarged view of the fifth A, and the fifth C is a cross-sectional view of the fifth A in the X-X' direction. The monomorph structure 50 is defined by two scan lines 51 and two data lines 52, but is not limited thereto. As described above, the semiconductor layer 54/55 having the transition seed generation region may form the soot structure 50. An edge region, for example, a semiconductor layer 54 is formed between the common line 53 and the data line 52, or a semiconductor layer 55 is formed between the scan line 51 and the data line 52. Further, the halogen structure 50 A halogen electrode 56 is used to drive the liquid crystal molecules, and a thin film transistor 57 is used to control the pixel electrode 56. The thin film transistor 57 is structured as in the prior art and includes a gate, a drain, a source, or The thin film transistor 57 may be other types of switching elements. Further, the pixel structure 50 includes a capacitor electrode 58 and a common storage line 53 forms a storage capacitor structure (Cst on common) formed on a common line, but the structure of the storage capacitor It may also be a Cst on gate formed on the scan line. Figure 5B shows the possible geometric configuration of the semiconductor layer. In order to form a transition seed generating region, the semiconductor layer 54 is hollowed out to form a polygon opening having a right angle, and the eight regions shown by double arrows in the figure are the transition seed generating regions. It is worth noting that the outline of the polygon may also include obtuse angles, acute angles, or other irregular contours and the like. Also, different semiconductor layers may have the same or different shape of the transition seed 201035656. The shape of the semiconductor layer, for example, the semiconducting am, the dry conductor layer 55 may be the same or different from the shape of the semiconductor layer 54. Figure 5 is a cross-sectional view of the fifth and eighth figures in the direction of χ-X. As shown, the common line 53 is formed on the shaped base substrate 59, the insulating layer (6) is formed on the common line 53, and the semiconductor over 54 having the transition seed generating region is formed on the insulating layer 60' wherein the semiconductor layer S4 is at least partially Located directly above the common (four), and the data line 52 is formed on the semiconductor layer 54. The 0.6 and the seventh figures show the shapes of the other two semiconductor layers having the #_ sub-generation region. For the sake of convenience of explanation, the same components of the following embodiments are denoted by the same reference numerals, and only the differences from the previous embodiments will be described, and the same portions will not be described again. In the sixth figure, the semiconductor layer 54 has a convex portion 61 as a transition seed generating region. In the seventh diagram, the semiconductor layer 54 is hollowed out to form a polygon (or more than one polygon) opening having a meandering angle, an obtuse angle or an acute angle, and the outer contour of the semiconductor layer 54 having the convex portion 61 as a turn State seed production area. The eighth to eighth figures D illustrate that the semiconductor layer having the transition seed generating region of the present invention can also be formed in the storage capacitor structure of the pixel structure. The eighth B diagram is a partial enlarged view of the eighth A diagram, and the eighth c diagram is a sectional view of the eighth diagram in the Y_Y' direction. As shown in the eighth and eighth figures, the semiconductor layer 62 is disposed under the electrode 58 of the capacitor 201035656, and has a convex portion 〇 as a transition seed generating region, and the potential of the capacitor electrode 58 is connected to the pixel electrode. The potential of %, the halogen electrode 56 is connected to the capacitor electrode % through the contact window 63. The eighth C diagram is a cross-sectional view of the eighth A diagram in the direction of γ-γ. As shown in the figure, the common line 53 is formed on the substrate "on, the insulating layer 6 is formed on the common "53", the semiconductor layer 62 having the transition seed generating region is formed on the insulating layer 60, and the capacitor electrode 58 is formed in the semiconductor On the layer 62, the protective layer 63 covers the capacitor electrode 58, and the pixel electrode 56 is connected to the semiconductor layer 62 via the contact window 63. The semiconductor layer 62 having the transition seed generation region as shown in the eighth C diagram is formed into a metal layer/insulation layer/metal layer (MIM; Metal/Insulation/

Metal)的儲存電容架構中’第二電極層的下方，但上述電 容電極58亦可以省略，如第八D圖所示，此時晝素電極 作為儲存電容的另一參考電極，並藉由接觸窗63與半導體 層62連接。 第九A圖至第九6圖顯示另外一種具有轉態種子產生區 域之半導體層的形狀，其中第九B圖係第九a圖的局部放 大圖。於圖中顯示’半導體層65被挖空形成多個多邊形的 開口，其輪廓包含直角、鈍角或銳角以作為轉態種子產生 區域。 201035656 第十A圖至第十B圖顯示另外一種具有轉態種子產生區 域之半導體層的形狀，其中第十B圖係第十A圖的局部放 大圖。於圖中顯示，半導體層66被挖空形成多個多邊形的 開口，開口的輪廓包含直角、鈍角或銳角以作為轉態種子 產生區域，同時，半導i體層66的外輪廓具有凸出部分作為 - ! 二..；： - ·.；；-： -々二- 轉態種子產生區域。； 以上各實施例的特徵，皆可用單一或組合的方式互相應 〇用，不限於圖示所揭露者。此外，第八A圖至第十B圖的 實施例也可以應用於形成在掃描線上的儲存電容結構(Cst on gate)，其不同處僅在於另一參考電極為掃描線而非共用 線，因此其圖示與說明省略。 而第四圖的方法可應用於上述各實施例中，其差異僅在Metal storage capacitor structure is below the second electrode layer, but the capacitor electrode 58 can also be omitted, as shown in the eighth D diagram, at this time, the pixel electrode serves as another reference electrode of the storage capacitor, and is contacted. The window 63 is connected to the semiconductor layer 62. Figures 9 through IX show the shape of another semiconductor layer having a transition seed generating region, wherein ninth B is a partial enlarged view of Fig. 9a. It is shown in the figure that the semiconductor layer 65 is hollowed out to form a plurality of polygonal openings whose outlines include a right angle, an obtuse angle or an acute angle as a transition seed generation region. 201035656 Figures 10A through 10B show another shape of a semiconductor layer having a transition seed generation region, wherein the tenth B is a partial enlargement of the tenth A diagram. As shown in the figure, the semiconductor layer 66 is hollowed out to form a plurality of polygonal openings, and the outline of the opening includes a right angle, an obtuse angle or an acute angle as a transition seed generating region, and at the same time, the outer contour of the semi-conductive body layer 66 has a convex portion as a - ! II..;: - ·.;;-: -々二 - The transition seed production area. The features of the above embodiments may be used in a single or combined manner, and are not limited to those disclosed in the drawings. Furthermore, the embodiments of FIGS. 8A to 10B can also be applied to a storage capacitor structure (Cst on gate) formed on a scan line, except that the other reference electrode is a scan line instead of a common line, and thus The illustration and description are omitted. The method of the fourth figure can be applied to the above embodiments, and the difference is only in

於第一電極層與第二電極層的電位來源不同。對於第五C ^ 圖的實施例而言，第一電極層為共用線，第二電極層為資 ❹ 料線，資料線的電位被導入半導體層。對於第八C圖的實 施例而言，第一電極層為共用線，第二電極層為電容電極， 晝素電極的電位被導入電容電極，再導入半導體層。對於 第八D圖的實施例而言，第一電極層為共用線，而晝素電 極可視為第二電極層，其電位透過接觸窗導入半導體層。 以上所揭露的晝素結構或形成晝素結構的方法，可應用 於一液晶顯示器，該液晶顯示器包含一薄膜電晶體陣列基 11 201035656 板與一彩色濾光片基板，該晝素結構被配置於薄膜電晶體 陣列基板上。而彩色濾光片基板包含一共用電極，共用電 極與薄膜電晶體陣列基板上的晝素電極之間形成電場可驅 動液晶分子。而根據以上的結構與方法，利用第一電極層 與第二電極層之間的電仏差產生橫向電廣:，使半導體層的 1轉態種子產生區域產生^!態種子，再藉由兩基板之間的電 場，使液晶彼此產生交互作用而傳播到其他區域，進而快 速完成熱機程序。根據實驗，轉態時間可被縮短至3秒鐘， 甚至1秒鐘以下。 而根據本發明所揭露的結構與方法，晝素電極並未被變 更，且具有轉態種子產生區域的半導體層所佔面積極小， 因此開口率機乎沒有受到影響。此外，本發明揭露的方法 與現有製程相符，形成具有轉態種子產生區域的半導體層 的步驟33可與形成薄膜電晶體57中的半導體層的步驟相 同，因此不需要額外的製程。綜上所述，本發明實為解決 光學補償雙折射液晶顯示器其熱機時間過慢的一良好方 案。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其他未脫離發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專 利範圍内。 12 201035656 【圖式簡單說明】 第一A圖與第一B圖顯示一習知的光學補償雙折射液晶顯 示器的液晶分子分布示意圖； 第二圖顯示一習知的光學補償雙折射液·晶顧示器的畫素結 構； ' 第三圖與第四圖顯示根據本發明實施例的液晶顯示器之晝 〇素結構的形成方法； 第五A圖至第七圖顯示根據本發明一實施例的液晶顯示器 之晝素結構與其變化；及 第八A圖至第十B圖顯示根據本發明一實施例的液晶顯示 器之畫素結構與其變化。 【主要元件符號說明】The potential sources of the first electrode layer and the second electrode layer are different. For the embodiment of the fifth C^ diagram, the first electrode layer is a common line, the second electrode layer is a material line, and the potential of the data line is introduced into the semiconductor layer. In the embodiment of the eighth C diagram, the first electrode layer is a common line, the second electrode layer is a capacitor electrode, and the potential of the halogen element is introduced into the capacitor electrode and then introduced into the semiconductor layer. For the embodiment of the eighth diagram, the first electrode layer is a common line, and the halogen electrode can be regarded as a second electrode layer, the potential of which is introduced into the semiconductor layer through the contact window. The halogen structure or the method for forming a halogen structure disclosed above can be applied to a liquid crystal display comprising a thin film transistor array substrate 11 201035656 plate and a color filter substrate, and the halogen structure is configured On a thin film transistor array substrate. The color filter substrate comprises a common electrode, and an electric field is formed between the common electrode and the halogen electrode on the thin film transistor array substrate to drive the liquid crystal molecules. According to the above structure and method, the electrical enthalpy difference between the first electrode layer and the second electrode layer is used to generate a lateral electric width: the 1-turn seed generation region of the semiconductor layer is generated by the seed, and then by the two The electric field between the substrates causes the liquid crystals to interact with each other and propagate to other areas, thereby quickly completing the heat engine program. According to the experiment, the transition time can be shortened to 3 seconds or even less than 1 second. According to the structure and method disclosed in the present invention, the halogen electrode is not changed, and the semiconductor layer having the transition seed generating region is actively occupied, so that the aperture ratio is not affected. Furthermore, the method disclosed in the present invention conforms to the prior art process, and the step 33 of forming the semiconductor layer having the transition seed generating region can be the same as the step of forming the semiconductor layer in the thin film transistor 57, so that no additional process is required. In summary, the present invention is a good solution for solving the thermal compensation time of an optically compensated birefringent liquid crystal display. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application. 12 201035656 [Simplified description of the drawings] The first A and the first B show a schematic diagram of the liquid crystal molecular distribution of a conventional optically compensated birefringent liquid crystal display; the second figure shows a conventional optically compensated birefringent liquid a pixel structure of the display; 'The third and fourth figures show a method of forming a pixel structure of a liquid crystal display according to an embodiment of the present invention; and FIGS. 5A to 7 show a liquid crystal according to an embodiment of the present invention. The pixel structure of the display and its variations; and the eighth to tenth B diagrams show the pixel structure of the liquid crystal display and its variations according to an embodiment of the present invention. [Main component symbol description]

10 光學補償雙折射液晶顯示器 11 液晶層 12 彩色渡光片基板 13 薄膜電晶體陣列基板 21 資料線 22 掃描線 23 開關電晶體 13 201035656 24 25a 25b 26a 26b 27a 27b 31 32 33 34 35 41 42 43 44 45 50 晝素電極 凹陷部份 凸出部分 凸出部分 凹陷部份 二:… ^ 凸出部# 凹陷部份 在晝素區域形成圖案化的第一電極層 形成絕緣層於第一電極層上 形成半導體層於絕緣層上 圖案化半導體層使形成多個轉態種子產生 區域 形成圖案化的第二電極層連接半導體層 給予一第一正電壓於第一電極層 半導體的底部聚集極性相反的電子層 給予一第二電壓於第二電極層，其中第一 正電壓大於第二正電壓 半導體層與第二金屬層的電位會連結 利用第一金屬層與第二金屬層之間的電位 差產生橫向電場，使半導體層的轉態種子 產生區域產生轉態種子 晝素結構 14 20103565610 Optically compensated birefringent liquid crystal display 11 Liquid crystal layer 12 Color light-drain substrate 13 Thin film transistor array substrate 21 Data line 22 Scan line 23 Switching transistor 13 201035656 24 25a 25b 26a 26b 27a 27b 31 32 33 34 35 41 42 43 44 45 50 昼 电极 电极 部份 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极 电极The semiconductor layer is patterned on the insulating layer to form a plurality of transition seed generating regions to form a patterned second electrode layer. The semiconductor layer is bonded to the bottom of the first electrode layer semiconductor to form an opposite polarity electron layer. Applying a second voltage to the second electrode layer, wherein the first positive voltage is greater than the potential of the second positive voltage semiconductor layer and the second metal layer to connect to generate a transverse electric field by using a potential difference between the first metal layer and the second metal layer, Making a transition seed seed producing region of the semiconductor layer to produce a transformed seed morpheme structure 14 201035656

51 掃描線 52 資料線 53 共用線 54 半導體層 55 半導體層 56 晝素電極 57 薄膜電晶體 58 電容電極 59 基板 60 絕緣層 61 凸出部分 62 半導體層 63 接觸窗 64 保護層 65 半導體層 66 半導體層 67 凸出部分 1551 scan line 52 data line 53 common line 54 semiconductor layer 55 semiconductor layer 56 germanium electrode 57 thin film transistor 58 capacitor electrode 59 substrate 60 insulating layer 61 protruding portion 62 semiconductor layer 63 contact window 64 protective layer 65 semiconductor layer 66 semiconductor layer 67 protruding part 15

Claims (1)

201035656 七、申請專利範圍： -種液晶顯示器之畫素結構的形成方法，包含： 在畫素區域形成一圖案化的第一電極層； 形成一絕緣層於該第一電極層上； 形成一半導體層於該絕緣層上； 域 區 圖案化該卓導體層使形成複數個轉態種子產!生 :以及 體層 形成圖案化的一第二電極層連接該半導 2.如申請專利範圍第1項的方法，尚包含： 給予一第一電壓於該第一電極層； ^該半導體層感應到該第—電極層的該第一電壓 在該半導體層的底《集極性相反的電子層或電洞層； 給予一第二電壓於該第二電極層，其中該第一 壓的電位大於或小於該第二電壓的電位； 該半導體層與該第二電極層的電位連結；以及 該第一電極層與該第二電極層之間的電位差產 橫向電場，使該半導體層的該轉態種子產生區域產生 態種子。 16 201035656 如申請專利範圍第1項的方法，其中該第 掃描線 極層係 4. 如 共用線 申請專利範圍第1項的方法，其中該第一 f極層係一 〇 5.如申請專利範圍第1項的方法，其中該第一 資料線位於同-層，並與該資料線連接。 極層與 6·如申請專利範圍第1項的方法，其中該第 資料線。 二 電極層係— 〇 7.如申請專利範圍第1項的方法，其 、昂一電極層係 儲存電容結構的電容電極。 μ 8·如申請專利範圍第1項的方法，盆中 ，、丫砀第二電極層係一 晝素電極，該晝素電極與該半導體層夕 瓶層之間尚具有一保講 層，該晝素電極透過一接觸窗連接該半導體層。 17 201035656 9.如申請專利範圍第1項的方法，其中該半導體層的材質 係多晶矽、微晶矽、或非晶矽的其中之一或其組合。 10.如申請專利範圍第ί項的方法'，尚包含進行一摻雜製 程，使該半導體層具有一摻雜區域，使該半導體層與該第 二電極層之間為歐姆接觸。 11.如申請專利範圍第1項的方法，其中該半導體層至少部 分位於該第一電極層的正上方。 12. —種液晶顯示器之晝素結構，包含複數個掃描線與複數 〇 個資料線所定義的複數個晝素，每一晝素包含： 一掃描線或一共用線，位於一薄膜電晶體基板上； 一絕緣層，位於該掃描線或該共用線上； 一半導體層，具有複數個轉態種子產生區域，位於該 絕緣層上；以及 一資料線，位於該半導體層上，且連接該半導體層。 18 201035656 · 13.如申請專利範圍第12項的畫素結構，其中該掃描線或 該共用線具有一第一電壓，該資料線具有一第二電壓，該 第一電壓與該第二電壓的電位差產生一橫向電場，使該半 導體層的該轉態種子產生區域產生轉態種子。 14.如申請專利範圍第12項的晝素結構，其中該半導體層 被挖空形成一個或一個以上的多邊形開口，多邊形的輪廓 包含直角、鈍角、銳角、或不規則的輪廓以構成該轉態種 子產生區域。 15.如申請專利範圍第12項的畫素結構，其中該半導體層 的外輪廓具有突出部分以構成該轉態種子產生區域。 16.如申請專利範圍第12項的晝素結構，其中該半導體層 被挖空形成一個或一個以上的多邊形開口，多邊形的輪廓 包含直角、鈍角或銳角，且該半導體層的外輪廓具有凸出 部分以構成該轉態種子產生區域。 19 201035656 17.如申請專利範圍第12項的晝素結構，其中該半導體層 至少部分位於該該掃描線或該共用線的正上方。 18. —種液晶顯示器之晝f結構，包含複數個掃描線與複數 I 個資料線所定義的複數個晝素，每一晝素包含： I 一掃描線或一共用線，位於一薄膜電晶體基板上； 一絕緣層，位於該掃描線或該共用線上； 一半導體層，具有複數個轉態種子產生區域，位於該 絕緣層上；以及 一第二電極層，位於該半導體層上方且連接該半導體 層0 19.如申請專利範圍第18項的晝素結構，其中該第二電極 層為一電容電極，該晝素結構尚包含一保護層位於該電容 電極上，以及一晝素電極位於該保護層上，該晝素電極透 過一接觸窗連接該電容電極。 20.如申請專利範圍第18項的晝素結構，其中該第二電極 層為一晝素電極，該晝素結構尚包含一保護層位於該半導 20 201035656 體層上，以及該晝素電極位於該晝素電極上，該晝素電極 透過一接觸窗連接該半導體層。 21.如申請專利範圍第18項的晝素結構，其中該掃描線或 t 該共用線具有一第一電壓，該資料線具有一第二電壓，該 第一電壓與該第二電壓的電位差產生一橫向電場，使該半 導體層的該轉態種子產生區域產生轉態種子。 22.如申請專利範圍第18項的晝素結構，其中該半導體層 被挖空形成一個或一個以上的多邊形開口，多邊形的輪廓 包含直角、鈍角、銳角、或不規則的輪廓以構成該轉態種 子產生區域。 23.如申請專利範圍第18項的晝素結構，其中該半導體層 的外輪廓具有突出部分以構成該轉態種子產生區域。 24.如申請專利範圍第18項的晝素結構，其中半導體層被 挖空形成一個或一個以上的多邊形開口，多邊形的輪廓包 21 201035656 含直角、鈍角或銳角，且該半導體層的外輪廓具有凸出部 分以構成該轉態種子產生區域。 25.如申請專利範圍第18項的晝素結，，其中該半導體層 至少部分位於該掃描線或該共用線的正上方。- - 22201035656 VII. Patent application scope: A method for forming a pixel structure of a liquid crystal display, comprising: forming a patterned first electrode layer in a pixel region; forming an insulating layer on the first electrode layer; forming a semiconductor Layered on the insulating layer; the domain region patterning the conductive layer to form a plurality of transitional seeds, and a second electrode layer patterned by the bulk layer is connected to the semiconductor. 2. As claimed in claim 1 The method further includes: applying a first voltage to the first electrode layer; ^ the semiconductor layer sensing the first voltage of the first electrode layer at the bottom of the semiconductor layer "collecting opposite polarity electron layers or holes a second voltage is applied to the second electrode layer, wherein a potential of the first voltage is greater than or less than a potential of the second voltage; a potential of the semiconductor layer is coupled to the second electrode layer; and the first electrode layer A potential difference between the second electrode layer and the second electrode layer produces a transverse electric field, such that the transition seed generation region of the semiconductor layer produces a seed. 16 201035656 The method of claim 1, wherein the first scan line layer is 4. The method of claim 1, wherein the first f pole layer is a 〇 5. The method of item 1, wherein the first data line is located in the same layer and is connected to the data line. The polar layer and the method of claim 1 of the patent scope, wherein the first information line. Two-electrode layer system - 〇 7. As in the method of claim 1, the An-electrode layer is a capacitor electrode of a storage capacitor structure. μ 8· The method of claim 1, wherein the second electrode layer of the basin is a monoterpene electrode, and the halogen electrode and the semiconductor layer have a layer of a layer between the layer of the semiconductor layer. The halogen electrode is connected to the semiconductor layer through a contact window. The method of claim 1, wherein the material of the semiconductor layer is one of a polycrystalline germanium, a microcrystalline germanium, or an amorphous germanium or a combination thereof. 10. The method of claim 5, further comprising performing a doping process such that the semiconductor layer has a doped region such that the semiconductor layer is in ohmic contact with the second electrode layer. 11. The method of claim 1, wherein the semiconductor layer is at least partially located directly above the first electrode layer. 12. A halogen structure of a liquid crystal display, comprising a plurality of pixels defined by a plurality of scan lines and a plurality of data lines, each element comprising: a scan line or a common line, located in a thin film transistor On the substrate; an insulating layer on the scan line or the common line; a semiconductor layer having a plurality of transition seed generation regions on the insulating layer; and a data line on the semiconductor layer and connecting the semiconductor Floor. 18 201035656 · 13. The pixel structure of claim 12, wherein the scan line or the common line has a first voltage, the data line has a second voltage, and the first voltage and the second voltage The potential difference produces a transverse electric field that causes the transition seed seeding region of the semiconductor layer to produce a transition seed. 14. The unitary structure of claim 12, wherein the semiconductor layer is hollowed out to form one or more polygonal openings, the outline of the polygon comprising a right angle, an obtuse angle, an acute angle, or an irregular contour to constitute the transition state Seed producing area. 15. The pixel structure of claim 12, wherein the outer contour of the semiconductor layer has a protruding portion to constitute the transition seed generating region. 16. The halogen structure of claim 12, wherein the semiconductor layer is hollowed out to form one or more polygonal openings, the outline of the polygon comprises a right angle, an obtuse angle or an acute angle, and the outer contour of the semiconductor layer has a convex shape Part to form the transition seed production area. 19. The substrate structure of claim 12, wherein the semiconductor layer is at least partially located directly above the scan line or the common line. 18. The structure of a liquid crystal display comprising a plurality of pixels defined by a plurality of scan lines and a plurality of data lines, each element comprising: I a scan line or a common line, located in a thin film transistor An insulating layer on the scan line or the common line; a semiconductor layer having a plurality of transition seed generation regions on the insulating layer; and a second electrode layer over the semiconductor layer and connected to the substrate The semiconductor layer 0. The halogen structure of claim 18, wherein the second electrode layer is a capacitor electrode, the halogen structure further comprises a protective layer on the capacitor electrode, and a halogen electrode is located On the protective layer, the halogen electrode is connected to the capacitor electrode through a contact window. 20. The halogen structure of claim 18, wherein the second electrode layer is a halogen electrode, the halogen structure further comprising a protective layer on the semiconducting layer 20 201035656 body layer, and the halogen electrode is located On the halogen electrode, the halogen electrode is connected to the semiconductor layer through a contact window. 21. The pixel structure of claim 18, wherein the scan line or the common line has a first voltage, the data line has a second voltage, and a potential difference between the first voltage and the second voltage is generated. A transverse electric field causes the transition seed producing region of the semiconductor layer to produce a transition seed. 22. The unitary structure of claim 18, wherein the semiconductor layer is hollowed out to form one or more polygonal openings, the outline of the polygon comprising a right angle, an obtuse angle, an acute angle, or an irregular contour to constitute the transition state Seed producing area. 23. The halogen structure of claim 18, wherein the outer contour of the semiconductor layer has a protruding portion to constitute the transition seed generating region. 24. The unitary structure of claim 18, wherein the semiconductor layer is hollowed out to form one or more polygonal openings, and the polygonal contour package 21 201035656 comprises a right angle, an obtuse angle or an acute angle, and the outer contour of the semiconductor layer has The projections are formed to constitute the transition seed generation region. 25. The bismuth junction of claim 18, wherein the semiconductor layer is at least partially located directly above the scan line or the common line. - - twenty two
TW098109533A 2009-03-24 2009-03-24 Pixel element of liquid crystal display and method for roducing the same TWI413839B (en)

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