CN108490709B - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN108490709B CN108490709B CN201810271131.1A CN201810271131A CN108490709B CN 108490709 B CN108490709 B CN 108490709B CN 201810271131 A CN201810271131 A CN 201810271131A CN 108490709 B CN108490709 B CN 108490709B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The present invention provides an array substrate, which includes: the pixel structure comprises a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are arranged in a crossed manner to define a plurality of pixel regions; the thin film transistors are arranged in the corresponding pixel regions and are respectively connected with the corresponding scanning lines and the corresponding data lines; the electrode layers are arranged between two corresponding adjacent thin film transistors, and at least part of the electrode layers and the corresponding scanning lines are overlapped and electrically insulated. The invention forms the semiconductor layer of the thin film transistor and also forms the electrode layer overlapped with the scanning line, so that the electrode layer and the scanning line form a capacitor with certain charge storage capacity, and the capacitor can store static electricity generated in the manufacturing process, thereby effectively reducing static electricity accumulation, avoiding the formation of micro short circuit between the scanning line and the semiconductor layer, improving the antistatic capacity, and further improving the yield of products and the reliability of devices.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to an array substrate and a manufacturing method thereof.
Background
With the development of the photoelectric and semiconductor technologies, the development of Flat Panel displays (Flat Panel displays) is also increased, and among many Flat Panel displays, Liquid Crystal Displays (LCDs) have become the mainstream of the market due to their excellent characteristics, such as high space utilization efficiency, low power consumption, no radiation, and low electromagnetic interference.
Currently, amorphous silicon thin film transistors (a-Si TFTs) are widely used as switching elements of LCDs, but a-Si TFT LCDs are still limited in satisfying requirements for thinness, light weight, high fineness, high brightness, high reliability, low power consumption, and the like. Low Temperature Polysilicon (LTPS) TFT LCDs have significant advantages over a-Si TFT LCDs in meeting these requirements.
In the current LTPS TFT, a gate insulating layer is provided between a scan line and an active layer (or semiconductor layer). However, since the gate insulating layer has a small thickness and a weak anti-process static electricity capability, electrostatic discharge in the subsequent process of the LTPS TFT easily causes a micro short circuit between the scan line and the active layer, thereby causing additional defects such as stress and line defects when the panel is lit, and further reducing the product yield.
Disclosure of Invention
In order to solve the technical problems in the prior art, an object of the present invention is to provide an array substrate capable of preventing a micro short circuit from being formed between a scan line and an active layer, and a method for manufacturing the same.
According to an aspect of the present invention, there is provided an array substrate, including: the pixel structure comprises a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are arranged in a crossed manner to define a plurality of pixel regions; the thin film transistors are arranged in the corresponding pixel regions and are respectively connected with the corresponding scanning lines and the corresponding data lines; and the electrode layers are arranged between two corresponding adjacent thin film transistors and at least partially overlap and are electrically insulated from the corresponding scanning lines.
Further, the electrode layer and the semiconductor layer of the thin film transistor are located on the same layer.
According to another aspect of the present invention, there is also provided an array substrate, including: a substrate; a plurality of semiconductor layers disposed on the substrate; a plurality of electrode layers disposed on the substrate, and the electrode layers are disposed between two corresponding adjacent semiconductor layers; a first insulating layer disposed on the plurality of semiconductor layers and the plurality of electrode layers; a plurality of gate electrodes and a plurality of scan lines disposed on the first insulating layer, the gate electrodes being connected to the corresponding scan lines and facing the corresponding semiconductor layers, the electrode layers being at least partially overlapped with the corresponding scan lines; a second insulating layer disposed on the plurality of gate electrodes and the plurality of scan lines; and the source electrodes and the drain electrodes penetrate through the second insulating layer and the first insulating layer to be in contact with the corresponding semiconductor layers.
According to another aspect of the present invention, there is provided a method for manufacturing an array substrate, including: simultaneously manufacturing and forming a plurality of semiconductor layers and a plurality of electrode layers on a substrate, wherein the electrode layers are arranged between two corresponding adjacent semiconductor layers; forming a first insulating layer on the plurality of semiconductor layers and the plurality of electrode layers; forming a plurality of grid electrodes and a plurality of scanning lines on the first insulating layer, wherein the grid electrodes are connected with the corresponding scanning lines and are opposite to the corresponding semiconductor layers, and the electrode layers are at least partially overlapped with the corresponding scanning lines; forming a second insulating layer on the plurality of grid electrodes and the plurality of scanning lines; and manufacturing and forming a plurality of source electrodes, a plurality of drain electrodes and a plurality of data lines on the second insulating layer, wherein the source electrodes are connected with the corresponding data lines, and the source electrodes and the drain electrodes penetrate through the second insulating layer and the first insulating layer to be in contact with the corresponding semiconductor layers.
Furthermore, the electrode layer and the semiconductor layer of the thin film transistor are both made of polysilicon.
Further, the projection of the electrode layer on the corresponding scanning line is located within the corresponding scanning line.
The invention has the beneficial effects that: the invention forms the semiconductor layer of the thin film transistor and also forms the electrode layer overlapped with the scanning line, so that the electrode layer and the scanning line form a capacitor with certain charge storage capacity, and the formed capacitor can store static electricity generated in the manufacturing process, thereby effectively reducing static accumulation, avoiding the formation of micro short circuit between the scanning line and the semiconductor layer, improving antistatic capacity, and further improving the yield of products and the reliability of devices.
Drawings
The above and other aspects, features and advantages of embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a top view of an array substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1;
fig. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
In the drawings, the thickness of layers, films, regions, and substrates are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification and drawings.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Alternatively, when an element is referred to as being "directly on" another element, there are no intervening elements present.
Fig. 1 is a top view of an array substrate according to an embodiment of the present invention. In fig. 1, the insulating layers are omitted in order to clearly show the relationship among the scanning lines, the data lines, and the semiconductor layer (i.e., the active layer), the gate electrode, the source electrode, and the drain electrode of the thin film transistor.
Referring to fig. 1, an array substrate according to an embodiment of the present invention includes: a plurality of scan lines 100, a plurality of data lines 200, a plurality of thin film transistors 300, and a plurality of electrode layers 400.
The plurality of scan lines 100 are spaced apart from and arranged in parallel with each other, and each scan line 100 extends in a row direction. The plurality of data lines 200 are spaced apart from and arranged in parallel with each other, and each data line 200 extends in a column direction. As such, the scan lines 100 and the data lines 200 are disposed to cross each other, thereby defining a plurality of pixel regions.
The tfts 300 are disposed in the corresponding pixel regions, and the tfts 300 are connected to the corresponding scan lines 100 and the corresponding data lines 200, respectively. Thus, the scan line 100 may provide a scan voltage to the thin film transistor 300, and the data line 200 may provide a data voltage to the thin film transistor 300.
Further, the gate electrode 330 of the thin film transistor 300 is connected to the corresponding scan line 100, and the source electrode 350 of the thin film transistor 300 is connected to the data line 200. In addition, the source electrode 250 of the thin film transistor 300 is also connected to the semiconductor layer (i.e., the active layer) 310, and the drain electrode 260 of the thin film transistor 300 is also connected to the semiconductor layer (i.e., the active layer) 310.
The electrode layer 400 is disposed between the two corresponding tfts 300. In the present embodiment, one electrode layer 400 is provided between every adjacent two thin film transistors 300 in all the thin film transistors 300 located on the same row. Further, the electrode layer 400 is at least partially overlapped with the corresponding scan line 100 and electrically insulated from each other. Therefore, a capacitor with certain charge storage capacity is formed between the electrode layer 400 and the corresponding scanning line 100, and the formed capacitor can store static electricity generated in the manufacturing process, so that static electricity accumulation can be effectively reduced, micro short circuit between the scanning line 100 and the semiconductor layer 310 is avoided, the antistatic capacity is effectively improved, and the yield of products and the reliability of devices are further improved.
In this embodiment, in order to facilitate the fabrication of the electrode layer 400 and not increase the manufacturing process of the array substrate, it is preferable that the electrode layer 400 and the semiconductor layer 310 are fabricated and formed in the same layer. Furthermore, the electrode layer 400 and the semiconductor layer 310 are formed simultaneously by using the same semiconductor material, such as polysilicon, in the same layer, which does not increase the manufacturing process of the array substrate and does not require additional material for forming the electrode layer 400.
In the present embodiment, in order to maximize the storage of electric charges in the formed capacitor, the projection of the electrode layer 400 on the corresponding scan line 100 is further positioned within the corresponding scan line 100.
Fig. 2 is a sectional view taken along line a-a in fig. 1. Fig. 3 is a sectional view taken along line B-B in fig. 1. Fig. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Referring to fig. 4, the method for manufacturing an array substrate according to the embodiment of the invention includes steps S410 to S450. The specific process of each step is described below with reference to fig. 4 and fig. 1 to 3.
In step S410, a plurality of semiconductor layers 310 and a plurality of electrode layers 400 are simultaneously formed on the substrate 500, and the electrode layers 400 are disposed between two corresponding adjacent semiconductor layers 310.
Further, a plurality of semiconductor layers 310 and a plurality of electrode layers 400 are simultaneously formed on the substrate 500 using polysilicon. Further, as described above, one electrode layer 400 may be provided between every adjacent two thin film transistors 300 in all the thin film transistors 300 located on the same row, but the present invention is not limited thereto.
In addition, before performing step S410, a plurality of light shielding layers (not shown) may be formed on the substrate 500 in advance. The light-shielding layers are opposite to the semiconductor layers 310 in a one-to-one correspondence manner, so as to prevent external light from directly irradiating the semiconductor layers 310. Further, after the light-shielding layer is formed, an insulating layer covering the light-shielding layer may be formed, and then the plurality of semiconductor layers 310 and the plurality of electrode layers 400 may be formed simultaneously on the insulating layer. Here, the light shielding layer may be made of, for example, a ferrous metal material, but the present invention is not particularly limited.
Next, in step S420, a first insulating layer (or gate insulating layer) 320 is formed on the plurality of semiconductor layers 310 and the plurality of electrode layers 400.
Next, in step S430, a plurality of gate electrodes 330 and a plurality of scan lines 100 are formed on the first insulating layer 320, the gate electrodes 330 are connected to the corresponding scan lines 100 and are opposite to the corresponding semiconductor layers 310, and the electrode layers 400 are at least partially overlapped with the corresponding scan lines 100.
Further, as described above, in order to allow the formed capacitor to store electric charges to the maximum, the projection of the electrode layer 400 on the corresponding scan line 100 is located within the corresponding scan line 100.
Next, in step S440, a second insulating layer 340 is formed on the plurality of gate electrodes 330 and the plurality of scan lines 100.
Finally, in step S450, a plurality of source electrodes 350, a plurality of drain electrodes 360 and a plurality of data lines 200 are formed on the second insulating layer 340, the source electrodes 350 are connected to the corresponding data lines 200, and the source electrodes 350 and the drain electrodes 360 penetrate the second insulating layer 340 and the first insulating layer 320 to contact the corresponding semiconductor layers 310.
In addition, each of the insulating layers may be made of an insulating material (such as SiN)xOr SiOx) The single-layer structure formed may be a stacked-layer structure formed of at least two kinds of insulating materials, such as SiNx/SiOxA stacked structure.
In summary, according to the array substrate and the manufacturing method thereof of the embodiment of the invention, the electrode layer overlapped with the scan line is formed while the semiconductor layer of the thin film transistor is formed, so that the electrode layer and the scan line form the capacitor with certain charge storage capability, and the formed capacitor can store static electricity generated in the manufacturing process, thereby effectively reducing static electricity accumulation, avoiding a micro short circuit formed between the scan line and the semiconductor layer, improving antistatic capability, and further improving yield of products and reliability of devices.
While the invention has been shown and described with reference to certain embodiments, those skilled in the art will understand that: various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (6)
1. An array substrate, comprising:
a substrate;
a plurality of semiconductor layers disposed on the substrate;
a plurality of electrode layers disposed on the substrate, and the electrode layers are disposed between two corresponding adjacent semiconductor layers;
a first insulating layer disposed on the plurality of semiconductor layers and the plurality of electrode layers;
a plurality of gate electrodes and a plurality of scan lines disposed on the first insulating layer, the gate electrodes being connected to the corresponding scan lines and facing the corresponding semiconductor layers, the electrode layers being at least partially overlapped with the corresponding scan lines;
a second insulating layer disposed on the plurality of gate electrodes and the plurality of scan lines;
and the source electrodes and the drain electrodes penetrate through the second insulating layer and the first insulating layer to be in contact with the corresponding semiconductor layers.
2. The array substrate of claim 1, wherein the projection of the electrode layer on the corresponding scan line is located within the corresponding scan line.
3. The array substrate of claim 1, wherein the electrode layer and the semiconductor layer of the thin film transistor are made of polysilicon.
4. A manufacturing method of an array substrate is characterized by comprising the following steps:
simultaneously manufacturing and forming a plurality of semiconductor layers and a plurality of electrode layers on a substrate, wherein the electrode layers are arranged between two corresponding adjacent semiconductor layers;
forming a first insulating layer on the plurality of semiconductor layers and the plurality of electrode layers;
forming a plurality of grid electrodes and a plurality of scanning lines on the first insulating layer, wherein the grid electrodes are connected with the corresponding scanning lines and are opposite to the corresponding semiconductor layers, and the electrode layers are at least partially overlapped with the corresponding scanning lines;
forming a second insulating layer on the plurality of grid electrodes and the plurality of scanning lines;
and manufacturing and forming a plurality of source electrodes, a plurality of drain electrodes and a plurality of data lines on the second insulating layer, wherein the source electrodes are connected with the corresponding data lines, and the source electrodes and the drain electrodes penetrate through the second insulating layer and the first insulating layer to be in contact with the corresponding semiconductor layers.
5. The method for manufacturing the array substrate according to claim 4, wherein the projection of the electrode layer on the corresponding scan line is located within the corresponding scan line.
6. The method for manufacturing the array substrate according to claim 4, wherein a plurality of semiconductor layers and a plurality of electrode layers are simultaneously formed on the substrate by using polysilicon.
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| CN201810271131.1A CN108490709B (en) | 2018-03-29 | 2018-03-29 | Array substrate and manufacturing method thereof |
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| CN201810271131.1A CN108490709B (en) | 2018-03-29 | 2018-03-29 | Array substrate and manufacturing method thereof |
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| CN108490709B true CN108490709B (en) | 2021-06-01 |
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| CN109283763B (en) * | 2018-11-16 | 2021-10-26 | 信利半导体有限公司 | Substrate structure, display panel and panel manufacturing method |
| CN109727999B (en) * | 2019-01-02 | 2020-07-03 | 合肥京东方显示技术有限公司 | Preparation method of array substrate, array substrate and display device |
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| CN101030588A (en) * | 2007-04-24 | 2007-09-05 | 友达光电股份有限公司 | Array base plate and its production |
| CN101136416A (en) * | 2007-10-12 | 2008-03-05 | 友达光电股份有限公司 | Pixel array structure and manufacturing method therefor |
| CN101207140A (en) * | 2007-04-24 | 2008-06-25 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| CN104699353A (en) * | 2015-04-01 | 2015-06-10 | 上海天马微电子有限公司 | Array substrate, driving method, display panel and display device |
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| CN1244012C (en) * | 2002-08-02 | 2006-03-01 | Nec液晶技术株式会社 | Liquid crystal device and manufacture thereof |
| JP4381063B2 (en) * | 2003-08-18 | 2009-12-09 | 東芝モバイルディスプレイ株式会社 | Array substrate and flat display device |
| KR100654569B1 (en) * | 2004-12-30 | 2006-12-05 | 엘지.필립스 엘시디 주식회사 | TFT array substrate and the fabrication method thereof |
| JP2007310334A (en) * | 2006-05-19 | 2007-11-29 | Mikuni Denshi Kk | Manufacturing method of liquid crystal display device using half-tone exposure method |
| KR101925540B1 (en) * | 2011-08-04 | 2019-02-28 | 삼성디스플레이 주식회사 | Thin-film transistor array substrate, organic light emitting display device comprising the same and manufacturing method of the same |
| CN205374925U (en) * | 2015-12-24 | 2016-07-06 | 上海中航光电子有限公司 | Prevent static array substrate and liquid crystal disply device |
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|---|---|---|---|---|
| CN101030588A (en) * | 2007-04-24 | 2007-09-05 | 友达光电股份有限公司 | Array base plate and its production |
| CN101207140A (en) * | 2007-04-24 | 2008-06-25 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| CN101136416A (en) * | 2007-10-12 | 2008-03-05 | 友达光电股份有限公司 | Pixel array structure and manufacturing method therefor |
| CN104699353A (en) * | 2015-04-01 | 2015-06-10 | 上海天马微电子有限公司 | Array substrate, driving method, display panel and display device |
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