CN114242736A - Display panel and display device - Google Patents
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- CN114242736A CN114242736A CN202111552423.0A CN202111552423A CN114242736A CN 114242736 A CN114242736 A CN 114242736A CN 202111552423 A CN202111552423 A CN 202111552423A CN 114242736 A CN114242736 A CN 114242736A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 15
- 229910052750 molybdenum Inorganic materials 0.000 claims description 15
- 239000011733 molybdenum Substances 0.000 claims description 15
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The application provides a display panel and a display device, the display panel is provided with a display area and a non-display area, the display panel comprises a first thin film transistor positioned in the display area, a second thin film transistor positioned in the non-display area and a first shielding layer, the first thin film transistor is an oxide transistor, the first thin film transistor comprises a first grid electrode and a first active layer, the second thin film transistor is a silicon transistor, the second thin film transistor comprises a second grid electrode and a second active layer, the first shielding layer is positioned on one side of the second grid electrode far away from the second active layer, the projections of the first shielding layer and the second grid electrode in the direction vertical to the surface of the second active layer are provided with an overlapping area, the first shielding layer and the first active layer are arranged on the same layer, the first shielding layer is connected with a fixed potential, in the embodiment of the application, the first shielding layer can be provided for the silicon transistor in the non-display area, and the electrostatic shielding effect can be achieved by the first shielding layer, the antistatic capacity of the non-display area is improved, and the display effect of the display panel is improved.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a display panel and a display device.
Background
In a display panel (panel), a display region in which a display unit may be disposed and a non-display region in which a driving circuit may be disposed may be included, and generally, the non-display region is disposed at the periphery of the display region. The Display region and the non-Display region may be provided with Thin Film Transistors (TFTs), and in a Display panel formed using a Hybrid TFT Display (HTD) technology, a variety of different transistors may be provided, and specifically, the Display panel may include an oxide Transistor and a silicon Transistor, for example, the Display region may be provided with an oxide Transistor, and the non-Display region may be provided with a silicon Transistor. The active layer in the oxide transistor may be an oxide, such as Indium Gallium Zinc Oxide (IGZO), and the active layer in the Silicon transistor may be Silicon, such as Low Temperature Polysilicon (LTPS).
However, the conventional display panel has a weak antistatic capability, so that static electricity is accumulated in the display panel to affect the characteristics of the TFT, and in a serious case, the display area has horizontal stripes.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a display panel and a display device, which improve the antistatic capability of the non-display area and improve the display effect of the display panel.
The embodiment of the application provides a display panel, has display area and non-display area, display panel includes:
a first thin film transistor located in the display region; the first thin film transistor is an oxide transistor and comprises a first grid electrode and a first active layer;
the second thin film transistor and the first shielding layer are positioned in the non-display area; the second thin film transistor is a silicon transistor and comprises a second grid electrode and a second active layer; the first shielding layer is located on one side, far away from the second active layer, of the second grid electrode, the projections of the first shielding layer and the second grid electrode in the direction perpendicular to the surface of the second active layer are provided with an overlapping region, the first shielding layer and the first active layer are arranged on the same layer, and the first shielding layer is connected with a fixed potential.
The embodiment of the application provides a display device, which comprises the display panel.
The embodiment of the application provides a display panel and a display device, the display panel is provided with a display area and a non-display area, the display panel comprises a first thin film transistor positioned in the display area, a second thin film transistor positioned in the non-display area and a first shielding layer, the first thin film transistor is an oxide transistor, the first thin film transistor comprises a first grid electrode and a first active layer, the second thin film transistor is a silicon transistor, the second thin film transistor comprises a second grid electrode and a second active layer, the first shielding layer is positioned on one side of the second grid electrode, which is far away from the second active layer, the projection of the first shielding layer and the second grid electrode in the direction vertical to the surface of the second active layer is provided with an overlapping area, the first shielding layer and the first active layer are arranged in the same layer, the first shielding layer is connected with a fixed potential, namely, in the embodiment of the application, the first shielding layer can be provided for the silicon transistor in the non-display area, the first shielding layer can play a role in electrostatic shielding, so that the antistatic capability of the non-display area is improved, and the display effect of the display panel is improved. In addition, the first shielding layer and the first active layer can be arranged on the same layer, and the forming step of the first shielding layer and film vacancy do not need to be designed on other layers, so that the steps of the manufacturing process are saved, the process is simplified, and the cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a display panel;
FIG. 2 is a schematic diagram of a display device according to the prior art;
FIG. 3 is a schematic top view of a display panel according to an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view along direction AA' of the display panel in FIG. 3;
FIG. 5 is another schematic cross-sectional view along direction AA' of the display panel in FIG. 3;
FIG. 6 is a schematic cross-sectional view illustrating an array substrate in a display panel according to an embodiment of the present disclosure;
FIG. 7 is a schematic cross-sectional view of an array substrate in another display panel according to an embodiment of the present application;
FIG. 8 is a schematic top view of an array substrate in a display panel according to an embodiment of the present disclosure;
FIGS. 9-14 are schematic cross-sectional views of array substrates in various display panels according to embodiments of the present disclosure;
FIG. 15 is a schematic top view of an array substrate in another display panel of the present application;
FIG. 16 is a schematic top view of an array substrate in another display panel of the present application;
FIGS. 17-20 are schematic cross-sectional views of array substrates in various display panels according to embodiments of the present disclosure;
fig. 21 is a schematic view of a display device according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the display panel, a display region in which a display unit may be disposed and a non-display region in which a driving circuit may be disposed may be included, and generally, the non-display region is disposed at a periphery of the display region. The display region and the non-display region may both be provided with TFTs, and in a display panel formed by using the HTD technology, a plurality of different transistors may be provided, specifically, the display panel may include an oxide transistor and a silicon transistor, for example, the display region may be provided with an oxide transistor, the non-display region may be provided with a silicon transistor, as shown in fig. 1, which is a schematic diagram of a display panel at present, the display region AA is provided with an oxide transistor, the oxide transistor includes an oxide layer 151, a gate electrode 161, and a cross-sectional contact structure 280, the non-display region NA is provided with a silicon transistor, the silicon transistor includes a silicon layer 221 and a gate electrode 231, and a contact structure 270, the oxide transistor and the silicon transistor are provided in a dielectric layer 240, and the dielectric layer 240 is provided on the substrate 200.
However, the conventional display panel has a weak antistatic capability, so that static electricity is accumulated in the display panel to affect the characteristics of the TFT, and in a serious case, the display area has horizontal stripes, as shown in fig. 2, which is a display diagram of a conventional display device, and the display screen in the gray frame has horizontal stripes. The inventor found in an Electrostatic Discharge (ESD) test that static electricity outside the display panel is conducted to the inside of the shield through the periphery of the display panel, so that static charge accumulation affects TFT characteristics, while the current display panel has no path for dissipating static electricity in the non-display region, resulting in static electricity accumulation.
In view of this, embodiments of the present application provide a display panel and a display device, where the display panel has a display area and a non-display area, the display panel includes a first thin film transistor located in the display area, and a second thin film transistor and a first shielding layer located in the non-display area, the first thin film transistor is an oxide transistor, the first thin film transistor includes a first gate electrode and a first active layer, the second thin film transistor is a silicon transistor, the second thin film transistor includes a second gate electrode and a second active layer, the first shielding layer is located on a side of the second gate electrode away from the second active layer, a projection of the first shielding layer and the second gate electrode in a direction perpendicular to a surface of the second active layer has an overlapping region, the first shielding layer is disposed on the same layer as the first active layer, and the first shielding layer is connected to a fixed potential, that is, in this embodiment, the first shielding layer may be provided for the silicon transistor in the non-display area, the first shielding layer can play a role in electrostatic shielding, so that the antistatic capability of the non-display area is improved, and the display effect of the display panel is improved. In addition, the first shielding layer and the first active layer can be arranged on the same layer, and the forming step of the first shielding layer and film vacancy do not need to be designed on other layers, so that the steps of the manufacturing process are saved, the process is simplified, and the cost is reduced.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
The embodiment of the present application provides a display panel, refer to fig. 3, which is a schematic top view diagram of the display panel in the embodiment of the present application, the display panel may have a display area AA and a non-display area NA, the display area AA has a display function, and is used for setting a display unit to display a content to be displayed, the non-display area NA is not used for displaying, and may have a circuit unit and a routing structure, the circuit unit may include a driving circuit, and is used for controlling the display unit of the display area AA to display the content to be displayed, and the driving circuit may include a VSR circuit, for example. Generally, the non-display area NA is disposed at the periphery of the display area AA, and thus the static electricity dissipation path of the non-display area NA is directly related to the static electricity accumulation of the entire display panel.
In the display area AA, the display unit may include a liquid crystal display unit or an Organic light-emitting diode (LED), and the display unit may be connected to a thin film transistor for controlling power supply of the display unit, thereby controlling display of the display unit. In the non-display area NA, the driving circuit may include a thin film transistor for connection with the display unit to control power supply of the display unit to control display of the display unit.
When the display unit includes a liquid crystal display unit, referring to fig. 4, which is a schematic cross-sectional view of the display panel in fig. 3 along the AA' direction, the display panel may include an array substrate 10, a color filter substrate 30, and a liquid crystal layer 20 between the array substrate 10 and the color filter substrate 30, where the array substrate 10 includes a substrate and a thin film transistor array, the color filter substrate 30 includes a substrate and a filter film array, and the thin film transistor array is used for driving the liquid crystal layer 20 to implement display of related content; when the display unit includes an organic light emitting diode, referring to fig. 5, which is another schematic cross-sectional view along direction AA' of the display panel in fig. 3, the display panel may include an array substrate 40 and an organic light emitting diode 50 on the array substrate 40, where the array substrate 40 includes a substrate and a thin film transistor array, and the thin film transistor array is used for driving the organic light emitting diode 50 to implement display of related content.
In a display panel formed by using the HTD technology, a plurality of different transistors may be disposed in an array substrate, so as to exert respective advantages of a plurality of devices, and fig. 6 is a schematic cross-sectional view of the array substrate in the display panel according to an embodiment of the present application. Specifically, the display panel may include an oxide transistor and a silicon transistor, the material of an active layer in the oxide transistor may be an oxide, for example, IGZO, and the active layer in the silicon transistor may be silicon, for example, LTPS. The display panel based on the LTPS TFT has limited high resolution, reaction speed block, high brightness, high aperture ratio and the like, so that the display panel becomes a hot choice for realizing energy conservation, refinement and large-scale production, but the LTPS TFT has large off-state current (namely leakage current), and the LTPD material with high mobility is difficult to prepare at low temperature and large area; IGZO's carrier mobility is big, can beat and improve TFT to the charge-discharge rate of pixel electrode, improves the response speed of pixel, realizes faster refresh rate, and faster response has also improved the line scanning rate of pixel greatly simultaneously, makes high resolution become possible in TFT-LCD, and IGZO display has higher energy efficiency level, and efficiency is higher.
Specifically, an oxide transistor may be disposed in the display area AA, which is referred to as a first thin film transistor, the first thin film transistor may include a first gate electrode 161 and a first active layer 151, a first gate dielectric layer 150 is disposed between the first gate electrode 161 and the first active layer 151, a portion of the first active layer 151 located at a projection position of the first gate electrode 161 on the first active layer 151 is used as a first channel region, first source and drain regions are disposed at two sides of the first channel region, and the first source and drain regions may include a first source region located at one side of the first channel region and a first drain region located at the other side of the first channel region. The material of the first active layer 151 may be IGZO, the material of the first gate dielectric layer 150 may be silicon oxide, and the material of the first gate electrode 161 may be copper or aluminum. The first active layer 151 may be obtained through a deposition process and an etching process. The first source drain region may be subjected to a conductive process, or may be additionally provided with a conductor structure connected to the first active layer 151. The electric conduction treatment of the IGZO may be doping of the IGZO, such as ion implantation of silicon IGZO, or the electric conduction treatment of the IGZO may be irradiation of the IGZO with UV light or light of a near UV band.
The first thin film transistor may further include a first auxiliary gate electrode 142 and a second auxiliary gate electrode 133, the first auxiliary gate electrode 142 and the second auxiliary gate electrode 133 being located at the same side of the first active layer 151, and the first gate electrode 161 being located at the other side of the first active layer 151, the first auxiliary gate electrode 142 and the second auxiliary gate electrode 133 being used to connect a control signal, thereby controlling the first channel region in the first active layer 151. The first and second auxiliary gate electrodes 142 and 133 may be separated by a first spacer 130, and the first auxiliary gate electrode 142 and the first active layer 151 may be separated by a second spacer 140. The first gate 161 may be covered by the capping layer 160.
Specifically, a silicon transistor may be disposed in the non-display area NA and is referred to as a second thin film transistor, the second thin film transistor may include a second gate electrode 131 and a second active layer 121, a second gate dielectric layer 120 is disposed between the second gate electrode 131 and the second active layer 121, a portion of the second active layer 121 located at a projection position of the second gate electrode 131 on the first active layer 151 is used as a second channel region, second source and drain regions are disposed at two sides of the second channel region, and the second source and drain regions may include a second source region located at one side of the second channel region and a second drain region located at the other side of the second channel region. The material of the second active layer 121 may be polysilicon, the material of the second gate dielectric layer 120 may be silicon oxide, and the material of the second gate electrode 131 may be copper or aluminum. The second active layer 121 may be obtained through a deposition process and an etching process. The second source drain region may be subjected to a conductive treatment, or may be additionally provided with a conductor structure connected to the second active layer 121. The conductivity treatment of the silicon may be doping of the silicon, for example ion implantation of the silicon layer.
The second thin film transistor may further include a third auxiliary gate electrode 141, and the fourth auxiliary gate electrode 141 and the second gate electrode 131 may be located at the same side of the second active layer 121, and the second auxiliary gate electrode 141 is used for connecting a control signal, thereby controlling the second channel region in the second active layer 121. The second gate electrode 131 and the second auxiliary gate electrode 133 may be formed at the same layer, and the third auxiliary gate electrode 141 and the first auxiliary gate electrode 142 may be formed at the same layer, so that the second gate electrode 131 and the second auxiliary gate electrode 133 may be separated by the first spacer 130.
The display panel may include a substrate 100, and the first thin film transistor and the second thin film transistor may be disposed at one side of the substrate 100, and for convenience of description, a direction from the substrate 100 to the first thin film transistor may be referred to as "up" and a direction from the first thin film transistor to the substrate 100 as "down", but such notation is for convenience regardless of a direction of gravity.
In order to facilitate the extraction of the first and second gate electrodes 161 and 131, the first gate electrode 161 may be disposed above the first active layer 151, the first gate electrode 161 may be extracted using a first gate contact structure, the second gate electrode 131 may be disposed above the second active layer 121, and the second gate electrode 131 may be extracted using a second gate contact structure. A buffer layer 110 may be disposed between the substrate 100 and the second active layer 121 to isolate the substrate 100 from the second active layer 121 while improving the film quality of the second active layer 121.
In order to shield the second thin film transistor electrostatically, a first shielding layer 152 may be disposed in the non-display area NA, as shown in fig. 6, the first shielding layer 152 may be located on a side of the second gate electrode 131 away from the second active layer 121, projections of the first shielding layer 152 and the second gate electrode 131 in a direction perpendicular to the surface of the second active layer 121 have an overlapping region, the first shielding layer 152 may be connected to a fixed potential, for example, the first shielding layer 152 may be grounded. Thus, the first shielding layer 152 can prevent static electricity from entering the second gate 131 from above the second gate 131 and from below the second gate 131, so as to achieve an electrostatic shielding effect on the second thin film transistor. When the second thin film transistor includes the third auxiliary gate electrode 141, the first shielding layer 152 is positioned at a side of the third auxiliary gate electrode 141 facing away from the second active layer 121.
The first shielding layer 152 and the first active layer 151 may be disposed on the same layer, so that the first shielding layer 152 and the first active layer 151 may be formed simultaneously or sequentially, and a forming step of the first shielding layer 152 and a film vacancy need not to be designed in other layers, thereby simplifying a manufacturing process. When the first active layer 151 is an IGZO layer, the material of the first shielding layer 152 may also be IGZO, and the IGZO serving as the first shielding layer 152 may be subjected to a conductive treatment, so that the first active layer 151 and the first shielding layer 152 may be formed simultaneously by using the same process, thereby further simplifying the process; of course, when the first active layer 151 is an IGZO layer, the material of the first shielding layer 152 may also be conductive treated silicon, or may be a metal layer, such as molybdenum (Mo), etc.
The second thin film transistor further includes a source and drain, and the source and drain of the second thin film transistor is connected to the second active layer 121 through the first conductor structure 170, specifically, the source and drain of the second thin film transistor includes a first source and a first drain, the first source is used for being connected to the second source region to provide a source potential for the second source region, and the first drain is used for being connected to the second drain region to provide a drain potential for the second drain region. The first shielding layer 152 and the first conductor structure 170 are separated by an isolation layer, which may be the first gate dielectric layer 150, and the first gate dielectric layer 150 fills the gap between the first shielding layer 152 and the first conductor structure 170 to avoid electrical connection therebetween.
The first conductor structure 170 of the second thin film transistor includes a first sub-structure 171 and a second sub-structure 172 in a direction perpendicular to the surface of the second active layer 121, a portion connected to the second active layer 121 is used as the first sub-structure 171, and a portion connected to the source and drain is used as the second sub-structure 172, and referring to fig. 7, a schematic cross-sectional view of an array substrate in another display panel provided in this embodiment of the present application is shown. The first substructure 171 is obtained by etching a first part of the dielectric layer covering the second active layer 121 to obtain a first through hole and filling the first through hole with a conductor material, the second substructure 172 is obtained by etching a second part of the dielectric layer covering the first part of the dielectric layer to obtain a second through hole and filling the second through hole with a conductor material, and the first through hole and the second through hole are arranged oppositely, so that compared with the one-side etching of the dielectric layer on the second active layer 121, the first through hole and the second through hole have smaller etching depth, the process difficulty is reduced, and the source-drain contact reliability is improved.
In the embodiment of the present application, the first pad layer 173 is disposed between the first substructure 171 and the second substructure 172, the material of the first pad layer 173 is IGZO, and the first pad layer 173 is subjected to the electrical conduction treatment, and the first pad layer 173 and the first shielding layer 152 are located in the same layer, so that the first pad layer 173 and the first active layer 151 are located in the same layer, and thus, the first pad layer 173 and the first active layer 151 can be simultaneously formed by using the same process, which simplifies the process. In addition, the material of the first substructure 171 may also be IGZO, and the first substructure 171 is subjected to a conductive treatment, so that the first substructure 171 and the first pad layer 173 may be formed by the same process, further simplifying the process.
In this embodiment, the non-display area NA may include a plurality of second thin film transistors having a plurality of second gate electrodes 131, the plurality of second gate electrodes 131 may be parallel to each other, and then at least one second gate electrode 131 may be correspondingly disposed with the first shielding layer 152. Specifically, the first shielding layer 152 may include a plurality of first portions 1521 having an extending direction consistent with the extending direction of the plurality of second gate electrodes 131, and a second portion 1522 connecting the plurality of first portions 1521, as shown in fig. 8, which is a schematic top view of the array substrate in the display panel according to the embodiment of the present application, wherein a projection of the first portion 1521 on the surface of the second active layer 121 and a projection of the second gate electrode 131 on the surface of the second active layer 121 have an overlapping region, so that the plurality of first portions 1521 may be utilized to provide an electrostatic shielding effect for the plurality of second thin film transistors, and the second portion 1522 is connected to the plurality of first portions 1521, so that the first portions 1521 are connected to a fixed potential.
In the embodiment of the application, a second shielding layer 101/111 may be further disposed in the non-display area NA, the second shielding layer 101/111 is located on a side of the second active layer 121 away from the second gate electrode 131, a projection of the second shielding layer 101/111 and the second gate electrode 131 in a direction perpendicular to the surface of the second active layer 121 has an overlapping region, the second shielding layer 101/111 may be connected to a fixed potential, for example, the second shielding layer 101/111 may be grounded. Thus, the second shielding layer 101/111 can prevent static electricity from entering the second active layer 121 from below the second active layer 121 and from above the second active layer 121, thereby achieving the electrostatic shielding effect on the second thin film transistor.
The second shielding layer may be a single layer or a plurality of layers, and may include a metal layer and/or a conductively treated semiconductor layer, the metal layer may be, for example, a molybdenum layer 111, and the semiconductor layer may be a polysilicon layer 101 and/or an IGZO layer.
In the embodiment of the present application, the polysilicon layer 101 may be disposed in the substrate 100, and a schematic cross-sectional view of an array substrate in another display panel provided in the embodiment of the present application is shown in fig. 9. Specifically, the substrate 100 may include a first PI layer, a first isolation layer, and a second PI layer stacked in sequence, the first PI layer is located on a side of the second PI layer away from the first thin film transistor and the second thin film transistor, and when the second shielding layer is the polysilicon layer 101 subjected to the conductive processing, the second shielding layer may be disposed between the first isolation layer and the second PI layer in the non-display area NA, that is, the substrate may include the first PI layer, the first isolation layer, the second shielding layer, and the second PI layer from bottom to top in sequence. The amorphous silicon layer of the non-display area NA may extend from the non-display area NA to the display area AA, and the portion of the amorphous silicon layer not subjected to the conductive treatment in the display area AA serves as a shielding impurity layer in the substrate 100.
In the embodiment of the present application, the molybdenum layer 111 may be disposed between the substrate 100 and the second active layer 121, and a schematic cross-sectional view of an array substrate in another display panel provided in the embodiment of the present application is shown in fig. 10. A buffer layer 110 is disposed between the substrate 100 and the second thin film transistor, and when the second shielding layer is a molybdenum layer 111, the second shielding layer may be disposed in the buffer layer 110. The buffer layer 110 may extend from the non-display area NA to the display area AA so as to be disposed between the substrate 100 and the first thin film transistor, and the molybdenum layer 111 of the non-display area NA may extend from the non-display area NA to the display area AA, and a portion of the molybdenum layer 111 located in the display area AA serves as a light blocking layer between the first thin film transistor and the substrate 100.
When the second shielding layer includes the polysilicon layer 101 and the molybdenum layer 111 that are subjected to the conductive treatment, referring to fig. 11, which is a schematic cross-sectional view of an array substrate in another display panel provided in an embodiment of the present application, the polysilicon layer 101 may be disposed in the substrate 100 in the non-display area NA, and the molybdenum layer 111 may be disposed in the buffer layer 110.
In this embodiment, a third shielding layer 153 may be further disposed in the non-display area NA, and referring to fig. 12, for a schematic cross-sectional view of the array substrate in another display panel provided in this embodiment, the third shielding layer 153 may be disposed on a side of the non-display area NA away from the display area AA, the third shielding layer 153 may be disposed perpendicular to the second active layer 121, and the third shielding layer 153 is connected to a fixed potential, for example, the third shielding layer 153 may be grounded. Thus, the third shielding layer 153 can prevent static electricity from entering the non-display area NA from the periphery of the non-display area NA and further entering the display area AA, thereby implementing an electrostatic shielding effect on the second thin film transistor. The third shield layer 153 may connect the first shield layer 152 and the second shield layer 101/111. When the third shield layer 153 is not provided, the first shield layer 152 and the second shield layer 101/111 may be connected by a via.
In summary, the first shielding layer 152 may be disposed above the second gate electrode 131, the second shielding layer 101/111 may be disposed below the second active layer 121, and the third shielding layer 153 may be disposed on a side of the second thin film transistor departing from the display area AA, so as to provide an electrostatic shielding effect for the second thin film transistor, improve the anti-static capability of the non-display area NA, and improve the overall anti-static capability of the display panel.
In addition, in the embodiment of the application, a shielding layer may be further disposed in the display area AA, and the shielding layer may be disposed on a side of the display area AA close to the non-display area NA, so as to prevent static electricity of the non-display area NA from moving into the display area AA, and improve antistatic capability of the display area AA.
In this embodiment, a third thin film transistor may be disposed on a side of the display area AA close to the non-display area NA, and referring to fig. 13, for a schematic cross-sectional view of an array substrate in another display panel provided in this embodiment of the present invention, the third thin film transistor may be a silicon transistor, the third thin film transistor may include a third gate electrode 132 and a third active layer 122, a third gate dielectric layer is disposed between the third gate electrode 132 and the third active layer 122, a portion of the third active layer 122 located at a projection position of the third gate electrode 132 on the third active layer 122 is a third channel region, the third channel region is flanked by third source drain regions, and the third source drain region may include a third source region located on one side of the third channel region and a third drain region located on the other side of the third channel region. The material of the third active layer 122 may be polysilicon, the material of the third gate dielectric layer may be silicon oxide, and the material of the third gate electrode 132 may be copper or aluminum. The third active layer 122 may be obtained through a deposition process and an etching process. The third source/drain region may be subjected to a conductive process, or may be additionally provided with a conductor structure connected to the third active layer 122.
The third gate electrode 132 may be positioned above the third active layer 122, and the third gate electrode 132 may be drawn using a third gate contact structure. The third gate electrode 132 and the second gate electrode 131 may be disposed at the same layer, and may have the same material, and the second active layer 121 and the third active layer 122 may be disposed at the same layer, and may have the same material, that is, the second active layer 121 and the third active layer 122 may be both polysilicon, so that the second thin film transistor and the third thin film transistor may be formed using the same process, and may be formed at the same time, which simplifies the process.
A fourth shielding layer 154 may be further disposed on a side of the display area AA close to the non-display area NA, the fourth shielding layer 154 may be disposed on a side of the third gate electrode 132 away from the third active layer 122, a projection of the fourth shielding layer 154 and the third gate electrode 132 in a direction perpendicular to the surface of the third active layer 122 has an overlapping region, the fourth shielding layer 154 may be connected to a fixed potential, for example, the fourth shielding layer 154 may be grounded. Thus, the fourth shielding layer 154 can prevent static electricity from entering the third gate 132 from above the third gate 132 and from below the third gate 132, so as to achieve an electrostatic shielding effect on the third thin film transistor.
The fourth shielding layer 154 and the first active layer 151 may be disposed on the same layer, so that the fourth shielding layer 154 and the first active layer 151 may be formed simultaneously or sequentially, and a forming step of the fourth shielding layer 154 and a film vacancy need not to be designed in other layers, thereby simplifying a manufacturing process. The fourth shielding layer 154 and the first active layer 151 may be made of the same material, and when the first active layer 151 is an IGZO layer, the fourth shielding layer 154 may also be made of IGZO, and the IGZO serving as the fourth shielding layer 154 may be subjected to a conductive treatment, so that the first active layer 151 and the first shielding layer 152 may be formed simultaneously by using the same process, thereby further simplifying the process; of course, when the first active layer 151 is an IGZO layer, the material of the fourth shielding layer 154 may also be conductively treated silicon, or may be a metal layer, such as a molybdenum layer.
Similar to the second thin film transistor, the third thin film transistor may include a source and a drain, and the source and the drain of the third thin film transistor are connected to the third active layer 122 through the second conductor structure 190, specifically, the source and the drain of the third thin film transistor include a second source and a second drain, the second source is used for being connected to the third source region to provide a potential for the third source region, and the second drain is used for being connected to the third drain region to provide a drain potential for the second drain region. The fourth shielding layer 154 and the second conductor structure 190 are separated by an isolation layer, which may be the first gate dielectric layer 150, and the first gate dielectric layer 150 fills the gap between the fourth shielding layer 154 and the second conductor structure 190 to avoid electrical connection therebetween.
The second conductor structure 190 in the third thin film transistor includes a third sub-structure 191 and a fourth sub-structure 192 in a direction of disposing the surface of the third active layer 122, and as shown in fig. 14, for a schematic cross-sectional view of the array substrate in another display panel provided in this embodiment of the application, a portion connected to the third active layer 122 is used as the third sub-structure 191, and a portion connected to the source and drain is used as the fourth sub-structure 192, which is beneficial to reducing the etching depth.
A second pad layer 193 may be disposed between the third and fourth sub-structures 191 and 192, the material of the second pad layer 193 may be IGZO, and the second pad layer 193 is subjected to a conductive treatment, and the second pad layer 193 and the fourth shield layer 154 are located at the same layer, so that the second pad layer 193 and the first active layer 151 are located at the same layer, and thus may be formed using the same process, which simplifies the process. In addition, the material of the third substructure 191 may also be IGZO, and the third substructure 191 is subjected to a conductive treatment, so that the third substructure 191 and the second pad layer 193 may be formed using the same process, further simplifying the process. Of course, the second pad layer 193 in the third thin film transistor and the first pad layer 173 in the second thin film transistor may be simultaneously formed.
In this embodiment, the display area AA may include a plurality of third thin film transistors having a plurality of third gates 132, the plurality of third gates 132 may be disposed in parallel, and at least one third gate 132 may be disposed with the fourth shielding layer 154. Specifically, the fourth shielding layer 154 may include a plurality of third portions 1541 extending in a direction consistent with the extending direction of the plurality of third gates 132, and a fourth portion 1542 connecting the plurality of third portions 1541, as shown in fig. 15, which is a schematic top view of the array substrate in another display panel provided in the embodiments of the present application, wherein a projection of the third portion 1541 on the surface of the third active layer 122 and a projection of the third gate 132 on the surface of the third active layer 122 have an overlapping region, so that the plurality of third portions 1541 may be utilized to provide an electrostatic shielding effect for the plurality of third thin film transistors, and the fourth portion 1542 connects the plurality of third portions 1541, so that the third portions 1541 are connected to a fixed potential.
In the embodiment of the present application, the third thin film transistor includes a switch type transistor and a driving type transistor, and referring to fig. 16, a schematic plan view of the array substrate in the display panel provided in the embodiment of the present application is shown, wherein an area of the third gate 132-1 in the switch type transistor is smaller than an area of the third gate 132-2 in the driving type transistor, and in order to achieve a good shielding effect without affecting the arrangement of other components in the device, an area of a third portion 1541-1 of the side of the third gate 132-1 in the switch type transistor facing away from the third active layer 122 may be set smaller than an area of a third portion 1541-2 of the side of the third gate 132-2 in the driving type transistor facing away from the third active layer 122.
In the embodiment of the present application, a fifth shielding layer 101/102 may be further disposed on a side of the display area AA close to the non-display area NA, the fifth shielding layer 101/102 is located on a side of the third active layer 122 away from the third gate electrode 132, a projection of the fifth shielding layer 101/102 and the third gate electrode 132 in a direction perpendicular to the surface of the third active layer 122 has an overlapping region, the fifth shielding layer 101/102 is connected to a fixed potential, for example, the fifth shielding layer 101/102 may be grounded. Thus, the fifth shielding layer 101/102 can prevent static electricity from entering the third active layer 122 from below the third active layer 122 and from above the third active layer 122, so as to achieve the electrostatic shielding effect on the third thin film transistor.
The fifth shielding layer may be a single layer or a plurality of layers, and the fifth shielding layer may include a metal layer and/or a conductive semiconductor layer, the metal layer may be, for example, a molybdenum layer 112, and the semiconductor layer may be a polysilicon layer 102 and/or an IGZO layer. The fifth shielding layer may be disposed on the same layer as the second shielding layer, for example, when the fifth shielding layer is the polysilicon layer 102 subjected to the conductive treatment, the fifth shielding layer may be disposed in the substrate 100, which is shown in fig. 17 as a schematic cross-sectional view of an array substrate in another display panel provided by an embodiment of the present application; when the fifth shielding layer is a molybdenum layer 112, the fifth shielding layer may be disposed in the buffer layer 110, as shown in fig. 18, which is a schematic cross-sectional view of an array substrate in another display panel provided in an embodiment of the present invention; when the fifth shielding layer includes the polysilicon layer 102 and the molybdenum layer 112 that are electrically conductive, the polysilicon layer 102 may be disposed in the substrate 100, and the molybdenum layer 112 may be disposed in the buffer layer 110, as shown in fig. 19, which is a schematic cross-sectional view of an array substrate in another display panel provided in an embodiment of the present invention. Of course, the fifth shielding layer and the second shielding layer may be disposed on different layers.
In this embodiment, a sixth shielding layer 155 may be further disposed on a side of the display area AA close to the non-display area NA, and referring to fig. 20, for a schematic cross-sectional view of an array substrate in another display panel provided in this embodiment of the application, the sixth shielding layer 155 may be disposed perpendicular to the third active layer 122, the sixth shielding layer 155 is connected to a fixed potential, for example, the sixth shielding layer 155 may be grounded. Thus, the sixth shielding layer 155 prevents static electricity from entering the display area AA from the non-display area NA, thereby achieving an electrostatic shielding effect of the third thin film transistor. Sixth shield layer 155 may connect fourth shield layer 154 and fifth shield layer 101/102. When the sixth shield layer 155 is not provided, the fourth shield layer 154 and the fifth shield layer 101/102 may also be connected by a via.
In summary, the third shielding layer 154 may be disposed above the third gate electrode 132, the second shielding layer 102/112 may be disposed below the third active layer 122, and the sixth shielding layer 155 may be disposed on a side of the third tft facing the non-display area NA, so as to provide an electrostatic shielding effect for the third tft, improve the anti-static capability of the display area AA, and improve the overall anti-static capability of the display panel.
The embodiment of the application provides a display panel, the display panel is provided with a display area and a non-display area, the display panel comprises a first thin film transistor positioned in the display area, a second thin film transistor positioned in the non-display area and a first shielding layer, the first thin film transistor is an oxide transistor, the first thin film transistor comprises a first grid electrode and a first active layer, the second thin film transistor comprises a second grid electrode and a second active layer, the first shielding layer is positioned on one side of the second grid electrode far away from the second active layer, the projection of the first shielding layer and the second grid electrode in the direction vertical to the surface of the second active layer is provided with an overlapping area, the first shielding layer and the first active layer are arranged on the same layer, the first shielding layer is connected with a fixed potential, namely, in the embodiment of the application, the first shielding layer can be provided for the silicon transistor in the non-display area, the first shielding layer can play a role in electrostatic shielding, so that the antistatic capability of the non-display area is improved, and the display effect of the display panel is improved. In addition, the first shielding layer and the first active layer can be arranged on the same layer, and the forming step of the first shielding layer and film vacancy do not need to be designed on other layers, so that the steps of the manufacturing process are saved, the process is simplified, and the cost is reduced.
Based on the display panel provided by the above embodiment, as shown in fig. 21, an embodiment of the present application further provides a display device, where the display device includes the display panel, and the display panel has a display area AA and a non-display area NA, and the non-display area is disposed to surround the display area, so that the antistatic capability of the display device is improved, and the corresponding display effect is also improved.
When introducing elements of various embodiments of the present application, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (19)
1. A display panel having a display region and a non-display region, the display panel comprising:
a first thin film transistor located in the display region; the first thin film transistor is an oxide transistor and comprises a first grid electrode and a first active layer;
the second thin film transistor and the first shielding layer are positioned in the non-display area; the second thin film transistor is a silicon transistor and comprises a second grid electrode and a second active layer; the first shielding layer is located on one side, far away from the second active layer, of the second grid electrode, the projections of the first shielding layer and the second grid electrode in the direction perpendicular to the surface of the second active layer are provided with an overlapping region, the first shielding layer and the first active layer are arranged on the same layer, and the first shielding layer is connected with a fixed potential.
2. The display panel according to claim 1, wherein the first shielding layer is an IGZO layer which is subjected to electrical conduction treatment, and wherein the first active layer is an IGZO layer.
3. The display panel according to claim 2, wherein the second thin film transistor further comprises a source and a drain, the source and the drain are connected to the second active layer through a first conductor structure, the first conductor structure comprises a first substructure and a second substructure in a direction perpendicular to a surface of the second active layer, a first pad layer is disposed between the first substructure and the second substructure, the first pad layer is made of IGZO, and the first pad layer and the first shielding layer are located on the same layer.
4. The display panel according to claim 1, wherein the second thin film transistors are plural, and second gate electrodes of the plural second thin film transistors are parallel to each other; the first shielding layer comprises a plurality of first parts and a second part, wherein the extending direction of the first parts is consistent with the extending direction of the second gates, and the second parts are connected with the first parts; the projection of the first part on the surface of the second active layer and the projection of the second grid electrode on the surface of the second active layer have an overlapping region.
5. The display panel according to claim 1, characterized in that the display panel further comprises:
the second shielding layer is positioned in the non-display area, the second shielding layer is positioned on one side, away from the second grid electrode, of the second active layer, the projections of the second shielding layer and the second grid electrode in the direction vertical to the surface of the second active layer are provided with an overlapping area, and the second shielding layer is connected with a fixed potential.
6. The display panel according to claim 5, wherein the second shielding layer comprises: a molybdenum layer, and/or a conductively treated polysilicon layer.
7. The display panel according to claim 5, characterized in that the display panel further comprises:
the third shielding layer is positioned on one side, far away from the display area, of the non-display area and is vertical to the second active layer; the third shielding layer is connected with a fixed potential.
8. The display panel according to claim 7, wherein the third shielding layer connects the first shielding layer and the second shielding layer.
9. The display panel according to any one of claims 1 to 8, characterized by further comprising:
the third thin film transistor and the fourth shielding layer are arranged on one side, close to the non-display area, of the display area; the third transistor is a silicon-based transistor, the third thin film transistor comprises a third grid electrode and a third active layer, the fourth shielding layer is positioned on one side, far away from the third active layer, of the third grid electrode, the projection of the fourth shielding layer and the projection of the third grid electrode in the direction vertical to the surface of the third active layer are provided with an overlapping area, and the fourth shielding layer is connected with a fixed potential.
10. The display panel according to claim 9, wherein the fourth shielding layer is an IGZO layer which is subjected to electrical conduction treatment, and wherein the first active layer is an IGZO layer.
11. The display panel according to claim 9, wherein the third thin film transistors are plural, and third gate electrodes of the plural third thin film transistors are parallel to each other; the third shielding layer comprises a plurality of third parts and fourth parts, wherein the extending direction of the third parts is consistent with the extending direction of the third gates; the projection of the third part on the surface of the third active layer and the projection of the third grid electrode on the surface of the third active layer have an overlapping area.
12. The display panel according to claim 11, wherein the third thin film transistor comprises a switching transistor and a driving transistor, and wherein an area of a third portion of a side of the third gate electrode facing away from the third active layer in the switching transistor is smaller than an area of a third portion of a side of the third gate electrode facing away from the third active layer in the driving transistor.
13. The display panel according to claim 9, characterized in that the display panel further comprises:
the display device comprises a display area, a third active layer and a fifth shielding layer, wherein the display area is close to one side of a non-display area, the fifth shielding layer is positioned on one side of the third active layer far away from the third grid electrode, projections of the fifth shielding layer and the third grid electrode in the direction vertical to the third active layer are provided with an overlapping area, and the fifth shielding layer is connected with a fixed potential.
14. The display panel according to claim 11, wherein the fifth shielding layer comprises: a molybdenum layer, and/or a conductively treated polysilicon layer.
15. The display panel according to claim 13, characterized by further comprising:
a sixth shielding layer positioned in the display area and close to one side of the non-display area, wherein the sixth shielding layer is arranged perpendicular to the third active layer; the sixth shielding layer is connected with a fixed potential.
16. The display panel according to claim 15, wherein the sixth shielding layer connects the fourth shielding layer and the fifth shielding layer.
17. The display panel according to claim 9, wherein the material of the second active layer and the third active layer is polysilicon, and the second active layer and the third active layer are located in the same layer.
18. The display panel according to any one of claims 1 to 8, wherein the first shield layer is grounded.
19. A display device characterized by comprising the display panel according to any one of claims 1 to 18.
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| CN115933232A (en) * | 2022-10-25 | 2023-04-07 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| WO2023216307A1 (en) * | 2022-05-07 | 2023-11-16 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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| WO2024087713A1 (en) * | 2022-10-25 | 2024-05-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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