CN112684645B - Double-gate array substrate and display device - Google Patents
Double-gate array substrate and display device Download PDFInfo
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- CN112684645B CN112684645B CN201910997730.6A CN201910997730A CN112684645B CN 112684645 B CN112684645 B CN 112684645B CN 201910997730 A CN201910997730 A CN 201910997730A CN 112684645 B CN112684645 B CN 112684645B
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Abstract
The present disclosure relates to a dual gate array substrate and a display device. A dual gate array substrate comprising: a plurality of gate lines, a plurality of main signal lines and sub signal lines; the pixel units comprise pixel electrodes, the main signal wires are led out by the driving units and are respectively connected with the pixel units adjacent to the main signal wires; the common electrode comprises a plurality of dry electrodes and a plurality of branch electrodes, and the orthographic projection of the dry electrodes on the array substrate does not overlap with the orthographic projection of the adjacent pixel electrodes on the double-grid array substrate and at least covers the main signal lines.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to a double-gate array substrate and a display device.
Background
As the resolution of the display panel increases, the performance and cost of the driving IC inevitably increase. Therefore, in order to reduce the cost of the driver IC and increase the bonding yield of the driver IC, a dual gate driving scheme is generally adopted for the display panel. However, there is still a need to further improve the aperture ratio and transmittance of the display panel.
Disclosure of Invention
An embodiment of the present disclosure provides a dual gate array substrate, including:
a plurality of gate lines arranged along a first direction, each gate line extending along a second direction, the second direction being perpendicular to the first direction;
a plurality of main signal lines and sub signal lines alternately arranged in a second direction, the main signal lines and the sub signal lines extending in the first direction;
two adjacent grid lines and the main signal line or the auxiliary signal line are in insulated overlapping and enclosing to form a plurality of pixel units, each pixel unit comprises a pixel electrode, and the main signal line is led out from the driving unit and is respectively connected with the adjacent pixel units;
the double-grid array substrate further comprises a common electrode which is different from the pixel unit in layer, and the common electrode comprises a plurality of dry electrodes and a plurality of branch electrodes;
wherein the orthographic projection of the dry electrode on the double-gate array substrate does not overlap the orthographic projection of two pixel electrodes adjacent to the main signal line on the double-gate array substrate and at least covers the main signal line.
In one embodiment, a line width of the sub signal line is not greater than a line width of the main signal line.
In one embodiment, the trunk electrode in the common electrode is arranged along the extending direction of the main signal line, the branch electrodes are parallel to the trunk electrodes, a common electrode pattern formed by any two adjacent trunk electrodes and the branch electrode between the two trunk electrodes corresponds to one pixel unit, and the auxiliary signal line is connected to the common electrode;
any two adjacent dry electrodes comprise a first dry electrode and a second dry electrode, the orthographic projection of the first dry electrode on the array substrate covers the main signal line and does not overlap with the orthographic projection of the adjacent pixel electrode on the double-grid array substrate, the orthographic projection of the second dry electrode adjacent to the first dry electrode on the double-grid array substrate covers the auxiliary signal line, and the orthographic projection of the pixel electrode adjacent to the auxiliary signal line on the double-grid array substrate does not overlap.
In one embodiment, an orthographic projection of a second dry electrode adjacent to the first dry electrode on the array substrate coincides with an orthographic projection of the secondary signal line on the array substrate.
In one embodiment, the trunk electrode in the common electrode is arranged along the extension direction of the main signal line, the branch electrodes are parallel to the trunk electrodes, and a common electrode pattern formed by any two adjacent trunk electrodes and the branch electrode between the two trunk electrodes corresponds to one pixel unit;
wherein the orthographic projection of the dry electrode on the array substrate at least covers the main signal line and does not overlap with the orthographic projection of the adjacent pixel electrode on the double-grid array substrate, and no dry electrode is arranged above the auxiliary signal line along the orthographic projection direction on the double-grid array substrate.
In one embodiment, the trunk electrodes in the common electrode are arranged along the extending direction of the main signal line, the branch electrodes are arranged along the direction intersecting with the main signal line, and a common electrode pattern formed by any two adjacent trunk electrodes and the branch electrode between the two trunk electrodes corresponds to two adjacent pixel units;
wherein orthographic projections of the two dry electrodes on the array substrate at least cover the main signal line and do not overlap orthographic projections of the pixel electrodes adjacent to the main signal line on the double-gate array substrate, and the branch electrodes are continuous in pattern at boundaries between adjacent pixel units.
In one embodiment, the sub signal line is made of metal or transparent oxide.
In one embodiment, the sub signal line is made of indium tin oxide. .
In one embodiment, the dual gate array substrate further includes spacers disposed at both sides of the sub signal line, the spacers having two end portions having different sizes;
wherein, in a space between each pair of the main signal line and the sub signal line and between each two pixel units, the thin film transistor is disposed on a side close to the main signal line in the space, and the spacer is disposed on a side close to the sub signal line in the space.
In one embodiment, the dual gate array substrate further comprises a metal pad disposed such that one end of the spacer having a larger dimension is disposed on a surface of the metal pad on a side away from the pixel electrode, wherein the metal pad and the source and drain electrodes of the thin film transistor are different portions of a same layer of the metal film.
The embodiment of the disclosure also provides a display device, which comprises a color film substrate and the double-gate array substrate.
In one embodiment, a black matrix is disposed in a position of the color filter substrate corresponding to the array substrate side sub signal line, wherein an orthographic projection of the black matrix on the array substrate coincides with an orthographic projection of the sub signal line on the array substrate.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 (a) and fig. 1 (b) are schematic diagrams of a conventional dual gate driven array substrate;
fig. 2 (a) and fig. 2 (b) are schematic structural diagrams of a dual gate array substrate provided by the present disclosure, wherein the dry electrode and the pixel electrode do not overlap in a projection direction on the array substrate;
FIG. 3 (a) is a schematic diagram of a common electrode pattern of a pixel unit in an array substrate corresponding to an FFS display mode;
FIG. 3 (b) is a schematic diagram of a common electrode pattern of a pixel unit in an array substrate corresponding to the AFFS display mode;
fig. 4 (a) is a schematic structural view of an array substrate in FFS display mode according to an embodiment of the present disclosure;
fig. 4 (b) is a cross-sectional view of an array substrate in an FFS display mode of an embodiment of the present disclosure, in which a projection direction of a dry electrode and a pixel electrode on the array substrate does not overlap;
fig. 5 (a) is a schematic structural diagram of an array substrate in an AFFS display mode according to an embodiment of the present disclosure;
fig. 5 (B) and 5 (c) are cross-sectional views ofbase:Sub>A sectionbase:Sub>A-base:Sub>A andbase:Sub>A section B-B, respectively, of an array substrate in an AFFS display mode in example 2 of the present disclosure;
fig. 6 is a cross-sectional view of an array substrate dual gate array substrate of an FFS display mode according to an embodiment of the present disclosure, wherein no dry electrode is disposed above the sub-signal line;
fig. 7 is a schematic structural diagram of an array substrate in an AFFS display mode according to an embodiment of the present disclosure, in which a spacer (PS) is disposed.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
The technical solutions according to the present disclosure are described in detail by the following specific examples, and the present disclosure includes, but is not limited to, the following examples.
As shown in fig. 1 (a) and fig. 1 (B), which are schematic diagrams of a conventional dual gate driving array substrate, for convenience of description, a Fringe Field Switching (FFS) display mode is taken as an example, and pixel cells are respectively defined as a pixel cell a and a pixel cell B adjacent to the pixel cell a in a horizontal direction; as shown in fig. 1 (a), the TFT devices of the two pixel units are respectively located above and below the pixel unit, and are connected to the same data line L through their respective sources S The gate of the TFT device is connected to the gate line L G As can be seen from the figure, two gate lines L are disposed between the pixel units adjacent to each other in the vertical direction G And double-gate driving is convenient to realize. As can be seen from the cross-sectional structure shown in fig. 1 (B), the adjacent pixel units a and B are connected to the data line L therebetween in the array substrate S And no data line is arranged between the pixel unit B and the other adjacent pixel unit A. As can be seen from fig. 1 (a) and 1 (b), the data line L is not provided between the two adjacent pixel electrodes 11 S An unnecessary coupling capacitance is generated, and thus, in order to reduce the coupling capacitance generated between the adjacent pixel electrodes, it is necessary to reduceThe dry electrode 121 of the common electrode 12 at the position (corresponding to the dotted line in the figure) is arranged to be larger, so that the orthographic projection of the dry electrode 121 of the common electrode at the position on the array substrate can be overlapped with the adjacent pixel electrode 11 respectively, and the influence of the coupling capacitance on the rotation of the liquid crystal is well blocked.
Compared with the related art, one grid line is added, and an additional black matrix is necessarily required to be correspondingly arranged on the color film substrate side, so that the aperture opening ratio of a panel formed by the array substrate is reduced, in other words, the penetration rate of the array substrate is reduced. Moreover, in order to reduce the coupling capacitance, the area of the common electrode at the gap between adjacent pixel units is large, and the structure also reduces the aperture ratio of the array substrate and the transmittance.
As shown in fig. 2 (a), a schematic structural diagram of a dual gate array substrate provided in the present disclosure is shown, the array substrate mainly includes: a plurality of gate lines 21 arranged in a first direction, each gate line extending in a second direction, the second direction being perpendicular to the first direction; a plurality of main signal lines 22 and sub signal lines 23 alternately arranged in the second direction, the main signal lines and the sub signal lines extending in the first direction, gate lines 21 surrounding the main signal lines 22 and the sub signal lines 23 to form a plurality of pixel units 24 while being insulated from and overlapped with the main signal lines 22 and the sub signal lines 23, the pixel units 24 adjacent to the main signal lines 22 being connected to the main signal lines 22, the main signal lines 22 being connected to a driving unit (not shown) as data lines, and the sub signal lines 23 being connected to the common electrode 25. The drawings are only for illustrating the connection relationship, and the specific film pattern structure is not really shown. The main signal line and the sub signal line in the present embodiment are illustrated as extending in the first direction and the gate line is illustrated as extending in the second direction, however, the main signal line and the sub signal line are not limited to straight lines as illustrated in the drawings, and the main signal line and the sub signal line may have an arc, may be a broken line, or the like, as necessary.
As can be seen from the cross-sectional view of fig. 2 (b) for section b-b, the array substrate mainly includes: a substrate 26, a first insulating layer 27, a first patterned pixel electrode 28, a main signal line 22 and a sub signal line 23 alternately arranged in a space between adjacent pixel electrodes 28, a second insulating layer 29 covering the pixel electrode 28 and the main signal line 22 and the sub signal line 23, and a common electrode 25 on the second insulating layer 29, wherein the sub signal line 23 can be electrically connected to the common electrode 25 through a via hole, or through other conventional methods.
The common electrode 25 includes a plurality of trunk electrodes 251 and a plurality of branch electrodes 252, the trunk electrodes 251 and the branch electrodes 252 are connected by a connection portion 253, and an orthogonal projection of the trunk electrode 251 on the dual gate array substrate above the main signal line does not overlap with an orthogonal projection of the pixel electrode 28 adjacent to the main signal line 22 on the dual gate array substrate, and covers at least the main signal line 22. In other words, the orthogonal projection of the dry electrode 251 on the double gate array substrate may cover the sub-signal line 23. The orthographic projection of the dry electrode 251 on the dual-gate array substrate does not overlap with the orthographic projection of the pixel electrode 28 adjacent to the sub-signal line 23 on the dual-gate array substrate.
According to the scheme, in order to improve the existing double-gate array substrate and improve the transmittance of the double-gate array substrate, the main signal line and the auxiliary signal line are alternately arranged at the gap position between every two adjacent pixel electrodes, wherein the main signal line is still led out from the driving unit and is connected with the source electrodes of the TFT devices in the pixel units at two sides at the corresponding position, so that the purpose that one main signal line drives and controls two pixel units is achieved; meanwhile, the size of the dry electrode above the main signal line is reduced, the dry electrode is not overlapped with the pixel electrode adjacent to the main signal line, the aperture opening ratio of the array substrate is increased due to the reduction of the size of the dry electrode, and the display performance is improved. Meanwhile, the auxiliary signal line is connected to the common electrode, so that the voltage of the auxiliary signal line is stable, the possibility of generating coupling capacitance with an adjacent pixel electrode is completely avoided, and the auxiliary signal line is also arranged to be not overlapped with the pixel electrode adjacent to the auxiliary signal line, so that the aperture ratio is further improved. Therefore, the embodiment of the disclosure overcomes the technical problem in the prior art that the coupling capacitance is reduced by increasing the size of the dry electrode, that is, the size of the dry electrode above the main signal line having a size larger than that of the auxiliary signal line can be reduced, and further, the aperture ratio of the array substrate is improved.
In the embodiments of the present disclosure, the main signal lines involved are data lines.
In another embodiment of the present disclosure, as shown in fig. 6, the structure of the present embodiment includes the structure shown in fig. 2, however, in the structure of the present embodiment, no dry electrode is provided above the sub signal line 23 in the sectional view shown in fig. 6. In the present embodiment, since the dry electrode is not provided above the sub signal line 23, the aperture ratio and the transmittance can be further provided. The main signal line 22 is provided with the dry electrode 251, the orthographic projection of the dry electrode 251 above the main signal line 22 on the double-gate array substrate is not overlapped with the orthographic projection of the pixel electrode 28 adjacent to the main signal line 22 on the double-gate array substrate, and the dry electrode 251 at least covers the main signal line 22, namely the orthographic projection of the dry electrode 251 on the double-gate array substrate at least covers the orthographic projection of the main signal line 22 on the double-gate array substrate; the dry electrode above the main signal line 22 is reduced in size, and the aperture ratio can be improved.
Further, in the embodiment of the disclosure, the line width of the sub signal line is not greater than the line width of the main signal line, so that the size of the black matrix corresponding to the color film substrate side can be reduced, and the aperture opening ratio of the dual-gate array substrate is improved.
In order to better describe the above scheme, the present disclosure is illustrated in the following specific examples. It should be explained that the present disclosure mainly addresses the structures of a dual-gate array substrate corresponding to two display modes, namely, fringe Field Switching (FFS) and Advanced Fringe Field Switching (AFFS), where a common electrode pattern corresponding to one pixel in the array substrate corresponding to the FFS display mode is shown in fig. 3 (a), a common electrode pattern corresponding to one pixel in the array substrate corresponding to the AFFS display mode is shown in fig. 3 (b), and the two structures are mainly different in the common electrode pattern, and the main electrode 31 and the branch electrode 32 in the dual-gate array substrate corresponding to the FFS display mode are arranged in parallel, and they extend almost along the direction of the data line, and are generally arranged in a zigzag shape in the drawing; the array substrate corresponding to the AFFS display mode has the main electrodes 33 and the branch electrodes 34 arranged approximately perpendicular to each other, the main electrodes 33 are arranged along the extending direction of the data lines, and the branch electrodes 34 are arranged between the adjacent main electrodes in a V shape. The dry electrode and the branch electrode are connected by connection portions 35, 36.
One embodiment of the present disclosure is described below in conjunction with fig. 4. As shown in fig. 4 (a), which is a schematic structural diagram of an array substrate in an FFS display mode according to an embodiment of the present disclosure, a common electrode pattern formed by two adjacent dry electrodes 411 in a common electrode 41 and a branch electrode 412 between the two dry electrodes 411 corresponds to one pixel unit P, and the dry electrodes 411 and the branch electrodes 412 are connected by a connection portion 413; referring to the sectional structure diagram of fig. 4 (b), the orthographic projection of the first dry electrode 411 (the left dry electrode in the figure) on the dual-gate array substrate does not have an overlapping area (the area indicated by the dashed oval frame in the figure) with the orthographic projection of the pixel electrode 42 adjacent to the main signal line 43 on the dual-gate array substrate and covers at least the main signal line 43, and the orthographic projection of the second dry electrode 411' (the right dry electrode in the figure) adjacent to the first dry electrode 411 on the dual-gate array substrate is located in the gap between the adjacent pixel electrodes 42 and covers the sub-signal line 44. In the present embodiment, the width of the dry electrode above the sub signal line 44 is the same as the width of the sub signal line 44. In addition, the dual gate array substrate further includes other relevant film layers such as an insulating layer, which are not shown for convenience of description. Based on the scheme, after the auxiliary signal line is connected to the common electrode, the generation of coupling capacitance between the auxiliary signal line and the adjacent pixel electrode is avoided, and the positive projection of the dry electrode above the auxiliary signal line on the double-gate array substrate is limited in the gap between the adjacent pixel electrodes and covers the auxiliary signal line, so that stable capacitance generated between the auxiliary signal line and the adjacent pixel electrode can be superposed with capacitance generated by the pixel electrode and the common electrode to form storage capacitance required by the double-gate array substrate, and therefore, the voltage at the junction of the pixel electrode and the common electrode can be better controlled. In addition, in the structure of the FFS display mode, the direction of the electric field required for the liquid crystal to rotate is the same as the direction of the electric field superimposed at the boundary, and is relatively stable, so that the electric field generated by the superimposed storage capacitor can promote the rotation of the liquid crystal at the boundary, thereby improving the transmittance of the panel. Here, it is to be noted that "first" and "second" do not represent the order, importance, or the like, but merely describe the names of two different dry electrodes. For example, in the present embodiment, the orthographic projections of the first dry electrode 411 on the array substrate respectively do not overlap with the orthographic projections of the adjacent pixel electrodes on the dual-gate array substrate and cover at least the primary signal lines, while the second dry electrode 411' is adjacent to the first dry electrode, and the orthographic projection of the second dry electrode on the dual-gate array substrate is located in the gap between the adjacent pixel electrodes and covers the secondary signal lines. Further, an orthogonal projection of a second dry electrode 411' (the dry electrode on the right in the drawing) adjacent to the first dry electrode 411 on the array substrate coincides with the sub signal line. Considering that the electric field required in the present disclosure is capable of rotating the liquid crystal is a fringe field between the pixel electrode and the common electrode, in order to enable the fringe field between the pixel electrode and the common electrode to be well overlapped with the fringe field between the pixel electrode and the sub-signal line and not to cause the fringe field between the pixel electrode and the sub-signal line to affect the fringe field between the pixel electrode and the common electrode, it is preferable that the positive projection of the dry electrode of the common electrode on the dual-gate array substrate is overlapped with the sub-signal line. Therefore, the superposed fringe field can reach the optimal value, the rotation of the liquid crystal at the junction of the pixel electrode and the common electrode is promoted, and the transmittance of the panel is further promoted.
One embodiment of the present disclosure is also described below in conjunction with fig. 5. As shown in fig. 5 (a), the schematic structure of the array substrate in AFFS display mode in one embodiment of the present disclosure is that, in the common electrode, the stem electrode 511 is disposed along the extending direction (first direction) of the main signal line 53, and the branch electrodes 512 are disposed along the transverse direction (second direction) of the main signal line 53, or the branch electrodes 512 are disposed along the direction crossing the main signal line 53, corresponding to two adjacent pixel units Q, or the span of the common electrode pattern formed by any two adjacent stem electrodes 511 and the branch electrodes 512 between the two stem electrodes 511 covers two pixel units Q. In the present embodiment, the main signal line and the sub signal line in the present embodiment are illustrated as extending in the first direction, and the gate line is illustrated as extending in the second direction, however, the main signal line and the sub signal line are not limited to straight lines as illustrated in the drawings, and the main signal line and the sub signal line may have an arc shape, and may be broken lines, as necessary.
As shown in the sectional view at the sectionbase:Sub>A-base:Sub>A shown in fig. 5 (B) and the sectional view at the section B-B shown in fig. 5 (c), the orthographic projections of the two stem electrodes 511 on the dual gate array substrate respectively cover at least the main signal line 53 and have no overlapping area with the orthographic projection of the adjacent pixel electrode 52 on the dual gate array substrate, and the pattern of the branch electrode 512 at the boundary between the adjacent pixel units Q is continuous. Based on the above scheme, the sub signal line 54 can be connected to the common electrode, and the sub signal line and the adjacent pixel electrode can be prevented from generating coupling capacitance; also, in this display mode, the direction of the electric field required for the liquid crystal to rotate is different from the direction of the electric field superimposed at the boundary, and therefore, it is possible to remove the dry electrode above the sub signal line while increasing the size of the pixel electrode adjacent to the sub signal line, thereby making the overlapping area of the sub electrode and the pixel electrode more (see the cross-sectional view shown in fig. 5 (c)). Moreover, the increase of the overlapping area can increase the electric field required by the rotation of the liquid crystal, and more importantly, the increased overlapping area is positioned at the junction of the pixel electrode and the auxiliary signal line, so that the liquid crystal at the junction can be promoted to rotate, and the transmittance of the panel is improved.
In this embodiment, the line width of the sub signal line may be not larger than the line width of the main signal line.
In the embodiment of the present disclosure, the sub signal line is made of metal or transparent oxide.
In one possible embodiment, the sub-signal line is made of ito to improve the transmittance of the dual-gate array substrate.
In one embodiment of the present disclosure, a dual gate array substrate is also provided. The present embodiment may be a modified form based on the above embodiments as shown in fig. 2 (2A, 2B), fig. 4 (4A, 4B), and fig. 5 (5A, 5B, 5C). As an example, the present embodiment includes a dual gate array substrate as shown in fig. 5, and further includes spacers (PS) 81. As shown in fig. 7, spacers 81 are disposed on the dual gate array substrate, as spacers during assembly of the dual gate array substrate, for example, spacers disposed between the dual gate array substrate and the color filter substrate during assembly, which is different from the spacers disposed on the color filter substrate in conventional design. In this embodiment, the dual gate array substrate may further include a metal pad 82; metal pads 82 are disposed at both sides of the sub-signal line 54 of the dual gate array substrate, and the metal pads 82 may be formed of a portion of a metal film for forming source and drain electrodes of a Thin Film Transistor (TFT). Here, the source and drain electrodes and the metal pad 81 may be formed at a time when the source and drain electrodes are formed, that is, by depositing a metal film and patterning the metal film into a source and drain electrode pattern of a Thin Film Transistor (TFT) and a pattern of the metal pad 82 through a patterning process at a time. In the present embodiment, the metal pad 82 is disposed corresponding to the thin film transistor. For example, between a pair of main signal line-sub signal line on the left side in fig. 7, a thin film transistor is provided on the right side of the main signal line 53, and at the same time, a metal pad 82 is provided on the left side of the sub signal line 54 on the right side of the main signal line 53, wherein the metal pad 82 and the source drain of the thin film transistor on the right side of the main signal line 53 are formed by the same metal layer through one patterning process. While between the pair of main signal line-sub signal line on the right side in fig. 7, a thin film transistor is provided on the left side of the main signal line 53, and at the same time, a metal pad 82 is provided on the right side of the sub signal line 54 on the left side of the main signal line 53. In other words, between each pair of the main signal line 53 and the sub signal line 54, a thin film transistor is disposed on a side close to the main signal line 53, and a metal pad 82 is disposed on a side close to the sub signal line 54, wherein the metal pad 82 and the source-drain electrode of the thin film transistor on the right side of the main signal line 53 are formed by the same metal layer through one patterning process. The metal pad 82 may be opaque and may replace the function of the black matrix, and in this embodiment, the metal pad 82 may replace a portion of the black matrix.
In the present embodiment, the spacer 81 is disposed on the metal pad 82, that is, one end portion of the spacer 81 is disposed on one side surface of the metal pad 82 away from the pixel electrode; or in other words, the metal pad 82 is disposed at an end of the spacer 81 facing the pixel electrode. From this, it is known that, in the space between each pair of the main signal line 53 and the sub signal line 54 and between each two pixel units, a thin film transistor is provided on the side close to the main signal line 53, and a spacer 81 (on the metal pad 82) is provided on the side close to the sub signal line 54.
In fig. 7 of the present embodiment, the metal pad 82 is shown as a rectangle, the spacer 81 is shown as a truncated cone, i.e., the end toward the array substrate has a larger diameter than the end away from the array substrate (so the end with the smaller diameter is inside the end with the larger diameter as viewed from one end in fig. 7), and the end with the larger diameter is disposed above the metal pad 82; however, the spacer 81 may have other shapes; the spacer 81 may be formed of a transparent material, for example, a resin material.
In the assembling process of the array substrate, a part of the array substrate is deformed by pressure, and the spacer 81 can play a supporting role to avoid the deformation of the array substrate. In the present embodiment, since the Thin Film Transistor (TFT) is provided in the vicinity of the main signal line 53, at least, for example, a source-drain metal layer, a semiconductor layer (active layer), and the like are provided, and these layers are not provided in the vicinity of the sub-signal line, so that a level difference is generated in a portion corresponding to the main signal line 53 and the sub-signal line 54 on the surface of the dual gate array substrate, which may cause uneven stress on the array substrate in subsequent assembly, whereas according to the present embodiment, the metal pad 82 is disposed in the vicinity of the sub-signal line 54, and further the spacer is provided on the metal pad 82, the level difference may be compensated, so that the layers on the surface of the entire array substrate are more flat, and at the same time, may serve as a support for a space where the liquid crystal cell is constructed. Further, it is advantageous that spacers are disposed on both sides of the sub signal line 54 and on the metal pads 82 of the source and drain electrodes of the thin film transistor, and the spacers 81 are away from the channel of the Thin Film Transistor (TFT), so that the spacers 81 do not generate pressure on the channel of the Thin Film Transistor (TFT), but the spacers are away from the thin film transistor so that the pressure applied to the channel is small, thereby preventing the channel characteristics from being affected by the pressure.
In other embodiments, for example, the embodiments shown in fig. 2 (2A, 2B) and fig. 4 (4A, 4B), a spacer (PS) similar to the above embodiments may also be included, and details are not repeated here.
In addition, the embodiment of the disclosure also provides a display device, which comprises a color film substrate and any one of the double-gate array substrates provided by the embodiment of the disclosure.
In one embodiment of the disclosure, a black matrix is arranged in a position of the color film substrate corresponding to the sub signal line on the side of the dual-gate array substrate, wherein an orthographic projection of the black matrix on the dual-gate array substrate is superposed with an orthographic projection of the sub signal line on the array substrate.
The display device disclosed by the disclosure can be any product or component with a display function, such as a liquid crystal panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.
While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present disclosure.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.
Claims (12)
1. A dual gate array substrate comprising:
a plurality of gate lines arranged along a first direction, each gate line extending along a second direction, the second direction being perpendicular to the first direction;
a plurality of main signal lines and sub signal lines alternately arranged in a second direction, the main signal lines and the sub signal lines extending in the first direction;
two adjacent grid lines and the main signal line or the auxiliary signal line are in insulated overlapping and enclosing to form a plurality of pixel units, each pixel unit comprises a pixel electrode, and the main signal line is led out from the driving unit and is respectively connected with the adjacent pixel units;
the double-grid array substrate also comprises a common electrode which is arranged at the different layer of the pixel unit, wherein the common electrode comprises a plurality of dry electrodes and a plurality of branch electrodes;
wherein the orthographic projection of the dry electrode on the double-gate array substrate does not overlap with the orthographic projection of two pixel electrodes adjacent to the main signal line on the double-gate array substrate and at least covers the main signal line;
the double-grid array substrate further comprises spacers arranged on two sides of the auxiliary signal line, and the spacers are provided with two end parts with different sizes;
wherein, in a space between each pair of the main signal line and the sub signal line and between each two pixel units, the thin film transistor is disposed on a side close to the main signal line in the space, and the spacer is disposed on a side close to the sub signal line in the space.
2. The double gate array substrate of claim 1, wherein a line width of the secondary signal lines is not greater than a line width of the primary signal lines.
3. The double gate array substrate as claimed in claim 1 or 2, wherein a trunk electrode of the common electrode is disposed along an extending direction of the main signal line, the branch electrodes are parallel to the trunk electrodes, a common electrode pattern formed by any two adjacent trunk electrodes and the branch electrode between the two trunk electrodes corresponds to one pixel unit, and the sub signal line is connected to the common electrode;
any two adjacent dry electrodes comprise a first dry electrode and a second dry electrode, the orthographic projection of the first dry electrode on the array substrate covers the main signal line and does not overlap with the orthographic projection of the adjacent pixel electrode on the double-grid array substrate, the orthographic projection of the second dry electrode adjacent to the first dry electrode on the double-grid array substrate covers the auxiliary signal line, and the orthographic projection of the pixel electrode adjacent to the auxiliary signal line on the double-grid array substrate does not overlap.
4. The dual gate array substrate of claim 3, wherein an orthographic projection of a second dry electrode adjacent to the first dry electrode on the array substrate coincides with an orthographic projection of the secondary signal line on the array substrate.
5. The double gate array substrate as claimed in claim 1 or 2, wherein a stem electrode of the common electrode is disposed along the extension direction of the main signal line, the branch electrodes are parallel to the stem electrodes, and a common electrode pattern formed by any two adjacent stem electrodes and the branch electrode between the two stem electrodes corresponds to two pixel units;
wherein the orthographic projection of the dry electrode on the array substrate at least covers the main signal line and does not overlap with the orthographic projection of the adjacent pixel electrode on the double-grid array substrate, and the dry electrode is not arranged above the auxiliary signal line along the orthographic projection direction on the double-grid array substrate.
6. The double gate array substrate as claimed in claim 1 or 2, wherein a trunk electrode of said common electrode is disposed along a direction in which said main signal line extends, said branch electrodes are disposed along a direction crossing said main signal line, and a common electrode pattern formed by any two adjacent trunk electrodes and the branch electrode between the two trunk electrodes corresponds to two adjacent pixel cells;
wherein orthographic projections of the two dry electrodes on the array substrate at least cover the main signal line and do not overlap with orthographic projections of the pixel electrodes adjacent to the main signal line on the double-gate array substrate, and the branch electrodes are continuous in pattern at the junctions between the adjacent pixel units.
7. The double gate array substrate of claim 1 or 2, wherein said sub-signal lines are made of metal or transparent oxide.
8. The double-gate array substrate of claim 7, wherein the sub-signal lines are formed of indium tin oxide.
9. The double gate array substrate of claim 1, wherein the spacers have a frustoconical shape.
10. The double gate array substrate of claim 1, further comprising metal pads disposed such that one larger dimension end of the spacer is disposed on a surface of the metal pad on a side away from the pixel electrode, wherein the metal pads are different portions of the same layer of metal film as the source and drain electrodes of the thin film transistor.
11. A display device comprises a color film substrate, and further comprises: the double gate array substrate of claim 1.
12. The display device according to claim 11, wherein a black matrix is disposed in the color filter substrate at a position corresponding to the array substrate side sub signal line, wherein an orthogonal projection of the black matrix on the array substrate coincides with an orthogonal projection of the sub signal line on the array substrate.
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