201032272 、 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種在半導體晶圓的雙面拋光過程中保持半導體 晶圓之載具。本發明亦關於一種使用該載具之用於半導體晶圓之 雙面拋光的方法。 【先前技術】 作為生產電子元件之基材之半導體晶圓的生產中，通常包含至 少一次半導體晶圓的雙面拋光，該雙面拋光係以一在單一步驟進 ® 行，且下文稱為DSP。在DSP過程中，一半導體晶圓與其它的半 導體晶圓一起在上下二個拋光盤之間，該等拋光盤係由拋光布覆 蓋且旋轉。具有置放半導體晶圓之切除部分的載具在拋光過程中 引導並保持半導體晶圓。該等載具在週邊具有一外部齒，在拋光 過程中，該等載具借助於該外部齒作為行星齒輪機構的行星齒 輪，圍繞它們自身的軸線和該拋光盤的軸線旋轉。半導體晶圓在 拋光劑存在之情況下被拋光，其係由上拋光盤供給且分佈於拋光 _ 布上。必須確保在半導體晶圓的二側都充分地供給拋光劑，以獲 得均勻的拋光去除。如果拋光係藉由微型設計的拋光機實現，則 拋光劑的充分供給係特別重要。這種類型僅能容納一個載具，該 載具係延展涵蓋整個下拋光盤，且該拋光盤和載具有一共同的旋 轉軸線。在這種情況下，缺少拋光劑具有以下的影響：半導體晶 圓以自身之軸心作旋轉時，其運動性受到一定程度之阻礙，使得 所累積之摩擦熱量引起半導體晶圓邊緣之部分區域之材料移除的 增加，且因此產生一種具楔形邊緣區段的半導體晶圓。為了防止 此種情況，EP 1 676 672 A1提出藉由在載具中至少15%的區域被 201032272 孔所佔據以改良對下拋光盤之拋光劑的供給，該等孔係提供拋光 劑通往下拋光盤之通道。 然而，本發明人已經確定，以一充足量之拋光劑供給到下拋光 盤誠然係必要的，但卻不一定能消除所有邊緣幾何結構缺陷。這 特別適用於所謂之邊緣下降（edge roll-off)，其係考量整個晶圓邊 緣且在DSP後觀測。所述邊緣下降在國際半導體設備材料產業協 會（SEMI)之標準M69中係描述為大直徑之半導體晶圓之邊緣區 域中的表面偏離。由於在半導體晶圓中，越來越多的區域要符合 電子元件生產的要求，且在現今極高品質的半導體晶圓中，邊緣 排除僅為1毫米，因此減少邊緣區域之幾何結構缺陷係漸受關 注。標準化參數，例如為在SEMI標準中所定義的邊緣局部正面 最小平方焦面範圍值（ESFQR)，可用於定量描述此等幾何結構缺 陷。 【發明内容】 本發明之一個目的是提供一種手段，藉此大幅地降低DSP後之 邊緣下降，並且可以獲得有利之邊緣幾何結構的半導體晶圓。 該目的係藉由一種在半導體晶圓的雙面拋光過程中保持半導體 晶圓的載具來實現，其包含用於接收半導體晶圓的切除部分和供 一在拋光過程中供給之拋光劑用的通道開口，其中部分該等通道 開口係由直徑為2毫米至8毫米之孔所組成且係安置在一路徑 上，該路徑係以1毫米至10毫米之距離圍繞該等切除部分且具有 一内部區段、一外部區段及二個界於該内部區段與該外部區段之 間的區段。 201032272 本發明人發現，將拋光劑供至下拋光盤之通道對邊緣下降之減 少具有明顯之貢獻，其係位於晶圓邊緣附近且以一均等距離安置 在晶圓邊緣。因此，本發明之載具不僅具有傳統的拋光劑通道開 口，且具有根據此洞察而置入之通道開口。該載具可以與其他者 一起使用在具有一行星齒輪機構的拋光機中或獨自使用在一微型 設計之拋光機中。 該載具較佳係由鋼、塑膠或陶瓷構成，尤佳係由硬化鋼構成， 且若適當係具有一低磨損且低摩擦的塗層。 ® 用於接收半導體晶圓的切除部分依傳統方式裝有塑膠之内襯以 保護敏感的晶圓邊緣，較佳係以5毫米至30毫米之規則距離裝有 具有切除部分之嵌體（inlays )。嵌體之較佳形式係如DE 100 18 338 C1中所例示述者。 該等安置遠離於切除部分之拋光劑通道開口原則上可根據需求 而設定形狀。具有周邊呈圓曲之三角形與四邊形或圓形之開口係 較佳的。例如在DE 102 47 200 A1中所述之通道開口係尤佳的。 _ 【實施方式】 下文中將參照圖式以詳細解釋本發明 第1圖所示之載具，係代表先前技術，其包括用以接收半導體 晶圓之切除部分1和在拋光過程中用以供給拋光劑之相對大的通 道開口 2。 如第2圖所示之根據本發明實施之載具，其與第1圖所示者之 主要差異在於由較小通道開口孔3所構成之環。該等孔具有2毫 米至8毫米之直徑且以1毫米之10毫米之距離圍繞該等切除部分 201032272 而安置’其巾該卿儲在不考慮賴的敎τ 除部之邊緣的最短距離。該等孔的中心點位於圍繞於切=分的 ==上。根據第一實施態樣中之載具，該圓形路徑係完 王由孔所估據。提供孔之其他實施態樣以形成—在—區段打開之 環。如果將圓形路徑視為分割成四個大致相等長度的區段，可區 分為：安置在-内部區段之孔3a;安置在一外部區段之孔t以 及安置在二介於内部與外部區段之中間區段之孔〜與^。 在第二實施態樣之載具的情況中，其係例示於第3圖該等孔 並未圍繞®形路徑之整侧周安置。這是因為本料人已發現， 佔據中間區段之孔已;i以獲得相當小的邊緣下降，特別在當載且 係作為-行星齒輪時。在内部及/或外部區段之孔㈣外安置主要 增加載具的硬度（stiffness)。因此，在第二實施態樣之載具的情 況中’該等孔係安置在中間區段上且及額外地在外部區段上。 在第三實施態樣之載具之情況中，其係例示於第4圖孔係安 置在圓形路徑的—個中間區段上以及一内部區段上。 ” 區段中相鄰的孔間距離為3毫米至3〇毫米且較佳係—直相同 包括相鄰區段之二個相鄰的孔之間。 實施例： 由矽構成之具有3〇〇米直徑的半導體晶圓在相同條件下於來自 製造商彼特沃爾特斯（Peter Wolters)之AC2000型DSP機5|上拖 光並檢測邊緣下降。於一實驗中使用第一實施態樣之載具，且於 一比較實驗中使用依第1圖中所示實施之載具。 第5圖和第6圖所示為在二個已拋光半導體晶圓之正面上以 201032272 距離A對直徑D所繪製之表面輪廓曲線。 在根據本發明拋光之半導體晶圓的情況中，在第5圖中所示之 晶圓表面輪廓曲線中，幾乎辨識不出邊緣下降。相對地，在比較 實驗之拋光半導體晶圓中展現出明顯的邊緣下降，該晶圓之表面 輪廓曲線係如第6圖所示。在根據本發明拋光之半導體晶圓之情 況中，考慮1毫米的邊緣排除，所測得的ESFQR係特別低。在多 個根據本發明拋光之半導體晶圓的測量顯示，ESFQRmax (即具有 最壞之邊緣幾何結構者）之變化係於100奈米至170奈米之範圍201032272, VI. Description of the Invention: [Technical Field] The present invention relates to a carrier for holding a semiconductor wafer during double-sided polishing of a semiconductor wafer. The invention also relates to a method for double-sided polishing of a semiconductor wafer using the carrier. [Prior Art] In the production of a semiconductor wafer as a substrate for producing electronic components, it is common to include double-sided polishing of at least one semiconductor wafer, which is performed in a single step, and is hereinafter referred to as DSP. . In the DSP process, a semiconductor wafer is placed between the upper and lower polishing disks together with other semiconductor wafers which are covered and rotated by a polishing cloth. A carrier having a cutout portion in which the semiconductor wafer is placed guides and holds the semiconductor wafer during polishing. The carriers have an external tooth at the periphery which, during polishing, rotates about their own axis and the axis of the polishing disk by means of the external teeth as planet gears of the planetary gear mechanism. The semiconductor wafer is polished in the presence of a polishing agent which is supplied by the upper polishing pad and distributed over the polishing cloth. It must be ensured that the polishing agent is adequately supplied on both sides of the semiconductor wafer for uniform polishing removal. If the polishing is achieved by a micro-designed polishing machine, then a sufficient supply of polishing agent is particularly important. This type can only accommodate one carrier that extends over the entire lower polishing disk and that has a common axis of rotation. In this case, the lack of polishing agent has the following effects: when the semiconductor wafer is rotated by its own axis, its mobility is hindered to a certain extent, so that the accumulated frictional heat causes a part of the edge of the semiconductor wafer. The increase in material removal, and thus the creation of a semiconductor wafer with wedge-shaped edge segments. In order to prevent this, EP 1 676 672 A1 proposes to improve the supply of the polishing agent to the lower polishing disk by at least 15% of the area in the carrier being occupied by the 201032272 hole, which provides a polishing agent to the next. The channel of the polishing disc. However, the inventors have determined that it is necessary to supply a sufficient amount of polishing agent to the lower polishing disk, but does not necessarily eliminate all edge geometry defects. This applies in particular to the so-called edge roll-off, which takes into account the entire wafer edge and is observed after the DSP. The edge drop is described in the International Semiconductor Equipment Materials Industry Association (SEMI) standard M69 as surface deviation in the edge region of a large diameter semiconductor wafer. Since more and more areas in semiconductor wafers are required to meet the requirements of electronic component production, and in today's extremely high quality semiconductor wafers, the edge exclusion is only 1 mm, so the geometrical defects of the edge region are reduced. Get attention. Standardized parameters, such as the edge local frontal least square focal length range value (ESFQR) defined in the SEMI standard, can be used to quantitatively describe such geometric defects. SUMMARY OF THE INVENTION It is an object of the present invention to provide a means whereby the edge drop after the DSP is greatly reduced and a semiconductor wafer of advantageous edge geometry can be obtained. The object is achieved by a carrier for holding a semiconductor wafer during double-sided polishing of a semiconductor wafer, comprising a cutout for receiving a semiconductor wafer and a polishing agent for supplying during polishing. a passage opening, wherein a portion of the passage openings are formed by holes having a diameter of 2 mm to 8 mm and are disposed on a path that surrounds the cut portions and has an interior at a distance of 1 mm to 10 mm A segment, an outer segment, and two segments that are bounded between the inner segment and the outer segment. 201032272 The inventors have found that the passage of the polishing agent to the lower polishing disk has a significant contribution to the reduction in edge drop, which is located near the edge of the wafer and is placed at the edge of the wafer at an equal distance. Thus, the carrier of the present invention not only has a conventional polish channel opening, but also has a passage opening that is placed in accordance with this insight. The carrier can be used with others in a polishing machine having a planetary gear mechanism or used alone in a micro-designed polishing machine. Preferably, the carrier is constructed of steel, plastic or ceramic, particularly preferably of hardened steel, and if appropriate has a low wear and low friction coating. The cut-off portion used to receive the semiconductor wafer is conventionally fitted with a plastic liner to protect the sensitive wafer edges, preferably at a regular distance of 5 mm to 30 mm with inlays with cut-outs. . The preferred form of the inlay is as exemplified in DE 100 18 338 C1. These polishing agent passages, which are disposed away from the cut-away portion, can in principle be shaped according to requirements. It is preferred to have a triangular shape with a rounded periphery and a quadrangular or circular opening. The passage opening as described, for example, in DE 102 47 200 A1 is particularly preferred. EMBODIMENT Hereinafter, a carrier shown in FIG. 1 of the present invention will be explained in detail with reference to the drawings, which represents a prior art, which includes a cutout portion 1 for receiving a semiconductor wafer and is used for supplying during polishing. A relatively large passage opening 2 of the polishing agent. The carrier according to the present invention as shown in Fig. 2 differs from the one shown in Fig. 1 in the ring formed by the smaller passage opening 3. The holes have a diameter of from 2 mm to 8 mm and are placed around the resected portion 201032272 by a distance of 10 mm from 1 mm to the shortest distance of the edge of the 敎τ division. The center point of the holes is located at == around the cut = minute. According to the carrier in the first embodiment, the circular path is estimated by the hole. Other embodiments of the aperture are provided to form a loop in which the section is open. If the circular path is considered to be divided into four sections of substantially equal length, it can be distinguished as: a hole 3a disposed in the -internal section; a hole t disposed in an outer section and disposed between the inner and outer portions Holes ~ and ^ in the middle section of the section. In the case of the carrier of the second embodiment, which is illustrated in Figure 3, the holes are not placed around the entire circumference of the ® path. This is because the source has found that the hole occupying the intermediate section has been; i to obtain a relatively small edge drop, especially when the carrier is a planetary gear. Placement outside the holes (4) of the inner and/or outer sections primarily increases the stiffness of the carrier. Thus, in the case of the carrier of the second embodiment, the holes are placed on the intermediate section and additionally on the outer section. In the case of the carrier of the third embodiment, it is illustrated that the hole system of Fig. 4 is placed on an intermediate section of the circular path and on an inner section. The distance between adjacent holes in the section is between 3 mm and 3 mm and preferably is the same between two adjacent holes of the adjacent section. Example: 3〇〇 consisting of 矽The rice-diameter semiconductor wafer was towed on the AC2000 type DSP machine 5| from the manufacturer Peter Wolters under the same conditions and the edge drop was detected. The carrier of the first embodiment was used in one experiment. And using a carrier implemented as shown in Figure 1 in a comparative experiment. Figures 5 and 6 show the diameter D plotted on the front side of the two polished semiconductor wafers at 201032272 distance A. Surface profile curve. In the case of a semiconductor wafer polished according to the present invention, almost no edge drop is recognized in the wafer surface profile shown in Fig. 5. In contrast, the polished semiconductor crystal in the comparative experiment A significant edge drop is exhibited in the circle, and the surface profile of the wafer is as shown in Fig. 6. In the case of a semiconductor wafer polished according to the present invention, the edge exclusion of 1 mm is considered, and the measured ESFQR system Especially low. In multiple roots Measurement of polishing a semiconductor wafer of the present invention display, ESFQRmax (i.e., having the worst edge geometry's) based on the variation range of 100 nm to 170 nm
【圖式簡單說明】 第1圖所示為一代表先前技術之載具。 第2圖所示為一根據本發明之第一實施態樣之載具。 第3圖所示為一根據本發明之第二實施態樣之載具。 第4圖所示為一根據本發明之第三實施態樣之載具。 第5及6圖顯示出相較於與先前技術相關之載具，根據本發明 _ 之載具在DSP後對半導體晶圓之邊緣幾何結構的不同影響。 【主要元件符號說明】 1 :切除部分 2:通道開口 3、3a、3b、3c、3d :孔[Simple Description of the Drawing] Figure 1 shows a carrier representing the prior art. Figure 2 shows a carrier according to a first embodiment of the invention. Figure 3 shows a carrier according to a second embodiment of the invention. Figure 4 shows a carrier according to a third embodiment of the present invention. Figures 5 and 6 show the different effects of the carrier according to the present invention on the edge geometry of the semiconductor wafer after the DSP compared to the prior art related carriers. [Main component symbol description] 1 : Cut-out part 2: Channel opening 3, 3a, 3b, 3c, 3d: hole