US20100210188A1 - Carrier For Holding Semiconductor Wafers During A Double-Side Polishing Of The Semiconductor Wafers - Google Patents

Carrier For Holding Semiconductor Wafers During A Double-Side Polishing Of The Semiconductor Wafers Download PDF

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Publication number
US20100210188A1
US20100210188A1 US12/692,685 US69268510A US2010210188A1 US 20100210188 A1 US20100210188 A1 US 20100210188A1 US 69268510 A US69268510 A US 69268510A US 2010210188 A1 US2010210188 A1 US 2010210188A1
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US
United States
Prior art keywords
semiconductor wafers
carrier
polishing
holes
double
Prior art date
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Abandoned
Application number
US12/692,685
Inventor
Klaus Roettger
Gerhard Heier
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Siltronic AG
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Siltronic AG
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Filing date
Publication date
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Assigned to SILTRONIC AG reassignment SILTRONIC AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HEIER, GERHARD, ROETTGER, KLAUS
Publication of US20100210188A1 publication Critical patent/US20100210188A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B41/00—Component parts such as frames, beds, carriages, headstocks
    • B24B41/06—Work supports, e.g. adjustable steadies
    • B24B41/067—Work supports, e.g. adjustable steadies radially supporting workpieces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping

Definitions

  • the invention relates to a carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers.
  • the invention also relates to a method for the double-side polishing of semiconductor wafers in which the carrier is used.
  • the production of semiconductor wafers for use as substrates for producing electronic components regularly comprises at least one double-side polishing of the semiconductor wafers, which is carried out in one step and hereinafter is called DSP.
  • DSP a semiconductor wafer is situated together with further semiconductor wafers between upper and lower rotating polishing plates that are covered with polishing cloth.
  • Carriers having cutouts in which the semiconductor wafers lie, guide and hold the semiconductor wafers during polishing.
  • the carriers have on their periphery, an outer toothing by means of which they are rotated as planetary gears of a planetary gear mechanism about their own axis and the axis of the polishing plates during polishing.
  • the semiconductor wafers are polished in the presence of polishing agent that is supplied from the upper polishing plate and is distributed on the polishing cloths. It is necessary to ensure that both sides of the semiconductor wafer are sufficiently supplied with polishing agent in order that a uniform polishing material removal is obtained.
  • the sufficient supply of polishing agent is particularly important if polishing is effected by means of a polishing machine of compact design. This type of machine accommodates only one carrier, which extends over the entire lower polishing plate, and the polishing plates and the carrier have a common axis of rotation.
  • EP 1 676 672 A1 proposes improving the supply of polishing agent to the lower polishing plate by at least 15% of the area of the carrier being occupied by holes that provide the polishing agent with a passage to the lower polishing plate.
  • the inventors of the present invention have determined, however, that a quantitively sufficient supply of polishing agent to the lower polishing plate is admittedly necessary, but does not necessarily counteract all faults of the edge geometry.
  • the edge roll-off is described in SEMI standard M69 as a surface deviation in the edge region of semiconductor wafers having a large diameter. Since more and more area of a semiconductor wafer is being qualified for the production of electronic components and the edge exclusion in present-day extremely high quality semiconductor wafers is only 1 mm, there is a growing interest in reducing geometry faults in the edge region. Standardized parameters, for example the ESFQR defined in the SEMI standard, are available for quantitively describing such geometry faults.
  • a carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during polishing, wherein some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged on a path which lies at a distance of 1 to 10 mm concentrically around the cutouts and has an inner section, an outer section and two sections between the inner and outer sections.
  • FIG. 1 shows a carrier representing the prior art.
  • FIG. 2 shows a carrier according to the invention in a first embodiment.
  • FIG. 3 shows a carrier according to the invention in a second embodiment.
  • FIG. 4 shows a carrier according to the invention in a third embodiment.
  • FIGS. 5 and 6 show the different effect which a carrier according to the invention has on the edge geometry of a semiconductor wafer after a DSP in comparison with a carrier associated with the prior art.
  • the carrier according to the invention has not only the customary passage openings for polishing agent, but also those which are positioned in accordance with this insight. It can be used together with others in a polishing machine with a planetary gear mechanism or by itself in a polishing machine of compact design.
  • the carrier is composed preferably of steel, plastic or ceramic, most preferably of hardened steel and is provided, if appropriate, with a low-abrasion and low-friction coating.
  • the cutouts for receiving semiconductor wafers are lined with plastic in the customary manner in order to protect the sensitive wafer edge, preferably with inlays having cutouts at regular distances of 5 to 30 mm.
  • inlays having cutouts at regular distances of 5 to 30 mm.
  • a particularly preferred form of inlays is described for example in DE 100 18 338 C1.
  • the passage openings for polishing agent which are arranged away from the cutouts can in principle be shaped as desired. Openings having a periphery in the shape of rounded triangles and quadrangles or of circles are preferred. Passage openings such as are described in DE 102 47 200 A1 are particularly preferred.
  • the carrier in accordance with FIG. 1 which represents the prior art, comprises cutouts 1 for receiving semiconductor wafers and relatively large passage openings 2 for a polishing agent supplied during the polishing.
  • the carrier embodied according to the invention in accordance with FIG. 2 differs from that shown in FIG. 1 essentially by virtue of a ring of smaller passage openings composed of holes 3 .
  • the holes have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the distance denotes the shortest distance between the hole edge and the edge of the cutout without taking account of an inlay.
  • the midpoints of the holes lie on a concentric circular path around the cutouts. In accordance with the first embodiment of the carrier, this circular path is completely occupied by the holes. Further embodiments provide for the holes to form a ring that is open in one section.
  • the circular path is regarded as subdivided into four sections having an approximately identical length, it is possible to differentiate between holes 3 a arranged on an inner section, holes 3 b arranged on an outer section, and holes 3 c and 3 d arranged on two central sections lying between the inner and outer sections.
  • the holes are not arranged around the entire circumference of the circular path. This is because the inventors have discovered that occupying the central sections with holes already suffices to obtain a significantly smaller edge roll-off, particularly if the carrier is used as a planetary gear.
  • the additional arrangement of holes on the inner and/or the outer section primarily increases the stiffness of the carrier. Accordingly, the holes in the case of the carrier in accordance with the second embodiment are arranged on the central sections and additionally on the outer section.
  • holes are arranged on the two central sections and on the inner section of the circular path.
  • the distance between adjacent holes of a section is 3 to 30 mm and is preferably always the same, including between two adjacent holes of adjacent sections.
  • FIG. 5 and FIG. 6 show the surface contour of the front side of two of the polished semiconductor wafers, plotted as distance A along the diameter D.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

The invention relates to a carrier for holding semiconductor wafers during a double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing. Some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and an inner or an outer section of a circular path.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to German application DE 10 2009 009 497.0 filed Feb. 18, 2009, which is herein incorporated by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers. The invention also relates to a method for the double-side polishing of semiconductor wafers in which the carrier is used.
  • 2. Background Art
  • The production of semiconductor wafers for use as substrates for producing electronic components regularly comprises at least one double-side polishing of the semiconductor wafers, which is carried out in one step and hereinafter is called DSP. During DSP, a semiconductor wafer is situated together with further semiconductor wafers between upper and lower rotating polishing plates that are covered with polishing cloth. Carriers, having cutouts in which the semiconductor wafers lie, guide and hold the semiconductor wafers during polishing. The carriers have on their periphery, an outer toothing by means of which they are rotated as planetary gears of a planetary gear mechanism about their own axis and the axis of the polishing plates during polishing. The semiconductor wafers are polished in the presence of polishing agent that is supplied from the upper polishing plate and is distributed on the polishing cloths. It is necessary to ensure that both sides of the semiconductor wafer are sufficiently supplied with polishing agent in order that a uniform polishing material removal is obtained. The sufficient supply of polishing agent is particularly important if polishing is effected by means of a polishing machine of compact design. This type of machine accommodates only one carrier, which extends over the entire lower polishing plate, and the polishing plates and the carrier have a common axis of rotation. In this case, a lack of polishing agent has the effect that the semiconductor wafer is restricted in its mobility with regard to the rotation about its own axis to an extent such that accumulated frictional heat brings about increased material removal in a partial region of the edge of the semiconductor wafer and a semiconductor wafer having a wedge-shaped edge section thus arises. In order to prevent this, EP 1 676 672 A1 proposes improving the supply of polishing agent to the lower polishing plate by at least 15% of the area of the carrier being occupied by holes that provide the polishing agent with a passage to the lower polishing plate.
  • The inventors of the present invention have determined, however, that a quantitively sufficient supply of polishing agent to the lower polishing plate is admittedly necessary, but does not necessarily counteract all faults of the edge geometry. This applies in particular to the so-called edge roll-off, which concerns the entire wafer edge and is observed after DSP. The edge roll-off is described in SEMI standard M69 as a surface deviation in the edge region of semiconductor wafers having a large diameter. Since more and more area of a semiconductor wafer is being qualified for the production of electronic components and the edge exclusion in present-day extremely high quality semiconductor wafers is only 1 mm, there is a growing interest in reducing geometry faults in the edge region. Standardized parameters, for example the ESFQR defined in the SEMI standard, are available for quantitively describing such geometry faults.
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide means with the aid of which the edge roll-off after DSP can be significantly reduced, and a semiconductor wafer having an advantageous edge geometry becomes available. These and other objects are achieved by means of a carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during polishing, wherein some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged on a path which lies at a distance of 1 to 10 mm concentrically around the cutouts and has an inner section, an outer section and two sections between the inner and outer sections.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a carrier representing the prior art.
  • FIG. 2 shows a carrier according to the invention in a first embodiment.
  • FIG. 3 shows a carrier according to the invention in a second embodiment.
  • FIG. 4 shows a carrier according to the invention in a third embodiment.
  • FIGS. 5 and 6 show the different effect which a carrier according to the invention has on the edge geometry of a semiconductor wafer after a DSP in comparison with a carrier associated with the prior art.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
  • The inventors have discovered that access for the polishing agent to the lower polishing plate, which is situated near to the wafer edge and is arranged at a uniform distance at the wafer edge, makes a significant contribution to reducing edge roll-off. Therefore, the carrier according to the invention has not only the customary passage openings for polishing agent, but also those which are positioned in accordance with this insight. It can be used together with others in a polishing machine with a planetary gear mechanism or by itself in a polishing machine of compact design.
  • The carrier is composed preferably of steel, plastic or ceramic, most preferably of hardened steel and is provided, if appropriate, with a low-abrasion and low-friction coating.
  • The cutouts for receiving semiconductor wafers are lined with plastic in the customary manner in order to protect the sensitive wafer edge, preferably with inlays having cutouts at regular distances of 5 to 30 mm. A particularly preferred form of inlays is described for example in DE 100 18 338 C1.
  • The passage openings for polishing agent which are arranged away from the cutouts can in principle be shaped as desired. Openings having a periphery in the shape of rounded triangles and quadrangles or of circles are preferred. Passage openings such as are described in DE 102 47 200 A1 are particularly preferred.
  • The invention is explained in more detail below with reference to figures.
  • The carrier in accordance with FIG. 1, which represents the prior art, comprises cutouts 1 for receiving semiconductor wafers and relatively large passage openings 2 for a polishing agent supplied during the polishing.
  • The carrier embodied according to the invention in accordance with FIG. 2 differs from that shown in FIG. 1 essentially by virtue of a ring of smaller passage openings composed of holes 3. The holes have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the distance denotes the shortest distance between the hole edge and the edge of the cutout without taking account of an inlay. The midpoints of the holes lie on a concentric circular path around the cutouts. In accordance with the first embodiment of the carrier, this circular path is completely occupied by the holes. Further embodiments provide for the holes to form a ring that is open in one section. If the circular path is regarded as subdivided into four sections having an approximately identical length, it is possible to differentiate between holes 3 a arranged on an inner section, holes 3 b arranged on an outer section, and holes 3 c and 3 d arranged on two central sections lying between the inner and outer sections.
  • In the case of the carrier in accordance with the second embodiment, which is illustrated in FIG. 3, the holes are not arranged around the entire circumference of the circular path. This is because the inventors have discovered that occupying the central sections with holes already suffices to obtain a significantly smaller edge roll-off, particularly if the carrier is used as a planetary gear. The additional arrangement of holes on the inner and/or the outer section primarily increases the stiffness of the carrier. Accordingly, the holes in the case of the carrier in accordance with the second embodiment are arranged on the central sections and additionally on the outer section.
  • In the case of the carrier in accordance with the third embodiment, which is illustrated in FIG. 4, holes are arranged on the two central sections and on the inner section of the circular path.
  • The distance between adjacent holes of a section is 3 to 30 mm and is preferably always the same, including between two adjacent holes of adjacent sections.
    • EXAMPLE
  • Semiconductor wafers composed of silicon having a diameter of 300 mm were polished on a DSP machine of the AC2000 type from the manufacturer Peter
  • Wolters under the same conditions, and the edge roll-off was examined. Carriers in accordance with a first embodiment of the invention were used in one experiment, and carriers embodied in accordance with the illustration in FIG. 1 were used in a comparative experiment.
  • FIG. 5 and FIG. 6 show the surface contour of the front side of two of the polished semiconductor wafers, plotted as distance A along the diameter D.
  • In the case of the semiconductor wafer polished according to the invention, the surface contour of which wafer is illustrated in FIG. 5, virtually no edge roll-off is discernable. By contrast, a semiconductor wafer polished in accordance with the comparative experiment, the surface contour of the wafer being illustrated in FIG. 6, exhibits a pronounced edge roll-off The ESFQR, measured taking account of an edge exclusion of 1 mm, was particularly low in the case of semiconductor wafers polished according to the invention. Measurements on a multiplicity of semiconductor wafers polished according to the invention showed that the ESFQRmax, that is to say the ESFQR in the sectors having the worst edge geometry, varied within the range of 100 to 170 nm.
  • While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.

Claims (8)

1. A carrier for holding semiconductor wafers during double-side polishing of the semiconductor wafers, comprising cutouts for receiving the semiconductor wafers and passage openings for a polishing agent supplied during the polishing, wherein some of the passage openings are formed by holes which have a diameter of 2 to 8 mm and are arranged at a distance of 1 to 10 mm around the cutouts, wherein the holes are arranged on two central sections and on at least one of an inner or an outer section of a circular path.
2. The carrier of claim 1, wherein the holes have an identical distance between holes of 3 to 30 mm.
3. The carrier of claim 1, wherein the holes are arranged on the central sections and additionally on the outer section and the inner section of the circular path.
4. The carrier of claim 2, wherein the holes are arranged on the central sections and additionally on the outer section and the inner section of the circular path.
5. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 1, during double-side polishing.
6. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 2, during double-side polishing.
7. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 3, during double-side polishing.
8. A method for the double-side polishing of semiconductor wafers, wherein the semiconductor wafers are held in a carrier of claim 4, during double-side polishing.
US12/692,685 2009-02-18 2010-01-25 Carrier For Holding Semiconductor Wafers During A Double-Side Polishing Of The Semiconductor Wafers Abandoned US20100210188A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009009497.0 2009-02-18
DE102009009497A DE102009009497A1 (en) 2009-02-18 2009-02-18 Runner disk for holding conductive disks during reciprocal polish, has recesses for supporting conductive disks and depressing openings for polishing agent supplying polish

Publications (1)

Publication Number Publication Date
US20100210188A1 true US20100210188A1 (en) 2010-08-19

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US12/692,685 Abandoned US20100210188A1 (en) 2009-02-18 2010-01-25 Carrier For Holding Semiconductor Wafers During A Double-Side Polishing Of The Semiconductor Wafers

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US (1) US20100210188A1 (en)
KR (1) KR20100094333A (en)
DE (1) DE102009009497A1 (en)
SG (1) SG164311A1 (en)
TW (1) TW201032272A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140008768A1 (en) * 2011-04-26 2014-01-09 Shin-Etsu Handotai Co., Ltd. Semiconductor wafer and manufacturing method thereof
JP2014195119A (en) * 2011-09-15 2014-10-09 Siltronic Ag Method for double-side polishing of semiconductor wafer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105666312B (en) * 2016-01-21 2017-08-01 苏州新美光纳米科技有限公司 Chip fast polishing device and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020115387A1 (en) * 2000-12-07 2002-08-22 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Double-side polishing process with reduced scratch rate and device for carrying out the process
US6793837B2 (en) * 2001-07-05 2004-09-21 Siltronic Ag Process for material-removing machining of both sides of semiconductor wafers
US20060178089A1 (en) * 2003-03-20 2006-08-10 Shin-Etsu Handotai Co., Ltd. Wafer-retaining carrier, double-side grinding device using the same, and double-side grinding method for wafer
US20080166952A1 (en) * 2005-02-25 2008-07-10 Shin-Etsu Handotai Co., Ltd Carrier For Double-Side Polishing Apparatus, Double-Side Polishing Apparatus And Double-Side Polishing Method Using The Same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000271858A (en) * 1999-03-24 2000-10-03 Sanko Spring Kk Carrier for lapping
DE10018338C1 (en) 2000-04-13 2001-08-02 Wacker Siltronic Halbleitermat Process for the production of a semiconductor wafer
DE10247200A1 (en) 2002-10-10 2004-04-29 Wacker Siltronic Ag Process for simultaneously removing material on both sides of one or more semiconductor wafers comprises using a plate which has chemically inert abrasion- and adhesion-resistant coating in partial regions on the front and rear sides

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020115387A1 (en) * 2000-12-07 2002-08-22 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag Double-side polishing process with reduced scratch rate and device for carrying out the process
US6793837B2 (en) * 2001-07-05 2004-09-21 Siltronic Ag Process for material-removing machining of both sides of semiconductor wafers
US20060178089A1 (en) * 2003-03-20 2006-08-10 Shin-Etsu Handotai Co., Ltd. Wafer-retaining carrier, double-side grinding device using the same, and double-side grinding method for wafer
US20080166952A1 (en) * 2005-02-25 2008-07-10 Shin-Etsu Handotai Co., Ltd Carrier For Double-Side Polishing Apparatus, Double-Side Polishing Apparatus And Double-Side Polishing Method Using The Same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140008768A1 (en) * 2011-04-26 2014-01-09 Shin-Etsu Handotai Co., Ltd. Semiconductor wafer and manufacturing method thereof
US9076750B2 (en) * 2011-04-26 2015-07-07 Shin-Etsu Handotai Co., Ltd. Semiconductor wafer and manufacturing method thereof
TWI501304B (en) * 2011-04-26 2015-09-21 Shinetsu Handotai Kk Semiconductor wafers and methods for manufacturing the same
JP2014195119A (en) * 2011-09-15 2014-10-09 Siltronic Ag Method for double-side polishing of semiconductor wafer

Also Published As

Publication number Publication date
TW201032272A (en) 2010-09-01
DE102009009497A1 (en) 2010-07-08
KR20100094333A (en) 2010-08-26
SG164311A1 (en) 2010-09-29

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Owner name: SILTRONIC AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROETTGER, KLAUS;HEIER, GERHARD;SIGNING DATES FROM 20100109 TO 20100112;REEL/FRAME:023837/0324

STCB Information on status: application discontinuation

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