TW201027724A - Depletion-mode charge-trapping flash device - Google Patents

Abstract

A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating later on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

Description

201027724 VI. Description of the Invention: [Technical Field] The present invention relates to a charge trap memory device including a charge trap memory device for use in a flash configuration. [Prior Art] Flash memory is a non-volatile integrated circuit memory. The memory system uses floating gate memory cells. As the memory device = the gate of the memory cell is close to the source, the problem is stored in the phase-moving gate, thus forming a limitation, so that the fast flash density of the floating open is not improved. Another - == cell;; charge trapping memory cell, which uses electricity 2 = ,, and mobilization pU: captures 5 cell memory cells using charge trapping material 'will not interact as a cell' and can be applied The typical transistor (FET) structure 'surge and * = wire and record' and borrow & dielectric material M away from the gate. Wherein the dielectric material comprises a tunneling dielectric g layer, the immersion and the channel are formed on the (s), the (N), the barrier dielectric: 2) the upper J storage layer is formed of tantalum nitride Shi Xi (8). This type of =8 oxygen: =) forms 'and the closed-pole is polycrystalline to enter the 仃 program, or the electric tunnel, electron release 3 201027724 One of the research directions of charge trapping memory cells is the NAND type structure. For example, the related research is Shin e. al., "A Highly Reliable SONOS-type NAND Flash Memory Cell with A1203 or Top

Oxide" IEDM, 2003 (MANOS) and Shin et al" "A Novel NAND-type MONOS Memory using 63nm Process

Technology for a Multi-Gigabit Flash EEPROMs,,, IEEE 2005. In the NAND type structure, the memory cells are arranged in a sequence, so the current of reading data can flow through a series of memory cells. This path through the memory cell limits the size and speed of the current-flow and also affects the efficiency of the read operation. 10 The inventor of this case has been involved in the study of charge trapping memory, which uses bandgap engineered charge trapping technology called BE-SONOS. Various embodiments of BE-SONOS memory cells can be found in U.S. Patent No. 7,426,440 B2 (Lue) and U.S. Patent Publication No. 2007/0029625 (Lueetal.^BE-SONOS is characterized by the ability to prevent charge tunneling in the case of relatively low electric fields. Very efficient tunneling can be achieved in the case of medium to high electric fields. BE-SONOS has the characteristics of durability and stability. At the same time, the following two documents have also suggested the use of BE in FinFET non-volatile memory. -SONOS technology: U.S. Patent Publication No. 2008/0087946 (Hsu et al.) and U.S. Patent Publication No. 2008/0087942 (Hsu et al.) One of the common problems with charge trapping devices is that they are faster than floating gate NAND. In terms of flash, the 'memory interval is usually upwards toward a positive Vt offset, and because this design requires a higher pass gate voltage, the circuit design is difficult. It has been used such as high work function gates and other techniques to make the wipe In addition to the sorrowful § recall interval is negative, however, this tendency in the higher critical class operation 4 201027724 will still cause problems. ▲ ▲ therefore generate demand, hoping to provide a way to improve NAN The structure of the D structure is easy to fabricate the dielectric charge to capture the memory cell. SUMMARY OF THE INVENTION The present invention discloses an integrated circuit memory device including a charge trap memory, which is similar to the finFET configuration and has a doping The buried channel area can be operated in a depleted mode. Therefore, for n-channel memory cells,

The buried channel has an n-type dopant to establish a normally "on" state for the memory cell. A charge trapping structure over the buried channel can store charge to induce one or more high threshold voltage states having a positive threshold voltage vT with a low critical state of a negative threshold voltage Vt (e.g., typically on). The structure can be completed using a "no-junction" configuration in which the buried channel region extends as a continuous region across a plurality of memory cells, and interferes with a source/drain region having a higher doping concentration. Alternatively, a source/drain region region can be used. Due to the design of the buried channel, in the conventional dielectric charge trapping memory cell, the state in which the threshold voltage Vt is shifted upward is compensated. Therefore, the memory cells disclosed herein can be applied to NAND flash memory. ^ The basic memory device disclosed herein comprises a plurality of body lines on a substrate, the semiconductor lines comprising doped buried channel regions that are operable in a depleted mode. a storage structure is disposed over the plurality of semiconductor lines, a tunneling insulating layer on the channel region of the fin, a charge storage layer on the tunneling layer, and a charge storage layer on the charge storage layer The barrier is over $layer. The complex digital element line is located above the storage structure and spans the semiconductor line 5 201027724 2 wherein a plurality of memory cells are located at the word line and the semiconductor line ^ ^ point. In the substrate close to it, that is, the solid conductor two conductor body like the finFET and the plurality of semiconductor wires

The buried channel region has the opposite conductivity. The H-line of the buried channel can be isolated from the substrate. The H-line can be read by the insulating structure or other squares. H is exposed. The memory cell contains NAND memory cells. The φ material extends and has a -end ridge, wherein the fin-shaped double-end ridge is located thereon and/or on the side of the ridge or is available for the vacant = track region. The shout channel is doped with an n-type dopant , operation, complex memory cell gate (for example, on the buried channel region where one of the fin lines is raised at the end of the word line, the charge is two-r--memory cell gate and the last memory cell gate. Under the dielectric gate ^ More than one (for example, 16 and 32) memory cells: what capture position contains multiple layers of wear-insulating structures, - the charge is placed on the current storage structure with the insulation structure and - the barrier insulation layer is set to φ and The first memory cell has a space between the poles, and there is a p-channel region at the end of the turn and the ridge. The electric radiation is the only way to strengthen the band, and the private supply is used to erase the mode material! The reinforced insulator is characterized by a valence band containing a plurality of materials. And the right drawing / the surface is less than 2 nm, the first distance == the valence band energy level, and the first distance of the surface of the channel region has a reduced valence band energy level. According to 6 201027724 An embodiment capable of processing an insulator, the combination of materials comprising a ruthenium oxide underlayer having a thickness of less than 2 nm, a tantalum nitride intermediate layer having a thickness of less than 2.5 nm, and an oxidized oxidized top layer having a thickness of less than 2,5 nm. Advantages will be described in detail in the following figures, embodiments and patent claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed embodiment of the present invention will be described with reference to Figs. 1 to 7 of the drawings. Figure 1 is a schematic cross-sectional view taken along the fin of a semiconductor body having four strings of memory cells located at the intersection of the key lines 15, 16, 17, 18. The fin is lightly bonded to the base edge' in this embodiment the substrate is p-type. The Hei ridge of the fin has a buried channel region u. Depletion mode operation. Therefore, in the n-channel memory cells, the burial is passed through two t; A typical n-type channel doping is about + to 1 x 10 cm, while the depth of the n-type channel is large. The channel U is isolated by the higher doped isolation region of the fin neck. A plurality of word lines 15, 16 f are covered by an interlayer dielectric 20. The word lines 15, 16, 17, 18: are formed of P+ type polysilicon, or the basin 18 is preferably: line 5, 17, 18 and buried channel area 9:: in the word 'buried channel area surface cell Can be formed at the intersection and point. Herein, the memory _N〇 structure includes a memory structure of 7 201027724 tunneling insulating layer (ΟΝΟ), a tantalum nitride charge trapping layer, and a yttria barrier layer. Further details of the preferred embodiment of the electrospray storage structure can be found in Figure 6 and later. In the first figure, the length of the gate is denoted L, which may correspond to the width of the word line, which in the preferred embodiment is a very small size; the representative gate length is between 30 nm and 10 nm. Although the storage structures (e.g., 19) are illustrated as separate stacks in the figures, other embodiments may be continuous overlays. FIG. 2 is a schematic cross-sectional view of a fin of a plurality of semiconductor bodies, which in this embodiment includes four fins 1 (M, 1〇_2, 1〇_3, and 1〇_/. - In the example shown, the fin is also referred to as the body contact (b kiss), and the edge is joined to the underlying substrate 10|. The neck region 12 of the fin has 13 = doping' thereby suppressing the parasitic device Formed between the continuations on the substrate 1 。. As shown, the word read 15 is located on the upper edge of the charge storage structure 19, and the trenches 21, 22, 23 separate the individual fins 1 (Μ, 1〇_2 In the case of 1〇3 blood, the 'width of the object is denoted by w' in the preferred embodiment/in centimeter, between about 3 〇 nm and 5 〇 nm. The f of the buried channel region is about 3 〇 nm. The thickness of the insulating trench is indicated as = 〇 nm = grade, which extends beyond the surface of the insulating trench "^ 30 thin, and its 3 is below the surface of the insulating trench _ in the buried channel region with the n-type dopant "10% 3 to 10% η3, and the insulating doping concentration is 2x10i8cm3. However, the representative doping concentration of the 邑 margin domain is about another alternative embodiment, which can be isolated by Shape A half-line layer separated from the substrate 1G will provide a circuit layout frame for the flash memory array of the NAND structure. FIG. 3 is a schematic diagram of the above-mentioned buried channel device. In this circuit layout, vertically arranged The semiconductor lines 10-1, 10-2, and 10-3 in Fig. 1 and HM are cross-sectional views of the line segment la in the third figure. Fig. 2 is a cross section of the line pair 2a to 2b in Fig. 3. Figure.

The complex digital element lines WL1 to WL32 are overlaid on the plurality of fins, wherein the word lines 1W32, W31 and W30 are numbered 15, 16, 17, which correspond to the structures similar to those of Figs. 1 and 2. The memory cell 60 is formed at the intersection of the word line W32 and the semiconductor line 1〇_2. Figure 3 illustrates a string select line SSL25 and a ground select line GSL26 on the opposite side of the complex digital line WL1 to WL32. In the preferred embodiment, the channel region under the SSL 25 and GSL 26 is p-type, so that the electro-crystalline system at the intersection of the fins with the SSL 25, GSL 26 (e.g., the illustrated elements 61, 62) operates in an enhanced mode, It has a positive threshold voltage Vt. The semiconductor lines are coupled to the opposite sides of the SSL 25 and GSL 26 by via holes (not shown) and upper (or lower) bit lines and ground lines, respectively. During the fabrication process, additional masks (including areas 3〇, 31) can separate the n-type doping of the channel region from the channel region under the SSL· and GSL lines and the memory cell, while allowing the gate oxide The shape of the job 0 is in the maintenance structure (different from the data storage structure 19), for example, it can be a single layer of oxidation or $th gate insulator. It is also possible to extend the chemical in the SSL and GSL transistors. The structure of the structure and the data stored in other examples. (5) The use of p-type doping in the gas/SSL laser can be selected in series: relatively high The critical voltage ντ. No-doping, in the junction 40 of the gate 40, FIG. 4 is a cross-sectional view of another embodiment of the semiconductor line, L in the buried channel region 45' between the gates 40, 4b 42 to enhance the conductivity of the semiconductor line Sex. As the first! Figure 9: 201027724 In an embodiment, the fin with body contact includes a neck region 36 having a P+ doping to separate the buried channel region 37 from the underlying substrate 35. However, the jointless structure as described in Fig. 1 does not require the use of the implant in some embodiments because the conductivity of the buried via region is sufficient for the high efficiency operation of the NAND memory cell. A fin dy-tied finFET structure having a body contact can be fabricated in accordance with US Patent Publication No. 2008/0087942, entitled "Vertical Channel Memory and Manufacturing Method Thereof and Operating Method Using the Same According to a process embodiment, a substrate may be provided first, and then a first layer of tantalum nitride is formed on the tantalum nitride. The substrate is arranged such that the P-type substrate is fitted with an n-type channel device and the n-type substrate is fitted with a p-type channel device. In another embodiment, a pad layer may be formed between the substrate and the first layer of tantalum nitride. The lithography process forms a pattern on the ninth layer of the nitrite layer. For example, the line of vaporization ♦ can be defined on the substrate, and the i line is 遮 with respect to the mask of the fin. Preferably, the nitriding lines 2 are trimmed by an anisotropic method or by other means to form a ruthenium=4' with a tantalum nitride line as an etch mask, and the substrate is etched into a number of recorded objects' In the last part of the secret part, there is a line of oxide pads. The true f is deposited between the ridges and fills the fins: at the same time, the lines of oxide 塾 and nitriding dreams are

Partially divided. In another embodiment, the oxide 塾' of the 〇 可 which can retain the fin L is defined as the channel region of the side of the sister near the end (four) portion. In the case of ', the shape of the scorpion' contains the oxidized stone eve, the nitrite eve, " covers a plurality of fins. The word m material layer (eg, 201027724 t曰曰:) is formed over the ONONO overlay layer, and then the word line layer is etched to define a word line that spans the plurality of fins and is created at the point of intersection Complex memory cells. In order to cause more obvious doping characteristics, the implantation step before forming the 〇n〇n〇 layer, or before depositing the oxide pad and the first tantalum nitride acoustic shape f In-situ doping is used: = The f-channel region can be formed by a lightly doped structure that extends along the ridge portion of the fin end. In another implementation, the radiation can be made into (10) 0N0 ❹ = row doping. After forming the (10)(10)0 cover layer, the implant has a lower thermal budget, and also has better doping. The fifth figure is the intention of two NAND strings. The SSL transistor 75 controlled by the SSL line is lightly coupled to the bit 3 BL-i. The memory cells 76-1 to 76_N are lightly connected in series, = the line 1 WU is controlled. The ground selection transistor ^ = i N forms a second series which is coupled by an SSL transistor 85;, 丨:=2. Ground select transistor 87 couples the second NAND string to source line SL. U string n 纠 状 料 " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " The function of the bit line: = : work = note; the voltage through the gate is low. In addition, in some cases, the characteristics of the second purchase can be improved. The bungee junction. If the f 4_ shows the additional source / 11 201027724 The stylized bias arrangement is shown in the figure and can be generated and applied to the integrated circuit structure as shown in the figure. The stylized bias is not required to be programmed. It is spontaneously doped with junctions. And the serious influence of the leakage current at the joint point. It is quite difficult to adjust the "well and the characteristics of the joint to achieve the memory effect; 4: the balance between performances". Therefore, it is not the spontaneous technology described in the previous section (it must use deep space to facilitate the spontaneous channel device, which can easily raise the bit line potential, because the n-type channels are all connected together. Therefore, it is a stylized memory cell. For example, the memory 诸 is in the word line WL7 ', for example, about "L: ΐϋϊ, the application time is about 2 〇 _. The bit line bl_i, the ground line. The passive VS VPASS is applied to the string all other, and the SSL line, The voltage is about 5V to 9VqGsl, the line is grounded, and the f source line is kept floating. The semiconductor body p-type well (Bu(10)) is also connected to the I. The bit line BL-2 is coupled to a suppression voltage, for example From the direct rumor to the memory cell (5) to the suppression voltage of the touch. The memory cell 86_7 that accepts the word line and = stylized voltage is the most appealed. Even after the end of the stylized interference, the memory cell is still 2 〇: The threshold voltage 'saves the read space required for the memory cell. The borrower's gentleman's road: Changlu's buried channel technology 'pass voltage can be reduced, and the conductivity of the string can be improved', thereby making the I set can have a lower Operational electric-green removal*bias In the above structure, it includes - the word crossing the memory cell =, ^ /, the negative bias of a conductor body 'which is about -14V to -18V, and the time for applying the dust is about 1 〇ms. The memory cell of the 疋 is applied. The relatively low pass power (such as low 12 201027724 at 5V) on the unselected word line, SSL· and GSL·. The read bias is applied to the selected word line. It is between the critical state of the memory cell. The first diagram is a simplified schematic diagram of the buried channel of the dielectric tunneling layer and the trapped mode charge trapping 5 cells. The memory cell contains a channel 90, which contains a light Doped material (on the order of 5E17cm_3) or undoped material, located in a relatively heavily doped 卩-type well to block the parasitic leakage path in a p-type semiconductor body (on the order of 1E17enf3), and the source 91 and 汲The region of the pole 92 is also n-type or undoped and is connected to the pass

Road. The gate 98 in this embodiment includes ρ+ polysilicon, and Ν+polysilicon can also be used. The gate 98 of other embodiments may utilize a metal, a metal compound, a metal composition, or a combination of a metal and a metal compound such as platinum, tantalum nitride, metal telluride, aluminum or other metal or metal compound gate material. In some applications, the preferred embodiment employs materials having a work function greater than 4.5 eV. U.S. Patent 6,912,163 provides a variety of high work function materials which are suitable for use in the gate terminal herein. These materials are usually mixed or deposited by CVD, and can be applied to the surface of the ion-reactive layer. The dielectric tunneling layer contains a composite material, including the first composition of yttrium oxide. Layer 93, also referred to as a tunneling layer, is located above surface 90a of I = , for example, a wide- and selective-selective liquefaction, which is deposited after use or when deposited Add a NO environment. The dioxin-layer % & is less than 20 angstroms, and in the preferred embodiment is less than 13 angstroms. a thin layer 94 composed of an oxygen vapor deposited tantalum nitride layer, also referred to as a first layer 93 of a band-compensating layer fossil, which is formed, for example, by a low pressure 13 201027724 LPCVD, for example, utilizing Dioxane (DCS) 盥 _ precursor in 68 (TC environment. In another process example / band compensation layer contains bismuth oxynitride, which uses a similar process with n2 〇 precursor. The thickness of 94 is less than 3G angstroms, preferably less than angstrom. The second layer 95, also known as the insulating layer, is located on the nitriding layer 94. Formed by a high temperature oxide ht〇 deposition such as LpcVD. The thickness of the second layer 95 of the oxidized oxide is less than about 3 angstroms, and in the preferred embodiment is less than 25 angstroms. The charge trapping layer 96 in this embodiment contains nitrogen. The ruthenium, which has a thickness greater than 50 angstroms, is about 70 angstroms in this embodiment, and is formed by a method such as LpcvD. Other charge trapping materials and structures can also be used, for example, it can be made of nitrogen oxides (SixOyNz), rich. Wei compound, rich 7 oxide, ^ capture layer containing buried nanoparticles, etc. The application number 2006/02614G41A1 discloses a variety of materials for the charge trapping layer, the name is r Novel Low Power Non-V〇latile Memory and Gate tack", the inventor is Bhattacharyya, the public day is 23 days. 'β 实例The resistive dielectric layer 97 comprises a dioxide dioxide, which utilizes a process, or both processes. The thickness of the film is about 70 angstroms. Another composite barrier layer may be used. In the present embodiment, the first layer 93 can be 311.311111, the second layer = the layer 94 can be 2 nm of nitride, and the insulating layer can be 2 5n^ The charge trapping layer 96 may be an 8 nm argon layer 97 which may be 7 nm of yttrium oxide. The gate material may be p+ polysilicon = 14 201027724. In such a multilayer structure, the interlayer is in contact with the channel and includes A combination of materials to establish a u-inversion energy that is relatively low in the valence band near the channel 11 domain - minus 丨 夕 ) ' ' ' 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 诵 诵It is. The valence band energy level (tantalum nitride) is increased, and the valence band energy level is lowered at a second distance from the second layer (for example, 3.3 nm) (the oxygen column is greater than the first distance. Other embodiments do not necessarily have The boundary layer of the boundary layer is still formed, but the U-shaped inversion valence band characteristic is still produced. Fig. 7 is a simplified schematic diagram of the integrated circuit with the buried channel array, which has the charge trapping memory cell disclosed in the present invention, such as the depletion mode. The FmFETBE_S〇N〇S NAND flash memory. The integrated circuit 165 includes a memory array 1_, which uses the non-volatile memory cell of the present invention, which is located above the semiconductor substrate. 16〇1 is coupled to the complex word line 1602, which is disposed along the horizontal array of the memory array. The memory cells described herein may be configured as a NAND array, and in other embodiments may also be configured as a NOR array. The SOI AND array, or other array structure. The row decoder 1603 is coupled to a plurality of bit lines 16〇4 that are arranged along the wales of the memory array 1600. The addresses can be provided by the bus bars 16〇5 to the row decoder 1603. And column decoder 1601. In block 1606 The amplifier and data input structure is coupled to the row decoder 16〇3 via data bus 1607. The data is passed from the input/output port to the integrated circuit 1650 via the data input line 1611, or from other internal or external sources. The body circuit 165A, to the data input structure in block 1606. The data is also passed through the data output line 1615, from the sense amplifier 1606 to the input/output port on the integrated circuit 1650, or to the data end point inside or outside the other integrated circuit. The bias adjustment state mechanism 1609 controls the voltage of the bias adjustment 1608. For example, the erase verification and the stylized verification voltage, and the bias for programming, erasing, and reading the memory cell 15 201027724 Pressure: Weekly, bias adjustment state The mechanism can apply a bias voltage to program with +FN, which includes a positive voltage between the gate and the channel, or a terminal located at one of the gate and the source and the pole (or both) a positive voltage that is sufficient to induce electron tunneling through the tunneling dielectric structure into the charge trapping structure. At the same time, the bias adjustment state mechanism can apply bias adjustment to utilize -FN tunneling for erasing, which includes a negative voltage between the gate and the channel, or a negative voltage between the gate and the terminal of one of the source and the drain (or both) to induce electricity The hole penetrates through the dielectric structure and enters the charge trapping structure. The array is combined with other modules on the integrated circuit, such as a processor, a memory array, a programmable logic, a dedicated logic, etc. The finFETBE-SONOS device of the depletion mode has been as described above. Compared with the conventional enhanced mode device of the flash memory, the device having the n-channel buried channel has an n-type top surface. Therefore, the threshold voltage VT is lowered, which is Operating normally in mode, it will reduce the critical distribution of erase and stylized states. The use of a structure similar to that of a corpse can enhance gate control while providing better dimensional effects. The buried channel device provides better read-current and overall conduction characteristics because the channel operates in a global inversion mode rather than in a conventional 増β-strong mode. In addition, the overall inversion is less sensitive to the corner edges of the MfmFET ends, so better consistency and less stylized and readable barriers are achieved. The depletion mode device disclosed herein can be applied to a junctionless embodiment that can be applied to smaller sizes, while at the same time because the channel is already n-type, there is no need to use additional implants between the word lines. In a NAND flash memory device, the device is typically erased to a negative voltage Vt and programmed into a positive voltage Vt. New empty mode (usually turned on) 16 201027724 Buried channel, no-connect n-channel flash memory device is exposed here. ^ NAND flash flashes the range of program and erase p/E % down to the range of traditional surface channel devices, while being more suitable for NAND flash memory devices. Since the starting VT is low, the device can exhibit a faster erasing speed and, at the same time, avoid reading interference. In addition, the buried channel device is greatly loaded, and the cycle endurance is less sensitive to the staging/wiping interface state (Dit). A lightly doped shallow (four) channel can also serve as a buried bit line and a source-level pole of a junctionless structure. Similar to the structure of the fmFET, the short channel effect can be overcome. Buried channel • ^Xia " flash memory uses the method of directly increasing the potential of the bit line, using the staging of the stylization, without the need for traditional spontaneous methods, induced deep space. The SONOS type '4's electric % capture structure is a preferred embodiment (for example, '^ Figure 6 shows the next generation of charge trapping device provided by the related description, which combines the fmFET-like structure to achieve perfection. ΠϊControl characteristics. The following describes some of the advantages of buried channel devices. (1) Faster erase speed to VT<〇V, while symmetric ντ distribution interval. Naturally easier due to lower starting voltage ντ The device is erased to ντ <ον. The rotation is in the electric system, and the wiping speed of such a device is usually lower than that of the floating-pole device. The distribution of ντ is low and buried in the device. More symmetrical, these features are conducive to the design of flash memory. (2) Large distribution boundaries: due to the lower starting VT, stylized and, except for interference (in the same underlying oxidation area Chengli time) More controllable; ντ<ον' is used for larger interference-free intervals. In addition, low gate 17 201027724 pole pass voltage (<5V) is also necessary for reading. == want to design: n Weizang The channel can be used as two τ = J, which connects all devices Therefore, there is no need to make additional joints between WLs. U , , , , 4 (4) No need for complex spontaneous stylization prohibits the joining of the joints with the _Wei. Refer to since == Big 7 :, Grasping 87, 鸠. At the same time, it is also subject to leakage. Therefore, it is necessary to strike a balance between the memory performance and the well/supplement that is carried out spontaneously. :甬; vacant to create a spontaneous traditional surface channel device, in the buried k device towel 'very (four) can be expected? η-type areas are connected. w匕, all of the extended component cycle endurance: the cycle capacity of the buried channel device is greatly improved. This is because the surface of the inverted channel is less sensitive to the surface state (Dit) produced after the cyclic stress. The fact that H increases VT after the P/E loop should be suppressed. In contrast to the typical surface channel device, the stylized/erased (Ρ/Ε) area of the buried channel device is parallel to the lower Vt (four). The lower ❹ start VT also increases the erase speed. At the same time, the Vt distribution of p/E is very symmetrical, and the low erased vT distribution provides a wider interference-free interval. In addition, the buried channel device described herein can be implemented by multi-level memory cells (MLC), so each device can store two bits or more of data, such that the erased state has a negative VT distribution, and the three or The above stylized state has a positive VT distribution. In the FinFET configuration, the domain channel device shows more component endurance than the surface channel mount 18 201027724. The buried channel device extends the high inversion electron density into the channel. The surface channel only has surface inversion. The buried channel device is less sensitive to the state density at the time of inversion. 1 t invention is better than the invention, the county is limited to these embodiments: various views, changes, and more, _, and the contents are 'obvious to those who are familiar with the technical field, neither It is out of the spirit and age of the present invention, that is, as claimed in the patent; jit. call

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a buried channel memory cell array disposed along a fin end ridge, which is taken from a junctionless embodiment, for example, along the third diagram. The line segment la_lb* is shown. Figure 2 is a schematic cross-sectional view of a buried channel memory cell shown across the fins. For example, it is depicted along line 2a-2b of Figure 3. Ο Figure 3 is a layout of a NAND array containing buried channel memory cells. Figure 4 is a cross-sectional view of another embodiment of a simplified buried channel memory cell array wherein the source/drain junctions are implanted between word lines. Figure 5 is a circuit diagram of two NAND strings using buried channel memory cells, showing a stylized bias arrangement. Figure 6 is a schematic cross-sectional view of a buried channel memory cell showing the data storage structure in the preferred embodiment of BE-SONOS. Figure 7 is a simplified block diagram of the 201027724 integrated circuit memory device including a buried channel array in which the ΒΕ-SONOS memory cell is placed in the NAND array. [Description of main component symbols] 10, 35: Substrate 10-1, 10-2, 10-3, 10-4: Fins 11, 37 · Buried channel area 12: Isolated areas 15, 16, 17, 18 : Word line 19: data storage structure 20: interlayer dielectric 21, 22, 23: insulating trench 25: selection line 26: ground line 30, 31: mask 36: neck region 40, 41, 42, 98 : Gate 44, 45: junction 60, 76, 86: memory cell 61, 62: intersection 75, 85, 87: transistor 90: channel 91: source region 92: drain region 93: hole tunneling layer 94: energy band with compensation layer 95 201027724 96 : charge trapping layer 97: barrier dielectric layer

Claims (1)

201027724 VII. Patent application scope A non-volatile memory device, comprising: a buried channel region, the doped wealth guide comprising a plurality of storage structures located in the plurality of semiconductors located in the plurality of buried channel regions The insulating layer is passed over the insulating layer to be transferred to a plurality of intersections of the body line. , " 二予兀线and these semi-guided guides 2 please = guidance == device, one of the shirts and extended to the resignation red ^. The ridge, which is integrated with the plurality of fins, wherein the channel region is 4. The doped region of the first domain is doped as a -th conductive crane, and the two channels are buried. The _: 3 == source/no-polar region of the opposite side of the word line is located at the source/drain region of the first guided lightning energy-, and the object has a first conductivity The doping of the type is higher than the buried channel region. 5. As stated in the device of paragraph j of the patent circumstance, wherein the layer is combined with the channel region of the _ memory cell to establish a relatively low valence band energy level at the surface of the surface at the same time The surface of the channel region is less than 2^22, the second valence band energy level, and the surface distance - the distance - the second distance at the second region of the channel region has a - reduced valence band energy level. The apparatus described in Item 12, further comprising - a specific Korean second, a livestock, a second body, the specific fin comprising an access transistor having n special fins, and Doping is performed in enhanced mode. The device of claim 1, wherein the plurality of memory cells are the device according to item 1, wherein the cells of the memory cells have n-type doping, and the concentration thereof is lower than lxl〇13/cm4. 5 6 7 8. The device of claim 9 further comprises a plurality of doped insulation layers between the (10)1 and lxl〇1W having a p-type doping at 9 Hz, and the substrate has a p-type doping The agricultural degree is located at ❹ 23 1 1. The device according to claim 1 of the patent application, further comprising a controller surface 2, a bias supply circuit, which can be operated-programmed, __ erased, ^, And the 3 dopants are used for the operation of the depletion mode; the miscellaneous n-type 4 ^ take operation 'the erase operation includes the application - the burial channel between the buried cell and the memory cell of the word line To initiate tunneling. /, 6 - an integrated circuit memory device, comprising: 7 - a semiconductor fin extending from a substrate and having an 8 . The fin comprises a buried channel along the end ridge, 201027724 plural The memory cell gate is disposed on the buried buried channel region bulging along the end of the binding body, and the plurality of memory cell gates comprise a first memory cell gate and a last memory cell gate, and are insulated The component isolates the gate of the series from the adjacent serial gate; the plurality of dielectric charge trapping locations are located under more than one of the plurality of serial memory gates, the dielectric charge trapping location comprising a plurality of a layer tunneling insulating structure, a charge storage layer is disposed over the tunneling insulating structure, and a barrier insulating layer is disposed over the charge storage layer; and a series of select gates is located at the end of the gate Above the ridge, it is separated from the first memory cell gate while having a P-type channel region located at the end of the fin. 13. The device of claim 12, wherein the substrate comprises a half conductor body' while the fin is integrated with the semiconductor body and extends outside of the semiconductor body. 14. The device of claim 12, further comprising a plurality of dopant source/drain regions over the fin, and a relative of the memory cell gates in the plurality of memory cell gates On the side, the plurality of dopant source/drain regions have n-type doping. The device of claim 12, wherein the multilayer tunneling insulating layer contacts a surface of the buried channel region and comprises a combination of materials that establish a relatively low valence band energy level Near the surface of the channel region, the surface has an increased valence band energy level at a first distance less than 2 nm of the surface of the channel region, and the surface in the channel region is greater than the first distance ^ A second distance has a reduced valence band energy level. 16. The device of claim 12, wherein the channel region has 24 201027724 n-type doping at a concentration of less than lxl 〇 i8 / cm 3 . 17. The device of claim 16, wherein the substrate comprises a p-type semiconductor body while the fin is integrated with the semiconductor body and extends outside the semiconductor body and comprises doping The insulating region has a concentration in the fin between lxl〇17/cm3 and lxl〇!8/cm3, and the doped insulating region has a p-type impurity. 18. The device of claim 5, wherein the device comprises a controller and a bias bias supply circuit, the executable-programming operation is performed - the erase operation, the medical operation, the operation operation, and the erase operation The tunneling channel is applied to apply a negative voltage to the word line and select the 5 cells to initiate tunneling. ❹ 25