TWI556354B - Memory device and method of manufacturing the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

In general, problems such as Junction Leakage and Floating Gate Short are encountered in the manufacturing process of memory elements. The junction leakage is caused by the tunneling dielectric layer during the plasma etching process; the floating gate short circuit is due to the patterning word line (Patterning Word Line), the adjacent floating gate Caused by residual gate material. However, if an over-etching process is used to completely remove the gate material between adjacent floating gates, the tunneling dielectric layer is damaged, thereby increasing the risk of junction leakage. Therefore, the junction leakage and the floating gate short circuit are in a trade-off relationship (Trade Off), both of which are the key factors affecting the yield and reliability of the product.

The invention provides a memory element and a manufacturing method thereof, which can solve the problem of junction leakage and floating gate short circuit, thereby improving product yield and reliability.

The present invention provides a memory device comprising: a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The substrate has a plurality of first regions and a plurality of second regions. The first zone and the second zone extend along the first direction and alternate with each other along the second direction. The tunneling dielectric layer is on the substrate. The tunneling dielectric layer extends along the second direction and traverses the first and second regions. Each isolation structure has an upper portion and a lower portion. The lower portion of the isolation structure is located in the substrate and alternates with the tunneling dielectric layer along the first direction. The upper part of the isolation structure is located on the lower part. The top cover layer is located on the upper portion of the isolation structure. The top surface of the top cover layer is a flat surface.

In an embodiment of the invention, the top surface of the upper portion of each isolation structure is higher than the top surface of each of the tunnel dielectric layers. The bottom surface of the upper portion of each isolation structure is equal to the top surface of each tunneling dielectric layer.

In an embodiment of the invention, a plurality of first conductor layers, a dielectric layer and a second conductor layer are further included. The first conductor layer is on the tunneling dielectric layer of the second region. A dielectric layer overlies the first conductor layer. The second conductor layer is on the dielectric layer. The second conductor layer has a body portion and a plurality of extensions. The extension and the first conductor layer alternate with each other along the first direction.

In an embodiment of the invention, the upper portion of each of the isolation structures and the structure of the cap layer on the upper portion satisfy the following formulas (1) to (2): Formula (1): b ≤ a < c, 2): b ≥ 1/3 a, where a is the bottom width of each extension of the second conductor layer, b is the top surface width of each cap layer, and c is the bottom surface width of the upper portion of each isolation structure.

In an embodiment of the invention, the material of the cap layer comprises a high dielectric constant material or a combination of a high dielectric constant material and a low dielectric constant material.

The present invention provides a memory device comprising a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The tunneling dielectric layer is on the substrate. Each isolation structure has an upper portion and a lower portion. The lower portion of the isolation structure is located in the substrate and alternates with the tunneling dielectric layer along the first direction. The upper part of the isolation structure is located on the lower part. The top cover layer is located on the upper portion of the isolation structure. The top surface of the top cover layer is a flat surface.

In an embodiment of the invention, the top surface of the upper portion of each isolation structure is higher than the top surface of each of the tunnel dielectric layers. The bottom surface of the upper portion of each isolation structure is equal to the top surface of each tunneling dielectric layer.

In an embodiment of the invention, the upper portion of each of the isolation structures and the structure of the cap layer on the upper portion satisfy the following formulas (1) to (2): Formula (1): b ≤ c-2 × T1 < c, Formula (2): b ≥ , where T1 is the thickness of the cap layer, b is the top surface width of each cap layer, and c is the bottom face width of the upper portion of each isolation structure.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A plurality of stacked layers are formed on the substrate. Each stacked layer includes a tunneling dielectric layer and a first conductor layer. The first conductor layer is on the tunneling dielectric layer. A plurality of isolation structures are formed in the stacked layer and the substrate. The stacked layers are used as a mask to remove a portion of the isolation structure to form a plurality of openings in the stacked layers. The bottom surface of the opening is higher than the top surface of the tunneling dielectric layer. Forming a dielectric layer on the isolation structure and the stacked layer. A second conductor layer is formed on the isolation structure. With the second conductor layer as a mask, a portion of the dielectric layer is removed to form a cap layer that exposes the surface of the first conductor layer. The first conductor layer and the second conductor layer are removed to expose a top surface of the tunneling dielectric layer.

In an embodiment of the invention, in the step of removing a portion of the dielectric layer, the etching selectivity ratio of the dielectric layer to the first conductor layer and the etching selectivity ratio of the dielectric layer to the second conductor layer are 1 to 15.

In an embodiment of the invention, the material of the dielectric layer comprises a high dielectric constant material or a combination of a high dielectric constant material and a low dielectric constant material.

Based on the above, the present invention utilizes the second conductor layer on the isolation structure as a mask layer to remove a portion of the dielectric layer to avoid damage to the tunnel dielectric layer caused by the overetch process. In another aspect, the present invention further utilizes a high etch selectivity ratio between the dielectric layer and the first conductor layer and the dielectric layer second conductor layer to completely remove the first conductor layer between each isolation structure, thereby Avoid floating gate shorts. In this way, the memory component and the manufacturing method thereof of the present invention can effectively solve the problem of junction leakage and floating gate short circuit, so as to improve the yield and reliability of the product.

The above described features and advantages of the invention will be apparent from the following description.

1A-1G are perspective views of a manufacturing process of a memory device according to an embodiment of the invention.

Referring to FIG. 1A, the present invention provides a method of manufacturing a memory element, the steps of which are as follows. First, a substrate 100 is provided. The substrate 100 has a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 extend along the first direction D1 and alternate with each other along the second direction D2. Although only one first region R1 and one second region R2 are separately illustrated in FIG. 1A, the present invention is not limited thereto, and may represent a plurality of first regions R1 and a plurality of second regions R2. The following figures are also equivalent to the same situation and will not be described again. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Next, a plurality of stacked layers 101 are formed on the substrate 100, and a plurality of isolation structures 10 are formed in the plurality of stacked layers 101 and the substrate 100. Each stacked layer 101 includes a tunneling dielectric layer 102 and a first conductor layer 104. As shown in FIG. 1A, the first conductor layer 104 is located on the tunnel dielectric layer 102. The material of the tunneling dielectric layer 102 may be, for example, hafnium oxide, which may be formed by a chemical vapor deposition method, a thermal oxidation method, or the like. In one embodiment, the thickness of the tunneling dielectric layer 102 is, for example, 50 to 150 angstroms. The material of the first conductor layer 104 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may utilize a chemical vapor deposition method. In an embodiment, the first conductor layer 104 can be, for example, one, two or more layers of conductor material. The two or more layers of the conductor material may be, for example, the same conductor material or different conductor materials. The thickness of the first conductor layer 104 is, for example, 500 to 1200 angstroms. The isolation structure 10 and the stacked layers 101 alternate with each other along the first direction D1. The material of the isolation structure 10 is, for example, doped or undoped cerium oxide, high density plasma oxide, cerium oxynitride, spin-on silicon oxide, low dielectric constant dielectric material. (Low-k dielectric) or a combination thereof. The isolation structure 10 is, for example, a shallow trench isolation structure.

In one embodiment, a plurality of stacked layers 101 are formed on the substrate 100, and a plurality of isolation structures 10 are formed in the plurality of stacked layers 101 and the substrate 100. The stacked material layers may be formed on the substrate 100 (not drawn). And a patterned mask layer (not shown), followed by a dry etching process such as Reactive Ion Etching (RIE), patterning the stacked material layers to form the stacked layer 101, and on the substrate A plurality of ditches (not shown) are formed in 100. Next, a high density plasma oxide layer is formed on the substrate 100 to fill the trenches. Thereafter, a high density plasma oxide layer on the substrate 100 is planarized by chemical mechanical polishing (CMP) to expose the top surface of the first conductor layer 104 of the stacked layer 101.

Referring to FIG. 1B , a portion of the isolation structure 10 is removed with the stacked layer 101 as a mask to form an opening 15 between the adjacent two stacked layers 101 to leave the isolation structure 20 . In this embodiment, this step can control the process conditions such that the bottom surface of the opening 15 is higher than the top surface of the tunneling dielectric layer 102, and the thickness T2 of the top surface of the isolation structure 20 to the top surface of the tunneling dielectric layer 102. It is from 15 nm to 40 nm. This thickness T2 is the Effective Field Oxide Height (EFH), which prevents the isolation structure 20 from being over-etched to protect the tunneling dielectric layer 102 from damage.

Referring to FIG. 1C, a dielectric layer 106 is conformally formed on the isolation structure 20 and the stacked layer 101. Dielectric layer 106 can be constructed from a single layer structure. The material of the single layer structure may be, for example, a high dielectric constant material. The high dielectric constant material refers to a dielectric material having a dielectric constant higher than 4, such as hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfAlO) or tantalum nitride (SiN). . Dielectric layer 106 can also be constructed of a multilayer structure. The multilayer structure may be composed of a combination of a high dielectric constant material and a low dielectric constant material, such as an oxide layer/nitride layer/oxide layer (ONO), an oxide layer/nitride layer/oxide layer/nitride layer/oxide layer. A stacked structure of (O(NO) _x NO, x is an integer greater than 1). The above-described method of forming the single layer structure and the multilayer structure may be a chemical vapor deposition method, a thermal oxidation method, or a combination thereof. In an embodiment, the dielectric layer 106 has a thickness T1 of 8 nm to 20 nm.

Referring to FIG. 1D, a second conductor layer 108 and a mask layer 110 are sequentially formed on the dielectric layer 106. The material of the second conductor layer 108 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method may be a chemical vapor deposition method. The mask layer 110 may be a single layer or a composite layer, such as cerium oxynitride (SiON), a carbonaceous material, an oxide, an amorphous germanium (a-Si), a nitride, a polycrystalline silicon (Poly-Si), or a combination thereof. . The carbonaceous material may be, for example, amorphous carbon (a-C), carbon-doped spin-on Resist. For example, the mask layer 110 may be sequentially formed of a composite layer of bismuth oxynitride, amorphous carbon, and cerium oxide, but the invention is not limited thereto.

Referring to FIGS. 1D and 1E, the mask layer 110 and the second conductor layer 108 are patterned to form a patterned mask layer 110a and a second conductor layer 108a, exposing the top of the dielectric layer 106 of the first region R1. surface. The second conductor layer 108a has a body portion 108b and an extension portion 108c. The extension portion 108c is connected to the main body portion 108b. The extension portion 108c is located in the opening 15 of the second region R2 and alternates with the first conductor layer 104 along the first direction D1. The second conductor layer 108d remains in the opening 15 of the first region R1. The second conductor layer 108d is overlaid on the dielectric layer 106 with a top surface lower than the top surface of the stacked layer 101. In the present embodiment, the second conductor layer 108d has a thickness of 30 nm to 45 nm. However, the present invention is not limited thereto. In other embodiments, as long as the thickness of the second conductor layer 108d is sufficient to resist the subsequent etching process, the underlying isolation structure 20 may be prevented from being eroded. In this way, the second conductor layer 108d can protect the underlying tunneling dielectric layer 102 to avoid damage to the interface between the isolation structure 20 and the tunneling dielectric layer 102. In addition, in the present embodiment, the second conductor layer 108a of the first region R1 may be, for example, a control gate or a word line (Word Line, WL).

Referring to FIGS. 1E and 1F, the second conductor layer 108d is used as a mask to perform an etching process to remove a portion of the dielectric layer 106, a dielectric layer 106a is formed in the second region R2, and a cap layer is formed in the first region R1. 106b and exposing the surface of the first conductor layer 104a. In this embodiment, when the material of the dielectric layer 106 is a combination of a high dielectric constant material and a low dielectric constant material, such as an oxide layer/nitride layer/oxide layer (ONO) or a combination thereof, the removed portion is introduced. The etching gas of the electric layer 106 may be, for example, CF ₄ , CHF ₃ , O _{2 ,} and H, and the etching gas for removing the portion of the dielectric layer 106 between the first conductor layer 104a and the second conductor layer 108d may be, for example, CF. ₄ , CH ₂ F ₂ , CHF ₃ , CH ₃ F, CH ₄ , O ₂ and He. In an embodiment, during the etching process, the etching selectivity ratio of the dielectric layer 106 to the first conductor layer 104a and the dielectric layer 106 and the second conductor layer 108d is 1 to 15, and thus, the first region R1 The dielectric layer 106 on the stacked layer 101 will be completely removed. Although there is a high etching selectivity ratio between the dielectric layer 106 and the first conductor layer 104a, a small portion of the first conductor layer 104a is removed, so the shape of the first conductor layer 104a may be slightly changed (as shown in FIG. 1F). Shown), but the change in shape of the first conductor layer 104a does not affect the subsequent process and operation of the associated memory element. In addition, during the etching process, the dielectric layer 106 of the sidewall of the second conductor layer 108d and the underlying partial isolation structure 20 are also removed, leaving the cap layer 106b and the isolation structure 20c in the first region R1. Thus, the upper portion 20a of the isolation structure 20c has a slight slope that affects the subsequent effective field oxide height (EFH) and shape, as will be described in detail in subsequent paragraphs.

Referring to FIGS. 1F and 1G, the first conductor layer 104a on the tunneling dielectric layer 102 and the second conductor layer 108d on the capping layer 106b are removed to expose the tunneling dielectric layer 102. The top surface. Since the first conductor layer 104a and the cap layer 106b and between the second conductor layer 108d and the cap layer 106b have a high etching selectivity ratio, the second conductor layer 108d and the first conductor layer 104a are removed. During the process, the cap layer 106b can protect the underlying isolation structure 20c from damage to the interface between the isolation structure 20c and the tunneling dielectric layer 102. In this way, the problem of junction leakage and floating gate short circuit can be solved, thereby improving product yield and reliability. On the other hand, since the top cover layer 106b of the first region R1 can protect the underlying isolation structure 20c from being damaged, it causes the top surface of the isolation structure 20c and the cap layer 106b to be a flat surface. Further, in the step of removing the first conductor layer 104a and the second conductor layer 108d, it may remove the partially patterned mask layer 110a while leaving the patterned mask layer 110b.

Referring to FIG. 1G and FIG. 2, the present invention provides a memory device including: a substrate 100, a plurality of tunneling dielectric layers 102, a plurality of isolation structures 20c, a plurality of first conductor layers 104b, a dielectric layer 106a, and a cap layer. 106b and the second conductor layer 108a. The substrate 100 has a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 extend along the first direction D1 and alternate with each other along the second direction D2. The tunneling dielectric layer 102 is located on the substrate 100. The tunneling dielectric layer 102 extends along the second direction D2 and traverses the first region R1 and the second region R2. Each of the isolation structures 20c has an upper portion 20a and a lower portion 20b. The upper portion 20a of the isolation structure 20c is located on the lower portion 20b, and the bottom surface of the upper portion 20a is equal to the top surface of each of the tunnel dielectric layers 102. The lower portion 20b of the isolation structure 20c is located in the substrate 100 and alternates with the tunneling dielectric layer 102 along the first direction D1. The cap layer 106b is located on the upper portion 20a of the isolation structure 20c. The top surface of the top cover layer 106b is a flat surface. The first conductor layer 104b (which may, for example, be a floating gate) is located on the tunnel dielectric layer 102 of the second region R2. The dielectric layer 106a covers the first conductor layer 104b between the first conductor layer 104b and the second conductor layer 108a. In this embodiment, the dielectric layer 106a can be regarded as a dielectric layer between the gates to electrically isolate the first conductor layer 104b from the second conductor layer 108c. A second conductor layer 108a (e.g., as a control gate or word line) is located on dielectric layer 106a. The second conductor layer 108a includes a body portion 108b and a plurality of extensions 108c. The extension portion 108c is connected to the main body portion 108b and extends between the two first conductor layers 104b. In other words, the extension portion 108c and the first conductor layer 104b alternate with each other along the first direction D1. Further, as shown in FIG. 2, the memory element of the present embodiment includes an isolation structure 20d between the extension 108c of the second region R2 and the substrate 100. Since the isolation structure 20d is covered by the dielectric layer 106a and the extension portion 108c above it, the isolation structure 20d is not damaged during the etching process described above. Therefore, the structural shape of the isolation structure 20d and the isolation structure 20c are not the same. In the present embodiment, the isolation structure 20d is substantially a rectangular body.

On the other hand, in the present embodiment, the upper portion 20a of each of the isolation structures 20c covers the top cover layer 106b, and the double layer structure composed of the upper portion 20a and the top cover layer 106b on the upper portion 20a is a trapezoidal body. The structure satisfies the following formula (1) to formula (2): Formula (1): b ≤ a < c, Formula (2): b ≥ 1/3 a, a is each extension portion 108c of the second conductor layer 108a Bottom width. b is the top surface width of each cap layer 106b. c is the width of the bottom surface of the upper portion 20a of each of the isolation structures 20c.

Further, in another embodiment, the angle θ between the side wall of the upper portion 20a of each of the isolation structures 20c and the bottom surface of the upper portion 20a is, for example, 40 to 87 degrees. In the present embodiment, the upper portion 20a of each of the isolation structures 20c may be a trapezoidal body, so the above-mentioned angle θ is, for example, 40 degrees to 87 degrees.

3 is a perspective view of a memory element in accordance with another embodiment of the present invention.

Referring to FIG. 3, the present invention provides another memory device including a substrate 100, a plurality of tunneling dielectric layers 102, a plurality of isolation structures 20c, and a cap layer 106b. The tunneling dielectric layer 102 is located on the substrate 100. Each of the isolation structures 20c has an upper portion 20a and a lower portion 20b. The upper portion 20a of the isolation structure 20c is located on the lower portion 20b, and the bottom surface of the upper portion 20a is equal to the top surface of each of the tunnel dielectric layers 102. The lower portion 20b of the isolation structure 20c is located in the substrate 100 and alternates with the tunneling dielectric layer 102 along the first direction D1. The cap layer 106b is located on the upper portion 20a of the isolation structure 20c. The top surface of the top cover layer 106b is a flat surface.

In the present embodiment, the upper portion 20a of each of the isolation structures 20c covers the top cover layer 106b, and the double layer structure of the upper portion 20a and the top cover layer 106b on the upper portion 20a is a trapezoidal body, and the structure thereof satisfies the following formula (3) ) to the formula (4): Formula (3): b ≤ c-2 × T1 < c, Formula (4): b ≥ , b is the top surface width of each of the cap layers 106b. c is the width of the bottom surface of the upper portion 20a of each of the isolation structures 20c. T1 is the thickness of the cap layer 106b.

Further, the angle θ between the side wall of the upper portion 20a of each of the isolation structures 20c and the bottom surface of the upper portion 20a is, for example, 40 to 87 degrees. In the present embodiment, the upper portion 20a of each of the isolation structures 20c may be a trapezoidal body, so the above-mentioned angle θ is, for example, 40 degrees to 87 degrees.

In summary, the present invention leaves a second conductor layer on the isolation structure as a mask layer, so that in the process of removing the dielectric layer on the stacked layer of the first region, the isolation structure below can be protected. The isolation structure has an effective field oxide height. In addition, since the isolation structure is covered by the cap layer, the cap layer can protect the isolation structure from isolation when the first conductor layer on the tunnel dielectric layer and the second conductor layer on the isolation structure are removed. The structure is over-etched to avoid damage to the interface between the isolation structure and the tunneling dielectric layer and to provide the isolation structure with an effective field oxide height. In another aspect, the present invention further utilizes a high etch selectivity ratio between the dielectric layer and the first conductor layer and between the dielectric layer and the second conductor layer to completely remove the first conductor layer isolation structure between the isolation structures. The upper second conductor layer and thereby avoiding the phenomenon of shorting of the floating gate. In this way, the memory element and the manufacturing method thereof of the present invention can effectively solve the problem of junction leakage and floating gate short circuit, so as to improve product yield and reliability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 20c, 20d‧‧‧ isolation structure
20a‧‧‧ upper
20b‧‧‧ lower
15‧‧‧ openings
100‧‧‧Base
101‧‧‧Stacked layers
102‧‧‧Tunnel dielectric layer
104, 104a, 104b, 108, 108a, 108d‧‧‧ conductor layer
106, 106a‧‧‧ dielectric layer
106b‧‧‧Top cover
108b‧‧‧ Main body
108c‧‧‧Extension
110, 110a, 110b‧‧‧ cover layer
a, b, c‧ ‧ width
D1‧‧‧ first direction
D2‧‧‧ second direction
Part P‧‧‧
T1, T2‧‧‧ thickness
R1, R2‧‧‧ θ‧‧‧ angle

1A-1G are perspective views of a manufacturing process of a memory device according to an embodiment of the invention. Figure 2 is an enlarged view of a portion P of Figure 1G. 3 is a perspective view of a memory element in accordance with another embodiment of the present invention.

20a‧‧‧ upper

20b‧‧‧ lower

20c‧‧‧Isolation structure

100‧‧‧Base

102‧‧‧Tunnel dielectric layer

106b‧‧‧Top cover

b, c‧‧‧width

T1, T2‧‧‧ thickness

D1‧‧‧ first direction

D2‧‧‧ second direction

Θ‧‧‧ angle

Claims (11)

A memory element, comprising: a substrate having a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions extend along a first direction and are mutually along a second direction Alternating; a plurality of tunneling dielectric layers are disposed on the substrate, the tunneling dielectric layers extending along the second direction and traversing the first regions and the second regions; a plurality of isolation structures, Each of the isolation structures has an upper portion and a lower portion, wherein the lower portions of the isolation structures are located in the substrate, and the tunneling dielectric layers alternate with each other along the first direction, and the upper portions of the isolation structures Located on the lower portions; and a plurality of cap layers on the upper portions of the isolation structures, wherein the top surfaces of the cap layers are a flat surface. The memory device of claim 1, wherein a top surface of the upper portion of each isolation structure is higher than a top surface of each tunneling dielectric layer, and a bottom surface of each upper portion of each isolation structure is worn by each The top surface of the tunnel dielectric layer is of equal height. The memory device of claim 1, further comprising: a plurality of first conductor layers on the tunneling dielectric layers of the second regions; a dielectric layer covering the first portions On the conductor layer; and a second conductor layer on the dielectric layer, the second conductor layer has a body portion and a plurality of extensions, the extensions and the first conductor layers along the first direction Alternate. The memory element according to claim 3, wherein the upper portion of each isolation structure and the structure of the top cover layer on the upper portion satisfy the following formulas (1) to (2): Formula (1): b ≤ a < c, Formula (2): b ≥ 1/3 a, where a is the bottom width of each extension of the second conductor layer, b is the top surface width of each cap layer, and c is per The width of the bottom surface of the upper portion of an isolation structure. The memory element of claim 1, wherein the material of the cap layer comprises a high dielectric constant material or a combination of a high dielectric constant material and a low dielectric constant material. A memory element comprising: a substrate; a plurality of tunneling dielectric layers on the substrate; a plurality of isolation structures, each isolation structure having an upper portion and a lower portion, wherein the lower portions of the isolation structures are located on the substrate And the tunneling dielectric layers alternate along a first direction, the upper portions of the isolation structures are located on the lower portions; and a plurality of cap layers are located on the upper portions of the isolation structures The top surface of the cap layers is a flat surface. The memory device of claim 6, wherein a top surface of the upper portion of each isolation structure is higher than a top surface of each tunneling dielectric layer, and a bottom surface of each upper portion of each isolation structure is worn by each The top surface of the tunnel dielectric layer is of equal height. The memory element according to claim 6, wherein the upper portion of each isolation structure and the structure of the top cover layer on the upper portion satisfy the following formulas (1) to (2): Formula (1): b ≤ c-2 × T1 < c, formula (2): b ≥ , where T1 is the thickness of the cap layer, b is the top surface width of each cap layer, and c is the upper portion of each of the isolation structures The width of the bottom surface. A method of fabricating a memory device, comprising: forming a plurality of stacked layers on a substrate, each stacked layer comprising a tunneling dielectric layer and a first conductive layer, wherein the first conductive layer is located in the tunneling dielectric layer Forming a plurality of isolation structures in the stacked layers and the substrate; using the stacked layers as a mask to remove portions of the isolation structures to form a plurality of openings in the stacked layers, the openings a bottom surface is higher than a top surface of the tunneling dielectric layer; a dielectric layer is formed on the isolation structures and the stacked layers; a second conductor layer is formed on the isolation structures; The layer is a mask, a portion of the dielectric layer is removed to form a cap layer to expose a surface of the first conductor layer; and the first conductor layer and the second conductor layer are removed to expose the tunneling layer The top surface of the electrical layer. The method of manufacturing a memory device according to claim 9, wherein in the step of removing a portion of the dielectric layer, an etching selectivity ratio of the dielectric layer to the first conductor layer and the dielectric layer and the first layer The etching selectivity ratio of the two conductor layers is from 1 to 15. The method of manufacturing a memory device according to claim 9, wherein the material of the dielectric layer comprises a high dielectric constant material or a combination of a high dielectric constant material and a low dielectric constant material.