TW201025806A - Transforming circuit and controller for reducing audio noise - Google Patents

Abstract

The present invention uses a discharge path to release the power stored in an output capacitor of a transforming circuit when the time interval between two adjacent switching thereof. Hence, the present invention can reduce the audio noise of the transforming circuit.

Description

201025806 VI. Description of the Invention: [Technical Field] The present invention relates to a conversion circuit and a controller thereof, and more particularly to a conversion circuit and a conversion controller having noise prevention. [Prior Art] Please refer to the first figure, which is a schematic diagram of a conventional DC-to-DC buck conversion circuit, which will convert the DC input voltage Vin into a DC output voltage v〇ut. The DC-to-DC step-down conversion circuit includes a first switch, a second switch Q2, an inductor L, a capacitor c, a voltage detector 50, a current detector Rcs, and a controller. The control state includes a current sense amplifier 1〇, an error amplifier 2〇, a pulse width modulation (p) comparator 30, and a frequency hopping mode control n (Skip M〇de c〇ntr〇ller) 4〇. The first switch Q1 and the second switch Q2 are connected in series between the DC input voltage VIN and ground. The inductor l and the capacitor C are connected in series between the connection point of the first switch Q1 and the second switch Q2 and the ground, and generate a DC output voltage v〇ut. The current controller RCS is connected to the inductor L to detect the magnitude of the current flowing through the inductor L and to generate a current subtraction GS. The voltage debt detector 50 is coupled to the power c, and the rib side outputs the voltage and generates a voltage detection signal VS. =, the differential amplifier steals the non-inverted terminal to receive the voltage detection signal and the reverse terminal receives a > test voltage 峨' and outputs a & error output signal EA at the output terminal. The pulse width modulation comparator 30 compares the sum of the error amplification signal EA with the current debt signal cs and the slope compensation signal sl〇pe to output a comparison signal _. Jump 201025806 The frequency mode controller 40 receives the comparison signal Comp and the current detection signal CS to output a first control number UGATE and a second control number LGATE to control the actions of the first switch Q1 and the second switch Q2, respectively. When the DC output voltage Vout is lower than a predetermined voltage, the frequency hopping mode controller 40 turns on the first switch Q1 and turns off the second switch Q2' to make the current from the DC input voltage.

Vin flows into capacitor C to charge and causes DC output voltage v〇ut to rise. When the sum of the current detection signal CS and the slope compensation signal slope rises to the top touch error amplification signal, 0 turns off the first-switching milk and turns on the second switch Q2, so that the current of the inductor L continues to flow through the second switch Q2. When the current of the inductor L is about to turn (that is, the capacitor c is switched from the stored energy to the released energy), the second switch Q2 is turned off, and the first switch Q1 is still turned off. DC to DC drop. The conversion circuit continuously supplies energy to the load through the electricity valley. In the next-cycle, when the DC and output VQUt are lower than the predetermined time, the jumping lake If 4G turns on the second switch Q1 and the second switch q2 again, so that the DC output voltage Vout is stabilized near the predetermined voltage. ❹ Age is too light, so that the direct A voltage Vout is still higher than the predetermined voltage in the next-week (four)'. At this time, the frequency hopping mode control--the general mode enters the frequency hopping mode, and the first switch Q1 is maintained during the cycle. The second switch is in an off state until the DC output voltage Vout is lower than a predetermined voltage. Thus, the first switch milk and the second switch (four) are not necessarily _ finely reduced. However, if the frequency between the first-on-two-on conduction in the frequency hopping mode is just within the range of 2 Hz to the surface Hertz of the audio, the DC-to-DC buck conversion circuit will generate audio impurities. News. 201025806 [Description of the Invention] In view of the above-mentioned DC-transfer money step-down conversion circuit, although the number of switching of the transistor switch can be reduced to reduce the switching loss, the problem of audio noise is encountered, and the conversion circuit with noise prevention provided by the present invention The DC-to-DC converter utilizes a discharge impurity to cause the DC-to-DC conversion circuit to discharge at a frequency of 2 Hz to _ Hz before the human ear to immediately discharge to eliminate audio noise (material). In order to achieve the above object, the present invention provides a conversion circuit 'including-conversion circuit and a controller having noise prevention. The conversion circuit is configured to convert the input voltage into a round output light output. The conversion circuit includes a switch and an energy storage element t, and the switch is input between an input power source and an energy component. The controller generates an arpeggio prevention signal according to the current flowing through the ship and the output voltage to generate a -th control signal and the current is less than - the predetermined current value exceeds - the predetermined time length h, wherein the conversion circuit generates One of the noise anti-hill circuit, ... 曰 # is used to control the transmission. The invention also provides a conversion circuit for the Meiyin prevention, comprising a switch: a controller. The conversion paste converts the input voltage into an output voltage. The conversion circuit includes a switch and an energy storage component, and the __ is a power supply and the ship component (10). The (4) one of the components - the output core is generated - the control signal controls the _, and according to the phase _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Drink _ shop for a voice to prevent the circuit. 201025806 The present invention also provides a (four) tone preventing touch _ for controlling the conversion circuit to convert the energy of the input power source into an output light, including - the first detecting unit, the - detecting unit And - drive control circuit. The second detection unit generates a current determination signal according to a current-sense signal of the conversion circuit. The second guessing unit screams according to the output - yelling. The time determining unit determines whether to generate a noise preventing signal according to the time interval of the current determining signal, wherein the soundproofing preventing signal is used to control the noise-proof circuit of the switching circuit, and the driving control circuit receives the dust back The signal signal, the current determination signal, and the noise prevention signal 'to generate at least one control signal to control the conversion circuit. Shuming X provides a conversion control (four) for the prevention of (four) sounds, which is used to convert the energy of the input power source into a turn-over voltage, including the 'single order 70', the second fine unit And a driving control circuit, the second detecting unit generates a current determining signal according to the current gamma signal of the converting circuit. The _th unit generates a voltage feedback signal based on the output. The time is determined as early as possible - the noise prevention signal is controlled to control the circuit of the noise exchange circuit - the noise prevention circuit 2 receives the dragon feedback signal, the current determination signal and the raft to prevent the λ number to generate _ - controlling the signal to control the switching circuit - the time determining unit determines whether the noise preventing signal is generated based on the time gate interval of the adjacent two first control signals and the first predetermined time length. The above summary and the detailed descriptions below are exemplary in nature, and are intended to be used in the scope of the patents of this month. Other objects and advantages of the present invention will be described in the following description and drawings. 7 201025806 [Embodiment] i test-A® ’ is the DC-to-DC conversion with noise prevention of the present invention. The money transfer money conversion circuit pack s conversion circuit - _ sound prevention circuit (5) and - control regret. The conversion circuit=including a first-switching milk, a synchronous diode, as an energy storage component, an inductor l, a capacitor C, and a voltage device (10) for converting an input voltage Vin into an output voltage V 〇Ut is out. The controller (10) includes a -th detecting unit 11 - a gamma unit it m, a time judging list s 13G, and a drive control circuit (10). The control t(10) receives a current _ lock and a voltage detection signal vs representing a voltage Vout, which is generated according to a current gn flowing through the inductor L and the turn-on voltage V〇ut to generate - Control signal GATE. When the field between the first-on power supply Vin and the inductor L is controlled by the control, vm_ is performed, the input voltage is stored in the inductor L, and when the switch is turned off, Electrical load (class). The synchronous diode (4) is the switch Q1, and the positive terminal is grounded. When the first switch Q1 is turned off, the release of L is performed. The voltage detection 11 150 secret output voltage Vou1: 'electric> gt; 〇丨 juice, with the ~ each C coupled to the inductor L ·, used to stabilize an output circuit Q3 village 咕 电 纽 纽 纽 纽 。 。. The noise prevention circuit Q3 is coupled to the conversion circuit and can be electrically connected to the circuit. The noise is prevented. The first detection unit 11fl is connected to the voltage detector 150, and the voltage detection signal is 201025806. The output voltage Voui: generates a voltage feedback signal FB when it is lower than a predetermined voltage value. The second detecting unit I20 is coupled to the inductor L to receive a current sensing signal CS' representing the magnitude of the inductor current IL. When the inductor current il is less than a predetermined current value, a current determining signal Skip is generated. The time judging unit 13 receives the current judging signal Skip and the voltage feedback signal FB, and generates a noise preventing signal when the current judging signal Skip continues to exceed a first predetermined time length while receiving the voltage feedback signal 叩OVER-CYCLE to control the noise prevention circuit such as. The drive control circuit 140 receives the voltage feedback signal 咫, and generates the control signal GATE when the output voltage Vout is lower than the predetermined voltage value. § When the noise prevention signal OVER-CYCLE is generated, the sound prevention circuit (10) is controlled to connect the inductance L to a reference potential (for example, ground) to make the capacitor

The energy is transmitted through the money L and the noise preventing circuit Q3, and the energy is stored in the column inductor L due to the re-current flow. In general, the noise prevention signal 〇ver_cycle can be designed to generate - the second _ length can be _ domain L heavy _ energy. In this way, the 'inductance L turns twice through the current when the interval is shorter than the range that the human ear can perceive', that is, fresher than 2__, and the function of preventing the material is achieved. " Please refer to the diagram of the circuit diagram of the invention for the noise-reducing DC-to-DC converter circuit. In the second diagram of FIG. A, for example, one end of the noise prevention circuit q3 of the embodiment is connected to the inductor L and the capacitor C', and the terminal is grounded, and the synchronous diode D2 is defeated by a second switch. Replace. In addition, the signal transmission inside the control 1GG is slightly different, and the internal operation of the controller (10) is described as follows. 201025806 η The first unit 110 is connected to the simple detector 15〇, and the receiving voltage detecting signal VS generates a voltage feedback signal FB when the output power v璧ut is lower than a predetermined electric dust value. The second_unit 12 is lightly connected to the inductor 1 to receive a current_signal GS' representing the magnitude of the inductor current 于, and a current determination signal Slap is generated when the crane current IL is less than the predetermined current value. The time judging unit 13 receives the current judging signal _ and the cake feedback signal FB, and the time interval between the adjacent two cake feedback signals FB exceeds the first ship day _ degree' generation - noise prevention 峨 —, To control the noise prevention circuit Q3. The dynamic control circuit (10) receives the voltage feedback signal FB and the current determination signal Skip. When the output voltage v(10) is lower than the predetermined voltage value, the first control signal is generated, and the energy of the input voltage is transmitted through the first switch Q1. Stored in the inductor L; when the output voltage v〇ut is higher than the predetermined voltage value and the inductor money a is greater than the thief listening, the second control ship number _, the energy stored in the inductor L is transmitted through the second opening _ Forming a current loop to store the capacitor c; when the output cake VQUt is higher than the silent cake value and the electrical power flow a is less than the predetermined current value, 'stopping outputting the first control signal UGATE and the second control signal LGATE to cut off the current The first switch and the second switch Q2. When the noise prevention signal __CYCLE is generated, the noise prevention circuit is controlled to make the capacitance c_- reference potential (for example, ground), so that the energy stored by the capacitor c is transmitted through the material to prevent electricity, so that the input The material pressure is finer than the predetermined voltage value. At this time, the drive control circuit will immediately generate the first control signal UGATE to cause the inductor L to re-current. In general, the noise prevention signal 0-CYCLE can be designed to generate a second predetermined length of time or the first control signal 201025806

'You can reach the first level Q1 re-conduction to make the inductor, the inductance L flows through the current twice, that is, the frequency is higher than 20000 Hz; the generation of wood 9 is caused by the inductive component adjacent to the two guides The length of time that no current flows through the power, soil = interval is equal to the human ear can be perceived ς L The voltage interval of the adjacent two voltage feedback signals FB (or the first control ❷UOTE) will contain red and no current. The time (if the circuit enters non-connected, ''motor only mode') and one or two or so controller 100 operating cycles. Since the controller 100 is at a high frequency (for example, 200 kHz or more), the cycle length is quite short and negligible in the human ear. Therefore, in the present embodiment, the system detects the need to generate a noise-free bribe surface - GYGLE can break the noise. In addition, since the noise source of the conversion circuit is that the frequency of the inductive component re-flowing through the electrical turbulence is in the audio range that can be perceived by the human ear, it can be applied not only to the inductor but also to a transformer or other inductive energy storage component. The conversion circuit can achieve the function of noise prevention. That is, the present invention can also be applied to a conversion circuit that requires an inductive storage element such as an AC to DC, an AC to a parent, or a DC to an AC. In addition, the drive control circuit 140 of the present invention may be a pulse width "variational (PWM) control circuit with a frequency hopping function or a pulse frequency modulation (pFM) control circuit, so the scope of application of the present invention is quite wide. Next, referring to FIG. 3A, it is a circuit diagram of a DC-to-DC conversion circuit having 11 201025806 as one of the embodiments corresponding to the second a diagram. In the pulse time frequency modulation controller of the control time of the embodiment, the first detection unit includes the first detection unit, the time determination unit, and the drive control circuit, wherein:] early, one zero point_unit阢 and −frequency hopping Judging unit _ = one-time detecting unit 155' The time judging unit includes - operation week _, hour _ unit fine, one pulse signal 1βη and - drive material. The controller can further include - frequency hopping enablement

= and - circuit reset is 17G. The flea energy unit can receive one hop frequency and reduce the EN, and accordingly generate a frequency hopping control signal, so the user can choose whether or not to control the hopping mode according to the application of the Wei. The circuit resets the Π0 to reset the signal P0R according to one of the pulse signals generated by the controller's power supply voltage vcc. When the field power supply voltage vcc rises to a starting voltage value, the reset signal P0R is generated to make the internal component logic of the controller Reset to the initial state.

The feedback detection unit 155 can be a comparator, and the non-inverting terminal receiving-reference voltage 'inverting terminal receives the voltage side signal π generated by the voltage detector 15 (), and generates a voltage feedback signal at the output end. FB. The zero-test unit 175 can also be a comparator's reverse-side current sense signal cs, and the non-inverted-end ground is grounded (in practical applications, it is - close to the positive reference of G volts), and the zero-point is generated at the wheel end. Judgment signal ZCD0UT. The frequency hopping judging unit 500 receives the zero point judging signal ζα) 〇υτ, and when the zero point judging signal ZGDGUT is at the 〒 level (representing the current cross zero crossing), the current determining signal Skip is locked and is locked in each period. Whether the side zero point judgment signal ZCDOUT generates 'stops outputting 12 when the zero point judgment signal ZC_T is no longer generated. 201025806 Current judgment signal Skip. The operation cycle detecting unit goo receives the reset signal p〇R, the voltage feedback signal FB, the frequency hopping control signal skip_M〇de, the current determination signal skip, the zero point determination signal ZCD0UT and a control signal GATE to determine whether the inductor current IL The duration of the zero current is maintained for longer than the first predetermined length of time, and if so, the audible noise prevention signal OVER-CYCLE is generated. The on-time control unit 3 receives the reset signal P0R, the frequency hopping control signal Skip-Mode, the current determination signal skip, and the noise prevention signal OVER-CYCLE, and generates at least one turn-on time when the noise prevention signal 〇VER_CYCLE is generated. Control signals S1 to SN. The pulse signal generating unit 働 is a fixed on-time pulse generating unit that receives the output voltage v〇ut and the input voltage to determine the ON time of the field and controls the signal according to at least one conduction time. The length of time. The pulse signal generating unit 400 also receives the voltage feedback signal .FB and the zero point judgment signal zcd〇ut, and generates a solid material pass pulse when receiving the voltage feedback signal FB of the high level and the zero point of the high level. Control I Tiger Con. The driving unit 6〇〇 receives the pulse control signal to generate the control parameter number GATE to drive the first switch q... The user's reference to the fourth A picture, the fifth picture, the sixth picture A and the seventh continuation The operation cycle detecting unit 200, the on-time control unit _, the pulse signal generating unit shed, and the pulse signal generating unit _ are preferably shown in Fig. A; Referring to the detailed A diagram, it is a circuit diagram of a preferred embodiment of the third embodiment. The operation cycle check 2200 includes an inverter 235, a gate 21 〇 and a weep 5, a lower edge trigger unit delay trigger unit 230, a D-type latch (Dlatch) 240, or a gate 245, 13 201025806 a delay circuit 250 and a riser question (SRiatch) 255. θ refers to the first-A picture at the same time. When the DC-to-DC conversion circuit is in the non-continuous conduction current mode at the beginning of the frequency hopping mode, the control signal of the low level turns off the switch Q1, and the inductor current iL is zero to make the zero point. Judging signal (10) and grasping the judgment signal Skip as the resignation 'and turning light (four) to turn above the predetermined electricity value to make the electric dust feedback signal FB low. At this time, the operation cycle detecting unit 200 does not operate. When the money is transferred to the money, the electric axis is transferred to the load, and the output is turned to the VQut. The light _ 峨 is turned into the high level. At this time, the inverter 2 〇 5 receives the control signal of the low level. Just, and reverse to the high level output. The gate 225 receives the output of the reverser 2〇5, the voltage feedback signal FB and the current determination signal. At this time, since the three signals are all high level, the signal of the high level of the gate 225 is cleared. _ At the same time, the gate (10) receives the frequency hopping control signal Skip-Mode and the zero point judgment signal ZCD, and outputs the high level because the frequency hopping control signal Sklp_Mode is high level (on behalf of the user to enable the frequency hopping function) and the zero point judgment signal ZCD0UT. The signal is processed by the lower edge trigger unit 22{) and the delay trigger unit 230. Subsequently, the controller outputs a high level control signal _ to turn on the first switch Q1 to transmit the energy of the input power Vin to the capacitor c. Because the high level control signal GATE is processed by the inverter 205 to output the low level signal, and the gate shifts the low level signal to stop clearing the D type flash 240. In addition, when the first switch is turned on, the inductor current IL rises, and the zero point judgment signal Ζ_τ is turned to the low level, so that the output of the gate 210 is also turned to the rear level. Since the output of the gate 21〇 is delayed by the delay trigger unit 230, the time point at which the trigger D is 24〇 is after the control signal cage 201025806 is turned into the high-precision signal, so when the gate 225 stops clearing the flash type When L is triggered, the single-digit 230 still outputs a high-level signal, so that the flash is stored in the input of the endpoint. Since the input of the D endpoint is fixed to the high level signal, the D type flash 24 输出 outputs a high level signal at the Q end point, and the Q end point outputs a low level signal. The delay circuit 25 接收 receives the output of the D-type terminal and outputs a high-level signal after receiving the high-level signal for a predetermined period of time. The predetermined length of time of the delay circuit 25() is used to determine whether the DC-to-DC conversion circuit is generating noise, so it is preferably set to or. When the predetermined length of time elapses, the output voltage _ remains above the value of the pre-charged > 1 'and the gate 225 continues to stop clearing the flash, and the D-type flash continues to output the high-level signal. length of time. Therefore, the delay circuit shifts and transmits (4) the level signal ', while the SR 255 receives the high level signal at the S end, and then inputs the (4) level noise prevention signal OVER-CYCLE, so that the lash prevention circuit (10) is turned on, and the capacitor C is permeable. The noise prevention circuit q3 releases the stored energy. When the capacitor c releases the stored energy to the inductor 1 through the click sound prevention circuit Q3, the inductor motor IL rises to cause the inductor 1 to re-storage. In this way, the current of the two currents flowing through the two currents is different from the length that can be perceived by the human ear to eliminate the effect of the flocculation. In addition, if the output voltage V〇ut is lower than the predetermined voltage value due to the energy release of the noise prevention circuit Q3, the voltage feedback signal fb is turned into a high level signal, and the gate 225 outputs a high level signal to clear D. The type flashes, at this time, the 输出 type asks the end point output high level signal to reset SR 255, so that the noise prevention circuit (10) stops conducting. When the current full signal Skip is turned to the low level, it is inverted by the inverter and closed or closed with the reset signal P0R. Therefore, when the controller starts to reset the signal 15 201025806 P0R to the high level ' and the current judgment signal sounds low when the frequency hopping mode is off, the output signal of the SR type flash 255 will be cleared to zero. Stopping the output noise prevention signal OVEIR-CYCLE As described above, when the DC-to-DC conversion circuit enters the frequency hopping mode, the operation cycle detecting unit 200 prepares the time when the inductor current IL is zero, when the _ to duration exceeds the predetermined time length When the operation period detecting unit releases the capacitor (4) by storing the energy through the noise preventing circuit Q3, the inductor L is forced to store energy again to achieve the function of noise prevention. Next, please refer to the fifth figure, which is a circuit diagram of a preferred embodiment of the on-time unit of the present side. The on-time control unit includes a coffee and a counting unit 310. When the (4) base Skip and the current touch signal Skip are both high level signals, the AND gate 3Q5 generates a high level signal to the start end ENB of the counting unit 310 to start the counting unit 310. When the counting unit 31 receives the noise prevention signal OVER-CYCLE, the representative output voltage v〇Lrt is maintained above the predetermined voltage level above the predetermined time, and the operating current IL is secreted by the zero current differential current ❹ (noise θ prevention When the circuit Q3 is turned on). This means that the first switch qi of the last cycle is turned on for too long, so that excess energy is transferred to the capacitor c. Therefore, the count unit 310 receives and accumulates the number of received noise prevention signals 〇ver_cycle after startup. After the startup, the cumulative reception of the noise prevention signal over_cycle is performed m times, the counting unit 310 outputs the high-level conduction time control signal Ν1~Νιη and the low-level conduction time control signal Nro-i from the output terminal B1~Μ. · 1~ΝΝ, to gradually shorten the on-time of the first switch q] as the number of times the audible-prevention signal OVER-CYCLE is received, 16 201025806 is to shorten the length of the control signal GATE. When the money-to-DC conversion circuit hopping frequency mode ' makes the current determination signal Skip low, the counting unit 310 stops operating' and resets all the on-time control signals N1 to NN to the low level. Further, referring to FIG. 6A, a schematic diagram of a circuit for generating a single-recognition-better signal for the pulse signal of the embodiment shown in FIG. Pulse signal generating unit 400 includes three switches S and si SN, a charging capacitor core comparator 4G5, a current source 41 〇,

^ 415, D-type flash 42G ' and the lower edge trigger single it 425. The current source 410 includes a plurality of Us I〇~IN, and according to the input voltage Vin and the output power M v〇ut, each 屯 [single IN 10 IN generates an appropriate current, and provides a larger current when the input voltage vin is higher ‘ It provides a small current when it is low; it supplies a small current when the output voltage is v〇u high, and provides a larger current. The current between each f-flow unit can have a certain proportional relationship, for example: 1U: U . 12 -«I - . ilN=1 · z · 4 · : 2 · : 2 Field straight scale money conversion t road in - When the domain is used for the private jump, the guide = control ship _ ~ _ is the scale money number, this __ only provides ^ Γ ΓΓ 10 charge the charging capacitor C1 to generate the conduction reference signal τ 〇 η. Comparison == General Reference Tiger Ton and reference money, when the reference signal - 420. At this time, the potential is turned on to turn off the high-level signal to reset the D charge charge ^ _ Q, and the end output high-level signal is turned on _ to make the turn-off zero. When the lower edge triggering unit 425 is connected to the (four) Lang (4) point, the fine recording of the lower edge of the fresh-keeping mosquito is stopped. 唬Toff—the fixed length of time (ie, the deadline time is 17 201025806 唬Toff is a low level for the fixed time length). The gate 415 receives the voltage feedback signal FB and the off-time signal Toff. When the output voltage v〇ut is lower than the predetermined voltage value, the off-time signal Toff is also a high level, and the 帛415 is a high-level guide signal. & 'Trigger D-type latch 420 detects the signal of the D endpoint. Since the D-end of the D-type latch 42〇 directly receives the signal of the high-level position, the D-type f_〗 42() immediately outputs the pulse signal cl〇 when the gate & 5 outputs the high-level conduction communication number & (±. Prepare the D-type flash output pulse signal ci〇ck at the same time 'q, the end output low-level signal makes the switch S cut off'. This 0-seek source 41〇 restarts charging the charging capacitor to the conduction reference signal Ton again To the level of the reference potential VR, the comparator shed resets the D-type latch to stop generating the pulse signal cl〇ck. Since the conduction reference signal τ〇η rises to the reference potential VR for a length of time 五 (f), where j is the current source The current is supplied. Under normal operation, the current source only supplies the current of the current cell ι〇', so the time length of the pulse signal nGck is established. However, when the vortex prevention signal 0VER-CYCLE starts production (4), it will be based on noise. The number of times the signal OVER-CYCLE is generated is prevented, and the switches S1 to SN are turned on one by one through the on-time control unit 3, so that the current source 410 also supplies more currents of the current unit according to the number of times the η 峨〇 峨〇 峨〇 VER_CYCLE is generated. Current. Therefore, the length of the conduction reference signal Ton rises to the reference potential VR will be shortened one by one, so that the pulse width of the pulse signal Clock is shortened until the noise prevention signal OVER CYCLE is no longer generated. When the current ^ continues to be zero for more than a predetermined length of time, the controller of the present invention will start to shorten the pulse width of the control signal until the length of the control signal W after a certain shortening no longer causes the current 201025806 sense current IL to continue to zero. More than the predetermined length of time. Further, „月> 考七A图' is the frequency hopping judgment of the embodiment shown in the third embodiment, the circuit display of the preferred embodiment. The frequency hopping judgment unit _ The inverters 502, 504, one and the idle 5, 6, the signal establishing unit 51, the signal holding unit 530 and the signal comparing unit 550. The inverters 502 and 504 respectively receive the pulse signal c1〇Ck and the signal establishing unit A latching reset signal Q_ζα) of 510 is output to the gates 506 and 506 to receive the outputs of the inverters 5〇2 and 5〇4, and outputs a reverse current determination signal after performing the calculation. LG. When the pulse When cl〇ck is at a low level (ie, when the first switch Q1 is turned off) and the latch re-signal Q-ZCD is at a low level (ie, the inductor current IL is zero and the output voltage v〇ut has not yet risen), The inductor current is transmitted through the synchronous diode _ stream, and the gate 5 〇 6 output high level reverse current judgment signal 1 ^. The signal establishment unit _ includes - or gate 512 and -D type flash 514, used to make a zero point The judgment signal ZCI, or (4) 2 receives the reset signal (10) and the voltage feedback signal FB, and clears the D-type 514 at the beginning of the system startup or when the output voltage v〇ut returns to the predetermined electrical value above β. When the zero-point judgment signal ZCD〇UT is at a high level, the signal received by the D-type 514 marriage D endpoint is triggered. Therefore, the signal establishing unit outputs the high-level latching re-signal Q-ZCD when the zero-point determining signal Z_T is at a high level, and stops the wheel-resetting re-signal 0_ZCD when the output power M Vout returns above the predetermined voltage value. . The signal holding unit 53G includes an inverter 532, an upper edge triggering unit 534, a coffee, a delay unit 536, 540, an or a 542, and a D-type secret for use in the zero-point determination signal _T generation when the high-precision One of the bits keeps the signal QC, and judges every 19 201025806 - the cycle is the turn point to touch the lion υ 财 财, 妓 讯 Q QC 'If otherwise stop output. D Lang 544 receives the reset signal and resets it at the beginning of the system startup. After the latching reset signal q-zcd is processed by the upper edge trigger unit and the delay unit 540, a first identification signal ^ is output to establish and maintain the generation of the hold signal QC. After the reverse current determination signal LG is processed by the inverter, the upper edge triggering unit 534, and the delay unit 536, the second identification signal L4' is output to stop generating the hold signal QC. The OR gate 542 receives the first identification signal L3 and the second identification signal L4 to trigger the lock reset signal Q_ZCD received by the D ground copper D terminal, and outputs the hold signal qC. Therefore, the D-type flash 544 outputs the high-level hold signal qc when the latch re-signal Q-ZCD is switched from the low level to the high level and the predetermined delay time length Td3 is passed through the delay unit 54. However, if there is a period-cycle, the DC-to-DC conversion circuit operates in the continuous current mode such that the -cycle does not generate the zero-point determination signal ZCD0UT, and the turn-off voltage v〇ut falls below the predetermined voltage-voltage value, causing the voltage The feedback signal FB turns to a high signal and clears the ^ 514 and stops the output latch re-signal Q_ZCD. At this time, the pulse signal cl〇ck is generated, so that the reverse: 电流 current determination signal LG is changed from the high level to the low level, and after the inverter 532 is triggered, the upper edge trigger unit 534 is delayed by a predetermined delay After the length of time is applied, the trigger D-type latch 544 detects the latch reset signal q-ZCD. Since the latch reset signal Q_ZCD is at a low level at this time, the D-type latch 544 outputs the low level hold signal qc. Since the first identification signal L3 and the second identification signal L4 are used to establish the generation of the hold signal QC and the stop hold signal QC, respectively, the predetermined delay time length Td3 must be shorter than the predetermined delay time length Td4. 20 201025806 Signal comparison unit 550 - D-type latch 552, XOR 〇 gate 554, lower edge delay unit 556, inverter 558 and inverse gate 560 for comparing current determination signal Skip and maintaining Signal qc to determine whether to change the current judgment signal

The state of Skip. The initial output of the D terminal of the D-type latch 552 is at a low level, so the current determination signal Skip is initially at a low level. The inverter 558 receives the reset signal p〇R, outputs a low level signal at the beginning of the system startup, and causes the D-type latch 552 to reset, and then outputs a high level signal. Therefore, after the system is fully started, the inverter brush outputs _ * level signal. At this time, the output of the gate 56 仅 is only controlled by the anti-cancellation signal. When the anti-cancellation signal EQ is low, reset. (4) Asking off, Shuo cancels the reset. When the DC-to-circuit circuit is under the wire, the zero-off _峨2(10) town is at a low level. Therefore, the hold signal QC is also at a low level, so that the exclusive OR non-logic gate 554 outputs a high-level lower edge delay unit 556. The input of the high level also outputs the anti-cancellation signal EQ of the high level to the opposite gate 56〇. When the inductor current is at (or close to) zero, the zero-point detection detects the zero-point determination signal ZCD〇UT of the high-level το 175 output, so that the signal establishing unit 510 outputs the high-missing latching mosquito, the occupational unit _ The high-level hold signal QC is also rotated after the delay time length Td3. At this time, the d-type 1 2, 'two-latch reset signal q-zcd triggers and outputs a high-level current determination signal. In the short message number QC, the delay time is delayed, and the delay is not converted to the high signal. (4) The 'axis misalignment logic 554 compares the high-order current determination I 1Ρ with the low-level retention signal Qc and rotates the low-level delay unit. The delay time of 556 is Geng ^ ± , 'i is lower than the gate length Td5. Since the delay time length Td5 is set longer than the delay time length, after the hold signal QC is also turned to the high level, the lower edge 21 201025806 delay unit 556 The low level anti-cancellation signal EQ is still not output and the d-type flash 552 is prevented from being improperly reset. When the DC-to-DC converter circuit operates from the discontinuous current mode to the continuous current mode', the signal holding unit 53 stops outputting the hold signal QC (i.e., outputs the low level hold signal QC). The exclusive OR non-logic gate 554 outputs a low level signal compared with the high level current determination signal Skip and the low level hold signal QC, and outputs a low level inverse cancellation signal EQ after being delayed by the lower edge delay unit 556. The D-type latch 552 is reset, and the current determination signal is turned to a low level. When the current is reduced to zero, the zero-point judgment signal ❹ ZCD0UT, the frequency hopping judgment unit immediately outputs the high-level current determination signal Skip frequency hopping judgment unit 5〇〇 and each subsequent cycle Detect if the zero point judgment signal ZCDOUT is generated again. When the zero-point judgment signal %(8) is not present in a certain cycle, the output current determination signal Skip is stopped. - Again, please refer to the third B diagram, which is a circuit diagram of a DC-to-DC conversion circuit with noise prevention and sound resistance corresponding to one of the embodiments of the second B diagram. Since the embodiment of the third embodiment shown in the third figure is a part of the electric material of the paper, it will be described here in different places, and the difference between the two embodiments will be more clearly understood. In the third A picture, due to the magnitude of the inductor current IL, the zero-point detection unit Π5 is used for detection, and the Nacha signal generation unit shed and the closed 415 operation processing, so that the conduction of the first-switch Q1 is in the inductance. After the current iL is zero. Although it can ensure that the control (4) operation is near the critical point of the discontinuous current mode and the continuous current mode, there is a relatively efficient efficiency. In the simple case, the conduction current of the Q1 is also fixed. Set the current size to reduce the requirements of -(1) 22 201025806 and inductor L剌 current. However, for heavy-duty situations, the DC-to-DC converter circuit needs to operate in continuous current mode to provide higher energy to the output per unit time, and the embodiment shown in Figure 3A will be more difficult to comply with. Therefore, in the third b diagram, the increase-limit recorder 165 receives the current reference potential TO and the reverse side receives the current side signal cs. When the current detection signal cs is lower than the current reference potential VB2, the 'p turbulence comparator 165 outputs the high current limit current determination signal CLIM to the AND gate 415 in the pulse signal generation unit 400, please also refer to the sixth ❹B ® . When the output voltage Vout is lower than the voltage value and the previous conduction time interval

The fixed length of time (the lower edge triggering unit 425 sets the delay between the materials in order to release the inductance L to the capacitor C), and the gate 415 turns out the high level signal to turn on the first switch Q1. In this way, it is ensured that the first switch Q1 can be stored again after the inductor current IL is lower than a predetermined current value, so that a higher energy transfer rate can be provided. Moreover, when the on-time is fixed, the maximum value of the inductor current IL is also indirectly limited, so that the first switch Q1 and the inductor L are not subjected to a large current that cannot be confirmed, and the risk is destroyed. 'By referring to the fourth B diagram, it is a circuit diagram of the operation cycle detection of the embodiment shown in the third β diagram. In this embodiment, the operation cycle detecting unit 200 determines whether the interval of generation of the voltage feedback signal fb exceeds a predetermined time length (in fact, the first control signal UGATE can be used instead of the voltage feedback signal FB as a judgment basis) Whether it is possible to produce a mouth sound and prevent it. Therefore, after receiving the frequency hopping control signal Skip_M〇de and the voltage feedback signal FB, and after the upper edge triggering unit 22〇 and the delay triggering unit 230 are processed, the D-type latch is detected to detect the D endpoint. 23 201025806 Based DC to DC conversion circuit in normal operation, the current is judged to be low level, so that the Blang 255 is in the clear state, so no noise is generated. When the DC-to-straight conversion circuit operates in the frequency hopping mode, the current is judged to reduce Slop to the scale position. When the dragon feedback 峨ρΒ is generated for more than a predetermined length of time, the SR 255 will generate a noise prevention signal R-cmE. In this implementation, the above-mentioned _ sending unit 22G, to _ feedback, is to judge the time of the voltage feedback, but in actual design, the termination of the feedback voltage feedback Time points, or a combination thereof, to judge. Different touches j although there is a - to - week_time drop. However, since the operating frequency of the control is turned over by the human ear, the noise prevention function of the present invention is not affected.第七Multiple Test No. 7B, which is a schematic diagram of a preferred real-time circuit of the frequency hopping judging unit of the embodiment shown in the third β diagram. In the example of the seventh Kirin, she only replaced the reverse current LG with the second control LGATE, so the operation is the same as the π king, so it will not be repeated here. In addition, the embodiment of the third embodiment shown in Fig. 3 and the embodiment of the second diagram can share the on-time control unit 300 of the fifth diagram, and therefore will not be described here. Next, the eye is referred to the eighth figure, which is a signal waveform timing chart of the circuit of the embodiment shown in the third B. Please also refer to the third B diagram. When the inductor current IL is lower than the predetermined current limit value 1〇 (that is, the current level represented by the current reference potential), the current limit comparator! 65 Output and level current limit judgment signal CLIM. As the inductor current IL becomes smaller, the output power > 1 Vout also gradually decreases 'when the output voltage v 〇ut is lower than the predetermined voltage value v ,, 24 201025806, the feedback unit 155 outputs the high-level county feedback signal which is. At this time, the first period T1 is entered. At the same time, the sixth β map is referred to. The squeaking time gambling, the current limiting determination signal CLIM and the voltage feedback (4) are all high levels, so that the gate 415 outputs the high level guiding side. _ 发D Lang. D rushes to the high level pulse signal Ci〇ck, and the switch s is turned off, so that the charging capacitor α starts to charge, and the conduction reference δ 5 tiger's level starts to rise. When the output voltage _ is higher than the predetermined voltage value ν 〇 "the feedback signal FB also turns to the low level; when the inductor current IL rises above the predetermined current limit value IQ", the pump signal α turns to the low level. When the level of the on reference signal Ton touches the reference potential VR, the comparator 4〇5 outputs a high level to clear the data of the D-type flash 420. Therefore, the D-slope stops outputting the pulse signal (10) (ie, ❹三准) and causes the lower-edge trigger unit 425 to stop outputting the off-time signal for a fixed time length. At this time, because the first switch Q1 is turned off, the inductor current starts, and the output dragon VQut also begins to fall. When the inductor current is slightly lower than the pre-limit current limit I. When the output voltage V〇= is lower than the predetermined voltage value V〇, the voltage feedback signal FB also turns to the high level and enters the second period Τ2. Since the thief current at the second cycle τ2 is greater than the inductor current of the first and the temple, that is, the load is reduced, the time required for the output voltage V〇ut to depend on the value Vc) is longer. Therefore, the second period T2 is longer than =yn. In addition, when the inductor current IL is zero, the frequency hopping judging unit _ (please 2, 7th 11th) immediately outputs the high level current judging signal Skip, and detects whether the I period is zero or not, and then turns off the signal ζ_τ until a certain When the job no longer appears, and the signal ZCD0UT is off, the output current judgment signal Skip is stopped. 25 201025806 Entering the third cycle Τ3, after the voltage feedback _ FB turns to the low level, the output v 〇ut continues to be higher than the predetermined voltage value ν〇, so that the voltage feedback signal fb maintains the low level for more than the predetermined length of time. Please refer to the fourth B picture, sr Lango will output the ancient level of the material to prevent the number cap eYaE, so that the noise is stopped (four) Q3 conduction. When the capacitor c passes through the noise prevention circuit q3 to release the stored energy, so that the output is slightly lower than the predetermined electric record ν〇, the Xia back signal FB turns to a high level and stops outputting the noise prevention signal CYCLE and enters The fourth cycle T4. d Long again outputs the pulse signal Clock, so that the first-on_on is turned on and the capacitor c is recharged: Please refer to the fifth W, because the counting unit (10) Wei to the noise prevention signal quasi-control time control signal N1, so that the current source increases the current The current of the unit n charges the charging capacitor C1, so the time for the reference signal Ton to rise to the reference potential VR is shortened, the pulse width of the pulse signal ci〇ck is shortened, and the transmitted energy is reduced. The buzzer preventing circuit q3 in the above embodiment is described by an external component, and the actual noise preventing circuit (10) can also be used to control the function of not preventing the (4) sound prevention. As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the invention. It should be noted that variations and permutations equivalent to the actual implementation are intended to be encompassed within the scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the following claims. 26 201025806 [Simple description of the diagram] The straight '"IL to DC conversion circuit is the first schematic diagram of the DC to DC drop display circuit. The first A diagram is the circuit with noise prevention of a preferred embodiment of the present invention. Block diagram. Conversion circuit. The second block is a circuit block diagram of another preferred embodiment of the present invention. The first embodiment has a DC second A picture of noise prevention. The circuit diagram of the real φ-to-DC conversion circuit. The DC-turn-β-picture is a schematic diagram of a circuit with a noise-proof DC conversion circuit corresponding to the second β-graph embodiment. The fourth diagram is the implementation shown in the second diagram. A circuit diagram of a preferred embodiment of an operational cycle detection unit. The fourth diagram is a circuit diagram of a preferred embodiment of the operational lion detection unit of the embodiment shown in the drawings. The schematic diagram of the circuit of the difficult-to-implement embodiment of the fresh-keeping element is shown in Fig. 1. and Fig. A is a schematic diagram of the pulse of the embodiment of the pulse signal shown in Fig. 3A. + <#第/, B图A circuit diagram of a preferred embodiment of the pulse signal generating unit of the embodiment shown in the figure. Fig. 7A is a circuit diagram of a preferred embodiment of the frequency hopping judging unit of the embodiment shown in Fig. A. 27 201025806 Figure 7B shows the implementation shown in Figure 3B. Circuit diagram of a preferred embodiment of the frequency hopping judging unit. The eighth diagram is a timing diagram of the signal waveform of the circuit of the embodiment shown in FIG. B. [Description of main component symbols] Prior art: Current sense amplifier 10 Error amplifier 20 Pulse Width Modulation Comparator 30 Frequency Hopping Mode Controller 40 Voltage Detector 50 DC Input Voltage Vin DC Output Voltage Vout First Switch Q1 Second Switch Q2

Inductance L

Capacitor C Current Detector RCS Current Detecting Signal CS Voltage Detecting Signal VS. Reference voltage signal VREF compensator Rccomp slope compensation signal Slope 201025806

Comparison signal Comp first control number signal UGATE second control number signal LGATE The present invention: controller 100 first detecting unit 110 second detecting unit 120

Time judging unit 130 driving control circuit 140 voltage detector 150 feedback detecting unit 155 frequency hopping enabling unit 160 current limiting comparator 165 circuit reset unit 170 zero point detecting unit 175 operation period detecting unit 200 inverter 205, 235 and gate 210, 225 delay debounce unit 215 lower edge trigger unit 220 upper edge trigger unit 220' 29 201025806 delay trigger unit 230 D type latch 240 or gate 245 delay circuit 250 SR type latch 255 reverse or gate 260 conduction time control unit 300

Gate 305 Q counting unit 310 pulse signal generating unit 400 comparator 405 current source 410 and gate 415 'D-type latch 420 lower edge trigger unit 425 & frequency hopping determining unit 500 inverter 502, 504 and gate 506 signal establishing unit 510 or gate 512 D-type latch 514 > signal holding unit 530 30 201025806 reverser 532 upper edge trigger unit 534, 538 delay unit 536, 540 or gate 542 D-type latch 544 signal comparison unit 550 D-type latch 552 φ XOR Non-logic gate 554 lower edge delay unit 556 reverser 558 reverse gate 560 drive unit 600

' Output B1 ~ BN

Capacitor C Charging Capacitor C1 Pulse Signal Clock Pulse Control Signal Con Current Sense Signal CS Synchronous Diode D2 Frequency Hopping Enable Signal EN Start ENB Anti-cancellation signal EQ 31 201025806

Voltage feedback signal FB control signal GATE current unit 10~IN inductor current IL predetermined current limit value 1〇 inductance L first identification signal L3 second identification signal L4 reverse current determination signal LG second control signal LGATE on time control signal N1 ~ 丽 noise prevention signal OVER-CYCLE reset signal P0R first switch Q1 second switch Q2 noise prevention circuit Q3 hold signal QC latch re-signal Q_ZCD switch S, S1 ~ SN on time control signal S1 ~ SN current judgment signal Skip jump Frequency control signal Skip_Mode 201025806 First period τι Second period Τ 2 Third period Τ 3 Fourth period Τ 4

Predetermined delay time length Td3, Td4, Td5 Turn on reference signal Ton Cutoff time signal Toff 10 First control signal UGATE Power supply voltage VCC Input power supply Vin Output voltage Vout Voltage detection signal VS Reference voltage VB Current reference potential VB2 ® Predetermined voltage value Vo Reference Potential VR Zero Judgment Signal ZCD0UT Guide Communication Number & 33

Claims (1)

201025806 VII. Patent application scope: 1. A conversion circuit with noise prevention, comprising: a conversion circuit for converting the input voltage into an output rhythm output, the conversion circuit comprising - the first switch and the "energy storage" And the first switch is lightly connected between the two input power source and the energy storage component; and a controller 'controls the first switch according to a current flowing through the energy storage component and the output voltage to generate a first control signal And the current is less than a predetermined power value exceeds - the first predetermined time length _ a sound prevention signal; &quot;L wherein the material prevents the signal from being controlled to be connected to the noise circuit of the conversion circuit. 2. The conversion circuit having noise prevention as described in the scope of claim 2, wherein the conversion circuit further includes a synchronization_, the synchronization_frequency-connecting the first--and the other-end ground to the first-off At the cutoff time, the energy release path of the energy storage component is made. 3. The noise-reducing conversion circuit as described in the scope of claim 2, wherein the conversion circuit further includes a second switch, and the second switch is connected to the first switch and the other end is grounded. Control signals to control the second switch. 4. The noise preventing conversion circuit of claim 3, wherein the controller simultaneously turns off the first switch and the second switch when the current is less than the predetermined current value. 5. The conversion circuit with noise prevention as described in claim 3, wherein the controller comprises: 34 201025806: the first-gamma|j single it, according to the round-out to generate the electricity-back feedback signal; The second detecting unit generates a current determining signal according to the current of the stream_storage element; and a time determining unit generates the noise preventing signal when the current is less than - the predetermined current value exceeds the first predetermined length of time; And driving control circuit 'receiving the dust feedback signal and the current determination signal to generate the first control signal and the second control signal. ❹ &amp; As stated in item 5 of the claim, (4) the conversion circuit of the audio system, wherein the drive control circuit includes a pulse width of the first control signal of the on-time control unit.疋 疋 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. 7. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 9. The noise-reducing conversion electrical power-receiving-capacitor energy storage component according to claim 8 of the patent application scope, wherein the energy storage tree is deducted to rotate the output power. 10. As described in claim 9 The circuit has a noise prevention conversion circuit, wherein the noise prevents the circuit from the capacitive ship tree, and the sound is prevented from controlling the noise by the signal--predetermined electric view, the electric ship is simple, and the light is low. 35 201025806 u. The conversion circuit of the squeaking prevention described in item 9 of the Φ patent scope wherein the (four) tone prevention signal causes the control noise prevention circuit to re-storage the energy storage element. For example, the noise-preventing conversion electric power described in the j-th aspect of the patent application, wherein the sound-preventing circuit is provided, the sound-preventing signal makes the ship component lightly connected - the reference potential is - the second predetermined length is transferred to the energy storage of the weaving component . 13. A conversion circuit with noise prevention, including ·· a conversion circuit for converting the input plane into an output (four) output, the conversion circuit package 3-the-off and the energy storage component, and the first-opening-connecting to an input power source and the energy storage component And a controller that generates a voltage feedback signal according to the output voltage, and controls the first-off based on the current flowing through the energy storage element and the output voltage to generate a -first control signal, and based on Two adjacent first-control signals or the face-back slave slave time__--the first-time-on-duty degree to determine whether to generate a...sound prevention signal, wherein the noise prevention signal controls the female to connect to the conversion circuit —Sound-proof circuit. 14. If there is a noise-preventing conversion circuit in the 13th remuneration of the material, the time interval of the (-)th signal is based on the generation time point and termination point of the voltage feedback signal of the first control signal. Or swearing. . The KM material Wei _13 item Wei has the conversion power of the material ^, wherein the conversion circuit further includes a synchronous switch, the synchronous switch-end-transfer far-_ and the other end are grounded to the first __ As the energy release path of the energy storage component 36 201025806. Road, two ^ please special fiber around the 13th Gu Xu riding noise to prevent the conversion of electricity - the end 1 Γ change circuit also contains "second switch, - the end _ the first switch and the miscellaneous more generated - the second control signal to control Following the second switch. In the middle 2, please turn over the (four) tone prevention conversion circuit described in Item 16. The controller is less than a predetermined current switch and the second switch.啊 第 第 第 第 第 第 第 第 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 申请 i 申请 i i 申请 申请 申请 i i i i 申请 i i i i i 申请, - - - - 单 S ' according to the current flowing through the energy storage tree - current determination signal; the inter-kiss judgment unit, the interval between the two adjacent - control signals or the voltage feedback signal exceeds the first The noise control number is generated for a predetermined length of time; and the drive control circuit is coupled to the (four) power (four) license and the current signal to generate the first control number and the second control signal. 19. The (four) tone preventing conversion circuit according to claim 18, wherein the crane (four) circuit includes a conduction_control element for determining a pulse width of the first control signal. 2. The noise-preventing conversion circuit according to the scope of the patent application, wherein the inter-handle control unit is adjusted according to the number of times the noise prevention signal is generated. 37 201025806 The pulse width of the first control signal is adjusted. . 21. The conversion circuit having a voice prevention as described in claim 13 wherein the energy storage element is an m-pressor or an inductive component. 22. The conversion circuit with a bath sound prevention as described in claim 21 of the patent application section further includes a capacitive ship element. 23. The noise-preventing switching circuit as described in claim 22, wherein the noise preventing circuit transmits the capacitive energy storage tree, and the noise preventing signal controls the noise preventing circuit to discharge the capacitive element The output voltage is caused to be lower than a predetermined voltage value. 24·If the noise protection is changed, the new noise storage device as described in item 22 of the patent application scope is used to control the noise prevention circuit to make the energy component 〇S The conversion electric-reference L-tone prevention circuit converts the ship component into a vertical-second time length to transfer the energy of the young component according to the noise prevention. - Input to convert the Yang sound to prevent the conversion controller, used to control - the conversion circuit converts the input power into the - wheel voltage, including: H measurement unit 'reduction of money 峨 _ voltage feedback signal; current judgment According to the current-side signal of the conversion circuit, a time judging unit is generated, and according to the time interval of the current judging signal, it is determined that 38 201025806 generates a noise-preventing signal, and the noise is prevented from being replaced by one of the circuits. The noise prevention circuit; and the turn-drive control circuit, the back-to-back bath sound prevention signal is generated to generate a signal to the handsome (4) signal and a control signal to control the conversion circuit. Qiao 27·If applying for the protection of the noise prevention mentioned in Item IF, the second detection unit includes a zero detection comparator according to the 电流 current detection signal and a zero reference potential to generate The current determination signal is based on the system __27 赖 叙 (4) sound prevention conversion, n, 丨 rhyme - Detective element further contains - current limit comparator, according to =. /The current production and - current limit reference electricity generation - current limit judgment signal controller 咐 咐 咐 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” Whether the at least one control signal is generated. 疋 30* ” the material fiber circumference of the first 赖 状 ( 四 四 四 四 四 四 四 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕 懕Touch to generate the feedback signal. The crying 31. The arm control preventing switching control as described in claim 26, wherein the driving circuit comprises an on-time control unit for determining the "pulse width of the first control signal." The switching control state with noise prevention as described in claim 31, wherein the on-time control unit adjusts the pulse width of the first control signal according to the number of occurrences of the noise prevention signal 39 201025806. a conversion controller for controlling a conversion circuit to convert an input power into an output voltage, comprising: a first-detection unit it, generating a voltage feedback signal according to the wheel voltage; and a second detection a unit, according to one of the conversion circuits, current detection: two current determination signals; a time determination material, generating a material prevention signal to control her to receive a noise prevention circuit of the conversion circuit; and a drive control circuit 'receiving the feedback The signal, the current judgment signal, and the m-day prevention function to generate a _th-control signal to (four) one of the first switches of the conversion circuit; ': The inter-office judgment unit determines whether or not the noise prevention signal is generated according to the length of the predetermined time period and the adjacent two control positions or the voltage feedback signals. ~ 34. The conversion control control with noise prevention described in the above section 33, wherein the drive control circuit further generates a second control signal to control the second circuit of the conversion circuit, and the first-off is different from the second switch 35. A noise-converting conversion controller as described in claim 33, wherein the second_unit includes a _zero-side comparator for generating a current reference signal and a 1-point reference The current determination signal 36. The noise prevention conversion control benefit as described in the scope of the patent application, wherein the second detection unit further includes a current limiting comparator, according to the current detection signal according to 201025806 and A current limiting reference potential is used to generate a current limit to determine the lanogram. I wish 37. The noise control conversion suppression benefit as described in claim 36, wherein the drive control circuit Receiving the current limit determination signal to determine whether the at least one control signal is generated. 38. The noise detection conversion device according to the scope of claim 2, wherein the first detection unit includes a feedback detection unit According to the round of the spring and the voltage reference potential to generate the electric dust feedback signal. 39. The noise prevention conversion controller of claim 33, wherein the drive control circuit comprises a conduction a time control unit for determining a pulse width of the first control signal. 40. A noise prevention conversion controller as described in the scope of the patent application, wherein the on-time control unit generates a signal according to the noise prevention signal The number of times adjusts the pulse width of the first control signal. ❹ 41