JP5486222B2 - Semiconductor integrated circuit and power supply device - Google Patents

Description

  The embodiments mentioned in this application relate to a semiconductor integrated circuit and a power supply device.

  2. Description of the Related Art In recent years, DC / DC converters (power supply devices) that convert a constant power supply voltage into a desired power supply voltage and output it have been widely used in various electric devices including portable terminals.

  By the way, for example, the on-time fixed bottom detection comparator type asynchronous DC-DC converter varies in frequency depending on the load, and when the load becomes very light, the switching frequency decreases to near 0 Hz.

  Conventionally, various DC / DC converters (switching regulators) have been proposed.

JP 2005-218166 A

  As described above, for example, an on-time fixed bottom detection comparator type asynchronous DC-DC converter has a low switching frequency at a light load, and the switching frequency is in an audible range (for example, about 20 Hz to 20 KHz). Become.

  That is, audible noise occurs due to the switching of the DC-DC converter, and it is therefore difficult to employ such a DC-DC converter as a power supply device for audio equipment.

  In addition, the problem of the switching frequency of a DC-DC converter and the noise in the electric equipment to which the DC-DC converter is applied is not limited to the case where the switching frequency is applied to the audible range of the audio equipment.

  That is, there is a similar problem when the switching frequency of the DC-DC converter is in a frequency range that can be a noise in an electrical device to which the DC-DC converter is applied.

  An object of this application is to provide a semiconductor integrated circuit and a power supply device that do not fall within a frequency range in which the switching frequency may become noise.

  According to one embodiment, switching of a power supply device comprising: a first switching element provided between a first power supply line and a first node; and a diode element provided between the first node and a second power supply line. A semiconductor integrated circuit for controlling the above is provided.

  The semiconductor integrated circuit controls switching of the power supply device at a switching frequency defined by the size of a load connected to the output terminal.

  The semiconductor integrated circuit is provided between the output terminal and the second power supply line, and controls the lowest switching frequency to be higher than the first frequency in accordance with a first signal for controlling the first switching element. A frequency clamp circuit is included.

  The disclosed semiconductor integrated circuit and power supply device have an effect that the switching frequency does not fall in a frequency range where noise can occur.

It is a block diagram which shows an example of a power supply device. It is a wave form diagram for demonstrating operation | movement of the power supply device of FIG. It is a block diagram which shows the power supply device of 1st Example. FIG. 4 is a circuit diagram illustrating an example of a delay circuit in the power supply device of FIG. 3. It is a wave form diagram for demonstrating operation | movement of the power supply device of FIG. It is a figure for demonstrating the characteristic of the power supply device of FIG. It is a block diagram which shows the power supply device as a comparative example. It is a figure for demonstrating the efficiency of the power supply device of 1st Example compared with the power supply device of FIG. It is a block diagram which shows the power supply device of 2nd Example. FIG. 10 is a block diagram illustrating an example of a frequency detection circuit in the power supply device of FIG. 9. It is a figure for demonstrating the characteristic of the frequency detection circuit of FIG. It is a figure for demonstrating the characteristic of the power supply device of FIG. It is a block diagram which shows the power supply device of 3rd Example. It is a wave form diagram for demonstrating operation | movement of the power supply apparatus of a current mode. It is a wave form diagram for demonstrating operation | movement of the power supply device of FIG. It is a block diagram which shows the power supply device of 4th Example.

  First, before describing the embodiment in detail, an example of a power supply device and problems of the power supply device will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a block diagram showing an example of a power supply device, and shows an example of an asynchronous DC-DC converter of a fixed on-time bottom detection comparator system.

  In FIG. 1, reference numeral 100 denotes a DC-DC converter (power supply device), 10 denotes a DC-DC converter IC (semiconductor integrated circuit), 1 denotes a comparator, and 2 denotes a one-shot circuit.

  Reference numeral 3 is an RS flip-flop, 51 is a switching transistor (main-side transistor: pMOS transistor), 52 is a diode element (diode), 6 is a coil, 7 is a smoothing capacitor, and 8 is a load. .

  As shown in FIG. 1, the power supply device 100 includes a semiconductor integrated circuit 10, a switching transistor 51, a diode 52, a coil 6, and a smoothing capacitor 7.

  Transistor 51 and diode 52 are connected in series between a high-potential power supply line to which power supply voltage Vin is applied and a ground line to which ground potential GND is applied.

  Here, in the power supply device 100 of FIG. 1, the transistor 51 and the diode 52 are provided outside the semiconductor integrated circuit 10, but may be provided inside the semiconductor integrated circuit 10.

  The gate of the transistor 51 is supplied with the signal Sa of the inverting output terminal / Q of the flip-flop 3, whereby the transistor 51 is on / off controlled.

  A connection node LX (LX terminal) of the transistor 51 and the diode 52 is connected to the output terminal OUT of the power supply device 100 via the coil 6, and a smoothing capacitor 7 is provided between the output terminal OUT and the ground line GND. Is provided.

  The semiconductor integrated circuit 10 includes a comparator 1, a one-shot circuit 2, an RS flip-flop 3, and resistors R1 and R2.

  The comparator 1 compares the voltage FB obtained by dividing the output voltage Vo with the resistors R1 and R2 with the reference voltage Vr, and supplies the output signal to the set terminal S of the flip-flop 3 when the voltage FB decreases to the reference voltage Vr.

  The output signal of the one-shot circuit 2 is supplied to the reset terminal R of the flip-flop 3, and the signal Sa from the flip-flop 3 is supplied to the input of the one-shot circuit 2. As a result, the signal Sa has a fixed on-time (period of low level “L”).

FIG. 2 is a waveform diagram for explaining the operation of the power supply device of FIG.
As shown in FIG. 2, when the output voltage Vo of the DC-DC converter 100 drops to a predetermined bottom voltage Vb, the comparator 1 detects that the voltage FB drops to the reference voltage Vr, and a high level “H” signal is detected. Is supplied to the set terminal S of the flip-flop 3.

  As a result, the signal Sa at the inverting output terminal / Q of the flip-flop 3 becomes low level “L”. Here, the one-shot circuit 2 outputs a signal “H” to the reset input R of the flip-flop 3 after a fixed on-time after the signal Sa changes to “L”.

  As a result, the signal Sa becomes “L” for a fixed on-time, and the switching transistor 51 is turned on only for the “L” period of the signal Sa.

  As a result, the potential of the LX terminal is pulled up toward the power supply voltage Vin, the coil current IL increases, and the output voltage Vo becomes the predetermined peak voltage Vp.

  Thereafter, when the signal Sa changes from “L” to “H” and the transistor 51 is turned off, the output voltage Vo decreases to a predetermined bottom voltage Vb with a slope (time) according to the magnitude of the load 8. Repeat the process.

  Here, the period from when the signal Sa changes from “L” to “H” and the transistor 51 turns off until the signal Sa changes from “H” to “L” and the transistor 51 turns on (off period T0off). As the load 8 becomes lighter, it becomes longer.

  That is, the switching period T0 becomes longer when the load 8 becomes lighter, and therefore the switching frequency f of the DC-DC converter 100 becomes lower when the load 8 becomes lighter.

  As a result, for example, when the switching frequency f of the DC-DC converter 100 is applied to an audible range (for example, about 20 Hz to 20 KHz), there is a possibility that noise of a device to which the power supply device is applied.

  In FIG. 1, the switching transistor 51 is a pMOS transistor, but it may be an nMOS transistor. In this case, the signal Sa uses the signal of the non-inverting logic terminal (positive logic terminal Q) of the flip-flop 3. Will do.

Hereinafter, embodiments of the semiconductor integrated circuit and the power supply device will be described in detail with reference to the accompanying drawings.
FIG. 3 is a block diagram showing the power supply device of the first embodiment, and shows an example of an asynchronous DC-DC converter of a fixed on-time bottom detection comparator system.

  As is clear from comparison between FIG. 3 and FIG. 1 described above, the DC-DC converter 100a (semiconductor integrated circuit 10a) of the first embodiment is the lowest frequency clamp circuit 4 with respect to the DC-DC converter 100 of FIG. Is to be provided.

  That is, the lowest frequency clamp circuit 4 includes a delay circuit 41, a discharge transistor (second switching element: nMOS transistor) 42 and a resistor 43.

  The resistor 43 and the transistor 42 are connected in series between the output terminal OUT and the ground line GND. Here, the output signal Sb of the delay circuit 41 is supplied to the gate of the transistor 42.

  4 is a circuit diagram showing an example of a delay circuit in the power supply device of FIG. 3, and FIG. 5 is a waveform diagram for explaining the operation of the power supply device of FIG.

  As shown in FIG. 4, the delay circuit 41 includes a current source 411, an inverter 412, an nMOS transistor 413, a capacitor 414, a comparator 415, and an AND gate 416.

  First, as shown in FIGS. 4 and 5, when the signal Sa changes from “H” to “L”, the transistor 413 is turned on by the signal inverted by the inverter 412. As a result, the voltage V1 becomes “L”, the output of the comparator 415 becomes “L”, and the output of the AND gate 416 also becomes “L”.

  Further, when the signal Sa changes from “L” to “H” after the fixed on time of the signal Sa, the transistor 413 is turned off, and the capacitor 414 has the current source 411 to which the circuit power supply voltage VCC is applied. Charge is accumulated by the current I1.

  When the voltage V1 becomes the reference voltage Vc for the delay circuit due to the charge accumulated in the capacitor 414, the output signal of the comparator 415 changes from “L” to “H” and the signal Sb from the AND gate 416 to “H”. Is output.

  That is, the output signal Sb of the delay circuit 41 changes from “H” to “L” in accordance with the change of the signal Sa from “H” to “L”, and then from “L” to “H” of the signal Sa. It changes from “L” to “H” at the timing when the change to is delayed.

  Here, as shown in FIGS. 3 and 5, the signal Sb is supplied to the gate of the transistor 42. After the signal Sa has changed from “L” to “H” and delayed for a predetermined time, the transistor 42 is turned on. Turns on and pulls down the output voltage Vo toward the ground potential GND.

  As a result, the output of the comparator 1 changes from “L” to “H”, and the next switching cycle in which the transistor (first switching element) 51 is turned on for a fixed on-time is started.

  Here, the delay time from when the signal Sa changes from “L” to “H” to when the signal Sb changes from “L” to “H” is, for example, the minimum value of the switching frequency f at light load. The frequency is set so that fmin is higher than the upper limit of the frequency range where noise can be generated.

  Specifically, for example, the signal Sa changes from “L” to “H” after the signal Sa changes from “L” to “H” depending on the capacitance of the capacitor 414 and the value of the reference voltage Vc for the delay circuit. Set the delay time until

  Thereby, the minimum frequency fmin of the switching frequency f of the DC-DC converter 100a is not applied to a frequency range (for example, an audible range of audio equipment: about 20 Hz to 20 KHz) that may be noise of a circuit that uses the switching frequency f. Can be set.

  FIG. 6 is a diagram for explaining the characteristics of the power supply device of FIG. Here, the curve L10 shows the relationship between the load current Io and the switching frequency f by the DC-DC converter 100 of FIG. 1, and the curve L11 shows the load current Io and the switching frequency by the DC-DC converter 100a of FIG. The relationship with f is shown.

  First, as shown by a curve L10, in the DC-DC converter 100 of FIG. 1, when the load 8 becomes light and the load current Io decreases, the switching frequency f decreases toward 0 Hz.

  That is, when the load 8 becomes lighter and the load current Io becomes smaller, the switching frequency f becomes lower, for example, in the audible range (about 20 Hz to 20 KHz).

  On the other hand, as indicated by the curve L11, the DC-DC converter 100a of FIG. 3 is lower than the lower limit of the switching frequency fmin even when the load 8 becomes light and the load current Io becomes small. There is nothing.

  That is, when the load 8 becomes light and the load current Io decreases, the switching frequency f decreases. At this time, the transistor 42 is forcibly turned on and the minimum frequency fmin is set higher than the audible range (for example, 20 KHz). ) Will be maintained.

  When the present embodiment is applied to an audio device, the minimum frequency fmin is set to, for example, 20 KHz, which is the upper limit of the audible range, but the application of the present embodiment is not limited to the audio device. Further, the minimum frequency fmin is not limited to 20 KHz.

  That is, when the switching frequency of the DC-DC converter is in a frequency range that can be noise in an electric device to which the DC-DC converter is applied, the minimum frequency fmin is set to a frequency higher than the upper limit of the frequency that can be noise. Will be.

  FIG. 7 is a block diagram showing a power supply device as a comparative example, and shows a synchronous rectification type DC-DC converter.

  As is clear from the comparison between FIG. 7 and FIG. 1, the synchronous rectification DC-DC converter 100 ′ of this comparative example is the synchronous side in which the signal Sa is supplied to the gate in parallel with the diode 52 in the power supply device of FIG. A transistor (nMOS transistor) 50 is provided.

  In FIG. 7, an nMOS transistor having a gate supplied with the signal Sa is provided in parallel with the diode 52. However, the synchronization transistor 50 is not an nMOS transistor but a pMOS transistor, and the signal Sa is logically inverted at the gate. A signal may be supplied.

  As shown in FIG. 7, in the DC-DC converter 100 ′ of this comparative example, during the period when the signal Sa is “L”, the pMOS transistor 51 is turned on and the nMOS transistor 50 is turned off. Pull up toward voltage Vin.

  On the other hand, during the period when the signal Sa is “H”, the transistor 51 is turned off and the transistor 50 is turned on to pull down the potential of the LX terminal toward the ground potential GND.

  Here, in actual use, although not shown, both transistors 50 and 51 are turned on so that no through current flows, for example, both at the time of switching using an AST (Anti Shoot Through) circuit. A short period of off can be inserted.

  As a result, the DC-DC converter 100 ′ shown in FIG. 7 repeats the process at a substantially constant switching frequency (fixed frequency).

  FIG. 8 is a diagram for explaining the efficiency of the power supply device of the first embodiment in comparison with the power supply device of FIG. 8A shows the synchronous rectification type DC-DC converter of FIG. 7, and FIG. 8B shows the comparator of the first embodiment having the lowest frequency clamp circuit 4 of FIG. 1 shows an asynchronous DC-DC converter of the type.

  First, as shown in FIG. 8A, in the DC-DC converter 100 'shown in FIG. 7, the switching frequency f is substantially constant. However, in the current where the load current Io is equal to or lower than the discontinuous mode, the loss is generated by the transistor 50 on the synchronization side, and the efficiency is greatly reduced.

  On the other hand, as shown in FIG. 8B, in the DC-DC converter 100a of the first embodiment, the loss due to the transistor 42 and the resistor 43 in the lowest frequency clamp circuit 4 is generated, which is slightly efficient. Decreases.

  However, in the DC-DC converter 100a of the first embodiment, the efficiency is lowered in the region where the switching frequency f is equal to or lower than the minimum frequency fmin.

  That is, as shown in FIG. 8B, when fmin is set to 20 kHz (the upper limit of the audible range), the switching frequency at a normal load current is about 500 kHz, so that the efficiency in a region with a sufficiently small load current is improved. Therefore, it is not a problem of substantial efficiency reduction.

  As is apparent from the comparison between FIG. 8A and FIG. 8B, the DC-DC converter 100a of the first embodiment compares the load in which the load current Io in the comparative example is equal to or less than the discontinuous mode. It can be seen that the efficiency can be significantly increased in the light region RR.

  FIG. 9 is a block diagram showing a power supply device of the second embodiment, FIG. 10 is a block diagram showing an example of a frequency detection circuit in the power supply device of FIG. 9, and FIG. 11 explains the characteristics of the frequency detection circuit of FIG. FIG.

  As is clear from comparison between FIG. 9 and FIG. 3, in the second embodiment, the lowest frequency clamp circuit 4 ′ includes a frequency detection circuit 44, a discharge transistor (second switching element: nMOS transistor) 42 and a resistor 43. Have.

  That is, in the DC-DC converter 100b of the second embodiment, a frequency detection circuit 44 is provided instead of the delay circuit 41 in the first embodiment, and the transistor 42 is controlled by the output signal Sc of the frequency detection circuit 44. It has become.

  In the DC-DC converter 100b of the second embodiment shown in FIG. 9, the transistor 51 and the diode 52 are built in the semiconductor integrated circuit 10b. However, as in the first embodiment described above, the semiconductor integrated circuit is provided. It may be provided outside the circuit.

  As shown in FIG. 10, the frequency detection circuit 44 receives the signal Sa from the flip-flop 3 and converts the frequency into a voltage, and a hysteresis comparator (Schmitt trigger) 442 having hysteresis characteristics. Have

  As shown by the curve L21 in FIG. 11, the F / V converter 441 outputs a voltage Vc corresponding to the frequency of the signal Sa, and as shown by the curve L22, the hysteresis comparator 442 has a hysteresis characteristic (fh). Then, the voltage Vc is compared with the reference voltage Vrc.

  That is, the hysteresis comparator 442 compares the voltage Vc with the reference voltage Vrc, and when the voltage Vc changes to the lower side, that is, when the frequency f changes to the lower side, the frequency fmin is set to the lowest frequency from “L”. The signal Sc changing to “H” is output.

  Thereby, when the switching frequency of the DC-DC converter 100b becomes the minimum frequency fmin, the transistor 42 is turned on, the output voltage Vo is pulled down toward the ground potential GND, and the next switching cycle is started.

  FIG. 12 is a diagram for explaining the characteristics of the power supply device of FIG. 9 and corresponds to the characteristic diagram shown in FIG. 11 rewritten in correspondence with FIG. 6 described above.

  Here, the curve L10 shows the relationship between the load current Io and the switching frequency f by the DC-DC converter 100 of FIG. 1, and the curve L31 shows the load current Io and the switching frequency by the DC-DC converter 100b of FIG. The relationship with f is shown.

  As shown by the curve L31, in the DC-DC converter 100b of FIG. 9, even if the load 8 becomes light and the load current Io decreases, the switching frequency f has a predetermined hysteresis characteristic (fh) and the frequency fmin. Is the lower limit, and it does not become lower than that.

  Of course, the application of the second embodiment is not limited to audio equipment, and the same applies to the embodiments described later.

  FIG. 13 is a block diagram showing a power supply device of a third embodiment, and shows a current mode (C-mode) DC-DC converter.

  In the first and second embodiments described above, the voltage FB generated by feeding back the output voltage Vo is compared with the reference voltage Vr by the error comparator 1, and the output signal of the comparator 1 is applied to the set terminal S of the RS flip-flop 3. You are typing.

  On the other hand, in the third embodiment shown in FIG. 13 (and the fourth embodiment shown in FIG. 16), the clock CLK is supplied to the set terminal S of the RS flip-flop 3. Further, the error amplifier 11 converts the potential difference between the voltage FB and the reference voltage Vr1 into a DC voltage signal COMP.

  Then, the comparator 12 compares the signal COMP with the reference voltage Vr2, and the comparator 13 compares the signal COMP with the output signal of the current detection circuit 9.

  As shown in FIG. 13, in the DC-DC converter 100 c of the third embodiment, the output signals of the comparators 12 and 13 are supplied to the reset terminal R of the RS flip-flop 3 via the OR gate 16.

  Note that a capacitor 14 and a resistor 15 connected in series are connected between an input to which the voltage FB of the error amplifier 11 is supplied and an output.

  The current detection circuit 9 is provided between the transistor 51 and the LX terminal, detects the coil current IL flowing from the high potential power line to the coil 6 during the ON period of the transistor 51, and generates a voltage Vs that rises correspondingly. Output.

  As apparent from the comparison between FIG. 13 and FIG. 3, the DC-DC converter 100c of the third embodiment is the same as the minimum frequency clamp circuit 4 in the DC-DC converter 100a of the first embodiment described above. Things are provided.

  In the DC-DC converter 100c of the third embodiment shown in FIG. 13, the transistor 51, the diode 52 and the current detector 9 are built in the semiconductor integrated circuit 10c, but are provided outside the semiconductor integrated circuit. You can also.

  FIG. 14 is a waveform diagram for explaining the operation of the current mode power supply device, and FIG. 15 is a waveform diagram for explaining the operation of the power supply device of FIG. Here, the waveform diagram shown in FIG. 14 shows the operation of the DC-DC converter 100c shown in FIG. 13 excluding the lowest frequency clamp circuit 4.

  As shown in FIG. 14, when the potential of the output signal COMP of the error amplifier 11 becomes equal to or higher than the reference voltage Vr2, the signal Sd becomes “L” according to the clock CLK, the transistor 51 repeats the switching operation, and the output voltage Vo is sawtooth. It rises in a wave shape.

  Then, as shown in FIG. 14, when the potential of the signal COMP becomes lower than the reference voltage Vr2, the signal Sd is held at “H”, the load current Io flows according to the magnitude of the load 8, and the output voltage Vo gradually increases. Lower.

  At this time, similarly to the case described with reference to FIG. 2, at the time of a light load, the operation cycle T10 of the DC-DC converter becomes long, and there is a possibility that it becomes noise of an electric device to which the DC-DC converter is applied. .

  In such a case, as shown in FIG. 15, in the DC-DC converter 100c of the third embodiment, the transistor 42 is forcibly turned on by the signal Se obtained by delaying the signal Sd by the delay circuit 41, and the output voltage Vo Is pulled down toward the ground potential GND.

  As a result, even when the load 8 is light and the load current Io hardly flows, the operation cycle T11 of the DC-DC converter 100c is limited to become noise of an electric device to which the DC-DC converter 100c is applied. Can be prevented.

FIG. 16 is a block diagram showing the power supply device of the fourth embodiment.
As is clear from comparison between FIGS. 16 and 13 and FIGS. 9 and 3, in the fourth embodiment shown in FIG. 16, a frequency detection circuit 44 is provided instead of the delay circuit 41 in the third embodiment described above. The transistor 42 is controlled by the output signal Sf of the frequency detection circuit 44.

  In the DC-DC converter 100d of the fourth embodiment shown in FIG. 16, the transistor 51, the diode 52 and the current detector 9 are provided outside the semiconductor integrated circuit 10d. It can also be provided.

  In each of the embodiments described above, for example, the transistors 51 and 42 are not limited to pMOS and nMOS transistors, and various switching elements can be applied.

  Furthermore, in each embodiment, the lowest frequency clamp circuits 4 and 4 'are merely examples, and it goes without saying that various modifications can be made.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
Switching of a power supply device having a first switching element provided between the first power supply line and the first node and a diode element provided between the first node and the second power supply line is connected to an output terminal. A semiconductor integrated circuit controlled at a switching frequency defined by the size of the load,
A minimum frequency clamp that is provided between the output terminal and the second power supply line and controls the minimum frequency of the switching frequency to be higher than the first frequency in response to a first signal that controls the first switching element. A semiconductor integrated circuit comprising a circuit.

(Appendix 2)
In the semiconductor integrated circuit according to attachment 1,
The semiconductor integrated circuit according to claim 1, wherein the first frequency is a maximum frequency that may cause noise in an electrical device to which the power supply device is applied.

(Appendix 3)
In the semiconductor integrated circuit according to appendix 1 or 2,
The minimum frequency clamp circuit is:
A second switching element provided between the output terminal and the second power supply line;
A delay circuit that detects an off timing of the first switching element based on the first signal and outputs a second signal, and turns on the second switching element based on the second signal from the delay circuit. A semiconductor integrated circuit.

(Appendix 4)
In the semiconductor integrated circuit according to attachment 3,
The delay circuit outputs the second signal with a delay from a timing when the first switching element is turned off by the first signal by a time for maintaining the switching frequency higher than the first frequency. A semiconductor integrated circuit.

(Appendix 5)
In the semiconductor integrated circuit according to appendix 1 or 2,
The minimum frequency clamp circuit is:
A second switching element provided between the output terminal and the second power supply line;
A frequency detection circuit that detects the switching frequency by the first signal and outputs a third signal, and turns on the second switching element by the third signal from the frequency detection circuit. A semiconductor integrated circuit.

(Appendix 6)
In the semiconductor integrated circuit according to attachment 5,
The frequency detection circuit compares the switching frequency detected by the first signal with the first frequency with a predetermined hysteresis characteristic, and maintains the switching frequency higher than the first frequency. A semiconductor integrated circuit characterized in that

(Appendix 7)
The semiconductor integrated circuit according to any one of appendices 1 to 6,
A coil provided between the first node and the output terminal;
And a smoothing capacitor provided between the output terminal and the second power supply line.

(Appendix 8)
The power supply apparatus according to appendix 7, wherein the power supply apparatus is a comparator type DC / DC converter.

(Appendix 9)
The power supply apparatus according to appendix 7, wherein the power supply apparatus is a current mode DC / DC converter.

DESCRIPTION OF SYMBOLS 1 Comparator 2 One shot circuit 3 RS flip-flop 4, 4 'Minimum frequency clamp circuit 6 Coil 7 Smoothing capacitor 8 Load 9 Current detection circuit 10, 10'; 10a-10d Semiconductor integrated circuit (IC for DC-DC converter)
41 delay circuit 42 second switching element (discharge transistor: nMOS transistor)
43 Resistor 44 Frequency detection circuit 50 Synchronous transistor (nMOS transistor)
51 1st switching element (main side transistor: pMOS transistor)
52 Diode element (diode)
100, 100 '; 100a to 100d Power supply (DC-DC converter)
441 F / V converter 442 Hysteresis comparator (Schmitt trigger)

Claims (7)

A first switching element provided between the first power supply line and the first node ;
A diode element provided between the first node and the second power supply line ;
A minimum frequency clamp circuit provided between an output terminal and the second power supply line;
With
The minimum frequency clamp circuit is:
A second switching element provided between the output terminal and the second power supply line;
A delay circuit that detects the off timing of the first switching element based on the first signal and outputs the second signal; or a frequency detection circuit that detects the switching frequency based on the first signal and outputs the third signal. ,
The lowest frequency clamp circuit turns on the second switching element by the second signal from the delay circuit or by the third signal from the frequency detection circuit. The circuit according to claim 1, wherein the lowest frequency clamp circuit maintains a lowest switching frequency higher than the first frequency based on the first signal. Before SL delay circuit, the first switching element is delayed from the time of OFF to output the second signal by the first signal, the delay time, the said minimum frequency of the switching frequency from the first frequency The circuit according to claim 2, wherein the circuit is set to be higher . Before Symbol frequency detection circuit, and a pre-Symbol switching frequency and the first frequency compared with a predetermined hysteresis characteristic, said third signal to said lowest frequency of the switching frequency is maintained higher than the first frequency you output circuit according to claim 2. The circuit according to any one of claims 1 to 4, wherein the first signal is a signal for controlling the first switching element. The circuit according to any one of claims 1 to 5, wherein the switching frequency is defined by a size of a load connected to an output terminal. And circuitry according to any one of claims 1 to 6,
A coil provided between the first node and the output terminal;
A smoothing capacitor provided between the output terminal and the second power supply line;
A power supply unit having

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