TW201025566A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW201025566A
TW201025566A TW098133278A TW98133278A TW201025566A TW 201025566 A TW201025566 A TW 201025566A TW 098133278 A TW098133278 A TW 098133278A TW 98133278 A TW98133278 A TW 98133278A TW 201025566 A TW201025566 A TW 201025566A
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Taiwan
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semiconductor device
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TW098133278A
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TWI383489B (en
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Kazuya Aizawa
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The present invention provides a semiconductor device for integrating a starting circuit and a peripheral circuit together. A main body region 15 is formed on the drain region 121 defined by a device separation region 13. An N-type first source region 16 is formed on the main body region 15. A first gate electrode 20 is configured between the drain region 121 and the first source region 16. The device separation region 13 includes: a ring part 131 defined therein an opening part 133; and a part 132 defined to connect to an extension region 122 of the drain region 121 via the opening part 133. A second source region 23 is formed on the extension region 122. A P-type second main body region 15 is formed on the drain region 121. An N-type third source region 16 is formed on the second main body region 15. A second gate electrode 331 is formed between the drain region 121 and the third source region 16.

Description

201025566 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置，詳細而言係關於一種高 耐壓半導體裝置。 【先前技術】 電源用IC(Integrated Circuit，積體電路）中所使用之起動 電路中，一般而言係使用高耐壓之MOSFET(Metallic Oxide Semiconductor Field Effect Transistor，金屬氧化物 β 半導體場效應電晶體），例如LDMOS(Laterally Diffused MOS，橫向擴散金屬氧化物半導體）。先前之起動電路如 圖32A所示，係於LDMOS 411之汲極-閘極間連接數ΜΩ之 電阻R，以控制LDMOS 411之驅動及斷開時之偏壓電流。 該電路構成中，當藉由主電源之導通而對起動端子T施 加高位準之電壓時，高位準之電壓經由電阻R被施加至 LDMOS 411之閘極，從而LDMOS 411導通，電流被供給至 内部電路412 » 其後，當内部電路412動作而將LDMOS之閘極電壓設為 低位準時，LDMOS 411斷開，朝向内部電路412之電流之 供給停止。 該起動電路中，經由電阻R而始終流動有與電源電壓相 應之偏壓電流。因此，不適合低功耗化。又，因LDMOS 411之汲極係直接打線接合於1C封裝之插腳，故而於施加 有靜電等之情形時，電阻有時會被破壞。 因此，考慮採用圖32B所示之電路構成，由JFET 413進 143696.doc 201025566 行LDMOS 411之驅動及洩漏電流之控制，藉此改善上述之 問題。藉由該電路構成，LDMOS 4 11斷開之期間之偏壓電 流被規定為JFET 41 3之飽和電流，相對於電壓之電流成為 固定值。又，因未使用對突波電壓較弱之高電阻，故破壞 變強。 然而，若將該起動電路直接1C化，則需要2個高耐壓元 件，從而會佔據較廣之晶片面積。 又，除起動電路以外，作為周邊電路，必需將用於流經 大電流之功率MOS、及用於檢測流經功率MOS之電流的感 測器MOS等連接於起動電路，從而較為煩雜。 又，眾所周知有使用JFET進行起動用元件之高耐壓化與 低導通電阻化之技術。然而，若採用如此之JFET之構成則 元件面積會增大，並且需要2個獨立之高耐壓元件，就此 點而言並無改變。 【發明内容】 [發明所欲解決之問題] 本發明係鑒於上述實際情況而完成者，其目的在於提供 一種將起動電路與周邊電路一併積體化所得之半導體電 路。 又，本發明另一目的在於將複數個電路元件高效地組裝 於單一之半導體裝置上。 [解決問題之技術手段] 為了達成上述目的，本發明之半導體裝置之特徵在於包 括： 143696.doc 201025566 第1複合半導體元件；以及第2半導體元件； 上述第1複合半導體元件包括： 第1導電型之層（11); 第2導電型之層（12)，其形成於上述第1導電型之層（11) 上； 第1導電型之元件分離區域（13)，其自上述第2導電型之 層（12)之表面區域到達上述第丨導電型之層（11)，規定作為 第2導電型之汲極區域（121)而發揮功鸫之元件區域； 第1導電型之第1區域（15)，其形成於上述元件區域； 第2導電型之第1源極區域（16)，其形成於該第i導電型 之第1區域（15); 第I閘極電極（20)，其於上述第丨導電型之第丨區域（15) 内，形成於位於上述汲極區域（121)與上述第丨源極區域 (16)之間的區域之上；以及 第2源極區域（23)，其於上述第2導電型之層（12)内，形 成於在逆偏壓時藉由自上述元件分離區域（13)、上述第1導 電型之層（11)、及上述第丨導電型之第丨區域（15)中之至少 任一者延伸之空乏層而控制與上述汲極區域（121)之間之通 道的位置處；且 上述第2半導體元件包括形成於上述元件區域之第丨導電 型之第2區域（15)、形成於該第1導電型之第2區域（15)之第 2導電型之第3源極區域（16)、及形成於位於上述沒極區域 (121)與上述第2導電型第3源極區域（16)之間之第i導電型 之第2區域（15)上的第2閘極電極（33 〇。 143696.doc 201025566 上述半導體裝置中亦可進而設置：形成於上述元件區域 之第1導電型之第3區域（15);形成於該第1導電型之第3區 域（15)之第2導電型之第4源極區域（16);及第3閘極電極 (321)，其形成於位於上述汲極區域（121)與上述第4源極區 域（16)之間之第1導電型之第3區域（15)上，且連接於上述 第2閉極電極（3 3 1)。 較好的是，上述第1導電型之第2區域（15)係連接於上述 元件分離區域（13)。 較好的是，上述第1導電型之元件分離區域（13)包括： 圈狀部（131)，其一部分形成有開口部（133)，且規定上述 没極區域（121);以及部分（132)，其規定經由上述開口部 (133)連接於上述沒極區域（12ι)之第2導電型之延伸區域 (122)； 上述第2導電型之第2源極區域（23)係形成於上述第2導 電型之延伸區域（122)。 較好的是，上述開口部（133)設置於上述元件分離區域 (13)之上述圈狀部〇31)之一部分。 較好的是，規定上述第2導電型之延伸區域（122)之部分 (132)係形成為圓弧狀，上述第2導電型之延伸區域（122)係 於上述圈狀部（131)與規定上述第2導電型之延伸區域（122) 之部分（132)之間形成為圓弧狀。 較好的是，於上述開口部（133)上形成絕緣膜（3 5)，於該 閘極絕緣膜（35)上配置閘極電極（36)，且可設定或調整施 加至該閘極電極（36)之閘極電壓。 143696.doc 201025566 較好的是，於上述開口部（133)内之上述第1導電型之層 (11)與上述第2導電型之層（12)之間，形成濃度比上述開口 部（133)内之上述第2導電型之層（12)之雜質濃度高之第2導 電型之第2區域（37)。 較好的是’上述第2導電型之第2區域（37)係使用可設定 開口率之離子遮罩藉由離子注入而形成。 較好的是’上述第2導電型之第2源極區域（23)係於上述 第1導電型之第1區域（15)與規定上述汲極區域（121)之上述 元件分離區域（13)之間，形成於上述汲極區域（12”之表面 區域。 較好的是，上述第2導電型之第2源極區域（23)係比上述 第1導電型之第1區域（15)及上述元件分離區域（13)形成為 更淺。 較好的是，於上述第2導電型之汲極區域（121)之中央部 形成有汲極引出區域（14) ’且上述第1導電型之第1區域 (15)以包圍該汲極引出區域（14)之方式而形成為圈狀。 較好的是，上述第1導電型之層（11)之表面區域上形成有 雜質濃度可調整之第2導電型之第1區域（22)。 較好的是，上述第2導電型之第丨區域（22)包括：形成於 汲極區域（121)之正下方之圓盤狀之區域（22C);以及形成 於第1導電型之第1區域（15)之下之環狀之區域（22R)。 較好的是，上述圓盤狀之區域（22C)及上述環狀之區域 (22R)分別包括尺部、倒尺部、及直線部，上述r部之雜質 濃度設為比上述直線部之雜質濃度高，並且上述直線部之 143696.doc 201025566 雜質濃度設為比上述倒R部之雜質濃度高。 較好的是，上述圓盤狀之區域（22C)及上述環狀之區域 (22R)係使用開口率可設定之離子遮罩並藉由離子注入而 形成，與上述圓盤狀之區域（22C)及環狀之區域（22R)之R 部對應之部分的開口率設為比與直線部對應之部分的開口 率高，並且與直線部對應之部分的開口率設為比與倒R部 對應之部分的開口率高。 較好的是，上述第2導電型之第1區域（22)係使用開口率 可設定之離子遮罩並藉由離子注入而形成。 較好的是，上述第1導電型之元件分離區域（丨3)係以包 圍上述第2導電型之第1區域（22)及上述第1導電型之第1區 域（15)之方式而形成為圈狀。 較好的是，上述第2導電型之第2源極區域（23)係於上述 第1導電型之第1區域（15)與上述元件分離區域（13)之間形 成為圈狀。 較好的是，上述第2導電型之第2源極區域（23)係於上述 第1導電型之第1區域（15)與上述元件分離區域（13)之間， 於圓周方向之一部分形成有1個或複數個。 例如，上述第2導電型之没極區域（丨21)、上述第2導電 型之第1源極區域（16)及閘極電極（20)構成LDMOS (Laterally Diffused MOS) ’上述第2導電型之汲極區域 (121)、第2導電型之第2源極區域（23)及上述第1導電型之 元件分離區域（13)構成 JFET(Juncti〇n Field_Effect Transistor)。 143696.doc 201025566 [發明之效果] 根據本發明’可將複合化有LDMOS及JFET之起動電 路、與構成周邊電路之其他半導體元件積體化。 【實施方式】 參照圖式說明本發明實施形態之半導體裝置及其製造方 法。 (參考用半導體裝置之說明） 於說明本發明實施形態之半導體裝置之前，對作為1(：化 之對象之半導體裝置之基本構成（第1參考例）進行說明。 本參考用半導體裝置100具有内置有LDMOS(Laterally Diffused MOS)與 JFET(Junction FET(Field-Effect Transistor) (接面型場效電晶體））的構成。 首先’參照圖1〜圖5說明該半導體裝置1〇〇之構成。圖卜 圖3係第1參考例之半導體裝置1〇〇之剖面圖，圖4係表示圖 1所示之磊晶層之表面區域中所呈現之雜質層之分布的平 面圖°圖5係表示電極配置之平面圖。圖1係圖4及圖5之八_ A線處之箭頭剖面圖，圖2係圖4及圖5之B-B線處之箭頭剖 面圖’圖3係圖4及圖5之C-C線處之箭頭剖面圖。 參照圖1〜圖5說明半導體裝置1〇〇之構成。 如圖1所示，半導體裝置1〇〇包括p型半導體基板（第1導 電型之層）11、磊晶層（第2導電型之層）12、p型之元件分離 區域（第1導電型之元件分離區域）13、汲極引出區域14、p 型之主體區域（第1導電型之第i區域）15、N型之源極區域 (第2導電型之第！源極區域）16、主體引出區域17、場絕緣 143696.doc 201025566 膜18、閘極絕緣膜19、閘極電極（第丨閘極電極）2〇、場板 21、N型嵌入區域（第2導電型之第！區域）22、N型之源極引 出區域（第2導電型之第2源極區域）23、表面絕緣膜140、汲 極電極141、源極電極161、主體電極171及源極電極231。 P型半導體基板11包括P型單晶矽基板。 遙晶層12為藉由蟲晶成長而形成於p型半導體基板η上 之Ν型單晶矽層。 表面絕緣膜140為形成於磊晶層12之整個表面之相對較 厚之Si〇2等絕緣體之層。 元件分離區域13係規定元件區域者，包括p型之擴散區 域，且具有自磊晶層12之表面到達p型半導體基板u之深 度。元件分離區域13包括相對高濃度之基板侧擴散區域部 位與相對低濃度之表面側擴散區域部位。元件分離區域i 3 係以與主體區域15相同之步驟而製造。再者，較理想的是 兀件分離區域13係以專用之步驟而形成，且將元件分離區 域13整體設為相對高濃度。 如圖1、圖2、圖4所示，元件分離區域13係以包圍ν型嵌 入區域（第2導電型之第1區域）22及主體區域15之方式而形 成為圈狀’詳細而言形成為環狀。元件分離區域13包括： 一部分形成有寬度為5〜1〇〇 μηι、例如3 0 μιη左右之開口部 133的圈狀詳細而言環狀的環狀部13 1 ;以及鄰接於環狀部 13 1且自開口部13 3延伸之圓弧狀之延伸部丨3 2。 由環狀部131與P型半導體基板^所圍成之ν型之島狀區 域係作為LDMOS與JFET所共用之N型汲極區域121而發揮 143696.doc •10, 201025566 功能。 又，環狀部131、延伸部132、及P型半導體基板u係規 定經由開口部133而連接於島狀區域（環狀部131所定義之 圓盤狀之N型汲極區域121)的N型延伸區域（第2導電型之延 伸區域）122。即，N型延伸區域122以沿著環狀部131之方 式於環狀部131與延伸部132之間形成為圓弧狀，即，蟲晶 層12包括N型沒極區域121及N型延伸區域122。 沒極引出區域14形成於N型汲極區域121之中央部之表面 區域，且如圖4所示’係平面形狀為環狀之n型高濃度層。 沒極引出區域14之中央部分配置有場絕緣臈24。 表面絕緣膜14〇上配置有包括A1(鋁）等導電體之汲極電 極141。汲極電極141經由接觸孔連接於汲極引出區域14。 汲極電極141亦可作為連接墊而發揮功能，例如，直接連 接（焊接）有接線。 汲極引出區域14實現LDMOS及JFET所共用之N型没極區 域121與沒極電極141之歐姆接觸。 主體Q域15為P型之擴散區域’且如圖4所示，於n型汲 極區域121内形成為圈狀詳細而言形成為環狀。位於主體 區域15之内周側且與閘極電極20對向之表面區域係作為 LDMOS之通道區域而發揮功能。又，主體區域15之其他 區域係作為LDMOS之主體區域而發揮功能。 源極區域16為N型之區域，且如圖4所示，於主體區域15 内形成為環狀。源極區域16係作為LDMOS之源極區域而 發揮功能。 143696.doc 201025566 主體引出區域17為P型之高濃度區域，且於主體區域15 内之源極區域1 6之外側形成為圈狀詳細而言形成為環狀。 如圖1及圖5所示，於主體引出區域17之上配置有包括乂等 導電體之環狀之主體電極171。主體電極171經由接觸孔而 與主體引出區域17接觸。主體引出區域17將自主體電極 171施加之主體電壓施加至主體區域15。 場絕緣膜 18 包括LOCOS(Local Oxidation of Silicon，碎 局部氧化）等相對較厚之絕緣膜。場絕緣膜18以包圍汲極 引出區域14之方式形成於N型汲極區域121上。 閘極絕緣膜19包括Si〇2膜等絕緣膜，且形成於場絕緣膜 18與源極區域16之間之通道區域上。 閘極電極20包括添加有雜質之多晶石夕膜或A1膜等導電 膜’且形成於閘極絕緣膜19之上及場絕緣膜18之端部之 上。 場板21包括經由絕緣膜211而彼此電容耦合之複數個環 狀之導電體。場板21將其正下方之n型汲極區域121之電位 之梯度維持為大致固定之梯度。 N型欲入區域22為形成於P型半導體基板u之表面區域上 且雜質濃度可調整之N型區域。該n型嵌入區域22若為要 求高耐壓之元件，則雜質濃度形成為相對較低，另一方 面，若為要求低導通電阻之元件，則雜質濃度形成為相對 較兩。 源極引出區域23為配置於N型延伸區域122之表面區域之 Ni之冋濃度層。如圖丨及圖5所示，於表面絕緣膜“ο之上 143696.doc 201025566 配置有包括A1等導電體之JFET之源極電極231。源極電極 231經由接觸孔連接於源極引出區域23。N型延伸區域 係作為JFET之源極區域而發揮功能。源極引出區域23係形 成源極引出電極231與N型延伸區域122之間之歐姆接觸。 上述之構成中，LDMOS之汲極區域包括]^型汲極區域 121，通道區域包括主體區域15之内周側之表面區域，源 極包括源極區域16,主體包括主體區域15，汲極電極包括 汲極電極141，閘極電極包括閘極電極2〇，源極電極包括 參 源極電極161，主體電極包括主體電極171，閘極絕緣膜包 括閘極絕緣膜19。 另一方面，JFET之汲極區域包括1^型汲極區域121，通 道區域包括元件分離區域13之開口部133，源極區域包括N 型延伸區域122，汲極電極包括汲極電極141，閘極電極包 括元件分離區域13，源極電極包括源極電極231。 於如此之構成之半導體裝置1〇〇上，例如，如圖6所示配 _ 置有電極墊。例如，汲極電極141上直接焊接有接線。 又，閘極電極20連接於電極墊31，LDM〇s之源極電極161 連接於電極墊32。進而，jFET之源極電極231連接於電極 墊33。各電極墊上焊接有接線。再者，該等電極墊之配置 之有無或配置位置等可任意設定。 藉由上述構成，如圖7之等價電路所示，半導體裝置1〇〇 構成具有共用之汲極區域（汲極電極141)之LDMOS 5 1與 JFET 52，進而形成於LDMOS 51與JFET 52之間之元件分 離區域13之開口部133構成JFET 52之閘極之一部分。 143696.doc -13- 201025566 考察在該狀態下，以如圖8所示之方式進行連接，而構 成與圖32B所示之起動電路相同之由LDMOS 51與JFET 52 形成之起動電路的情形。 該構成中，元件分離區域13(JFET 52之閘極電極）及 LDMOS 51之主體電極171均接地。又，LDMOS 51之閘極 電極20與JFET 52之源極電極231相連接。又，LDMOS 51 及JFET 52之共用之汲極電極141連接於施加汲極電壓Vd之 電源。進而，LDMOS 51之源極電極161與JFET 52之源極 電極231均連接於内部電路413。 若在該狀態下向汲極電極141施加正之汲極電壓Vd，則 電流（汲極-源極間電流Ids)按照汲極電極141 —汲極引出區 域14—N型汲極區域121 —環狀部131之開口部133 —延伸區 域122 —源極引出區域23 —源極電極231之路徑而流經JFET 5 2之没極-源極間。 而且，若使汲極電壓Vd逐漸上升，則如圖1 0所示， JFET 52之汲極-源極間電流Ids逐漸增加。又，藉由汲極-源極間電流Ids，LDMOS 5 1之閘極電極20得到充電，電流 亦流經LDMOS 51之汲極-源極間，且伴隨汲極電壓Vd之上 升而電流增加。 藉由將正之汲極電壓Vd施加至汲極電極141，從而正之 電壓經由没極引出區域14而施加至遙晶層12。於是，由元 件分離區域13之P型之環狀部131及P型半導體基板11與N型 之磊晶層12所構成之PN接面，會因施加至磊晶層12之正之 電壓而發生逆偏壓。因此，如圖9 A〜圖9C模式性地所示， 143696.doc -14· 201025566 伴隨汲極電壓Vd之上升，自PN接面起於磊晶層12之開口 邛133，空乏層DL逐漸擴展。如此，若汲極電壓Vd低於特 定值（飽和電壓：圖10中為電壓乂8^)，則環狀部131之開口 部133不會被空乏層DL封閉，通道被導通（控制），汲極-源 極間流動有電流Ids。 另一方面’若汲極電壓達到特定值（飽和電壓：圖 中為電壓Vsat)，則如圖9D模式性地所示，環狀部131之開 口部133(JFET 52之通道區域）中磊晶層12整體被空乏層DL 封閉’通道被阻斷（控制），成為夾斷（pinch 〇ff)狀態。如 圖ίο所示，夾斷以後，JFET 52之汲極-源極間電流Ids飽 和，而成為大致固定。 因此’根據上述構成之起動電路，LDMOS 51與JFET 52 並聯連接’不僅可高耐壓化，而且藉由對LDMOS 5 1及 JFET 52所共用之没極電極141施加特定電壓（電壓vsat)以 上之汲極電壓Vd而成為夾斷狀態，jFET 52之汲極-源極間 電流Ids被限制為固定值，從而可抑制功耗。 又’上述構成之半導體裝置1〇〇中，形成於LDMOS 51與 JFET 52之間之元件分離區域13之開口部133構成JFET 52 之閘極之一部分，進而LDMOS 51與JFET 52共有N型汲極 區域121 ’ JFET 52沿著LDMOS 51之外周而形成。因此， 以相對較小之佔有面積便可形成2個半導體元件。 又’藉由使汲極電極141形成為相對較大，而可直接焊 接於汲極電極141上，從而無需自元件之中心引出高壓配 線。又’汲極電極141兼作焊墊’因此無需設置汲極電極 J43696.doc -15- 201025566 141用之焊塾’從而不需要用於連接之焊墊面積。 因可直接焊接於汲極電極141上，故不再另外需要保護 兀件，且，以LDMOS 51之耐受量便可實現針對突波之保 護。 、 以上之說明中，係將形成於環狀部13丨之作為通道區域 之開口部133的寬度（JFET 52之閘極電極之寬度）設為3〇 μηι 左右進行說明，但開口部133之大小亦可進行適當設定以 獲得目標飽和電壓及飽和電流。即，可適當變更開口部 133之大小、雜質濃度、Ν型延伸區域122之雜質濃度、大 小等’藉此控制空乏層之擴展。而且，藉此，可將飽和電 壓及飽和電/;IL 疋為所期望之值，或者以任意之特性進行 控制。 又，以上之說明中，係使P型半導體基板u及元件分離 區域13(JFET 52之閘極電極）接地，但施加至各區域之電壓 為任意。例如，在理論上亦可藉由對p型半導體基板^及卩 型之元件分離區域13施加負電壓，從而使自元件分離區域 13與磊晶層12之PN接面延伸之空乏層DL進一步擴展以降 低飽和電壓及飽和電流。 圖11表示使P型半導體基板11及P型之元件分離區域13之 電位（對元件分離區域13之施加電壓）強制性變化之情形時 的沒極電壓Vd與JFET 52之汲極-源極間電流ids的關係。如 圖所示，藉由使JFET 52之閘極電壓Vg(對元件分離區域13 之施加電壓）變化’成為夾斷之電壓（飽和電壓Vsat)發生變 化’並且飽和電流Isat亦發生變化。 143696.doc -16- 201025566 又，如圖12中之剖面所示，於元件分離區域13之開口部 133(JFET 52之通道區域）上形成絕緣膜（閘極絕緣膜）35。 而且，亦可構成為於該閘極絕緣膜3 5上配置閘極電極3 6， 且可設定或調整施加於閘極電極36之閘極電壓。 若以接地電位（P型半導體基板U之電位）為基準而對閘 極電極36施加正之閘極電壓vg，則JFET 52之通道區域（開 口部133内之N型磊晶層12)上所生成之空乏層難以延伸。 因此，隨著進一步正增大閘極電壓Vg，飽和電壓Vsat及飽 參 和電流Isat均可增大。再者，閘極電極3 6可僅配置於開口 部133之上，或者’亦可呈環狀地整體配置。 又’如圖13之剖面所示，藉由將n型嵌入區域（第2導電 型之第2區域）37配置於JFET 52之通道區域（開口部133)， 可調整飽和電流Isat。即，藉由於開口部133内之p型半導 體基板11與磊晶層12之間，形成高濃度（以開口部133内之 N型蟲晶層12之雜質濃度為基準）之n型嵌入區域37，且調 φ 整N型嵌入區域37之雜質濃度與N型嵌入區域37之上面之 :木度’從而可調整汲極-源極間之飽和電流isat。 比起未配置N型嵌入區域37之情形，藉由配置n型嵌入 區域37，自p型半導體基板n側延伸之空之層之位置更 低，飽和電壓Vsat更大，飽和電流isat亦更大。再者，n型 嵌入區域37亦能以開口部133内之N型磊晶層12為基準而設 為低雜質濃度。 又，N型嵌入區域37例如，可如圖14八所示僅形成於 JFET 52之通道區域，可如圖14B所示形成於JFET 52之通 143696.doc -17· 201025566 道區域及其附近，亦可如圖14c所示形成於JFEt 52之通道 區域及N型延伸區域122内。如此，N型嵌入區域37所佔之 面積越大’則飽和電壓Vsat及飽和電流Isat越大。又，亦 可如圖14D所示使N型嵌入區域37延伸而與N型嵌入區域22 構成為一體。進而，亦可如圖14e所示，不形成（除去）主 體區域15之一部分’而調整飽和電壓Vsat及飽和電流 Isat ° 一般而言，只要其他條件相同，則N型嵌入區域37之N 型之雜質濃度越高’飽和電壓Vsat及飽和電流Isat越上 升；N型嵌入區域37越深，飽和電壓Vsat及飽和電流lsat越 上升；N型嵌入區域37越寬，飽和電壓Vsat及飽和電流lsat 越上升。 再者’ N型嵌入區域22、37之濃度或濃度分布，例如， 可如後述般，藉由適當設定離子注入（擴散）時所使用之離 子遮罩之開口率而進行調整。 又’亦可藉由變更JFET 52之源極引出區域23及源極電 極23 1之位置，而調節飽和電流Isat。例如，如圖〗5所示， 伴隨使自開口部133至源極引出區域23及源極電極231的位 置由距離JFET 52之通道區域（開口部133)較近之第1位置pi 起依序遠離至P2、P3，可縮小飽和電流Isat。尤其是藉由 設置由環狀部131與圓弧狀之延伸部132所夾持之圓弧狀之 N型延伸區域122，不會過度增大JFET 52之大小便可縮小 飽和電流Isat。 (實施形態之半導體裝置之說明） 143696.doc • 18· 201025566 以上說明之參考用半導體裝置之構成中，開口部133之 大小（寬度）被限定，伴隨汲極電壓Vd之上升’環狀部m 之開口部133中之磊晶層内之空乏層DL自3方向（左右之 環狀部131與下方之p型半導體基板UipN接面）起延伸， 因此，當汲極電壓Vd相對較小時，閘極區域夾斷。因此， 難以獲得較大之飽和電壓及飽和電流。相反，即便擴大開 口部133之寬度，亦無法抑制自與p型半導體基板nipN接 面起延伸之空乏層’從而飽和電壓及飽和電流之增大化有 ® 限。 對此，以下將說明獲得相對較大之飽和電壓及飽和電流 之半導體裝置200。 (第2參考例） 上述參考用（第1參考例之）半導體裝置1〇〇中，係以沿著 LDMOS 51之外周之方式，於環狀部131之外側形成有JFET 52之N型延伸區域（源極區域）122。與此相對，本參考例之 φ 半導體裝置200中，係將JFET 52之源極區域配置於LDM〇s 之元件區域内。藉此可使半導體元件之佔有區域進一步小 • 型化。而除此以外之構成除以下特別說明之情形外與第1 參考例之半導體裝置100相同。 圖16與圖17表示第2參考例之半導體裝置2〇〇之結構，圖 16係半導體裝置200之剖面圖，圖17係表示圖“所示之磊 晶層12之表面區域中所呈現之雜質層之分布的平面圖。圖 18A〜圖18C係模式性地表示伴隨汲極電壓vd之上升 ((XV2KV22)而空乏層如何自主體區域似元件分離區域 143696.doc ln 201025566 13延伸之圖。圖19係表示另一磊晶層之表面區域中所呈現 之雜質層之分布的平面圖。再者，圖16相當於圖17及圖19 之A-A線處之箭頭剖面圖。 如圖所不’本參考例中，元件分離區域丨3係以包圍N型 没極區域121之方式而形成為圈狀詳細而言形成為環狀， 且未配置有延伸部132。元件分離區域13形成為一重之環 狀。 主體區域15以包圍汲極引出區域14之方式而形成為環 狀。 JFET 52之源極引出區域23為濃度高於n型汲極區域ι21 之N型之區域。源極引出區域23係於主體區域15與規定N 型没極區域121之元件分離區域13之間，在n型汲極區域 121之表面區域上形成為環狀。源極引出區域23係比鄰接 之主體區域15及元件分離區域13形成為更淺。表面絕緣膜 140上之與源極引出區域23對向之位置處配置有源極電極 23 1 ’且經由接觸孔而連接於源極引出區域23。 又’ N型故入區域22包括：形成於N型汲極區域121之正 下方之圓盤狀之區域22C;以及形成於主體區域15之下之 壤狀之區域22R。 該構成中’例如，若將LDMOS之主體區域15之電壓、 元件分離區域13之電壓、P型半導體基板u之電壓分別設 為接地位準（接地電位），則伴隨汲極電壓Vd之上升，如圖 18A〜圖18C模式性地所示，空乏層DL自P型之主體區域 15、P型之元件分離區域13、及P型半導體基板11與1^型之 143696.doc -20· 201025566 磊晶層12及環狀之區域22R之間的PN接面起延伸。而且， 若汲極電壓Vd達到固定位準V22(V22>V21>〇)，則會夾 斷。 根據該構成，JFET 52之通道區域存在於N型之蠢晶層12 内’該N型之磊晶層12存在於P型之主體區域15、p型之元 件分離區域13、P型半導體基板11之區域之間。而且，伴 隨没極電壓Vd之上升，空乏層DL自N型之蠢晶層12與主體 區域I5之PN接面，及N型之磊晶層12與P型半導體基板u 之PN接面之上下2方向起延伸並夾斷。該jfet 52為藉由自 上下2方向延伸之空乏層DL而夾斷之構成。因此，可使與 閘極之橫方向之長度（本參考例中為圓形之LdMOS ,因此 相當於源極引出區域23之圓周長）對應的電流（汲極_源極間 電流Ids)流動。而且，主體區域15、源極引出區域23、及 作為JFET 52之閘極電極的元件分離區域13均係到達 LDMOS之全周而形成為環狀，因此在可確保JFET 52之大 小較小之同時，確保JFET 52之飽和電流Isat較大。此處， 飽和電流Isat係依存於jfet 52之大小，但亦可流動至數十 mA為止。 再者，JFET 52之源極引出區域23並不限於全周形成為 環狀之構成，亦可如圖19所示，於圓周方向之一部分形成 有1個或複數個。藉此，比起如圖17所示之源極引出區域 23到達全周而形成為環狀之結構，JFET 52之閘極電極寬 度更窄，且在維持飽和電壓Vsat(夾斷電壓）之狀態下可使 飽和電流Isat更小。 143696.doc •21- 201025566 又，如圖18A〜圖18C所示，利用N型嵌入區域22R之有 無，可控制自與P型半導體基板11之PN接面起之空乏層的 延伸，亦可調整飽和電壓Vsat。 又，圖16及圖17所示之結構中，與半導體裝置100不 同，N型嵌入區域22包括N型汲極區域121之正下方之N型 嵌入區域22C及主體區域15之附近之環狀之N型嵌入區域 22R。該N型嵌入區域22C、22R尤其可藉由適當設定環狀 之N型嵌入區域22R之位置、大小及雜質濃度，而控制空 乏層之擴展，且可將飽和電壓Vsat及飽和電流Isat設定為 所期望之值，或者以任意之特性進行控制。 例如，將如圖20A所示之配置於主體區域15之下之N型 嵌入區域22R，如圖20B所示延伸至源極引出區域23之下 方為止，藉此可使飽和電壓Vsat上升。 例如，將如圖20C所示之相對較淺之N型嵌入區域22R， 如圖20D所示形成為較深，藉此可使飽和電壓Vsat上升。 例如，將如圖20E所示之主體區域15，如圖20F所示設得 較淺，藉此可使飽和電壓Vsat上升。 又，將如圖20G所示之主體區域15與源極引出區域23之 距離，如圖20H所示設為較長，藉此可使飽和電壓Vsat上 升。 進而，如圖21A及圖21B所示，亦可將配置於主體區域 15之下之N型嵌入區域22R於圓周方向之一部分形成1個或 複數個。其中，飽和電壓Vsat係由不存在N型嵌入區域22R 之部分所規定。 143696.doc -22- 201025566 進而，亦可為N型汲極區域121正下方之N型嵌入區域 22C或配置於主體區域15之下之N型嵌入區域22R之任一者 不配置之構成。 再者，N型嵌入區域22R、22C之濃度或濃度分布例如後 述般，藉由適當設定離子注入（擴散）時所使用之離子遮罩 之開口率而實施。201025566 VI. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a high withstand voltage semiconductor device. [Prior Art] Generally, a high-voltage MOSFET (Metallic Oxide Semiconductor Field Effect Transistor) is used in the starting circuit used in a power supply IC (Integrated Circuit). For example, LDMOS (Laterally Diffused MOS). As shown in Fig. 32A, the previous starting circuit is connected to a resistor R of a few Ω Ω between the drain and the gate of the LDMOS 411 to control the bias current when the LDMOS 411 is driven and turned off. In the circuit configuration, when a high level voltage is applied to the start terminal T by the conduction of the main power source, a high level voltage is applied to the gate of the LDMOS 411 via the resistor R, so that the LDMOS 411 is turned on and the current is supplied to the inside. Circuit 412 » Thereafter, when internal circuit 412 operates to set the gate voltage of LDMOS to a low level, LDMOS 411 is turned off, and supply of current toward internal circuit 412 is stopped. In the starting circuit, a bias current corresponding to the power supply voltage is always flowing through the resistor R. Therefore, it is not suitable for low power consumption. Further, since the drain of the LDMOS 411 is directly bonded to the pins of the 1C package, the resistance may be broken when static electricity or the like is applied. Therefore, considering the circuit configuration shown in Fig. 32B, the driving of the LDMOS 411 and the control of the leakage current are performed by the JFET 413 into 143696.doc 201025566, thereby improving the above problem. With this circuit configuration, the bias current during the period in which the LDMOS 4 11 is turned off is defined as the saturation current of the JFET 41 3, and the current with respect to the voltage becomes a fixed value. Further, since the high resistance to the surge voltage is not used, the damage becomes strong. However, if the starting circuit is directly 1C, two high withstand voltage elements are required, which occupies a relatively large wafer area. Further, in addition to the start-up circuit, it is necessary to connect the power MOS for flowing a large current and the sensor MOS for detecting a current flowing through the power MOS to the start-up circuit as a peripheral circuit, which is complicated. Further, it is known that a JFET is used to perform high voltage resistance and low on-resistance of a starting element. However, if such a JFET is used, the area of the element is increased, and two independent high-voltage members are required, and there is no change in this point. [Problem to be Solved by the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor circuit in which a starter circuit and a peripheral circuit are integrated. Further, another object of the present invention is to efficiently assemble a plurality of circuit elements on a single semiconductor device. [Means for Solving the Problems] In order to achieve the above object, a semiconductor device of the present invention includes: 143696.doc 201025566 a first composite semiconductor element; and a second semiconductor element; and the first composite semiconductor element includes: a first conductivity type a layer (11); a second conductivity type layer (12) formed on the first conductivity type layer (11); and a first conductivity type element isolation region (13) from the second conductivity type The surface region of the layer (12) reaches the layer (11) of the second conductivity type, and defines an element region that functions as a drain region (121) of the second conductivity type; and a first region of the first conductivity type ( 15) formed in the element region; a first source region (16) of the second conductivity type formed in the first region (15) of the ith conductivity type; and a first gate electrode (20) In the second region (15) of the second conductivity type, formed on a region between the drain region (121) and the third source region (16); and a second source region (23) ) in the layer (12) of the second conductivity type formed by self-reverse bias Controlling the above-described drain region with the depletion layer extending at least one of the element isolation region (13), the first conductivity type layer (11), and the second conductivity type second region (15) 121) a position between the channels; and the second semiconductor element includes a second region (15) of a second conductivity type formed in the element region, and a second region (15) formed in the first conductivity type a third source region (16) of the second conductivity type and a second region of the ith conductivity type formed between the non-polar region (121) and the second conductivity type third source region (16) (15) The second gate electrode (33 〇. 143696.doc 201025566 The semiconductor device may further include: a third region (15) of the first conductivity type formed in the element region; formed in the first a fourth source region (16) of a second conductivity type of the third region (15) of the conductivity type; and a third gate electrode (321) formed in the drain region (121) and the fourth source Preferably, the third region (15) of the first conductivity type between the pole regions (16) is connected to the second cathode electrode (3 3 1). The second region (15) of the first conductivity type is connected to the element isolation region (13). Preferably, the element isolation region (13) of the first conductivity type includes: a ring portion (131) a part of the opening (133) is defined, and the non-polar region (121) is defined; and a portion (132) defining a second conductivity type connected to the non-polar region (12i) via the opening (133) The extension region (122); the second source region (23) of the second conductivity type is formed in the extension region (122) of the second conductivity type. Preferably, the opening (133) is provided in a portion of the ring portion 31) of the element isolation region (13). Preferably, the portion (132) defining the extension region (122) of the second conductivity type is formed in an arc shape, and the extension region (122) of the second conductivity type is attached to the loop portion (131) and The portion (132) defining the extended region (122) of the second conductivity type is formed in an arc shape. Preferably, an insulating film (35) is formed on the opening (133), and a gate electrode (36) is disposed on the gate insulating film (35), and can be set or adjusted to be applied to the gate electrode. (36) The gate voltage. 143696.doc 201025566 Preferably, a concentration ratio of the opening (133) is formed between the first conductivity type layer (11) and the second conductivity type layer (12) in the opening (133). The second region (37) of the second conductivity type in which the second conductivity type layer (12) has a high impurity concentration. Preferably, the second region (37) of the second conductivity type is formed by ion implantation using an ion mask capable of setting an aperture ratio. Preferably, the second source region (23) of the second conductivity type is the first region (15) of the first conductivity type and the element isolation region (13) defining the drain region (121). Formed in a surface region of the drain region (12". Preferably, the second source region (23) of the second conductivity type is larger than the first region (15) of the first conductivity type The element isolation region (13) is formed shallower. Preferably, a drain extraction region (14) is formed in a central portion of the second conductivity type drain region (121), and the first conductivity type is The first region (15) is formed in a ring shape so as to surround the drain lead-out region (14). Preferably, the impurity concentration can be adjusted on the surface region of the first conductive type layer (11). The first region (22) of the second conductivity type. Preferably, the second region (22) of the second conductivity type includes a disk-shaped region (22C) formed directly below the drain region (121). And a ring-shaped region (22R) formed under the first region (15) of the first conductivity type. Preferably, the disk-shaped region is 22C) and the annular region (22R) include a ruler, a ruled portion, and a straight portion, wherein the impurity concentration of the r portion is higher than an impurity concentration of the straight portion, and the straight portion is 143696.doc 201025566 The impurity concentration is set to be higher than the impurity concentration of the inverted R portion. Preferably, the disk-shaped region (22C) and the annular region (22R) are formed by using an ion mask whose aperture ratio can be set. Formed by ion implantation, the aperture ratio of the portion corresponding to the R portion of the disc-shaped region (22C) and the annular region (22R) is set to be higher than the aperture ratio of the portion corresponding to the linear portion, and the straight portion The aperture ratio of the corresponding portion is set to be higher than the aperture ratio of the portion corresponding to the inverted R portion. Preferably, the first region (22) of the second conductivity type is an ion mask that can be set with an aperture ratio. It is preferable that the first conductivity type element isolation region (丨3) surrounds the first region (22) of the second conductivity type and the first region of the first conductivity type ( 15) is formed into a ring shape. Preferably, the second item is The second source region (23) of the electric type is formed in a loop shape between the first region (15) of the first conductivity type and the element isolation region (13). Preferably, the second conductivity type The second source region (23) is formed between the first region (15) of the first conductivity type and the element isolation region (13), and is formed in one or a plurality of portions in the circumferential direction. The second conductivity type non-polar region (丨21), the second conductivity type first source region (16), and the gate electrode (20) constitute an LDMOS (Laterally Diffused MOS) 'the second conductivity type drain The region (121), the second source region (23) of the second conductivity type, and the element isolation region (13) of the first conductivity type constitute a JFET (Juncti〇n Field_Effect Transistor). 143696.doc 201025566 [Effect of the Invention] According to the present invention, a starter circuit in which an LDMOS and a JFET are combined can be integrated with other semiconductor elements constituting a peripheral circuit. [Embodiment] A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the drawings. (Description of Reference Semiconductor Device) Before describing a semiconductor device according to an embodiment of the present invention, a basic configuration (first reference example) of a semiconductor device to be used will be described. The reference semiconductor device 100 has a built-in The configuration of LDMOS (Laterally Diffused MOS) and JFET (Junction FET (Field-Effect Transistor)). First, the configuration of the semiconductor device 1 will be described with reference to FIGS. 1 to 5 . 3 is a cross-sectional view of a semiconductor device 1 of a first reference example, and FIG. 4 is a plan view showing a distribution of an impurity layer present in a surface region of the epitaxial layer shown in FIG. 1. FIG. 5 is an electrode configuration. Fig. 1 is an arrow cross-sectional view taken along line -8 of Fig. 4 and Fig. 5, Fig. 2 is an arrow cross-sectional view taken along line BB of Fig. 4 and Fig. 5, Fig. 3 is a CC line of Fig. 4 and Fig. 5 The cross-sectional view of the arrow will be described with reference to Fig. 1 to Fig. 5. As shown in Fig. 1, the semiconductor device 1 includes a p-type semiconductor substrate (layer of the first conductivity type) 11, and an epitaxial layer. (layer of the second conductivity type) 12, p-type component separation The field (the element-separated region of the first conductivity type) 13, the drain region 14 and the p-type body region (the ith region of the first conductivity type) 15 and the source region of the N-type (the second conductivity type! Source region) 16, body lead-out region 17, field insulation 143696.doc 201025566 film 18, gate insulating film 19, gate electrode (third gate electrode) 2 〇, field plate 21, N-type embedded region (2nd a conductivity type region! 22, an N-type source lead-out region (second conductivity type second source region) 23, a surface insulating film 140, a drain electrode 141, a source electrode 161, a body electrode 171, and a source The pole electrode 231. The P-type semiconductor substrate 11 includes a P-type single crystal germanium substrate. The crystal layer 12 is a germanium-type single crystal germanium layer formed on the p-type semiconductor substrate η by the growth of the crystallites. The surface insulating film 140 is formed. a relatively thick layer of an insulator such as Si〇2 on the entire surface of the epitaxial layer 12. The element isolation region 13 defines a device region, including a p-type diffusion region, and has a surface from the epitaxial layer 12 to the p-type. The depth of the semiconductor substrate u. The element isolation region 13 includes a relatively high concentration substrate side expansion The region portion and the relatively low concentration surface side diffusion region portion. The element isolation region i 3 is manufactured in the same step as the body region 15. Further, it is preferable that the element separation region 13 is formed by a dedicated step. Further, the entire element isolation region 13 is set to have a relatively high concentration. As shown in FIGS. 1, 2, and 4, the element isolation region 13 surrounds the ν-type embedded region (the first region of the second conductivity type) 22 and the body region. The pattern of 15 is formed into a ring shape 'detailed in a ring shape. The element isolation region 13 includes: a ring-shaped annular portion 13 1 having a ring-shaped detailed annular portion 133 having a width of 5 to 1 μm, for example, about 30 μm; and an annular portion 13 1 adjacent to the annular portion 13 1 And an arc-shaped extension portion 丨3 2 extending from the opening portion 13 3 . The ν-type island region surrounded by the annular portion 131 and the P-type semiconductor substrate functions as the N-type drain region 121 shared by the LDMOS and the JFET, and functions as 143696.doc •10, 201025566. Further, the annular portion 131, the extending portion 132, and the P-type semiconductor substrate u are defined to be connected to the island-shaped region (the disk-shaped N-type drain region 121 defined by the annular portion 131) via the opening 133. A type extension region (an extension region of the second conductivity type) 122. That is, the N-type extension region 122 is formed in an arc shape between the annular portion 131 and the extending portion 132 along the annular portion 131, that is, the insect layer 12 includes the N-type non-polar region 121 and the N-type extension. Area 122. The electrodeless lead-out region 14 is formed in the surface region of the central portion of the N-type drain region 121, and as shown in Fig. 4, the n-type high-concentration layer having a ring-shaped planar shape is formed. A field insulation 臈 24 is disposed in a central portion of the immersed lead-out area 14. A drain electrode 141 including a conductor such as A1 (aluminum) is disposed on the surface insulating film 14A. The drain electrode 141 is connected to the drain lead-out region 14 via a contact hole. The drain electrode 141 can also function as a connection pad, for example, directly connected (welded) with wiring. The drain lead-out region 14 realizes ohmic contact between the N-type non-polar region 121 shared by the LDMOS and the JFET and the electrodeless electrode 141. The main body Q region 15 is a P-type diffusion region ′ and, as shown in Fig. 4, is formed in a ring shape in the n-type ytterbium region 121 in a ring shape in detail. The surface region located on the inner peripheral side of the main body region 15 and facing the gate electrode 20 functions as a channel region of the LDMOS. Further, the other regions of the main body region 15 function as the main region of the LDMOS. The source region 16 is an N-type region, and as shown in FIG. 4, is formed in a ring shape in the body region 15. The source region 16 functions as a source region of the LDMOS. 143696.doc 201025566 The main body lead-out area 17 is a P-type high concentration region, and is formed in a ring shape on the outer side of the source region 16 in the main body region 15 in a ring shape. As shown in Figs. 1 and 5, a ring-shaped body electrode 171 including a conductor such as a crucible is disposed on the main body lead-out area 17. The body electrode 171 is in contact with the body lead-out region 17 via the contact hole. The body lead-out area 17 applies a body voltage applied from the body electrode 171 to the body region 15. The field insulating film 18 includes a relatively thick insulating film such as LOCOS (Local Oxidation of Silicon). The field insulating film 18 is formed on the N-type drain region 121 so as to surround the drain lead-out region 14. The gate insulating film 19 includes an insulating film such as a Si 2 film, and is formed on a channel region between the field insulating film 18 and the source region 16. The gate electrode 20 includes a polycrystalline film or a conductive film such as an A1 film to which an impurity is added, and is formed on the gate insulating film 19 and on the end portion of the field insulating film 18. The field plate 21 includes a plurality of loop-shaped electric conductors that are capacitively coupled to each other via the insulating film 211. The field plate 21 maintains the gradient of the potential of the n-type drain region 121 directly below it to a substantially fixed gradient. The N-type in-progress region 22 is an N-type region formed on the surface region of the P-type semiconductor substrate u and having an adjustable impurity concentration. In the case where the n-type embedded region 22 is an element requiring a high withstand voltage, the impurity concentration is relatively low, and on the other hand, if the element is required to have a low on-resistance, the impurity concentration is formed to be relatively large. The source lead-out region 23 is a Ni concentration layer disposed in the surface region of the N-type extension region 122. As shown in FIG. 5 and FIG. 5, a source electrode 231 of a JFET including a conductor such as A1 is disposed on the surface insulating film "ο 143696.doc 201025566. The source electrode 231 is connected to the source lead-out region 23 via a contact hole. The N-type extension region functions as a source region of the JFET. The source extraction region 23 forms an ohmic contact between the source extraction electrode 231 and the N-type extension region 122. In the above configuration, the drain region of the LDMOS The gate region includes a surface region on the inner peripheral side of the body region 15, the source includes a source region 16, the body includes a body region 15, the drain electrode includes a drain electrode 141, and the gate electrode includes The gate electrode 2A, the source electrode includes a reference source electrode 161, the body electrode includes a body electrode 171, and the gate insulating film includes a gate insulating film 19. On the other hand, the drain region of the JFET includes a 1^ type drain region 121, the channel region includes an opening portion 133 of the element isolation region 13, the source region includes an N-type extension region 122, the drain electrode includes a drain electrode 141, the gate electrode includes an element isolation region 13, and the source electrode includes The electrode electrode 231. On the semiconductor device 1 thus constructed, for example, an electrode pad is disposed as shown in Fig. 6. For example, the gate electrode 141 is directly soldered to the wiring. Further, the gate electrode 20 is connected to The electrode pad 31 and the source electrode 161 of the LDM 〇s are connected to the electrode pad 32. Further, the source electrode 231 of the jFET is connected to the electrode pad 33. Wires are soldered to the electrode pads. Further, the arrangement of the electrode pads is Or the arrangement position or the like can be arbitrarily set. With the above configuration, as shown in the equivalent circuit of FIG. 7, the semiconductor device 1A constitutes the LDMOS 5 1 and the JFET 52 having the common drain region (the drain electrode 141), and further The opening portion 133 of the element isolation region 13 formed between the LDMOS 51 and the JFET 52 constitutes a part of the gate of the JFET 52. 143696.doc -13- 201025566 In this state, connection is performed as shown in FIG. The configuration of the starter circuit formed by the LDMOS 51 and the JFET 52 is the same as that of the starter circuit shown in Fig. 32B. In this configuration, the element isolation region 13 (the gate electrode of the JFET 52) and the body electrode 171 of the LDMOS 51 are both Ground. Also, LDM The gate electrode 20 of the OS 51 is connected to the source electrode 231 of the JFET 52. Further, the common drain electrode 141 of the LDMOS 51 and the JFET 52 is connected to a power source to which the gate voltage Vd is applied. Further, the source electrode of the LDMOS 51 161 and the source electrode 231 of the JFET 52 are both connected to the internal circuit 413. If a positive drain voltage Vd is applied to the drain electrode 141 in this state, the current (drain-source current Ids) follows the drain electrode 141. - a drain-exit region 14 - an N-type drain region 121 - an opening portion 133 of the annular portion 131 - an extended region 122 - a source lead-out region 23 - a path of the source electrode 231 and flowing through the gate-source of the JFET 5 2 Extremely. Further, when the drain voltage Vd is gradually increased, as shown in FIG. 10, the drain-source current Ids of the JFET 52 gradually increases. Further, by the drain-source current Ids, the gate electrode 20 of the LDMOS 51 is charged, and current also flows between the drain and the source of the LDMOS 51, and the current increases as the gate voltage Vd rises. By applying a positive drain voltage Vd to the drain electrode 141, a positive voltage is applied to the crystal layer 12 via the no-pole lead-out region 14. Therefore, the PN junction formed by the P-shaped annular portion 131 of the element isolation region 13 and the P-type semiconductor substrate 11 and the N-type epitaxial layer 12 is reversed by the positive voltage applied to the epitaxial layer 12. bias. Therefore, as shown schematically in FIGS. 9A to 9C, 143696.doc -14· 201025566 is accompanied by an increase in the drain voltage Vd, and the opening layer 133 of the epitaxial layer 12 is opened from the PN junction, and the depletion layer DL is gradually expanded. . As described above, when the drain voltage Vd is lower than a specific value (saturation voltage: voltage 乂8^ in FIG. 10), the opening portion 133 of the annular portion 131 is not closed by the depletion layer DL, and the channel is turned on (controlled), There is a current Ids flowing between the pole and the source. On the other hand, if the threshold voltage reaches a specific value (saturation voltage: voltage Vsat in the figure), as shown schematically in FIG. 9D, the opening portion 133 of the annular portion 131 (the channel region of the JFET 52) is epitaxial. The layer 12 as a whole is closed by the depletion layer DL 'the channel is blocked (controlled) and becomes a pinch 〇 ff state. As shown in Fig., after the pinch-off, the drain-source current Ids of the JFET 52 is saturated and becomes substantially constant. Therefore, the LDMOS 51 and the JFET 52 are connected in parallel according to the start-up circuit configured as described above. Not only high voltage resistance but also a specific voltage (voltage vsat) applied to the gate electrode 141 shared by the LDMOS 51 and the JFET 52 can be applied. The drain voltage Vd becomes a pinch-off state, and the drain-source current Ids of the jFET 52 is limited to a fixed value, thereby suppressing power consumption. Further, in the semiconductor device 1 having the above configuration, the opening portion 133 of the element isolation region 13 formed between the LDMOS 51 and the JFET 52 constitutes one of the gates of the JFET 52, and the LDMOS 51 and the JFET 52 share the N-type drain. The region 121' JFET 52 is formed along the outer circumference of the LDMOS 51. Therefore, two semiconductor elements can be formed with a relatively small occupied area. Further, by forming the gate electrode 141 to be relatively large, it can be directly soldered to the gate electrode 141, so that it is not necessary to draw the high voltage wiring from the center of the element. Further, the gate electrode 141 doubles as a pad. Therefore, it is not necessary to provide a pad electrode for the gate electrode J43696.doc -15-201025566 141, so that the pad area for connection is not required. Since it can be directly soldered to the drain electrode 141, there is no need to additionally protect the element, and the protection against the surge can be achieved with the tolerance of the LDMOS 51. In the above description, the width of the opening portion 133 (the width of the gate electrode of the JFET 52) formed in the annular portion 13A as the channel region is set to about 3〇μηι, but the size of the opening portion 133 is described. It can also be appropriately set to obtain the target saturation voltage and saturation current. In other words, the size of the opening 133, the impurity concentration, the impurity concentration of the 延伸-type extension region 122, the size, and the like can be appropriately changed, thereby controlling the expansion of the vacant layer. Further, by this, the saturation voltage and the saturation power /; IL can be set to a desired value or controlled by any characteristic. In the above description, the P-type semiconductor substrate u and the element isolation region 13 (the gate electrode of the JFET 52) are grounded, but the voltage applied to each region is arbitrary. For example, it is theoretically possible to further extend the depletion layer DL extending from the element isolation region 13 and the PN junction of the epitaxial layer 12 by applying a negative voltage to the p-type semiconductor substrate and the element isolation region 13 of the germanium type. To reduce the saturation voltage and saturation current. FIG. 11 shows the gate voltage-source between the gate voltage and the source of the P-type semiconductor substrate 11 and the P-type element isolation region 13 (the voltage applied to the element isolation region 13) is forcibly changed. The relationship of current ids. As shown in the figure, the gate voltage Vg (applied voltage to the element isolation region 13) of the JFET 52 changes to a pinch-off voltage (saturation voltage Vsat) and the saturation current Isat also changes. 143696.doc -16- 201025566 Further, as shown in the cross section of Fig. 12, an insulating film (gate insulating film) 35 is formed on the opening portion 133 (channel region of the JFET 52) of the element isolation region 13. Further, a gate electrode 36 may be disposed on the gate insulating film 35, and a gate voltage applied to the gate electrode 36 may be set or adjusted. When a positive gate voltage vg is applied to the gate electrode 36 with reference to the ground potential (potential of the P-type semiconductor substrate U), the channel region of the JFET 52 (the N-type epitaxial layer 12 in the opening portion 133) is generated. The vacant layer is difficult to extend. Therefore, as the gate voltage Vg is further increased, the saturation voltage Vsat and the saturation and current Isat can be increased. Further, the gate electrode 36 may be disposed only on the opening portion 133 or may be disposed integrally in a ring shape. Further, as shown in the cross section of Fig. 13, the saturation current Isat can be adjusted by disposing the n-type embedded region (the second region of the second conductivity type) 37 in the channel region (opening portion 133) of the JFET 52. In other words, an n-type embedded region 37 having a high concentration (based on the impurity concentration of the N-type crystal layer 12 in the opening portion 133) is formed between the p-type semiconductor substrate 11 and the epitaxial layer 12 in the opening portion 133. And adjusting the impurity concentration of the N-type embedded region 37 and the upper surface of the N-type embedded region 37: the degree of wood', thereby adjusting the saturation current isat between the drain and the source. By arranging the n-type embedded region 37, the position of the empty layer extending from the p-type semiconductor substrate n side is lower, the saturation voltage Vsat is larger, and the saturation current isat is larger than that in the case where the N-type embedded region 37 is not disposed. . Further, the n-type embedded region 37 can also have a low impurity concentration based on the N-type epitaxial layer 12 in the opening 133. Further, the N-type embedded region 37 can be formed only in the channel region of the JFET 52 as shown in FIG. 14 and can be formed in the vicinity of the FET 143696.doc -17· 201025566 region of the JFET 52 as shown in FIG. 14B. It may also be formed in the channel region of the JFEt 52 and the N-type extension region 122 as shown in FIG. 14c. Thus, the larger the area occupied by the N-type embedded region 37, the larger the saturation voltage Vsat and the saturation current Isat. Further, as shown in Fig. 14D, the N-type embedded region 37 may be extended to be integrated with the N-type embedded region 22. Further, as shown in FIG. 14e, the saturation voltage Vsat and the saturation current Isat may be adjusted without forming (removing) a portion 'of the body region 15'. Generally, as long as other conditions are the same, the N-type of the N-type embedded region 37 is The higher the impurity concentration, the higher the saturation voltage Vsat and the saturation current Isat; the deeper the N-type embedded region 37, the higher the saturation voltage Vsat and the saturation current lsat; the wider the N-type embedded region 37, the higher the saturation voltage Vsat and the saturation current lsat . Further, the concentration or concentration distribution of the N-type embedded regions 22 and 37 can be adjusted, for example, by appropriately setting the aperture ratio of the ion mask used in ion implantation (diffusion) as will be described later. Further, the saturation current Isat can be adjusted by changing the positions of the source lead-out region 23 and the source electrode 23 1 of the JFET 52. For example, as shown in FIG. 5, the position from the opening 133 to the source lead-out region 23 and the source electrode 231 is sequentially followed by the first position pi which is closer to the channel region (opening portion 133) of the JFET 52. Keep away from P2 and P3 to reduce the saturation current Isat. In particular, by providing the arc-shaped N-type extension region 122 sandwiched by the annular portion 131 and the arc-shaped extending portion 132, the saturation current Isat can be reduced without excessively increasing the size of the JFET 52. (Description of the semiconductor device of the embodiment) 143696.doc • 18· 201025566 In the configuration of the reference semiconductor device described above, the size (width) of the opening 133 is limited, and the rise of the gate voltage Vd is described as the 'annular portion m' The depletion layer DL in the epitaxial layer in the opening portion 133 extends from the third direction (the left and right annular portions 131 and the lower p-type semiconductor substrate UipN junction), and therefore, when the drain voltage Vd is relatively small, The gate area is pinched off. Therefore, it is difficult to obtain a large saturation voltage and a saturation current. On the other hand, even if the width of the opening portion 133 is widened, the depletion layer " extending from the nip N interface of the p-type semiconductor substrate cannot be suppressed, and the increase in saturation voltage and saturation current is limited. In this regard, a semiconductor device 200 that obtains a relatively large saturation voltage and saturation current will be described below. (Second Reference Example) In the semiconductor device 1 of the reference (first reference example), the N-type extension region of the JFET 52 is formed on the outer side of the annular portion 131 along the outer circumference of the LDMOS 51. (source area) 122. On the other hand, in the φ semiconductor device 200 of the present reference example, the source region of the JFET 52 is disposed in the element region of the LDM 〇s. Thereby, the occupied area of the semiconductor element can be further reduced. The other configuration is the same as that of the semiconductor device 100 of the first reference example except for the case where it is specifically described below. 16 and 17 show the structure of the semiconductor device 2 of the second reference example, Fig. 16 is a cross-sectional view of the semiconductor device 200, and Fig. 17 shows the impurity present in the surface region of the epitaxial layer 12 shown in Fig. A plan view of the distribution of the layers. Fig. 18A to Fig. 18C schematically show how the depletion layer extends from the main body region-like element separation region 143696.doc ln 201025566 13 along with the rise of the gate voltage vd ((XV2KV22). A plan view showing the distribution of the impurity layer present in the surface region of the other epitaxial layer. Further, Fig. 16 corresponds to an arrow cross-sectional view taken along line AA of Figs. 17 and 19. The element isolation region 丨3 is formed in a ring shape so as to surround the N-type non-polar region 121, and is formed in a ring shape in detail, and the extension portion 132 is not disposed. The element isolation region 13 is formed in a single ring shape. The body region 15 is formed in a ring shape so as to surround the gate lead-out region 14. The source lead-out region 23 of the JFET 52 is an N-type region having a higher concentration than the n-type drain region ι21. The source lead-out region 23 is attached to the body. Area 15 and defined N-type immersion area The element isolation region 13 of 121 is formed in a ring shape on the surface region of the n-type drain region 121. The source extraction region 23 is formed shallower than the adjacent body region 15 and the element isolation region 13. Surface insulating film A source electrode 23 1 ' is disposed at a position opposite to the source lead-out region 23 at 140, and is connected to the source lead-out region 23 via a contact hole. Further, the 'N-type incident region 22 includes: formed in the N-type 汲a disk-shaped region 22C directly below the polar region 121; and a land-shaped region 22R formed under the body region 15. In this configuration, for example, if the voltage of the body region 15 of the LDMOS, the element isolation region 13 When the voltage and the voltage of the P-type semiconductor substrate u are respectively set to the ground level (ground potential), the drain layer voltage Vd rises, as schematically shown in FIGS. 18A to 18C, the depletion layer DL is from the P-type body region. 15. The P-type element isolation region 13 and the P-type semiconductor substrate 11 extend from the PN junction between the epitaxial layer 12 and the annular region 22R of 143696.doc -20·201025566. The drain voltage Vd reaches a fixed level V22 (V22>V21&gt According to this configuration, the channel region of the JFET 52 exists in the N-type stray layer 12. The N-type epitaxial layer 12 exists in the P-type body region 15, and the p-type element The region between the region 13 and the P-type semiconductor substrate 11 is separated. Further, with the rise of the gate voltage Vd, the depletion layer DL is bonded from the PN junction of the N-type stray layer 12 and the body region I5, and the N-type epitaxial layer The layer 12 extends from the PN junction of the P-type semiconductor substrate u in the lower two directions and is pinched off. The jfet 52 is formed by being pinched off by the depletion layer DL extending from the upper and lower directions. Therefore, it is possible to flow a current (dip-source-to-source current Ids) corresponding to the length of the gate in the lateral direction (the circular LdMOS in the present reference example, which corresponds to the circumferential length of the source lead-out region 23). Further, since the main body region 15, the source lead-out region 23, and the element isolation region 13 which is the gate electrode of the JFET 52 are formed in a ring shape up to the entire circumference of the LDMOS, the size of the JFET 52 can be ensured while being small. To ensure that the saturation current Isat of JFET 52 is large. Here, the saturation current Isat depends on the size of the jfet 52, but may flow to several tens of mA. Further, the source lead-out area 23 of the JFET 52 is not limited to being formed in a ring shape over the entire circumference, and as shown in Fig. 19, one or a plurality of ones may be formed in one of the circumferential directions. Thereby, the gate electrode region 23 is formed in a ring shape as compared with the case where the source lead-out region 23 as shown in FIG. 17 reaches the entire circumference, and the gate electrode width of the JFET 52 is narrower and maintains the saturation voltage Vsat (pinch-off voltage). The saturation current Isat can be made smaller. 143696.doc •21-201025566 Further, as shown in FIGS. 18A to 18C, the presence or absence of the N-type embedded region 22R can control the extension of the depletion layer from the PN junction of the P-type semiconductor substrate 11, and can also be adjusted. The saturation voltage Vsat. Further, in the configuration shown in FIGS. 16 and 17, unlike the semiconductor device 100, the N-type embedded region 22 includes the N-type embedded region 22C directly under the N-type drain region 121 and the ring-shaped portion in the vicinity of the body region 15. N-type embedded region 22R. In particular, the N-type embedded regions 22C and 22R can control the expansion of the depletion layer by appropriately setting the position, size, and impurity concentration of the annular N-type embedded region 22R, and can set the saturation voltage Vsat and the saturation current Isat to Expected value, or controlled by any characteristic. For example, the N-type embedded region 22R disposed under the body region 15 as shown in Fig. 20A extends as shown below the source lead-out region 23 as shown in Fig. 20B, whereby the saturation voltage Vsat can be raised. For example, the relatively shallow N-type embedded region 22R as shown in FIG. 20C is formed deep as shown in FIG. 20D, whereby the saturation voltage Vsat can be raised. For example, the body region 15 as shown in Fig. 20E is set shallow as shown in Fig. 20F, whereby the saturation voltage Vsat can be raised. Further, the distance between the body region 15 and the source lead-out region 23 as shown in Fig. 20G is set to be long as shown in Fig. 20H, whereby the saturation voltage Vsat can be raised. Further, as shown in Figs. 21A and 21B, one or a plurality of N-type embedded regions 22R disposed under the main body region 15 may be formed in one of the circumferential directions. Among them, the saturation voltage Vsat is defined by a portion where the N-type embedded region 22R is not present. 143696.doc -22- 201025566 Further, any one of the N-type embedded region 22C immediately below the N-type drain region 121 or the N-type embedded region 22R disposed under the body region 15 may be disposed. Further, the concentration or concentration distribution of the N-type embedded regions 22R and 22C is carried out by appropriately setting the aperture ratio of the ion mask used for ion implantation (diffusion) as will be described later.

如此，根據半導體裝置200，由LDMOS 5 1之主體區域 15、元件分離區域13、P型半導體基板11、及藉由該等而 夾持之N型之磊晶層12構成LDMOS 51之閘極部，並且 LDMOS 51與JFET 52共有N型汲極區域121，主體區域15與 元件分離區域13之間設置源極引出區域23，因此以一個元 件面積便可獲得LDMOS與JFET之兩個特性。 又，因將LDMOS與JFET並聯複合化，故而為高耐壓。 又，可直接焊接於汲極電極，因此不再另外需要用於連 接之焊墊面積，且無需自半導體裝置之中心部引出高壓之 配線。 因可直接焊接於汲極電極141，故不再另外需要保護元 件，且以LDMOS之耐受量便可進行保護。 無需較大地變更製造製程，僅利用N型嵌入區域22R之 濃度、長度、位置之調整便可設定JFET 52之飽和電壓 Vsat與飽和電流Isat。 上述第1及第2參考例中，係將LDMOS設為圓形，為了 進一步大電流化，亦可設為棒狀或梳齒狀。 如此之構成之半導體裝置之平面構成示於圖22中。再 143696.doc -23- 201025566 者’圖22係表示露出於磊晶層12之表面之半導體區域，汲 極引出區域14形成為梳形。 以包圍汲極引出區域14及場絕緣膜24之方式，將場絕緣 膜18、場板21、閘極絕緣膜19、閘極電極20、主體區域 1 5、源極區域16、主體引出區域丨7、源極引出區域23、及 元件分離區域13分別形成為圈狀。 因此’例如，圖22之D-D線、E-E線、F-F線處之剖面係 以圖16所示之構成進行說明。再者，汲極引出區域14是否 形成為環狀、是否配置場絕緣膜24為任意。 根據如此之構成’可使電流（汲極-源極間電流Ids)之電 流路徑形成為較寬，且可控制大電流。 再者，以上之說明中，係將jFET 52之源極區域（相當於 第1參考例之N型延伸區域122)配置於主體區域15與元件分 離區域13之間。然而，並不限定於此，亦可與第丨參考例 相同，於主體區域1 5之外形成具有開口部13 3之環狀部 13 1。而且，沿著LDMOS配置經由該開口部133連接於N型 汲極區域121之N型延伸區域122。進而，亦可於N型延伸 區域122上形成源極引出區域23及源極電極231。 於LDMOS之元件結構設為棒狀之情形時，有電場集中 於以包圍没極之方式彎曲之部分（11部；圖22中為朝向下凸 出彎曲之區域），而使LDMOS之对壓降低之虞。另一方 面，電場未集中於雖彎曲但不包圍汲極之部分（倒r部；圖 22令朝向上凸出管曲之區域）。因此，為了緩和尺部之電 場’較為有效的是將R部之N型嵌入區域22C、22R之雜質 143696.doc •24- 201025566 濃度設為比直線部之N型嵌入區域22C、22R之雜質濃度 高，將直線部之N型嵌入區域22C、22R之雜質濃度設為比 倒R部之N型嵌入區域22C、22R之雜質濃度高。 "亥清形時，右僅針對區域變更離子注入或雜質擴散之濃 度’則需要相應於離子注入之位置而變更注入製程，且必 需追加步驟，從而會導致成本上升。 該情形時，藉由對離子注入時或者雜質擴散時之遮罩進 行研究而可進行適當之濃度設定。 例如，當形成如圖22所示之梳形之元件結構的半導體裝 置100或200之嵌入區域22C時，可使用圖23八概略所示之 離子遮罩41作為離子注入遮罩。 該離子遮罩41之與如圖22之元件之R部對應之部分之開 口 OP的開口率（每單位面積之開口面積），設為比與直線部 對應之部分（例如，區域ST)之開口 OP的開口率高（寬），並 且與直線部對應之部分之開口 〇p的開口率設為比與倒尺部 對應之部分之開口 OP的開口率高（寬）。 因此，例如，如圖23B模式性地所示，於P型半導體基板 Π上配置離子遮罩41，若自離子照射源42以均一之密度將 離子束IB照射至整個面上，則以適當之濃度將離子注入至 p型半導體基板Π之表面區域。注入之離子於之後之熱處 理中擴散，藉此可獲得適當之濃度分布之N型嵌入區域 22 ’即後步驟中所形成之梳形LDMOS之彎曲部所對應之 部分（電場容易相對集中之部分）處雜質濃度較高、而直線 部所對應之部分（電場難以相對集中之部分）處雜質濃度較 143696.doc -25- 201025566 低之N型嵌入區域22。因此，即便未控制離子注入之摻雜 量或能量，亦可於彎曲部形成適當之濃度分布之N型埋設 區域22。 再者，離子遮罩41並不限於離子注入，亦可用作任意之 擴散方法之雜質遮罩。 再者，無需整體以1片離子遮罩41而形成。例如，如圖 24A〜圖241所示，準備開口 OP之圖案或開口率不同之複數 個遮罩（或注入遮罩形成用之光罩）4la〜41i，例如，亦可於 離子注入時，以彎曲部中使用開口率高之遮罩且直線部中 使用開口率低之遮罩的方式，一面切換所使用之離子遮罩 一面進行離子注入。例如，圖24A〜圖24C中，適當調整圓 形之開口 OP之直徑、數量、配置等以調整開口率。又，圖 24E〜圖24G中，適當調整條紋狀之開口 OP之長度、寬度、 數量、配置等以調整開口率。圖24D及圖24H中，進而調 整開口 OP之形狀以調整開口率。圖241中，可給予濃度分 布以梯度。 如上述般，藉由調整N型嵌入區域22C之濃度，可改善 及變更LDMOS之耐壓、Vd-Id特性等。例如，自尚未呈現 出圖25A所示之飽和區域且元件耐壓較低之狀態起，適當 設定N型嵌入區域22之濃度及其分布，藉此可明確呈現出 如圖25B所示之飽和區域，從而可變更為元件耐壓較高之 特性。 (實施形態） 其次，說明於1晶片上積體化有上述之LDMOS 51與 143696.doc -26· 201025566 JFET 52之複合元件及其他任意之半導體元件的實施形 態。 此處，如圖26所示’除了 LDMOS 51與JFET 52之外’亦 使如下電路共用没極地形成於1晶片上’該電路包括用於 大電流所流經之功率LDM0S 53、及用於檢測流經功率 LDMOS 53之電流的感測器LDMOS 54。 圖27表示於1晶片上形成圖26所示之電路時之區域配置 與電極配置之一例。該構成係採用圖1〜3所示之構成作為 ® LDMOS 51及JFET 52時之示例。 圖27中，區域411上形成有上述LDMOS 51及JFET 52。 自N型汲極區域121引出延伸區域122，N型汲極區域121上 配置有LDMOS 51之閘極電極20、源極電極161、及主體電 極171。進而，延伸區域122上配置有JFET 52之源極電極 23 1。區域411之剖面G-G與自圖1之剖面之汲極電極141算 起的右半分為相同之構成。 又，區域412上形成有感測器LDMOS 54，感測器 ❷ LDMOS 54上配置有閘極電極（第3閘極電極）321與源極電 極322。其他區域上形成有功率LDMOS 53，且配置有：於 區域411處開口且以包圍汲極電極141之方式而配置之閘極 電極（第2閘極電極）331，及於區域411及區域412具有開口 部且以包圍汲極電極141之方式而配置之源極電極332。 功率LDMOS 53之閘極電極331與感測器LDMOS 54之閘 極電極321形成為一體。又，LDMOS 51之閘極電極20、功 率LDMOS 53之閘極電極331及感測器LDMOS 54之閘極電 143696.doc -27· 201025566 極321係異體地構成。進而，功率LDMOS 53之源極電極 3 32、感測器LDMOS 54之源極電極322、LDMOS 51之源極 電極161、及JFET 52之源極電極231分別異體地構成。 再者，功率LDMOS 53之主體引出區域與主體電極以任 意之大小而形成於任意之位置。 功率LDMOS 53之剖面H-H、及感測器LDMOS 54之剖面 I-Ι具有共同之構成，且如圖29所示，除了未設置JFET 52 之源極區域23、主體區域（第1導電型之第2區域）15與元件 分離區域13係連接之外，與上述LDMOS 51之構成相同。 再者，功率LDMOS 53用之主體區域（第1導電型之第2區 域）15與感測器LDMOS 54用之主體區域（第1導電型之第3 區域）15構成為一體。又，LDMOS 51及JFET 52用之主體 區域15與功率LDMOS 53及感測器LDMOS 54用之主體區域 15係異體地構成。再者，功率LDMOS 53用之主體區域15 與感測器LDMOS 54用之主體區域15亦可為異體。 而且，於元件區域之中央部配置有4個元件之共用之N型 汲極區域121，其中央配置有汲極引出區域14與汲極電極 141。 圖28表示於1晶片上形成圖26所示之電路時之區域配置 與電極配置之另一例。該構成為採用圖16及圖17所示之構 成作為LDMOS 51及JFET 52之情形時的構成例。圖28中， 區域411上形成有LDMOS 51與JFET 52，且形成有LDMOS 51之閘極電極20、源極電極161及主體電極171。而且，主 髏電極171與元件分離區域13之間配置有JFET 52之源極電 143696.doc •28· 201025566 極231。區域4 11之剖面G-G與自圖16之剖面之没極電極141 算起的右半部分為相同之構成。 又，鄰接於區域411之區域412上形成有感測器LDMOS 54，且配置有閘極電極321與源極電極322。其他區域上形 成有功率LDMOS 53，且配置有：於區域413處開口且以包 圍汲極電極141之方式配置之閘極電極331，及於區域412 及區域413具有開口部且以包圍汲極電極141之方式配置成 C字狀的源極電極332。 _ 又，功率LDMOS 53之主體引出區域與主體電極以任意 之大小而形成於任意之位置。 功率LDMOS 53之剖面H-H、及感測器LDM0S 54之剖面 I-Ι之構成如圖29所示，除了未設置JFET 52之源極區域 23、及主體區域（第1導電型之第2區域）15與元件分離區域 13係連接之外，與上述LDMOS 51之構成相同° 再者，功率LDMOS 53之閘極電極33 1與感測器LDMOS 54之閘極電極321形成為一體。又，LDMOS 51之閘極電極 20與功率LDMOS 53之閘極電極331及感測器LDMOS 54之 . 閘極電極321係異體地構成。進而’功率LDMOS 53之源極 電極332與感測器LDMOS 54之源極電極322係異體地構 成。 晶片之周緣部配置有功率LDMOS閘極電極連接墊、功 率LDMOS源極電極墊、感測器LDMOS源極電極墊、 LDMOS源極電極墊、及LDMOS閘極墊電極等，且分別經 由未圖示之配線及觸點而連接於對應之電極。 143696.doc -29· 201025566 再者，功率LDMOS 53之主體引出區域與主體電極以任 意之大小而形成於任意之位置。 功率LDMOS 53之剖面H-H、及感測器LDMOS 54之剖面 1_1具有共同之構成，且如圖29所示，除了未設置JFET 52 之源極區域23、及主體區域（第1導電型之第2區域）15與元 件分離區域13係連接之外，與上述LDMOS 51之構成相 同。 再者，功率LDMOS 53用之主體區域（第1導電型之第2區 域）15與感測器LDMOS 54用之主體區域（第1導電型之第3 區域）15係構成為一體。 又，LDMOS 51及JFET 52用之主體區域15與功率 LDMOS 53及感測器LDMOS 54用之主體區域15係異體地構 成。再者，功率LDMOS 53用之主體區域15與感測器 LDMOS 54用之主體區域15亦可為異體。 而且，於元件區域之中央部配置有4個元件之共用之N型 汲極區域121，N型汲極區域121之中央部配置有汲極引出 區域14與汲極電極141。 藉由如此之構成之半導體裝置，例如，i)藉由LDMOS 51與JFET 52構成起動電路，於起動時開始對内部電路412 進行電力之供給從而起動内部電路412，ii)起動之内部電 路412起動作為周邊電路之功率ldm〇S 53而將大電流供給 至對象電路，進而’根據作為周邊電路之感測器LDMOS 54之輸出而可進行監控電流值之動作，從而不再另外需要 原本所需之分立裝置。 143696.doc •30· 201025566 又，藉由調整配置之電極墊，可設定任意之元件之使 用、不使用。例如，於不需要感測器LDMOS 54之情形 時，亦可不配置感測器用之電極墊。又，於不需要高耐壓 開關之情形時，亦可不配置功率LDMOS 53用之電極墊。 再者，亦可不組裝元件本身。 以上之例中，係將4個半導體元件組裝於基板11上，而 組裝何種半導體元件為任意，可僅組裝4個半導體元件中 之2個或3個，或者亦可組裝其他種類之元件等。 例如，可將JFET複合化於功率LDMOS 53上，而對共計 5個元件進行1晶片化（積體化）。該情形時，例如，如圖30 所示，將功率LDMOS 53設為圖1〜圖3所示之構成，且可於 任意之位置，例如於區域414上，在功率LDMOS 53之環狀 之元件分離區域13形成開口部，並引出延伸部132，於該 延伸部132形成源極引出區域，且配置源極電極232。進 而.，配置JFET用之電極塾。 又，例如，如圖31所示，將功率LDMOS 53設為如圖16 及圖17所示之構成，並於任意之位置，例如於區域415 上，在功率LDMOS 53之主體區域（第1導電型之第2區 域）15與元件分離區域13之間形成源極引出區域，並配置 源極電極232。又，配置JFET用之電極墊。 若設為如此之構成，例如，可將功率LDMOS與JFET之 複合體、LDMOS與JFET之複合體、感測器LDMOS等以共 用汲極的方式組裝於1個晶片上，從而不需要分立裝置。 又，為了進一步增高功率LDMOS 53之耐壓且可進行大 143696.doc -31 - 201025566 電流驅動’而可與圖22所例示之LDMOS相同，將沒極設 為梳齒狀，且將功率LDMOS 53之閘極及源極沿著梳齒狀 之沒極區域而配置。 本發明並不限於上述實施形態，可進行各種修正及應 用。元件結構為一例，可進行適當變更。 本申請案係基於且主張2008年9月30曰申請的曰本專利 申請案第2008-255760號、及2009年9月25日申請的日本專 利申請案第2009-221683號之優先權，且包含該申請案之 發明之詳細說明（說明書）、申請專利範圍、圖式及發明之 概要。日本專利申請案第2〇〇8_25576〇號及2〇〇9 221683號 所揭示之内容以引用的方式全部併入本文。 【圖式簡單說明】 圖1係本發明第丨參考例之半導體襞置之剖面圖，相當於 圖4及圖5之A-A線剖面圖； 圖2係本發明第1參考例之半導體裝置之剖面圖，相當於 圖4及圖5之B-B線剖面圖； 圖3係本發明第！參考例之半導體裝置之剖面圖，相當於 圖4及圖5之C-C線剖面圖； 圖4係表示本發明第1參考例之半導體裴置之磊晶層表面 之雜質層的配置構成之平面圖； 圖5係表不本發明第丨參考例之半導體裝置之電極的配置 構成之平面圖； 圖6係表不本發明第1參考例之半導體裝置之電極及焊塾 的配置構成之平面圖； 143696.doc -32. 201025566 圖7係本發明第丨參考例之半導體裝置之等價電路之電路 圖； 圖8係將本發明第丨參考例之半導體裝置用作起動電路之 情形時之電路圖； 圖9 A係模式性地表示本發明第丨參考例之半導體裝置 中，伴隨汲極電壓Vd之上升（Vd=〇)，空乏層於分離區域之 開口部處如何延伸之圖； 圖9B係模式性地表示本發明第1參考例之半導體裝置 t ’伴隨汲極電壓Vd之上升(Vd=v”，$乏層於分離區域 之開口部處如何延伸之圖； 圖9C係模式性地表示本發明第j參考例之半導體裝置 中，伴隨没極電壓Vd之上升（Vd=V2)，空乏層於分離區域 之開口部處如何延伸之圖； 圖9D係模式性地表#本發明第1參考例之半導禮裝置 中伴隨;及極電壓Vd之上升（Vd=V3)，$乏層於分離區域 ^ 之開口部處如何延伸之圖； 圖1〇係表示本發明第1參考例之半導體裝置中，汲極電 壓Vd與JFET之没極-源極間電流⑷之關係之圖； 圖11係表不本發明第！參考例之半導體裝置中，使 之閘極電壓vg變化之情形時的沒極電壓vd與之没極_ 源極間電流Ids之關係的圖； 圖12係本發明第i參考例之半導體裝置中，元件分離區 域之開口 上配置有閘極絕緣膜及開極電極之構成的說明 圖； 143696.doc -33· 201025566 圖13係本發明第丨參考例之半導體裝置中，元件分離區 域之開口部上配置有嵌入區域之構成的說明圖； 圖14A係表示本發明第〗參考例之半導體裝置中圖13所 示之N型嵌入區域之平面性配置例的圖； 圖14B係表示本發明第丨參考例之半導體裝置中，圖13所 示之N型嵌入區域之平面性配置例的圖； 圖14C係表示本發明第1參考例之半導體裝置中圖13所 示之N型嵌入區域之平面性配置例的圖； 圖14D係表示本發明第丨參考例之半導體裝置中，圖^所 示之N型嵌入區域之平面性配置例的圖； 圖14E係表示本發明第丨參考例之半導體裝置中主體區 域之平面性配置例的圖； 圖15係本發明第1參考例之半導體裝置中，使之源 極電極之配置變化之例的說明圖； 圖16係本發明第2參考例之半導體裝置之剖面圖，相當 於圖17之A-A線剖面圖； 圖17係表示本發明第2參考例之半導體裝置之磊晶層之 表面上之雜質層的配置構成之平面圖； 曰 圖18A係模式性地表示本發明第2參考例之半導體裝置 令，伴隨汲極電壓Vd之上升（Vd=〇)，空乏層如何自主體區 域及分離區域起延伸的圖； 圖18B係模式性地表示本發明第2參考例之半導體裝置 中’伴隨汲極電壓Vd之上升（Vd=V21)，*彡a 二之屬如何自主 體Εΐ域及分離區域起延伸的圖； 143696.doc • 34 - 201025566 圖18C係模式性地表示本發明第2參考例之半導體裝置 中，伴隨汲極電壓vd之上升（Vd=V22)，空乏層如何自主 體區域及分離區域起延伸的圖； 圖19係表示本發明第2參考例之半導體裝置之變形例的 磊晶層之表面上之雜質層之配置構成的平面圖； 圖20A係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20B係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20C係用於說明N型嵌入區域之·構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20D係用於說明N型嵌入區域之構成之變化對飽和電 壓及飽和電流所造成的影響之圖； 圖20E係用於說明主體區域之構成對飽和電壓及飽和電 流所造成的影響之圖； 圖2 0F係用於說明主體區域之構成對飽和電壓及飽和電 流所造成的影響之圖； 圖20G係用於說明主體區域與源極引出區域之距離對飽 和電壓及飽和電流所造成的影響之圖； 圖20H係用於說明主體區域與源極引出區域之距離對飽 和電壓及飽和電流所造成的影響之圖； 圖21A係表示N型嵌入區域之構成之變形例的圖； 圖21B係表示N型嵌入區域之構成之另一變形例的圖； 圖22係表示第2參考例之半導體裝置之磊晶層之表面區 143696.doc -35- 201025566 域之雜質層的配置構成之平面圖； 圖23A係表示用於形成第2參考例之半導體裝置之n型嵌 入區域的離子遮罩之構成之圖； 圖23B係使用用於形成第2參考例之半導體裝置之n型欲 區域的離子遮罩使雜質擴散之製程之說明圖； 圖24A係表示開口率不同之離子遮罩之一例的圖； 圖24B係表示開口率不同之離子遮罩之一例的圖； 圖24C係表示開口率不同之離子遮罩之一例的圖； 圖24D係表示開口率不同之離子遮罩之一例的圖； 圖24E係表示開口率不同之離子遮罩之一例的圖； 圖24F係表示開口率不同之離子遮罩之—例的圖； 圖24G係表示開口率不同之離子遮罩之—例的圖； 圖24H係表示開口率不同之離子遮罩之一例的圖； 圖241係表示開口率不同之離子遮罩之一例的圖； 圖25A係表示藉由調㈣型嵌入區域之雜質濃度而汲極 電壓-源極、汲極電流特性發生變化之圖； 圖25B係表示藉由調㈣型嵌入區域之雜質濃度而汲極 電壓-源極、汲極電流特性發生變化之圖； 圖26係表示本發明實施形態之半導體裝置之等價電路之 電路圖； ' 圖27係表示本發明實施形態之半導體裝置之電極配置之 第1例之平面圖； 圖28係表示本發明實施形態之半導體裝置之電極配置之 第2例之平面圖； 143696.doc -36- 201025566 圖29係本發明實施形態之半導體裝置之剖面圖，相當於 圖27、28之H-H線及I-Ι線剖面圖； 圖30係表示將JFET複合化於本發明實施形態之半導體裝 置之功率LDMOS之第1例的平面圖； 圖3 1係表示將JFET複合化於本發明實施形態之半導體裝 置之功率LDMOS之第2例的平面圖； 圖32A係表示先前之起動電路之構成之電路圖；及 圖32B係使用JFET與LDMOS之起動電路之電路圖。 【主要元件符號說明】 11 P型半導體基板（第1導電型之層） 12 蟲晶層（第2導電型之層） 13 p型之元件分離區域（第1導電型之元 件分離區域） 14 汲極引出區域 15 P型之主體區域（第I導電型之第1區域） 16 N型之源極區域（第2導電型之第1源極區 域） 17 主體引出區域 18、24 場絕緣膜 19 閘極絕緣膜 20 閘極電極（第1閘極電極） 21 場板 22 N型嵌入區域（第2導電型之第1區域） 22C 圓盤狀之區域 143696.doc 201025566 22R 23 31 、 32 、 33 35 、 211 36 37 41 4 la〜41i 42 51 、 411 52 、 413 53 54 100 ' 200 121 122 131 132 133 140 141 161 、 231 、 環狀之區域 N型之源極引出區域（第2導電型之第2 源極區域） 電極墊 絕緣膜 閘極電極 第2導電型之第2區域 離子遮罩 遮罩 離子照射源 LDMOS JFET 功率LDMOS 感測器LDMOS 半導體裝置 第2導電型之汲極區域 第2導電型之延伸區域 圈狀部 部分 開口部 表面絕緣膜 汲極電極 源極電極 322 ' 332 143696.doc -38- 201025566 171 主體電極 321 第3閘極電極 331 第2閘極電極 411 、 412 、 413、414、415 區域 412 内部電路 DL 空乏層 IB 離子束 ❿ Ids 電流 OP 開口 PI ' P2 ' P3 位置 R 電阻 ST 區域 T 起動端子 V21 、 V22 固定位準 Vd、VI、V2、 ❿ V3 汲極電壓 Vg 閘極電壓 Vsat 電壓 143696.doc •39-As described above, according to the semiconductor device 200, the main body region 15, the element isolation region 13, the P-type semiconductor substrate 11, and the N-type epitaxial layer 12 sandwiched by the LDMOS 51 constitute the gate portion of the LDMOS 51. And the LDMOS 51 and the JFET 52 share the N-type drain region 121, and the source lead-out region 23 is provided between the body region 15 and the element isolation region 13, so that two characteristics of the LDMOS and the JFET can be obtained with one element area. Further, since the LDMOS and the JFET are combined in parallel, the voltage is high. Further, it can be directly soldered to the drain electrode, so that the pad area for connection is not additionally required, and it is not necessary to draw high voltage wiring from the center portion of the semiconductor device. Since it can be directly soldered to the drain electrode 141, the protection element is no longer required and can be protected by the tolerance of the LDMOS. The saturation voltage Vsat and the saturation current Isat of the JFET 52 can be set only by adjusting the concentration, length, and position of the N-type embedded region 22R without greatly changing the manufacturing process. In the first and second reference examples, the LDMOS is formed in a circular shape, and may be formed in a rod shape or a comb shape in order to further increase the current. The planar configuration of the semiconductor device thus constructed is shown in FIG. Further, 143696.doc -23-201025566' Fig. 22 shows a semiconductor region exposed on the surface of the epitaxial layer 12, and the cathode lead-out region 14 is formed in a comb shape. The field insulating film 18, the field plate 21, the gate insulating film 19, the gate electrode 20, the body region 15, the source region 16, and the body lead-out region are surrounded by the drain region 14 and the field insulating film 24. 7. The source lead-out area 23 and the element isolation area 13 are each formed in a ring shape. Therefore, for example, the cross-sections at the D-D line, the E-E line, and the F-F line in Fig. 22 will be described with reference to the configuration shown in Fig. 16. Further, whether or not the drain electrode lead-out region 14 is formed in a ring shape or whether the field insulating film 24 is disposed is arbitrary. According to such a configuration, the current path of the current (drain-source current Ids) can be made wider, and a large current can be controlled. In the above description, the source region of the jFET 52 (corresponding to the N-type extension region 122 of the first reference example) is disposed between the body region 15 and the element isolation region 13. However, the present invention is not limited thereto, and the annular portion 13 1 having the opening portion 13 3 may be formed outside the main body region 15 as in the second embodiment. Further, the N-type extension region 122 of the N-type drain region 121 is connected via the opening portion 133 along the LDMOS. Further, the source lead-out region 23 and the source electrode 231 may be formed on the N-type extension region 122. When the element structure of the LDMOS is set to a rod shape, an electric field is concentrated on a portion that is bent in a manner that surrounds the pole (11 portions; in FIG. 22, a region that is convex toward the lower side), and the voltage of the LDMOS is lowered. After that. On the other hand, the electric field is not concentrated on the portion that is curved but does not surround the bungee (inverted r; in Fig. 22, the region that protrudes upward from the pipe). Therefore, in order to alleviate the electric field of the ruler, it is effective to set the impurity concentration of the N-type embedded regions 22C and 22R of the R portion to 143696.doc •24-201025566 as the impurity concentration of the N-type embedded regions 22C and 22R of the straight portion. When the height is high, the impurity concentration of the N-type embedded regions 22C and 22R in the straight portion is higher than the impurity concentration of the N-type embedded regions 22C and 22R in the inverted R portion. "Haiqing shape, the right only changes the concentration of ion implantation or impurity diffusion for the region', and the injection process needs to be changed corresponding to the position of the ion implantation, and an additional step is necessary, which leads to an increase in cost. In this case, an appropriate concentration setting can be performed by investigating the mask at the time of ion implantation or when the impurities are diffused. For example, when the embedded region 22C of the semiconductor device 100 or 200 having the comb-shaped element structure shown in Fig. 22 is formed, the ion mask 41 schematically shown in Fig. 23 can be used as the ion implantation mask. The aperture ratio (opening area per unit area) of the portion OP of the ion mask 41 corresponding to the R portion of the element of FIG. 22 is set to be larger than the portion corresponding to the straight portion (for example, the region ST). The aperture ratio of the OP is high (wide), and the aperture ratio of the opening 〇p corresponding to the straight portion is set to be higher (wider) than the aperture ratio of the opening OP corresponding to the step portion. Therefore, for example, as schematically shown in FIG. 23B, the ion mask 41 is disposed on the P-type semiconductor substrate, and if the ion beam IB is irradiated to the entire surface from the ion irradiation source 42 at a uniform density, it is appropriate. The concentration implants ions into the surface region of the p-type semiconductor substrate. The implanted ions are diffused in the subsequent heat treatment, whereby an N-type embedded region 22' of a suitable concentration distribution, that is, a portion corresponding to the bent portion of the comb-shaped LDMOS formed in the subsequent step (the portion where the electric field is relatively concentrated) is obtained. The N-type embedded region 22 having a higher impurity concentration and a portion corresponding to the straight portion (the portion where the electric field is difficult to be concentrated) has a lower impurity concentration than 143696.doc -25-201025566. Therefore, even if the doping amount or energy of the ion implantation is not controlled, the N-type buried region 22 of an appropriate concentration distribution can be formed in the bent portion. Further, the ion mask 41 is not limited to ion implantation, and can also be used as an impurity mask for any diffusion method. Furthermore, it is not necessary to form the entire ion mask 41 as a whole. For example, as shown in FIG. 24A to FIG. 241, a plurality of masks (or masks for injecting masks) 4a to 41i having different patterns or openings of openings OP are prepared, for example, at the time of ion implantation. In the curved portion, a mask having a high aperture ratio is used, and a mask having a low aperture ratio is used in the straight portion, and ion implantation is performed while switching the ion mask used. For example, in Figs. 24A to 24C, the diameter, the number, the arrangement, and the like of the circular opening OP are appropriately adjusted to adjust the aperture ratio. Further, in Figs. 24E to 24G, the length, the width, the number, the arrangement, and the like of the stripe-shaped opening OP are appropriately adjusted to adjust the aperture ratio. In Figs. 24D and 24H, the shape of the opening OP is further adjusted to adjust the aperture ratio. In Figure 241, the concentration distribution can be given as a gradient. As described above, by adjusting the concentration of the N-type embedded region 22C, the withstand voltage and Vd-Id characteristics of the LDMOS can be improved and changed. For example, since the saturation region shown in FIG. 25A is not present and the element withstand voltage is low, the concentration of the N-type embedded region 22 and its distribution are appropriately set, whereby the saturated region as shown in FIG. 25B can be clearly exhibited. Therefore, the characteristics of the component with higher withstand voltage can be changed. (Embodiment) Next, an embodiment in which a composite element of the above-described LDMOS 51 and 143696.doc -26 201025566 JFET 52 and any other semiconductor element are integrated on one wafer will be described. Here, as shown in FIG. 26, 'except for the LDMOS 51 and the JFET 52', the following circuits are collectively formed on the 1st wafer. The circuit includes the power LDM0S 53 for a large current, and is used for detection. A sensor LDMOS 54 that flows through the current of the power LDMOS 53. Fig. 27 shows an example of an arrangement of regions and an arrangement of electrodes when a circuit shown in Fig. 26 is formed on a wafer. This configuration is an example in which the configurations shown in Figs. 1 to 3 are used as the ® LDMOS 51 and the JFET 52. In FIG. 27, the LDMOS 51 and the JFET 52 are formed on the region 411. The extension region 122 is drawn from the N-type drain region 121, and the gate electrode 20, the source electrode 161, and the body electrode 171 of the LDMOS 51 are disposed on the N-type drain region 121. Further, the source electrode 23 1 of the JFET 52 is disposed on the extension region 122. The section G-G of the region 411 is divided into the same configuration as the right half of the gate electrode 141 of the section of Fig. 1. Further, a sensor LDMOS is formed in the region 412. The sensor ❷ LDMOS 54 is provided with a gate electrode (third gate electrode) 321 and a source electrode 322. The power LDMOS 53 is formed in another region, and is provided with a gate electrode (second gate electrode) 331 which is opened at the region 411 and is disposed to surround the gate electrode 141, and has a region 411 and a region 412 The source electrode 332 is disposed to surround the drain electrode 141. The gate electrode 331 of the power LDMOS 53 is formed integrally with the gate electrode 321 of the sensor LDMOS 54. Further, the gate electrode 20 of the LDMOS 51, the gate electrode 331 of the power LDMOS 53, and the gate electrode 143696.doc -27·201025566 of the LDMOS 54 are formed separately. Further, the source electrode 3 32 of the power LDMOS 53 , the source electrode 322 of the sensor LDMOS 54 , the source electrode 161 of the LDMOS 51 , and the source electrode 231 of the JFET 52 are formed separately. Further, the main body lead-out area of the power LDMOS 53 and the main body electrode are formed at arbitrary positions in an arbitrary size. The profile HH of the power LDMOS 53 and the profile I-Ι of the sensor LDMOS 54 have a common configuration, and as shown in FIG. 29, the source region 23 and the body region of the JFET 52 are not provided (the first conductivity type) The 2 region) 15 is the same as the above-described LDMOS 51 except that it is connected to the element isolation region 13. Further, the main body region (the second region of the first conductivity type) 15 for the power LDMOS 53 and the body region (the third region of the first conductivity type) 15 for the sensor LDMOS 54 are integrally formed. Further, the body region 15 for the LDMOS 51 and the JFET 52 is configured separately from the body region 15 for the power LDMOS 53 and the sensor LDMOS 54. Furthermore, the body region 15 for the power LDMOS 53 and the body region 15 for the sensor LDMOS 54 may be foreign bodies. Further, a common N-type drain region 121 of four elements is disposed in the central portion of the element region, and a drain lead-out region 14 and a drain electrode 141 are disposed in the center thereof. Fig. 28 shows another example of the arrangement of the regions and the arrangement of the electrodes when the circuit shown in Fig. 26 is formed on one wafer. This configuration is a configuration example in the case where the configuration shown in Figs. 16 and 17 is used as the LDMOS 51 and the JFET 52. In FIG. 28, an LDMOS 51 and a JFET 52 are formed in a region 411, and a gate electrode 20, a source electrode 161, and a body electrode 171 of the LDMOS 51 are formed. Further, a source 143696.doc • 28· 201025566 pole 231 of the JFET 52 is disposed between the main drain electrode 171 and the element isolation region 13. The section G-G of the region 4 11 has the same configuration as the right half of the pillar electrode 141 of the section of Fig. 16. Further, a sensor LDMOS 54 is formed on a region 412 adjacent to the region 411, and a gate electrode 321 and a source electrode 322 are disposed. The power LDMOS 53 is formed in another region, and is provided with a gate electrode 331 which is opened at the region 413 and is disposed to surround the gate electrode 141, and has an opening portion in the region 412 and the region 413 to surround the gate electrode In the manner of 141, the source electrode 332 is formed in a C shape. Further, the main body lead-out area of the power LDMOS 53 and the main body electrode are formed at arbitrary positions in an arbitrary size. The cross section HH of the power LDMOS 53 and the cross section I-Ι of the sensor LDM0S 54 are as shown in Fig. 29, except that the source region 23 of the JFET 52 and the main body region (the second region of the first conductivity type) are not provided. 15 is connected to the element isolation region 13 in the same manner as the above-described LDMOS 51. Further, the gate electrode 33 1 of the power LDMOS 53 and the gate electrode 321 of the sensor LDMOS 54 are formed integrally. Further, the gate electrode 20 of the LDMOS 51 is connected to the gate electrode 331 of the power LDMOS 53 and the sensor LDMOS 54. The gate electrode 321 is formed separately. Further, the source electrode 332 of the power LDMOS 53 and the source electrode 322 of the sensor LDMOS 54 are formed separately. A power LDMOS gate electrode connection pad, a power LDMOS source electrode pad, a sensor LDMOS source electrode pad, an LDMOS source electrode pad, and an LDMOS gate pad electrode are disposed on a peripheral portion of the wafer, and are respectively illustrated by The wiring and contacts are connected to the corresponding electrodes. 143696.doc -29· 201025566 Furthermore, the main body lead-out area of the power LDMOS 53 and the main body electrode are formed at arbitrary positions in an arbitrary size. The cross section HH of the power LDMOS 53 and the cross section 1_1 of the sensor LDMOS 54 have a common structure, and as shown in FIG. 29, the source region 23 and the main body region (the first conductivity type 2) in which the JFET 52 is not provided are provided. The region 15 is connected to the element isolation region 13 in the same manner as the above-described LDMOS 51. Further, the main body region (the second region of the first conductivity type) 15 for the power LDMOS 53 and the body region (the third region of the first conductivity type) 15 for the sensor LDMOS 54 are integrally formed. Further, the body region 15 for the LDMOS 51 and the JFET 52 is formed separately from the body region 15 for the power LDMOS 53 and the sensor LDMOS 54. Furthermore, the body region 15 for the power LDMOS 53 and the body region 15 for the sensor LDMOS 54 may be foreign bodies. Further, a common N-type drain region 121 of four elements is disposed in a central portion of the element region, and a drain lead region 14 and a drain electrode 141 are disposed at a central portion of the N-type drain region 121. With the semiconductor device thus constituted, for example, i) the startup circuit is constituted by the LDMOS 51 and the JFET 52, the supply of power to the internal circuit 412 is started at the start of the startup, and the internal circuit 412 is started, and the internal circuit 412 of the startup is started. As the power of the peripheral circuit ldm 〇 S 53 , a large current is supplied to the target circuit, and the operation of monitoring the current value can be performed based on the output of the LDMOS 54 as the peripheral circuit, so that the original required value is no longer required. Discrete device. 143696.doc •30· 201025566 Also, by adjusting the electrode pads of the configuration, you can set the use of any component or not. For example, when the sensor LDMOS 54 is not required, the electrode pad for the sensor may not be disposed. Further, when a high withstand voltage switch is not required, the electrode pad for the power LDMOS 53 may not be disposed. Furthermore, the components themselves may not be assembled. In the above example, four semiconductor elements are mounted on the substrate 11, and any semiconductor elements are assembled, and only two or three of the four semiconductor elements may be assembled, or other types of components may be assembled. . For example, the JFET can be composited on the power LDMOS 53, and a total of five elements can be wafer-formed (integrated). In this case, for example, as shown in FIG. 30, the power LDMOS 53 is configured as shown in FIGS. 1 to 3, and may be at any position, for example, on the region 414, in the ring-shaped component of the power LDMOS 53. The separation region 13 forms an opening portion, and the extension portion 132 is taken out, a source lead-out region is formed in the extension portion 132, and the source electrode 232 is disposed. Further, the electrode 塾 for the JFET is configured. Further, for example, as shown in FIG. 31, the power LDMOS 53 is configured as shown in FIGS. 16 and 17, and is located at any position, for example, on the region 415, in the main region of the power LDMOS 53 (first conductive). A source lead-out region is formed between the second region 15 of the type and the element isolation region 13, and the source electrode 232 is disposed. Further, an electrode pad for a JFET is disposed. With such a configuration, for example, a composite of a power LDMOS and a JFET, a composite of an LDMOS and a JFET, a sensor LDMOS, or the like can be assembled on one wafer in a common drain, so that a discrete device is not required. Further, in order to further increase the withstand voltage of the power LDMOS 53 and perform current driving of 143696.doc -31 - 201025566, the same as the LDMOS illustrated in Fig. 22, the immersion is set to a comb shape, and the power LDMOS 53 is used. The gate and the source are arranged along the comb-toothed region. The present invention is not limited to the above embodiment, and various modifications and applications are possible. The element structure is an example and can be changed as appropriate. The present application is based on and claims the priority of Japanese Patent Application No. 2008-255760, filed on Sep. 30, 2008, and Japanese Patent Application No. 2009-221683, filed on Sep. 25, 2009. A detailed description (instructions) of the invention of the application, a patent application scope, a drawing, and an outline of the invention. The contents disclosed in Japanese Patent Application Laid-Open No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a semiconductor device according to a reference example of the present invention, which corresponds to a cross-sectional view taken along line AA of FIG. 4 and FIG. 5; FIG. 2 is a cross section of a semiconductor device according to a first reference example of the present invention. Figure 3 is a cross-sectional view taken along line BB of Figures 4 and 5; Figure 3 is the first aspect of the present invention! The cross-sectional view of the semiconductor device of the reference example corresponds to the CC line cross-sectional view of FIG. 4 and FIG. 5; FIG. 4 is a plan view showing the arrangement of the impurity layers on the surface of the epitaxial layer of the semiconductor device of the first reference example of the present invention; 5 is a plan view showing an arrangement of electrodes of a semiconductor device according to a first reference example of the present invention; and FIG. 6 is a plan view showing an arrangement of electrodes and pads of a semiconductor device according to a first reference example of the present invention; 143696.doc -32. 201025566 FIG. 7 is a circuit diagram of an equivalent circuit of a semiconductor device of a reference example of the present invention; FIG. 8 is a circuit diagram showing a case where the semiconductor device of the second reference example of the present invention is used as a starting circuit; In the semiconductor device according to the first reference example of the present invention, a graph of how the depletion layer extends at the opening of the separation region is accompanied by an increase in the gate voltage Vd (Vd=〇); FIG. 9B schematically shows the present invention. The semiconductor device t' of the first reference example is accompanied by a rise of the gate voltage Vd (Vd=v", a diagram of how the spent layer extends at the opening of the separation region; and FIG. 9C schematically shows the jth parameter of the present invention. In the semiconductor device of the example, the pattern of how the depletion layer extends at the opening of the separation region is accompanied by the rise of the electrode voltage Vd (Vd=V2); FIG. 9D is a schematic representation of the semi-guide of the first reference example of the present invention. With the rise of the pole voltage Vd (Vd=V3), how does the excess layer extend at the opening of the separation region? FIG. 1 is a diagram showing the drain of the semiconductor device according to the first reference example of the present invention. FIG. 11 is a diagram showing the relationship between the voltage Vd and the gate-source current (4) of the JFET; FIG. 11 is a diagram showing the stepless voltage vd when the gate voltage vg is changed in the semiconductor device of the reference example of the present invention. FIG. 12 is a view showing a configuration in which a gate insulating film and an open electrode are disposed in an opening of an element isolation region in the semiconductor device according to the i-th reference example of the present invention; 133696.doc -33. 201025566 FIG. 13 is an explanatory view showing a configuration in which an embedded region is disposed in an opening portion of an element isolation region in a semiconductor device according to a reference example of the present invention; and FIG. 14A is a semiconductor showing a reference example of the present invention. N type shown in Figure 13 of the device FIG. 14B is a view showing a planar arrangement example of the N-type embedded region shown in FIG. 13 in the semiconductor device of the reference example of the present invention; FIG. 14C shows the first embodiment of the present invention. FIG. 14D is a view showing a planar arrangement example of the N-type embedded region shown in FIG. 13 in the semiconductor device of the reference example; FIG. 14D is a view showing the planarity of the N-type embedded region shown in FIG. FIG. 14 is a view showing a planar arrangement example of a main body region in a semiconductor device according to a first reference example of the present invention; and FIG. 15 is a configuration of a source electrode in the semiconductor device according to the first reference example of the present invention; FIG. 16 is a cross-sectional view of a semiconductor device according to a second reference example of the present invention, and corresponds to a cross-sectional view taken along line AA of FIG. 17. FIG. 17 is a view showing an epitaxial layer of a semiconductor device according to a second reference example of the present invention. FIG. 18A is a schematic view showing a semiconductor device according to a second reference example of the present invention, with the rise of the drain voltage Vd (Vd=〇), how the depletion layer is self-body region and FIG. 18B is a schematic diagram showing the rise of the threshold voltage Vd (Vd=V21) in the semiconductor device according to the second reference example of the present invention, how the genus of the 彡a 2 is from the main domain and FIG. 18C is a schematic diagram showing a semiconductor device according to a second reference example of the present invention, in which the depletion layer is self-subjected with a rise in the gate voltage vd (Vd=V22). FIG. 19 is a plan view showing an arrangement of impurity layers on the surface of an epitaxial layer of a modification of the semiconductor device according to the second reference example of the present invention; FIG. 20A is for explaining N-type embedding. Figure 20B is a diagram illustrating the effect of changes in the composition of the N-type embedded region on saturation voltage and saturation current; Figure 20C is used to illustrate the effect of changes in the composition of the region on the saturation voltage and saturation current; A diagram illustrating the influence of the change in the configuration of the N-type embedded region on the saturation voltage and the saturation current; FIG. 20D is a diagram for explaining the change in the configuration of the N-type embedded region to the saturation voltage and the saturation current. Figure 20E is a diagram illustrating the effect of the composition of the body region on saturation voltage and saturation current; Figure 2 0F is used to illustrate the effect of the composition of the body region on saturation voltage and saturation current Figure 20G is a diagram illustrating the effect of the distance between the body region and the source lead-out region on the saturation voltage and saturation current; Figure 20H is used to illustrate the distance between the body region and the source lead-out region versus saturation voltage and FIG. 21A is a view showing a modification of the configuration of the N-type embedded region; FIG. 21B is a view showing another modification of the configuration of the N-type embedded region; and FIG. 22 is a view showing the second reference. The surface area of the epitaxial layer of the semiconductor device of the example 143696.doc -35-201025566 is a plan view of the arrangement of the impurity layer of the domain; and FIG. 23A shows the ion mask of the n-type embedded region of the semiconductor device for forming the second reference example. FIG. 23B is an explanatory view showing a process for diffusing impurities using an ion mask for forming an n-type region of the semiconductor device of the second reference example; FIG. 24A is a view showing FIG. 24B is a view showing an example of an ion mask having different aperture ratios; FIG. 24C is a view showing an example of an ion mask having different aperture ratios; and FIG. 24D is a diagram showing an aperture ratio. Fig. 24E is a view showing an example of an ion mask having different aperture ratios; Fig. 24F is a diagram showing an example of an ion mask having different aperture ratios; and Fig. 24G is a diagram showing different aperture ratios. FIG. 24H is a view showing an example of an ion mask having different aperture ratios; FIG. 241 is a diagram showing an example of an ion mask having different aperture ratios; FIG. 25A is a diagram showing an example of an ion mask; Diagram of the impurity concentration of the embedded region and the change of the drain voltage-source and drain current characteristics; Figure 25B shows the drain voltage-source and drain current characteristics occurring by adjusting the impurity concentration of the (4-) type embedded region FIG. 26 is a circuit diagram showing an equivalent circuit of a semiconductor device according to an embodiment of the present invention; FIG. 27 is a plan view showing a first example of an electrode arrangement of a semiconductor device according to an embodiment of the present invention; A plan view of a second example of an electrode arrangement of a semiconductor device according to an embodiment of the present invention; 143696.doc-36-201025566 FIG. 29 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, which corresponds to the HH line and I- of FIGS. 27 and 28. FIG. 30 is a plan view showing a first example of a power LDMOS in which a JFET is integrated in a semiconductor device according to an embodiment of the present invention; and FIG. 31 is a view showing a power of a JFET in a semiconductor device according to an embodiment of the present invention. A plan view of a second example of the LDMOS; Fig. 32A is a circuit diagram showing the configuration of the prior starter circuit; and Fig. 32B is a circuit diagram of a starter circuit using JFET and LDMOS. [Description of main component symbols] 11 P-type semiconductor substrate (layer of the first conductivity type) 12 Molecular layer (layer of the second conductivity type) 13 P-type element isolation region (element separation region of the first conductivity type) 14 汲Pole lead region 15 P-type body region (first region of the first conductivity type) 16 N-type source region (first source region of the second conductivity type) 17 Body lead-out region 18, 24 Field insulating film 19 gate Pole insulating film 20 Gate electrode (first gate electrode) 21 Field plate 22 N-type embedded region (first region of the second conductivity type) 22C Disc-shaped region 143696.doc 201025566 22R 23 31, 32, 33 35 211 36 37 41 4 la~41i 42 51 , 411 52 , 413 53 54 100 ' 200 121 122 131 132 133 140 141 161 , 231 , the source lead-out area of the N-type ring region (the second conductivity type 2 Source region) Electrode pad insulating film gate electrode Second conductivity type second region ion mask mask ion irradiation source LDMOS JFET power LDMOS sensor LDMOS semiconductor device second conductivity type drain region second conductivity type Extending area ring portion opening Partial surface insulating film drain electrode source electrode 322 ' 332 143696.doc -38- 201025566 171 body electrode 321 third gate electrode 331 second gate electrode 411, 412, 413, 414, 415 area 412 internal circuit DL empty Layer IB ion beam ❿ Ids current OP opening PI ' P2 ' P3 position R resistance ST area T start terminal V21 , V22 fixed level Vd, VI, V2, ❿ V3 drain voltage Vg gate voltage Vsat voltage 143696.doc • 39 -

Claims (1)

201025566 七、申請專利範圍： 1. 一種半導體裝置’其特徵在於包括： 第1複合半導體元件以及第2半導體元件； 上述第1複合半導體元件包括： 第1導電型之層（11); 第2導電型之層（12)，其形成於上述第1導電型之層 (11)上； 第1導電型之元件分離區域（13)，其自上述第2導電型 之層（12)之表面區域到達上述第丨導電型之層（η)，規定 作為第2導電型之汲極區域（121)而發揮功能之元件區 域； 第1導電型之第1區域（15)，其形成於上述元件區域； 第2導電型之第1源極區域（16)’其形成於該第1導電型 之第1區域（15); 第1閘極電極（20)，其於上述第1導電型之第1區域Q 5) 内’形成於位於上述汲極區域（121)與上述第丨源極區域 (16)之間的區域之上；以及 第2源極區域（23)，其於上述第2導電型之層（12)内， 形成於在逆偏壓時藉由自上述元件分離區域（丨3)、上述 第1導電型之層（11)、及上述第1導電型之第i區域（15)中 之至少任一者延伸之空乏層而控制與上述汲極區域（121) 之間之通道的位置處；且 上述第2半導體元件包括形成於上述元件區域之第1導 電型之第2區域（15)、形成於該第1導電型之第2區域（15) 143696.doc 201025566 之第2導電型之第3源極區域（1_ 6)、及形成於位於上述汲 極區域（121)與上述第3源極區減（16)之間之第1導電型之 第2區域（I5)上的第2閘極電極（；331)。 2_如請求項1之半導體裝置，其中更包括：形成於上述元 件區域之第1導電型之第3區域（15);形成於該第1導電型 之第3區域（15)之第2導電型之第4源極區域（16);及第3 閘極電極（321)，其形成於位於上述汲極區域（121)與上 述第4源極區域（16)之間之第1導電型之第3區域（15)上， 且連接於上述第2閘極電極（3 31)。 3_如請求項1之半導體裝置，其中上述第丨導電型之第2區 域（15)係連接於上述元件分離區域（13)。 4. 如請求項1之半導體裝置，其栌 上述第1導電型之元件分離區域（13)包括：圈狀部 (131)，其一部分形成有開口部（133)，且規定上述汲極 區域（121);以及部分〇32)，其規定經由上述開口部 (I33)連接於上述汲極區域（121)之第2導電型之延伸區域 (122)； 上述第2導電型之第2源極區域（23)係形成於上述第2導 電型之延伸區域（122)。 5. 如請求項4之半導體裝置，其中上述開口部（133)設置於 上述元件分離區域（13)之上述圈狀部（131)之一部分。 6. 如請求項4之半導體裝置，其中規定上述第2導電型之延 伸區域（122)之部分（132)係形咸為圓弧狀，上述第2導電 型之延伸區域（m)係於上述圈狀部（1S1)與規定上述第2 143696.doc 201025566 導電型之延伸區域（122)之部分（132)之間形成為圓弧 狀。 7. 如請求項4之半導體裝置，其中於上述開口部（133)上形 成絕緣膜（35)，於該閘極絕緣膜（35)上配置閘極電極 (36)，且可設定或調整施加至該閘極電極（36)之閘極電 壓。 8. 如請求項4之半導體裝置，其中於上述開口部（133)内之 上述第1導電型之層（11)與上述第2導電型之層（12)之間， 形成濃度比上述開口部（133)内之上述第2導電型之層 (12)之雜質濃度高之第2導電型之第2區域（3 7)。 9. 如請求項8之半導體裝置，其中上述第2導電型之第2區 域（3 7)係使用開口率可設定之離子遮罩且藉由離子注入 而形成。 10. 如請求項1至3中任一項之半導體裝置，其中上述第2導 電型之第2源極區域（23)係於上述第1導電型之第1區域 (15)與規定上述没極區域（121)之上述元件分離區域（13) 之間’形成於上述汲極區域（121)之表面區域。 11. 如請求項10之半導體裝置，其中上述第2導電型之第2源 極區域（23)係比上述第1導電型之第1區域（15)及上述元 件分離區域（13)形成為更淺。 12. 如請求項10之半導體裝置，其中於上述第2導電型之汲 極£域（121)之中央部形成有淡極引出區域（14)，且上述 第1導電型之第1區域（15)以包圍該汲極引出區域（14)之 方式而形成為圈狀。 143696.doc 201025566 13. 如請求項ι〇之半導體裝置，其中上述第1導電型之層（ll) 之表面區域上形成有雜質濃度可調整之第2導電型之第j 區域（22)。 14. 如請求項13之半導體裝置，其中上述第2導電型之第1區 域（22)包括·形成於沒極區域（121)之正下方之圓盤狀之 區域（22〇;及形成於第1導電型之第i區域（15)之下之環 狀之區域（22R)。 15. 如請求項14之半導體裝置，其中上述圓盤狀之區域（22C) 及上述環狀之區域（22R)分別包括R部、倒r部、及直線 部，上述R部之雜質濃度設為比上述直線部之雜質濃度 高’並且上述直線部之雜質濃度設為比上述倒r部之雜 質濃度高。 16. 如請求項15之半導體裝置，其中上述圓盤狀之區域（22c) 及上述環狀之區域（22R)係使用開口率可設定之離子遮罩 並藉由離子注入而形成，與上述圓盤狀之區域（22c)及環 狀之區域（22R)之R部對應之部分的開口率設為比與直線 部對應之部分的開口率高，並且與直線部對應之部分的 開口率設為比與倒R部對應之部分的開口率高。 17. 如請求項13之半導體裝置，其中上述第2導電型之第工區 域（22)係使用可設定開口率之離子遮罩並藉由離子注入 而形成。 18. 如請求項12之半導體裝置，其中上述第丨導電型之元件 分離區域（13)係以包圍上述第2導電型之第丨區域（22)及 上述第1導電型之第丨區域（15)之方式而形成為圈狀。 143696.doc 201025566 19.如請求項18之半導體裝置，其令上述第2導電型之第2源 極區域(23)係於上述第！導電型之第ι區域(15)與上述元 件分離區域（13)之間形成為圈狀。 20·如明求項18之半導體裝置，其中上述第2導電型之第2源 極區域（23)係於上述第1導電型之第丨區域（15)與上述元 件分離區域（13)之間，於圓周方向之一部分形成有1個或 複數個。 143696.doc201025566 7. Patent application scope: 1. A semiconductor device characterized by comprising: a first composite semiconductor element and a second semiconductor element; wherein the first composite semiconductor element includes: a first conductivity type layer (11); and a second conductivity a layer (12) formed on the first conductivity type layer (11); a first conductivity type element isolation region (13) reaching from a surface region of the second conductivity type layer (12) The layer (n) of the second conductivity type defines an element region functioning as a drain region (121) of the second conductivity type; and the first region (15) of the first conductivity type is formed in the element region; The first source region (16) of the second conductivity type is formed in the first region (15) of the first conductivity type, and the first gate electrode (20) is in the first region of the first conductivity type Q 5) the inner portion is formed over a region between the drain region (121) and the third source region (16); and the second source region (23) is formed by the second conductivity type In the layer (12), formed in the reverse bias region by the separation region (丨3) from the above element a layer of the first conductivity type layer (11) and at least one of the first conductivity type ith region (15) extending to control the position of the channel between the drain region (121) and the drain region And the second semiconductor element includes a second region (15) of the first conductivity type formed in the element region, and a second conductivity type formed in the second region (15) 143696.doc 201025566 of the first conductivity type The third source region (1_6) and the second region (I5) formed on the second region (I5) of the first conductivity type between the drain region (121) and the third source region minus (16) Gate electrode (; 331). The semiconductor device according to claim 1, further comprising: a third region (15) of the first conductivity type formed in the element region; and a second conductivity formed in the third region (15) of the first conductivity type a fourth source region (16) of the type; and a third gate electrode (321) formed in the first conductivity type between the drain region (121) and the fourth source region (16) The third region (15) is connected to the second gate electrode (3 31). The semiconductor device of claim 1, wherein the second region (15) of the second conductivity type is connected to the element isolation region (13). 4. The semiconductor device according to claim 1, wherein the element isolation region (13) of the first conductivity type includes a ring portion (131), a portion of which is formed with an opening portion (133), and the drain region is defined ( And a part 〇 32) defining a second conductivity type extension region (122) connected to the drain region (121) via the opening (I33); and a second source region of the second conductivity type (23) is formed in the extension region (122) of the second conductivity type. 5. The semiconductor device of claim 4, wherein the opening (133) is provided in a portion of the ring portion (131) of the element isolation region (13). 6. The semiconductor device according to claim 4, wherein the portion (132) of the extension region (122) of the second conductivity type is defined as an arc shape, and the extension region (m) of the second conductivity type is The loop portion (1S1) is formed in an arc shape with a portion (132) defining the extension region (122) of the second type 143696.doc 201025566 conductive type. 7. The semiconductor device according to claim 4, wherein an insulating film (35) is formed on the opening portion (133), and a gate electrode (36) is disposed on the gate insulating film (35), and can be set or adjusted. The gate voltage to the gate electrode (36). 8. The semiconductor device according to claim 4, wherein a concentration ratio of the layer between the first conductivity type layer (11) and the second conductivity type layer (12) in the opening portion (133) is formed The second region (37) of the second conductivity type having a higher impurity concentration of the layer (12) of the second conductivity type in (133). 9. The semiconductor device according to claim 8, wherein the second region (37) of the second conductivity type is formed by ion implantation using an ion mask of which an aperture ratio can be set. 10. The semiconductor device according to any one of claims 1 to 3, wherein the second source region (23) of the second conductivity type is in the first region (15) of the first conductivity type and defines the said immersion The element isolation region (13) of the region (121) is formed between the surface regions of the above-described drain region (121). 11. The semiconductor device according to claim 10, wherein the second source region (23) of the second conductivity type is formed more than the first region (15) of the first conductivity type and the element isolation region (13). shallow. 12. The semiconductor device according to claim 10, wherein a pale-electrode lead-out region (14) is formed in a central portion of the second conductivity type (12), and the first region of the first conductivity type (15) ) is formed in a ring shape so as to surround the drain lead-out area (14). The semiconductor device of claim 1, wherein the j-th region (22) of the second conductivity type in which the impurity concentration is adjustable is formed on the surface region of the first conductivity type layer (11). 14. The semiconductor device according to claim 13, wherein the first region (22) of the second conductivity type includes a disk-shaped region (22 〇 formed directly under the electrodeless region (121); and is formed in the A ring-shaped region (22R) under the ith region (15) of the conductive type. The semiconductor device of claim 14, wherein the disk-shaped region (22C) and the annular region (22R) Each of the R portion, the inverted r portion, and the linear portion, the impurity concentration of the R portion is higher than the impurity concentration of the linear portion, and the impurity concentration of the linear portion is higher than the impurity concentration of the inverted r portion. The semiconductor device of claim 15, wherein the disc-shaped region (22c) and the annular region (22R) are formed by using an ion mask of an aperture ratio and formed by ion implantation, and the disc The aperture ratio of the portion corresponding to the R portion of the region (22c) and the annular region (22R) is set to be higher than the aperture ratio of the portion corresponding to the straight portion, and the aperture ratio of the portion corresponding to the straight portion is set to be The aperture ratio of the portion corresponding to the inverted R portion is high. The semiconductor device of item 13, wherein the second conductive type working region (22) is formed by ion implantation using an ion mask capable of setting an aperture ratio. 18. The semiconductor device according to claim 12, wherein the above The element-conducting element isolation region (13) is formed in a ring shape so as to surround the second conductivity type second region (22) and the first conductivity type second region (15). 143696.doc 201025566 The semiconductor device according to claim 18, wherein the second source region (23) of the second conductivity type is between the first conductivity type first region (15) and the element isolation region (13) The semiconductor device according to claim 18, wherein the second source region (23) of the second conductivity type is connected to the second region (15) of the first conductivity type and the element isolation region Between (13), one or a plurality of ones are formed in one of the circumferential directions. 143696.doc
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US9859399B2 (en) 2013-11-05 2018-01-02 Vanguard International Semiconductor Corporation Lateral diffused semiconductor device with ring field plate

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