201023507 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種數位解調變裝置，且特別是有關 於一種數位解調變裝置及數位解調變方法。 【先前技術】 電視訊號傳輸系統在現代人的生活中已廣為使用。傳 統的電視訊號傳輸系統之接收器包含數位解調變裝置以 做為頻率鎖相迴路，用以鎖住輸入訊號之頻率年來， 數位頻率鎖相迴路被用以取代傳統類比的頻率鎖相迴路。 然而，如何在鎖住輸入訊號之頻率的過程中，適時地放大 或縮減鎖相迴路頻寬，以準確地鎖住頻率，是相當困難的 挑戰。如果調整的時機不正確，則整體解調變系統之效能 將大幅降低。並且，如果在經過很長的一段時間，系統都 無法鎖定輸入訊號的頻率，亦須要重置之機制來使系統重 新開啟追蹤鎖定之過程。 因此’如何設計一個新的數位解調變裝置及數位解調 變方法，使輸入頻率能在適時地放大或縮減鎖相迴路頻寬 後，快速地被鎖定，乃為此一業界亟待解決的問題。 【發明内容】 因此本發明的目的就是在提供一種數位解調變裝置， 係設置於接收器内，其中數位解調變裝置係接收輸入訊 號’數位解調變裝置包含：分相器、複數乘法器、頻率°自 201023507 動控制器、限制器、重複追蹤器、相位俛測器、振盪器以 及後乘法器。分相器用以根據輸入訊號產生複數訊號；複 數乘法器用以將複數訊號乘以第一相位訊號及第二相位訊 號以產生第一基頻帶訊號及第二基頻帶訊號；頻率自動控 制器用以接收第一基頻帶訊號以產生第一輸出訊號；限制 器用以根據第一輸出訊號以產生一趨勢訊號；重複追蹤器 用以根據第一輸出訊號產生調整訊號；相位偵測器用以將 趨勢訊號及第二基頻帶訊號相乘以產生相乘訊號及根據調 整訊號對相乘訊號進行調整；振盪器用以根據相位偵測器 之輸出’產生第一及第二相位訊號；以及後乘法器用以將 趨勢訊號分別乘以第一及第二基頻帶訊號，以產生數位解 調變輸出。 本發明的另一目的是在提供一種數位解調變方法，係 用於數位解調變裝置中，以調整鎖相迴路頻寬，數位解調 變方法包含下列步骤：根據輸入訊號產生複數訊號；將複 數訊號乘以第一相位訊號及第二相位訊號以產生第一基頻 帶訊號及第二基頻帶訊號；根據第一基頻帶訊號以產生第 一輸出訊號；根據第一輸出訊號以產生趨勢訊號；將趨勢 訊號及第二基頻帶訊號相乘以產生相乘訊號；產生調整訊 號；接收相乘訊號並根據調整訊號，藉由改變數位解調變 裝置之至少一頻寬變數，調整相乘訊號之相位，以產生第 二輸出訊號；根據第二輸出訊號產生第一及第二相位訊 號；以及將趨勢訊號分別乘以第一及第二基頻帶訊號，以 產生數位解調變輸出。 201023507 本發明之優點在於能夠利用即時地移除頻率及相位之 誤差，以鎖定複數訊號，並能在雜訊過大無法鎖住頻率時， 進行數位解調變裝置的重置’以重新啟動鎖頻過程，進行 快速地鎖頻，而輕易地達到上述之目的。 在參閱圖式及隨後描述之實施方式後，該技術領域具 有通常知識者便可瞭解本發明之目的，以及本發明之技術 手段及實施態樣。 【實施方式】 請參照第1圖，係為本發明之一實施例之接收器i之 方塊圖。接收器1包含調譜器1〇、數位解調變裝置12以及 影像處理器14。調諧器10用以自天線接收無線射頻（radi〇 frequency ; RF)訊號11，並且將無線射頻訊號u轉換為 中頻訊號（intermediate frequency ; IF )、經過帶通渡波並 控制調整中頻訊號之振幅。再經過類比至數位的轉換後， 類比的中頻訊號即轉換為數位訊號13，即數位解調變裝置 12之輸入訊號13。數位解調變裝置12接收輸入訊號13， 並以頻率追蹤機制對輸入訊號13的頻率進行鎖定，以移除 所接受的訊號中，頻率以及相位上的誤差。在鎖定輸入訊 號13的頻率之後’產生基頻訊號15。影像處理器14更進 一步的對基頻訊號15做處理’如等化（equalizati〇n)、解 碼、解交錯（de-interleaving)、解隨機化（de-rand〇mizing)， 以產生影像訊號17至顯示面板上（未繪示）。 8 201023507 第2圖係為本發明之第一實施例中之數位解調變裝置 12之方塊圖。數位解調變裝置12包含：分相器200、複數 乘法器202、頻率自動控制器204、限制器206、重複追蹤 器212、相位偵測器218以及振盪器214。分相器200用以 接收如前所述之輸入訊號13,並進一步將輸入訊號13分成 實部及虛部，以產生複數訊號S201。複數乘法器202實質 上包含一實部乘法器202a及一虛部乘法器202b，以將複數 訊號S201乘以第一相位訊號S203及第二相位訊號S205以 產生第一基頻帶訊號S207及第二基頻帶訊號S209。其中 第一及第二相位訊號S203 、S205間之相位差係為90度。 第一基頻帶訊號S207對應至相乘後之實部，而第二基頻帶 訊號S209對應至相乘後之虛部。 頻率自動控制器204用以接收第一基頻帶訊號S2〇7以 產生第一輸出訊號S211。當第一基頻帶訊號§207與系統 内部之一電壓控制振蘯器（未續示）之輸出電壓間的頻率 誤差愈小，則第一輸出訊號S211的絕對值愈大。而相反地， 虽頻率誤差愈大，則第一輸出訊號S2丨丨的絕對值愈小。當 内建之電壓頻率大於第一基頻帶訊號S2〇7的頻率時，第一 輸出訊號S211的值即為正值，而小於時即為負值。限制器 206接著根據第一輸出訊號S2U以產生趨勢訊號當 第輸出訊號S211係為正值，則趨勢訊號S213係為+ 1， 而當第-輸rfm號S211係為負值或G，_勢訊號S213 係為〜1。 相位伯測益218包含乘法模組2〇8以及相位自動控制 201023507 器210。乘法模組208用以將趨勢訊號S213及該第二基頻 帶訊號S209相乘以產生相乘訊號S215。相位自動控制器 210接收相乘訊號S215及由重複追蹤器212產生之調整訊 號S217 ’以藉由改變相位自動控制器210之至少一鎖相迴 路頻寬變數（迴路增益、Ki、Kp)，調整相乘訊號S215之 相位。 重複追蹤器212偵測頻率自動控制器204之第一輸出 訊號S211，並將第一輸出訊號S2U與複數個臨界值進行比 較以產生調整訊號S217。其中，臨界值係可根據輸入訊號 13而計算出來。舉例來說，於一實施例中，臨界值係根據 輸入訊號13於一現在時間間隔中之一振幅強度之平均絕對 峰值（absolute peak value)決定。於其他實施例中，重複 追蹤器212係偵測第一輸出訊號S211於一預設時間間隔内 之一平均值與臨界值進行比較以產生調整訊號S217。在經 過相位自動控制器210對鎖相迴路頻寬變數之調整後，相 位自動控制器210產生一相乘訊號之調整結果S215’，並輸 出至振盪器214。振盪器214於本實施例中係為係為一數值 控制震盪器，以根據相乘訊號之調整結果S215，產生第一及 第二相位訊號S203、S205 ^ —旦複數訊號S201之頻率被 鎖疋住，第一及第一:基頻帶訊號S 207及S209即透過一後 乘法器216的處理後，輸出至影像處理器14。後乘法器216 將趨勢訊號S213分別乘以第一及第二基頻帶訊號S2〇7及 S209，以產生數位解調變輸出。 第3圖更進一步繪示了本發明之第一實施例，於第2 201023507 圖中所示之相位自動控制器210之方塊圖。相位自動控制 器210主要包含一具有迴路增益之放大器3〇，以及兩個頻 寬變數控制器31 (Ki)及32 (Kp)。於其他實施例中，係 可根據不同之調整需求而設計不一樣的相位自動控制器。 由重複追蹤器212所產生之調整訊號S217，實質上控制了 放大器30以及頻寬變數控制器3卜32，以調整鎖相迴路頻 寬。相位自動控制器21〇更包含了開關33及低通濾波器 34。開關33係在頻寬變數之調整期間斷開，並在調整結束 後，連接至相乘訊號S215e其中，開關33係僅在複數訊號 S20i被鎖定後，經過低通濾波器34接收相乘訊號s2i5, 以產生無雜訊的相乘訊號之調整結果S215，。 為詳細說明由重複追蹤器212提供之頻率鎖定機制， 請參照第4圖’係為本發明—實施例中，帛2圖所緣示之 重複追蹤器212 ’在輸入訊號未被鎖定時，重複追縱器212 產生調整訊號S217以進行追縱之流程圖。於步驟4〇1，重 複追縱器212根據輸人訊號13的平均值計算複數個臨界 值。舉例來說’於本實施例中’係、根據輸入訊號13即時之 現在平均值計算最树界值此』、巾間臨界值以及 最大臨界值thr—Η ^計算之方式可以表示為： thr一L = A* (現在平均值） thr_M = B * (現在平均值） thr—H = C * (現在平均值） 其甲A、B、C係為適當選擇的常數，且A<B<C。 臨界值係用以判斷鎖相迴路頻寬的收敛狀況。頻率自 201023507 動控制器204之第一輸出訊號S2U的絕對值將在頻率誤差 接近0時，變成一個較大的數字。 在步驟402中，係判斷複數訊號S2〇1在一臨界時間間 隔内是否被鎖定住。當複數訊號S2〇1於一臨界時間間隔内 均並未被鎖定，第一輸出訊號S2n將在步驟4〇3中與最小 臨界值thr—L進行比較。當第一輸出訊號S2U小於最小臨 界值thr_L，則重複追蹤器212將於步驟4〇4 _重置數位解 鲁 調變裝置12。而當第一輸出訊號S211大於最小臨界值 thr—L，重複追蹤器212將判斷數位解調變裝置12係在雜訊 相當大的情況下，但是複數訊號S2〇i仍然是可以信賴的， 並於步驟405中進一步判斷複數訊號S2〇1係已被鎖定。 如果尚未超過臨界時間間隔’則於步驟4 〇 6中，將判 斷第一輸出訊號S211是否大於中間臨界值thr_M；。當第一 輸出訊號.S211大於中間臨.界值thr_M時，重複追蹤器212 產生之調整訊號S217將於步驟407a中對頻寬變數進行調 β 整’以在未低於一最小頻寬臨界值的情形下，縮減數位解 調變裝置12之鎖相迴路頻寬，以接近複數訊號S201之頻 率。當第一輸出訊號S211小於中間臨界值thr_M時，重複 追蹤器212產生之調整訊號S217將於步驟407b中對頻寬 變數進行調整，以在未高於一最大頻寬臨界值的情形下， 增加數位解調變裝置12之鎖相迴路頻寬，以接近複數訊號 S201之頻率。最大頻寬臨界值及最小頻寬臨界值為了避免 鎖相迴路頻寬過大或過小而設置。於步驟408中，將判斷 第一輸出訊號S211是否大於最大臨界值thr Η。當第一輸 12 201023507 出訊號S211係大於最大臨界值thr_H，.則重複追蹤器.212 將於步驟409判斷複數訊號S201係已被鎖定。當第一輸出 訊號S211係小於最大臨界值thr_H，則將返回步驟401以 繼續追蹤複數訊號S2〇l之頻率。 4參照第5圖，係為本發明一實施例中，第2圖所緣 不之重複追蹤器212，在複數訊號S201被鎖定後，系統由 於干擾變成不穩定時，重複追蹤器212產生調整訊號S217201023507 IX. Description of the Invention: [Technical Field] The present invention relates to a digital demodulation device, and more particularly to a digital demodulation device and a digital demodulation method. [Prior Art] The television signal transmission system has been widely used in the lives of modern people. The receiver of the conventional television signal transmission system includes a digital demodulation device as a frequency phase-locked loop for locking the frequency of the input signal. The digital frequency phase-locked loop is used to replace the conventional analog frequency-locked loop. However, how to properly amplify or reduce the bandwidth of the phase-locked loop to accurately lock the frequency during the process of locking the frequency of the input signal is a very difficult challenge. If the timing of the adjustment is not correct, the performance of the overall demodulation system will be greatly reduced. Also, if the system cannot lock the frequency of the input signal after a long period of time, a reset mechanism is required to restart the tracking lock. Therefore, 'how to design a new digital demodulation device and digital demodulation method, so that the input frequency can be quickly locked up or down after the frequency of the phase-locked loop is properly locked, which is an urgent problem to be solved in the industry. . SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a digital demodulation device that is disposed in a receiver, wherein the digital demodulation device receives an input signal. The digital demodulation device includes: a phase splitter, a complex multiplication , frequency ° from 201023507 dynamic controller, limiter, repeat tracker, phase detector, oscillator and post multiplier. The phase splitter is configured to generate a complex signal according to the input signal; the complex multiplier is configured to multiply the complex signal by the first phase signal and the second phase signal to generate the first baseband signal and the second baseband signal; and the frequency automatic controller is configured to receive the first a baseband signal for generating a first output signal; a limiter for generating a trend signal according to the first output signal; a repeat tracker for generating an adjustment signal according to the first output signal; and a phase detector for using the trend signal and the second base The frequency band signals are multiplied to generate a multiplied signal and the multiplied signals are adjusted according to the adjustment signal; the oscillator is configured to generate the first and second phase signals according to the output of the phase detector; and the back multiplier is used to separate the trend signals The first and second baseband signals are multiplied to produce a digital demodulation output. Another object of the present invention is to provide a digital demodulation method for use in a digital demodulation device to adjust a phase-locked loop bandwidth. The digital demodulation method includes the following steps: generating a complex signal according to an input signal; Multiplying the complex signal by the first phase signal and the second phase signal to generate a first baseband signal and a second baseband signal; generating a first output signal according to the first baseband signal; generating a trend signal according to the first output signal Multiplying the trend signal and the second baseband signal to generate a multiplied signal; generating an adjustment signal; receiving the multiplied signal and adjusting the multiplied signal by changing at least one bandwidth variable of the digital demodulation device according to the adjustment signal Phase to generate a second output signal; generate first and second phase signals according to the second output signal; and multiply the trend signal by the first and second baseband signals respectively to generate a digital demodulation output. 201023507 The invention has the advantages that the frequency and phase errors can be removed instantaneously to lock the complex signal, and the digital demodulation device can be reset when the noise is too large to lock the frequency to restart the frequency locking. The process, which quickly locks the frequency, easily achieves the above purpose. The object of the present invention, as well as the technical means and embodiments of the present invention, will be apparent to those skilled in the art in the light of the appended claims. [Embodiment] Please refer to Fig. 1, which is a block diagram of a receiver i according to an embodiment of the present invention. The receiver 1 includes a spectrometer 1A, a digital demodulation device 12, and an image processor 14. The tuner 10 is configured to receive a radio frequency (RF) signal 11 from the antenna, and convert the radio frequency signal u into an intermediate frequency (IF), pass the bandpass wave, and control the amplitude of the adjusted intermediate frequency signal. . After analog to digital conversion, the analog IF signal is converted to digital signal 13, which is the input signal 13 of the digital demodulation device 12. The digital demodulation device 12 receives the input signal 13 and locks the frequency of the input signal 13 by a frequency tracking mechanism to remove errors in the received signal, frequency and phase. The baseband signal 15 is generated after the frequency of the input signal 13 is locked. The image processor 14 further processes the fundamental frequency signal 15 as equalization, decoding, de-interleaving, and de-rand 〇 mizing to generate the image signal 17 To the display panel (not shown). 8 201023507 FIG. 2 is a block diagram of the digital demodulation device 12 in the first embodiment of the present invention. The digital demodulation device 12 includes a phase splitter 200, a complex multiplier 202, a frequency automatic controller 204, a limiter 206, a repeat tracker 212, a phase detector 218, and an oscillator 214. The phase splitter 200 is configured to receive the input signal 13 as described above, and further divide the input signal 13 into real and imaginary parts to generate a complex signal S201. The complex multiplier 202 substantially includes a real multiplier 202a and an imaginary multiplier 202b for multiplying the complex signal S201 by the first phase signal S203 and the second phase signal S205 to generate a first baseband signal S207 and a second Baseband signal S209. The phase difference between the first and second phase signals S203 and S205 is 90 degrees. The first baseband signal S207 corresponds to the multiplied real part, and the second baseband signal S209 corresponds to the multiplied imaginary part. The frequency automatic controller 204 is configured to receive the first baseband signal S2〇7 to generate the first output signal S211. When the frequency error between the first baseband signal § 207 and the output voltage of one of the voltage control oscillators (not shown) in the system is smaller, the absolute value of the first output signal S211 is larger. Conversely, the larger the frequency error, the smaller the absolute value of the first output signal S2丨丨. When the built-in voltage frequency is greater than the frequency of the first baseband signal S2〇7, the value of the first output signal S211 is a positive value, and when it is less than, it is a negative value. The limiter 206 then generates a trend signal according to the first output signal S2U. When the output signal S211 is positive, the trend signal S213 is +1, and when the first-transmission rfm number S211 is negative or G, the potential is Signal S213 is ~1. Phase Burson 218 includes a multiplication module 2〇8 and a phase auto-control 201023507 210. The multiplication module 208 is configured to multiply the trend signal S213 and the second baseband signal S209 to generate a multiplication signal S215. The phase automatic controller 210 receives the multiplication signal S215 and the adjustment signal S217' generated by the repeat tracker 212 to adjust the at least one phase-locked loop bandwidth variable (loop gain, Ki, Kp) of the phase automatic controller 210. Multiply the phase of signal S215. The repeat tracker 212 detects the first output signal S211 of the frequency automatic controller 204, and compares the first output signal S2U with a plurality of threshold values to generate an adjustment signal S217. The threshold value can be calculated based on the input signal 13. For example, in one embodiment, the threshold is determined based on an average peak value of the amplitude of one of the input signals 13 in a current time interval. In other embodiments, the repeat tracker 212 detects that the first output signal S211 is compared with a threshold value by one of the preset time intervals to generate the adjustment signal S217. After the phase auto-controller 210 adjusts the phase-locked loop bandwidth variable, the phase auto-controller 210 generates an adjustment result S215' of the multiplied signal and outputs it to the oscillator 214. In this embodiment, the oscillator 214 is a numerically controlled oscillator for generating the first and second phase signals S203 and S205 according to the adjustment result S215 of the multiplied signal. The frequency of the complex signal S201 is locked. The first and first: the baseband signals S 207 and S209 are processed by the post-multiplier 216 and output to the image processor 14. The post multiplier 216 multiplies the trend signal S213 by the first and second baseband signals S2〇7 and S209, respectively, to generate a digital demodulation output. Figure 3 further illustrates a block diagram of the phase auto-controller 210 shown in the second embodiment of the present invention, in the first embodiment of the present invention. The phase auto-controller 210 mainly includes an amplifier 3〇 having a loop gain, and two bandwidth variable controllers 31 (Ki) and 32 (Kp). In other embodiments, different phase automatic controllers can be designed according to different adjustment requirements. The adjustment signal S217 generated by the repeat tracker 212 substantially controls the amplifier 30 and the bandwidth variable controller 3 32 to adjust the phase-locked loop bandwidth. The phase automatic controller 21 further includes a switch 33 and a low pass filter 34. The switch 33 is turned off during the adjustment of the bandwidth variable, and after the adjustment is completed, is connected to the multiplied signal S215e, and the switch 33 receives the multiplied signal s2i5 through the low pass filter 34 only after the complex signal S20i is locked. , to generate an adjustment result S215 of the multiplication signal without noise. To explain in detail the frequency locking mechanism provided by the repeat tracker 212, please refer to FIG. 4, which is the present invention. In the embodiment, the repeat tracker 212' shown in FIG. 2 repeats when the input signal is not locked. The tracker 212 generates a flow chart of the adjustment signal S217 for tracking. In step 4〇1, the repeat tracker 212 calculates a plurality of threshold values based on the average value of the input signal 13. For example, in the present embodiment, the method of calculating the maximum tree boundary value based on the current average value of the input signal 13 and the threshold value and the maximum threshold value thr_Η ^ can be expressed as: thr L = A* (now average) thr_M = B * (now average) thr - H = C * (now average) Its A, B, and C are appropriately selected constants, and A < B < C. The critical value is used to determine the convergence of the phase-locked loop bandwidth. The absolute value of the first output signal S2U of the frequency controller from 201023507 will become a larger number when the frequency error is close to zero. In step 402, it is determined whether the complex signal S2〇1 is locked within a critical time interval. When the complex signal S2〇1 is not locked for a critical time interval, the first output signal S2n will be compared with the minimum threshold thr-L in step 4〇3. When the first output signal S2U is less than the minimum critical value thr_L, the repeat tracker 212 will reset the digital decoding device 12 in step 4〇4_. When the first output signal S211 is greater than the minimum threshold thr_L, the repeat tracker 212 determines that the digital demodulation device 12 is in a relatively large amount of noise, but the complex signal S2〇i is still reliable, and It is further determined in step 405 that the complex signal S2〇1 has been locked. If the critical time interval has not been exceeded, then in step 4 〇 6, it will be determined whether the first output signal S211 is greater than the intermediate threshold thr_M; When the first output signal .S211 is greater than the intermediate threshold value thr_M, the adjustment signal S217 generated by the repeat tracker 212 will adjust the bandwidth variable in step 407a to be less than a minimum bandwidth threshold. In the case, the phase-locked loop bandwidth of the digital demodulation device 12 is reduced to approach the frequency of the complex signal S201. When the first output signal S211 is smaller than the intermediate threshold thr_M, the adjustment signal S217 generated by the repeat tracker 212 will adjust the bandwidth variable in step 407b to increase in a case where the threshold value is not higher than a maximum bandwidth. The phase-locked loop bandwidth of the digital demodulation device 12 is close to the frequency of the complex signal S201. The maximum bandwidth threshold and the minimum bandwidth threshold are set to avoid excessive or too small a phase-locked loop bandwidth. In step 408, it is determined whether the first output signal S211 is greater than the maximum threshold thr Η. When the first input 12 201023507 signal S211 is greater than the maximum threshold thr_H, the repeat tracker .212 will determine in step 409 that the complex signal S201 has been locked. When the first output signal S211 is less than the maximum threshold thr_H, then step 401 is returned to continue tracking the frequency of the complex signal S2〇1. 4 is a repeating tracker 212 in the second embodiment of the present invention. After the complex signal S201 is locked, the repeating tracker 212 generates an adjustment signal when the system becomes unstable due to interference. S217
以進行追蹤之流程圖。如果雜訊在接收器丨中突然產生， 則輸入訊號將被雜訊所影響，而頻率鎖定機制將無法再鎖 住之前已被鎖定的複數訊號S2〇1。因此，重複追蹤器212 必須產生調整訊號S217以儘快重新鎖定複數訊號S2〇1。 在步驟501中，將如前述之步驟撕一般，計算複數個臨 界值。接著於步驟502，係將第一輸出訊號S211與最小臨 界值thr-L進行比較，以判斷第一輸出訊號S211是否小於 = 界值thr〜L。當第一輸出訊號S211小於最小臨界值 thr_L則於步鄉5()3,將檢查鎖相迴路頻寬是否大於最大 頻寬臨界值。如第_輸出訊冑S2U並未小於最小臨界值 ，則將返回步驟50卜當第一輸出訊號S211小於最小 臨界值加』’且鎖相迴路頻寬係小於最大頻寬臨界值時， 調整訊號S217俜於半峨^,士， '、、步驟504產生以調整至少一頻寬變 = = 變裝置12之鎖相迴路頻寬。如果鎖相迴路 ==寬臨界值時，則重複追蹤器212將重置 数位解調變裝置12。 請參照第 亦為本發明一實施例中，第2圖所繪 13 201023507 示之重複追蹤器212，在複數訊號S201被鎖定後，系統由 於干擾變成不穩定時，重複追蹤器212產生調整訊號S2n 以進行追蹤之流程圖。首先’在步驟601中，將仍如前述 之步驟501 —般’計算複數個臨界值。接著於步驟6〇2，係 將第一輸出訊號S211與最大臨界值thr_H進行比較，以判 斷第一輸出訊號S211是否大於最大臨界值thr—η。當第— 輸出訊號S211大於最大臨界值thr_H，則於步驟603，將 檢查鎖相迴路頻寬是否小於最小頻寬臨界值。如第一輸出 Λ號S211並未大於最大臨界值thr_H ’則將返回步驟6〇 1。 冨第一輸出訊號S211大於最大臨界值thr一Η，且鎖相迫路 頻寬係大於最小頻寬臨界值時，調整訊號；5217係於步驟 6〇4產生以調整至少一頻寬變數，以縮減數位解調變裝置 12之鎖相迴路頻寬。如果鎖相迴路頻寬係大於最大頻寬臨 界值時，則重複追蹤器212將不做處理而返回步驟6〇1。 本發明所提供之數位解調變裝置及數位解調變方法， 係可即時地移除頻率及相位之誤差，以鎖定複數訊號 S201。如果因為過多的雜訊而無法對複數訊號s2〇i進行鎖 疋，則重複追蹤器將重置數位解調變裝置以重新啟動新的 追蹤鎖定程序，以儘速地重新鎖定複數訊號S2〇1。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範_，當可作各種之更動_#，因此本發明之保 濩範圍當視後附之申請專利範圍所界定者為準。 201023507 【圖式簡單說明】 優點與實施例 為讓本發明之上述和其他目的、特徵、 能更明顯易懂，所附圖式之詳細說明如下. 第1圖係為本發明之一實施例之接收器之方塊圖· 之方塊圖 第2圖係為本發明之第—實施财之數位解調變裝置A flow chart for tracking. If the noise is suddenly generated in the receiver, the input signal will be affected by the noise, and the frequency lock mechanism will no longer be able to lock the previously locked multi-signal S2〇1. Therefore, the repeat tracker 212 must generate the adjustment signal S217 to relock the complex signal S2〇1 as soon as possible. In step 501, a plurality of critical values are calculated by tearing the steps as described above. Next, in step 502, the first output signal S211 is compared with the minimum critical value thr-L to determine whether the first output signal S211 is less than the = boundary value thr~L. When the first output signal S211 is less than the minimum threshold thr_L, then in step 5()3, it is checked whether the phase-locked loop bandwidth is greater than the maximum bandwidth threshold. If the _output signal S2U is not less than the minimum threshold, then the process returns to step 50. When the first output signal S211 is less than the minimum threshold plus 』' and the phase-locked loop bandwidth is less than the maximum bandwidth threshold, the signal is adjusted. S217 俜 峨 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , If the phase locked loop == wide threshold, the repeat tracker 212 will reset the digital demodulation device 12. Referring to the first embodiment of the present invention, the repeat tracker 212 shown in FIG. 2 is shown in FIG. 2, 201023507. After the complex signal S201 is locked, the system becomes the adjustment signal S2n when the system becomes unstable due to interference. A flow chart for tracking. First, in step 601, a plurality of threshold values are still calculated as in step 501 above. Next, in step 6〇2, the first output signal S211 is compared with the maximum threshold value thr_H to determine whether the first output signal S211 is greater than the maximum threshold value thr-η. When the first output signal S211 is greater than the maximum threshold thr_H, then in step 603, it is checked whether the phase locked loop bandwidth is less than the minimum bandwidth threshold. If the first output nickname S211 is not greater than the maximum threshold value thr_H ', then step 6 〇 1 will be returned. When the first output signal S211 is greater than the maximum threshold value thr, and the phase-locked channel bandwidth is greater than the minimum bandwidth threshold, the signal is adjusted; 5217 is generated in step 6〇4 to adjust at least one bandwidth variable to The phase-locked loop bandwidth of the digital demodulation device 12 is reduced. If the phase-locked loop bandwidth is greater than the maximum bandwidth threshold, the repeat tracker 212 will return to step 6〇1 without processing. The digital demodulation device and the digital demodulation method provided by the present invention can instantaneously remove the error of frequency and phase to lock the complex signal S201. If the complex signal s2〇i cannot be locked due to excessive noise, the repeat tracker will reset the digital demodulation device to restart the new tracking lock program to re-lock the complex signal S2〇1 as quickly as possible. . Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the present invention, and the present invention can be made variously without departing from the spirit and scope of the present invention. The scope of coverage is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent and understood. Block Diagram of Receiver · Block Diagram 2 is the digital demodulation device of the present invention
第3圖係為本發明之第一實施例中之相位自動控制器 之方塊圖 第4圖係為本發明一實施例中，第2圖所緣示之重複 追蹤器在輸入訊號未被鎖定時，重複追蹤器產生調整訊號 以進行追蹤之流程圖； 第5圖係為本發明一實施例中，第2圖所繪示之重複 追縱器’在複數訊號被鎖定後，系統由於干擾變成不穩定 時’重複追蹤器產生調整訊號以進行追蹤之流程圖；以及 第6圖係為本發明一實施例中，第2圖所繪示之重複 追蹤器’在複數訊號被鎖定後，系統由於干擾變成不穩定 時’重複追蹤器產生調整訊號以進行追蹤之流程圖。 【主要元件符號說明】 1 :接收器 10 :調諧器 11 :無線射頻訊號 12:數位解調變裝置 13 :輸入訊號 14 :影像處理器 15 :基頻訊號 17 :影像訊號 15 201023507 200 :分相器 S201 :複數訊號 202 :複數乘法器 202a :實部乘法器 202b :虛部乘法器 S203 :第一相位訊號 204 :頻率自動控制器 S205 :第二相位訊號 206 :限制器 S207 :第一基頻帶訊號 208 :乘法模組 S209 :第二基頻帶訊號 210 :相位自動控制器 S211 :第一輸出訊號 212 :重複追蹤器 S213 :趨勢訊號 214 :振盪器 S215 :相乘訊號 S215’ ：相乘訊號調整結果 216 ： 後乘法器 S217 :調整訊號 218 ： 相位偵測器 30 :放大器 31、 32 :頻寬變數控制器 33 :開關 34 ： 低通滤波器 Ο 163 is a block diagram of a phase automatic controller in a first embodiment of the present invention. FIG. 4 is an embodiment of the present invention, and the repeat tracker shown in FIG. 2 is not locked when the input signal is not locked. The repeating tracker generates a flow chart for adjusting the signal for tracking. FIG. 5 is a repeating tracker of the second embodiment of the present invention. After the complex signal is locked, the system becomes non-interfering due to interference. When it is stable, the repeat tracker generates a flow chart for tracking the tracking; and FIG. 6 is a repeat tracker of the second embodiment of the present invention. After the complex signal is locked, the system is disturbed. When it becomes unstable, the repeat tracker generates a flow chart for adjusting the signal for tracking. [Main component symbol description] 1 : Receiver 10 : Tuner 11 : Radio frequency signal 12 : Digital demodulation device 13 : Input signal 14 : Image processor 15 : Base frequency signal 17 : Video signal 15 201023507 200 : Split phase S201: complex signal 202: complex multiplier 202a: real multiplier 202b: imaginary multiplier S203: first phase signal 204: frequency automatic controller S205: second phase signal 206: limiter S207: first baseband Signal 208: Multiplication module S209: Second baseband signal 210: Phase automatic controller S211: First output signal 212: Repeat tracker S213: Trend signal 214: Oscillator S215: Multiplying signal S215': Multiplying signal adjustment Result 216: Post multiplier S217: adjustment signal 218: phase detector 30: amplifier 31, 32: bandwidth variable controller 33: switch 34: low pass filter Ο 16