201020763 九、發明說明： 【發明所屬之技術領域】 種儲存設備的故 本發明係關於一種故障模擬系統，特別是— 障模擬系統。 【先前技術】 硬碟(Hard DlSk，HD)是電腦系統中最主要的儲存設備，作為 電腦用戶的資料和資訊的載體，硬碟上往往保存有大量重要資 #料。在一般的伺服器十由於飼服器長時間不間斷地運行，以二 來自網路的巨大的數據訪問量，伺服器硬碟幾乎是Μ小時不停地 運轉，承受著巨大的工作量，造成硬碟運行中發生不同程度= 壞。雖然大多數硬碟的平均無故障時間已達3〇〇〇〇〜5〇〇〇〇小時以 上，然而對料知戶，特別是龍用戶而言，—次普通的硬碟 故障便足以造成災難性後果。 -般而言’各電腦製造廠商於電腦組裝完成後，都必須檢測 ❹電腦系統對硬碟存取過程中進行容錯能力的檢測，如壓力測試與 錯誤檢測(例如硬碟掉電、資料線路短路或資料線路斷路等等）。經 由上述的各種容錯能力的檢測，可_在錯誤發生時，電腦系統 疋否可以正常存取硬碟。然而上述容錯能力的檢測往往先挑出具 有各種錯誤的硬碟外，再經由人工一一進行測試’此種方式，除 了特定錯誤之硬料賴料，作#AS財玉方式將具有產生 特定錯誤麵的硬碟，對數以千計之電腦或服務器進行檢測，其 7 201020763 作業方式不僅程序繁複，需耗費大量人力 所完成硬碟的錯誤檢測亦不盡可靠。 ^ &加成本，而 【發明内容】 鑒於以上的問題’本發明提供—種故障模擬 系統於存取儲存設備的過程中 、，藉由待測 產生儲存謂崎應轉賴擬命令而 因此，本發明所揭露之儲存設備 =統與••間’待測系統: 匕3.第-存取介面電性輪於待測系統；第 置 存取介面對應並電性麵接於儲存設備；連接模组電性一 第一在跑入“ 連接模、、且破致動時，選擇性地將 接模擬今1至與之對應的第二存取介面；控制單元承 ❹ 雜第一存取 面與第—存取介面電_接或分離以產生對應故障。 其=述對應故__擬裝置依據接收到的模擬命 ，接触進行設扣產輯應闕擬命令的故障。 ^外’a故障模擬敦置更可包含控制主機，電性祕於控制單 兀工制單几係承接由控制主機傳送過來之模擬命令。 $利系”克可電性轉接於控制主機並發出模擬命令予控 制主機。 201020763 於此，待測系統可電性耦接於控制單元並發出模擬命令。 其中，第一存取介面包括：第一訊號接頭與第一電源接頭， ' 第二存取介面包括：第二訊號接頭與第二電源接頭。連接模組被 ，致動時’選擇性地將第-§〖號接頭與號接頭電性搞接或分 離’或選擇性地將第一電源接頭與第二電源接頭電性叙接或分離。 此外，連接模組將第一訊號接頭與第二訊號接頭分離時，可 將第一ifl號接頭電性連接至第一預定電位。 • 於此’第一預定電位可為第一接地電位、第-低電位或第一 高電位。 另外’第-訊號接頭可包括第-差分接頭，第二訊號接頭可 包括第二差分接頭，第-差分接頭與第二差分接頭對應，在連接 模組將第一讯號接頭與第二訊號接頭分離時，可將第一差分接頭 與第二差分接頭反向對接。 此外，第-訊號接頭可包括第—差分接頭，第二訊號接頭可 ❸包括$二差分接頭，第-差分接頭與第二差分接頭對應，在連接 模組將第-訊號接頭與第二訊號接頭分離時，可將第一差分接頭 ' 與第二差分接頭連接成懸空狀態。 ' 其中，連接模組被致動時，可選擇性將第-電源接頭與第二 電源接頭電性耦接或分離。 於此，連接模組將第-電源接頭與第二電源接頭分離時，可 將第二電源接頭電性連接至一第二預定電位。 9 201020763 ▲最後，第二預定電位可為第二接地電位、第二低電位或第二 南電位。 - 減本發贿提供的之故_織置，可雜轉模擬裝置 '接收模擬命令，產生各種不同對應故障，並由不同故障對待測系 統於存取齡設備的過針進行容魏力檢測。 有關本發_舰與㈣，驗合齡作最佳實補詳細說 明如下。 【實施方式】 請參考「第1圖」所示，其係為依據本發明的一實施例之架 構示意圖。本發明所揭露之一種故障模擬裝置其設置於SATA硬 2間，待測系統存取嶋硬碟，故障模擬裝置適於接收模擬 h而產生SATA硬碟的對應故障。故障模擬裝置⑺包含：第一 ^取介面12、第二存取介面14、連接模組16與控制單元m ❹ 盘第第二存取介面12電性域於待_統3Q。第二存取介面^ ^第一存取介面12對應並電_接於_ _ %。連接模组 έ祕於第—存取介面12與第二存取介面！4之間，連接模 組16被致動時，選擇性地將第一存取 、 庫的篦入 ίφ12電性祕至與之對 應的第-存取介面14。控制單元18承接顯命令， 令致動連接她16選擇性地將第—麵介 、擬命 14電性_或分糾纽職轉。 〜第―存取介面 前述的待測系統係為任何需向儲存設備進行存取作業的系 201020763 統’此待測系統可以是但不限於個人電腦(Pers〇nal C〇mputer， PC)、飼服器、或磁碟陣列(Redundant Array of Independent Disks， 系統，但熟知此項技藝人士應可應用於其他待測系統，是故 不逐列舉。儲存設備一般而言可以是，但不限於具有微控序列 先進技術連接裝置(Serial Advanced Technology Attachment，以下簡 稱SATA硬碟)硬碟、固態硬碟(Solid State Disk，SSD) 〇儲存設備 的傳輸介面可為整合電子式驅動(Integrated Mve Electr(mics，IDE) .介面、SATA 介面、IEEE1394 (Institute of ElectronicaUnd electronic201020763 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a fault simulation system, particularly a barrier simulation system. [Prior Art] Hard DlSk (HD) is the most important storage device in computer systems. As a carrier of data and information for computer users, a large number of important materials are often stored on the hard disk. In the general server ten, because the feeding machine runs continuously for a long time, and the huge data access from the network, the server hard disk runs almost every hour, and suffers a huge workload, resulting in a huge workload. The hard disk runs different degrees = bad. Although the average time between failures of most hard disks has reached 3 〇〇〇〇 to 5 〇〇〇〇 hours, it is enough for the households, especially the dragon users, that the ordinary hard disk failure is enough to cause disaster. Sexual consequences. - Generally speaking, after computer assembly is completed, all computer manufacturers must detect the fault tolerance of the computer system during hard disk access, such as stress testing and error detection (such as hard disk power failure, data line short circuit). Or the data line is broken, etc.). Through the detection of the above various fault tolerance capabilities, the computer system can access the hard disk normally when an error occurs. However, the above-mentioned fault-tolerant detection often picks out the hard disk with various errors, and then tests it manually. This way, in addition to the specific error of the hard material, the #AS 财玉 method will have a specific error. The hard disk is tested on thousands of computers or servers. The 7 201020763 operation mode is not only complicated, but also requires a lot of manpower to complete the error detection of the hard disk. ^ & add cost, and [invention] In view of the above problems, the present invention provides a fault simulation system in the process of accessing the storage device, and the storage of the prediction by the test is expected to be transferred to the intended command. The storage device disclosed in the present invention is a system to be tested: 匕3. The first access interface is electrically connected to the system to be tested; the first access interface is electrically connected to the storage device; The module first selects the second access interface corresponding to the analog 1 to the first access interface when the user enters the "connecting mode" and breaks the actuation; the control unit carries the first access surface Connected or separated from the first access interface to generate a corresponding fault. The = corresponding to the __ device according to the received analog life, contact with the fault that the set production should be simulated. The analog control can also include the control host, the electrical secret is controlled by the single-worker system, and the analog commands transmitted by the control host are received. The system is electrically connected to the control host and sends an analog command to the control. Host. 201020763 Here, the system under test can be electrically coupled to the control unit and issue an analog command. The first access interface includes: a first signal connector and a first power connector, and the second access interface includes: a second signal connector and a second power connector. The connection module is selectively "electrically coupled or separated" from the first connector to the connector or selectively electrically disconnects or separates the first power connector from the second power connector. In addition, when the connection module separates the first signal connector from the second signal connector, the first ifl connector can be electrically connected to the first predetermined potential. • The first predetermined potential may be a first ground potential, a first low potential or a first high potential. In addition, the 'the first signal connector may include a first differential connector, the second signal connector may include a second differential connector, the first differential connector corresponds to the second differential connector, and the first signal connector and the second signal connector are connected to the connector module. When separated, the first differential connector can be reversed to the second differential connector. In addition, the first signal connector may include a first differential connector, the second signal connector may include a second differential connector, and the first differential connector corresponds to the second differential connector, and the first signal connector and the second signal connector are connected to the connector module. When separated, the first differential joint 'and the second differential joint can be connected in a suspended state. Where the connection module is actuated, the first power connector and the second power connector are selectively electrically coupled or separated. Wherein, when the connection module separates the first power connector from the second power connector, the second power connector can be electrically connected to a second predetermined potential. 9 201020763 ▲ Finally, the second predetermined potential may be the second ground potential, the second low potential or the second south potential. - The reason for reducing the cost of bribery _ weaving, can be mixed into the analog device 'receives the analog command, produces a variety of different faults, and the fault detection system is used to detect the force of the device. For the details of this issue, the ship and (4), the best actual compensation for the combined age is as follows. [Embodiment] Please refer to Fig. 1 for a schematic view of a structure according to an embodiment of the present invention. A fault simulation device disclosed in the present invention is disposed between the SATA hard disks 2, the system to be tested accesses the hard disk, and the fault simulation device is adapted to receive the analog h to generate a corresponding fault of the SATA hard disk. The fault simulation device (7) comprises: a first interface 12, a second access interface 14, a connection module 16 and a second access interface 12 of the control unit m, which is electrically connected to the system 3Q. The second access interface ^^ corresponds to the first access interface 12 and is connected to __%. The connection module is secretive to the first access interface 12 and the second access interface! Between 4, when the connection module 16 is actuated, the first access, the bank's intrusion ίφ12 is selectively secreted to the corresponding access-access interface 14. The control unit 18 takes over the command to cause the actuating connection 16 to selectively rotate the first face, the first power, or the new one. ~ The first access interface The system to be tested is any system that needs to access the storage device. 201020763 The system to be tested can be, but is not limited to, a personal computer (Pers〇nal C〇mputer, PC), feeding Redundant Array of Independent Disks (systems, but well-known to those skilled in the art should be applicable to other systems to be tested, so it is not enumerated. Storage devices can generally be, but are not limited to, micro Serial Advanced Technology Attachment (SATA hard disk) hard disk, Solid State Disk (SSD) 〇 storage device transmission interface can be integrated electronic drive (Integrated Mve Electr (mics, IDE).Interface, SATA interface, IEEE1394 (Institute of ElectronicaUnd electronic
engineers ’ IEEE)介面、外接式 SATA(Extemal Serial ATA，eSATAJ 介面、通用序列匯流排(Universal Serial Bus，USB)介面等等。 其中，上述對應故障可為故障模擬裝置1〇依據接收到的模擬 命令後，對連接模組16進行設定以產生對應於模擬命令的故障。 此外，所述之控制單元18，一般而言可以是但不限於微控制 器(Micro Controller Unit，MCU) ’所述之第一存取介面12與第二 參存取介Φ Μ，-般而言可以是但不限於SATA介面。控制單元Μ 於此可具數條賴擬按鍵，频轉模擬按鍵可依據實際需求 產生各種轉槪命令。當轉模擬賴被軸後(亦即被按下 時），即可傳送模擬命令至控制單元ls。第一存取介面U與第二 存取介面14之罐傳輸方式可為有線傳輸或無線傳輸。 於此，除上述由控制單元的故障模擬按鍵，產生對應的模擬 命令。亦可由控制主機產生模擬命令至控制單元、或由待測主機 201020763 —待㈣透過嫩機產生模擬 控制早70 °以下分別就上述架構進行說明。 2·錢柳由控制主機產生顯命令至控鮮元，請參考「第 明所揭1:一：為依據本發明的另-實施例之架構示意圖。本發 路種故障模擬裝置其設置於sata硬碟之間，待測系 硬:取SATA硬碟’故障模擬裝置適於接收 Μ 參 =對應故障。故障模擬裝置10包含:第一存取介面以 =面H'糊組16、晴元咖9。斗 丨2 於待測d麵介* Η盘第 介面12對應並電_接於⑽硬❹。連 输於第—存取細12與第二存取介面14之間，連接模㈣ 被選擇性地將第—存取細軸接至與之對庫的第 1二1=:=主機19電性_制單元18。控制單元 係承接由控制主機19傳送過來之模擬命令 動連接模組16選擇性地將第—存取介面！ ^面二致 性_或分離以產生對應故障。 存取〃面14電 之間的電性耦接可透過 ’上述對應故障可為故障 對連接模組16進行設定 其中控制主機19與控制單元18 RS232埠連結，以傳 模擬裝置1G _接收_模擬命令後， 以產生對應於模擬命令的故障。 此外，所述之控制單元18 -般而言可叹㈣限於微控制 12 201020763 器(Micro Contro〗ier Unit，MCU)。所述之第—存取介面 、 存取介面14，一般而言可以是但不限於从^八 /、 一 第存承^介 ^2與第二存取介面】4之訊號傳輪方式可為有線傳輸或無線傳 輸0 然後，說明由待測主機產生模擬命令至控制單元，請參考「第 3圖」所示，其係為依據本發明的次—實施例之架構示意圓。样 明所揭露之-種轉觀裝置其設置於sata硬碟之間，待嶋 φ統存取SATA硬碟，故障觀裝置適於接收模擬命令而產生嶋 硬碟的對應故障。故障模擬裝錢包含··第—存取介面η、第二 存取介面Μ、連接模組16、控制單元18與控制主機a。其中， 第一存取介面電性搞接於待測系統3〇。第二存取介面！核第 二_ U對應並電性_於SATA硬碟2〇。連接模組Μ電 H第-存取介面12與第二存取介面14之間，_組Μ β二#2，選娜地將第—存取細12 接至與之對應的第 子”面14。待測系統3〇係電性搞接於控制主機並發出模 擬命7予控制主機19，控制主機19電性於控制單元^。和 18 __令’並蝴紐命令致接馳Μ選擇 ::將第存取介面12與第二存取介面Μ電性耗接或分離以產 生對應故障。 -中待測系統30與控制主機19之間的電性輕接、控制主 幾’、控制單疋18之間的電性輕接可透過RS232埠連結，以傳 13 201020763 輸模擬命令。此外，所述之控鮮元18，—般的可以是但 於微控制器(Micro Controller Unit，Mcu)。所述之第一存取义 ' 12與第二存取介面14 ’―般而言可以是但不限於SATA介面:第 .一存取細12與第三存取介面Η之訊號傳輪方式 或無線傳輪。 〇鱗傳輸 —2後’說明由待測主機透過控制主機產生模擬命令至控制單 二=考「第4圖」所示’其係為依據本發明的再—實施例之 架構不_。本發騎揭露之—種故障顯裝置其設置於$概 =:間’待測系統存取SATA硬碟，故障模擬裝置適於接收模 擬中令而產生SATA硬碟的對應故障。故障模雜置W包含、 =取介面12、第二存取介面14、連接模組16與控制單元^。 二中存崎面12電_胁制緒3G。帛二存取介面 與第-麵細12對舰雜_於隨㈣％ 接於第一存取介面_ ，選擇性地將第—存取介面12電_接至與之 發出才取介面14。待測系統30電性麵接於控制單元18並 =親命”控制單元α承接模擬命令，並依據模擬命令致動 2模組16選擇性地將第—存取介面12與第二存取介㈣電性 耦接或分離以產生對應故障。 κ823!1*]Γ'^30 18 ⑽’以傳輸模擬命令。此外，所述之控制單元ΐ8 14 9 —* 201020763 般而:可以疋但不限於微控制器(Micro Controller Unit，MCU)。所 、八★子取"面12與第二存取介面1心一般而言可以是但不限 - 於SATA介面。第—户说人 卜 、 子取"面12與第二存取介面14之訊號傳輸 • ;可為有線傳輪或無線傳輸。 八另外’ 4配合參考「第卜2、3與4圖」所示，其中第一存 取"面12 ’可包括：第—訊號接頭122與第-電源接頭126，第 :存取介面14可包括：第二峨接頭142與第二電源接頭146。 ♦當連接模組I6被致動時，選擇性地將第一訊號接頭⑵與第二訊 :接頭142電f生輕接或分離，或選擇性地將第一電源接頭i26與 第電源接頭146電性輕接或分離。其中，當第一訊號接頭⑵ 與第二訊號_ I42 _時，會產生域基本電位。另外，分別 於第一訊號接頭122與第二域接頭142各加人-麵電單元， 以控制第-訊號接頭122與第二訊號接頭142電性耦接或分離。 於此，繼電單元-般而言可以是但不限於訊號繼電器 ©Relay)。 其中’連接模組16將第一訊號接頭122與第二訊號接頭142 分離時，可將第二訊號接頭142電性連接至第一預定電位。 於此，第一預定電位可為第一接地電位、第一低電位或第一 高電位。其中第-接地電位為訊號基本電位為零，第—低電位為 電位低於訊號基本電位，第-高電位為電位高於訊號基本電位。 另外，第一§fl號接碩122包括第一差分接頭124，第二訊號接 201020763 頭142包括第二差分接頭144。第一差分接頭124係與第二差分接 頭144對應，在連接模組16將第一訊號接頭122與第二訊號接頭 142分離時’係將第一差分接頭124與第二差分接頭144反向對接。 此外，第一訊號接頭122包括第一差分接頭124，第二訊號接 頭142包括第二差分接頭144。第一差分接頭124係與第二差分接 頭144對應，在連接模組16將第一訊號接頭122與第二訊號接頭 142分離時，係將第一差分接頭124與第二差分接頭144接成懸空 φ 狀態。此處的懸空狀態可為第一訊號接頭122與第二訊號接頭142 保留多餘未使用的接腳，將第一差分接頭124連接至與未使用的 接腳連接懸空狀態，或是將第二差分接頭144連接至與未使用的 接腳連接懸空狀態。 於此’使用高頻切換晶片分別電性連接至電性連接第一訊號 接頭122與第二訊號接頭142，以使訊號傳輸率超過3.0Gbps並可 控制第一差分接頭124與第二差分接頭144中訊號接腳之連接關 ❹係。其中’高頻切換晶片一般而言可以是但不限於DS25CP104晶 片、DS25CP102 晶片、或 DS25CP152 晶片。 其中，上述第一差分接頭124與第二差分接頭144,更可分別 包含：正相差分接收訊號接腳(positive differential signal receiver， RxP)、反相差分接收訊號接腳(negative differential signal receiver， RxN)、正相差分輸出訊號接腳(p0Sitive differential signal transfer， TxP)、反相差分輸出訊號接腳(negative differential signal transfer， 201020763 ΤχΝ)與數個接地接腳(GND)。其中，RxP與RxN用以接收差分訊 5虎，TxP與TxN用以輸出差分訊號；第一差分接頭與第二差分接 - 頭對應係為分別將第一差分接頭的RxP、RxN、TxP與TxN對應 . 至第二差分接頭的RxP、RxN、TxP與TxN。上述反向對接係為 將第一差分接頭的TxP、TxN、RxP與RxN對應至第二差分接頭 的 RxP、RxN、TxP 與 ΤχΝ。 另外，連接模組16被致動時，係選擇性地將第一電源接頭126 ❿與第二電源接职46電_接或分離。其中，當第一訊號接頭122 與第二訊號接頭142耦接時，會產生電源基本電位。 於此，使用電源控制單元電性連接於第一電源接頭126與第 二電源接頭146,以電源控制單元控電源接頭126與第二電 源接頭146電性祕或分離。於此，電源控制單元一般而言可以 疋但不限於金氧半電晶體(metal_〇xide semief)nduetOT MOSFET) 〇 ❹ 其中’上述第一電源接頭126與第二電源接頭146，更可分別 包含：3.3伏特電源接腳、5伏特電源接腳、12伏特電源接腳與數 個接地接腳(GND)。 此外’連接核組I6將第一電源接頭m與第二電源接頭146 分離時，係將第二電源接頭146電性連接至第二預定電位。 古於此，第二預定電位可為第二接地電位、第二低電位或第二 馬電位。其中第二接地電位為電源基本電位為零，第二低電位為 17 201020763 電位=:本電位，第二高電位為電位高於電源基本電位。 離，可㈣ 命令使第一存取介面與第二存取介面電性分 ，/據貫際情況由控制主機發出各種不_ 令進細，但並非用以限定本發Γγ原斷電三種不同控制命 首先請=:第5圖」所示’其係為依據本發明實施例之流程圏。 第一存取介面電性_至第二^八擬°ρ令致動連接模組使 可:=::::== 今，祛笙7力卜控制主機再發出模擬命 二二Γ介面與第二存取介面電性分離(步驟_。_， _ 取命令，並偵測是否可正常存取齡設備(步驟 路拾、目丨、1考第6圖」所不，其係為依據本發明實施例之訊號短 ^程圖。在此’對於步驟S300可包括以下實 模擬命令將第二差分接财秘、細、Txp與TXN其中任一 2 接腳電性連接至第—預定電位，並使訊號基本電位等於第一預定 電位(步驟S310)，其中第_預定電位可為第一接地電位、第一低 電位或第一高電位。 · 參考第7圖」所示，其係為依據本發明實施例之訊號短 18 201020763 路檢測流賴。在此，對於步驟纖可包括以下實施步驟。依據 模擬命令將第二差分接頭中、歸、Τχρ與ΤχΝ其中任二個 '接腳電⑨連接至第―預疋電位，並使訊號基本電位等於第一預定 ，電位(步驟S320)，其中第—就顿可為第—接地賴、第一低 電位或第一高電位。 ι考苐8圖」戶斤示’其係為依據本發明實施例之訊號短 路檢測流糊。在此’對於步驟S3⑻可包括以下實施步驟。依據 ❹模擬中令將第二差分接頭中ΜΡ、、丁χρ與ΤχΝ其中任三個 接腳電性連接至第-預定電位，並使訊號基本電位等於第一預定 電位(步驟S330)，其中第-預定電位可為第一接地電位、第一低 電位或第一高電位。 〇月參考第9圖」戶斤示’其係為依據本發明實施例之訊號短 路檢測流程圖。在此，對於步驟S3〇〇可包括以下實施步驟。依據 模擬命令將第二差分接頭+ RXP、⑽、Τχρ與ΤχΝ其中四個接 β卿電性連接至第一預定電位，並使訊號基本電位等於第-預定電 位(步驟S34〇)，其中第-預定電位可為第一接地電位、第一低電 位或第一高電位。 5青參考「第10圖」所示，其係為依據本發明實施例之訊號斷 路"^測流程圖。在此，對於步驟S300可包括以下實施步驟。依據 模擬命令將第一訊號接頭與第二訊號接頭分離(步驟S350)，並使 第一差分接頭與第二差分接頭反向對接(步驟S352)，於此反向對 19 201020763 接係為將第一差分接頭的ΤχΡ、ΤχΝ、RxP與RxN對應至第二差 分接頭的RxP、RxN、TxP與ΤχΝ。 - 請參考「第11圖」所示，其係為依據本發明實施例之訊號斷 • 路檢測流程圖。在此，對於步驟S300可包括以下實施步驟。依據 模擬命令將第一訊號接頭與第二訊號接頭分離(步驟S36〇)，並使 第一差分接頭與第二差分接頭接成懸空狀態(步驟S362)。於此懸 空狀態可為將第一差分接頭的TxP、TxN、與或第二差 ❹分接頭的RxP、RxN、ΤχΡ與TxN巾，任何一個或多個訊號接腳 連接至未使用的多餘接腳以成為懸空狀態。 請參考「第I2圖」所示，其係為依據本發明實施例之電源斷 電檢測流糊。在此，對於麵漏可包括町實施步驟。依據 模擬命令將第-電源接頭與第二電源接頭分離(步驟S3·，並使 喊基本電位等於第二預定輪(步驟现），其中第二預定電位 可為第二接地電位、第二低電位或第二高電位。 參 根據本發明所提供的之故障模擬裝置，可依據故障模擬裝置 接收模擬命令，產生各種不同對應故障，並由不同故障對待測系 統__存設備的過射進行容錯能力檢測。 ^雖然本發日⑽前述之較佳實施纖露如上，然其並非用以限 疋本，明’任何熟習相像技藝者，在不脫離本發明之精神和範圍 内，當可作些許之更動卿飾，因此本㈣之專娜護範圍須視 本說明書所附之申請專利範圍所界定者為準。 20 201020763 【圖式簡單說明】 f1圖係為依據本發明的-實施例之架構示意圖。 第2圖係為依據本發明的另一實施例之架構示意圖。 ，3圖係為依據本發明的次一實施例之架構示意圖。 ，4圖係為依據本發明的再—實施例之架構示意圖。 ，5圖係為依據本發明實施例之流糊。 第6圖係為依據本發明實施例之訊號短路檢測流程圖。 圖係為依據本發明實施例之訊號短路檢測流程圖。 第8圖係為依據本發明實施例之訊號短路檢測流程圖。 第9圖係為依據本發明實施例之訊號短路檢測流程圖。 第10圖係為依據本發明實施例之訊號斷路檢測流程圖。 第11圖係為依據本發明實施例之訊號斷路檢測流程圖。 第12圖係為依據本發明實施例之電源斷電檢測流程圖。 【主要元件符號說明】Engineers 'IEEE' interface, external SATA (External Serial ATA, eSATAJ interface, Universal Serial Bus (USB) interface, etc. Among them, the corresponding fault can be fault simulation device 1 according to the received analog command Then, the connection module 16 is set to generate a fault corresponding to the analog command. In addition, the control unit 18 can be generally, but not limited to, a Micro Controller Unit (MCU) An access interface 12 and a second access interface Φ Μ can be, but are not limited to, a SATA interface. The control unit can have a plurality of analog buttons, and the frequency conversion analog button can be generated according to actual needs. The transfer command can transmit an analog command to the control unit ls after the analog display is turned on (ie, when pressed). The tank transfer mode of the first access interface U and the second access interface 14 can be wired. Transmission or wireless transmission. Here, in addition to the above-mentioned fault simulation button of the control unit, a corresponding analog command is generated. The control host may also generate an analog command to the control unit or the host to be tested 201. 020763 - Waiting for (4) Simulate the above structure by generating the simulated control through the tender machine. The above structure is explained separately. 2· Qian Liu is generated by the control panel to display the command to the control element. Please refer to “The first disclosure: 1: Based on this Schematic diagram of another embodiment of the invention. The fault simulation device of the invention is arranged between sata hard disks, and the system to be tested is hard: the SATA hard disk 'fault simulation device is suitable for receiving Μ parameter=corresponding fault. The device 10 includes: a first access interface to the surface H' paste group 16, and a clear color coffee 9. The bucket 2 corresponds to the d interface of the device to be tested, and corresponds to (10) hard. Between the first access module 12 and the second access interface 14, the connection module (4) is selectively connected to the first access node to the first two 1 === host 19 electrical_ The control unit 18 receives the analog command transmitted from the control host 19 and the connection module 16 selectively separates the first access interface from the first access interface to generate a corresponding fault. The electrical coupling between the electric and the connection module 16 can be set for the fault through the above corresponding fault. The host computer 19 is coupled to the control unit 18 RS232埠 to transmit the analog device 1G_receive_analog command to generate a fault corresponding to the analog command. Furthermore, the control unit 18 is generally sighable (four) limited to the micro control 12 201020763 (Micro Contro ier unit, MCU). The first access interface, access interface 14, generally can be, but not limited to, from ^ 八 /, a first deposit 承 ^ 2 and The two-access interface 4 can be wired or wirelessly transmitted. Then, the analog command is generated by the host to be tested to the control unit. Please refer to FIG. 3, which is based on the present invention. The structure of the sub-embodiment is circular. The device disclosed in the sample is arranged between the sata hard disks, and the NAND hard disk accesses the SATA hard disk, and the fault viewing device is adapted to receive the analog command to generate the corresponding fault of the hard disk. The fault simulation loading includes a first access interface η, a second access interface Μ, a connection module 16, a control unit 18, and a control host a. The first access interface is electrically connected to the system to be tested. Second access interface! The second _U corresponds to the _ SATA hard disk 2 〇. The connection module is connected between the first access interface 12 and the second access interface 14, _ group Μ β2 #2, and selects the first access fine 12 to the corresponding first sub-surface. 14. The system to be tested is electrically connected to the control host and sends an analog command to the control host 19, and the control host 19 is electrically connected to the control unit ^ and 18 __ The first access interface 12 and the second access interface are electrically deducted or separated to generate corresponding faults. - The electrical connection between the system under test 30 and the control host 19 is electrically connected, and the main control is controlled. The electrical connection between the single cymbals 18 can be connected via RS232 , to transmit the analog command of 13 201020763. In addition, the control unit 18 can be a microcontroller (Micro Controller Unit, Mcu). The first access interface '12 and the second access interface 14' may be, but are not limited to, a SATA interface: a first access fine 12 and a third access interface Mode or wireless transmission. 〇 scale transmission - 2 after 'describes from the host to be tested through the control host to generate an analog command to the control unit 2 = test "Figure 4" The architecture of the re-embodiment according to the present invention is not. The fault display device of the present invention is arranged to access the SATA hard disk by the system to be tested, and the fault simulation device is adapted to receive the corresponding fault of the SATA hard disk generated by the simulation. The fault module W includes, = the interface 12, the second access interface 14, the connection module 16 and the control unit ^. Second, the memory of the Sakisaki 12 _ threat system 3G. The second access interface and the first-side thin 12-pair are connected to the first access interface _, and selectively connect the first access interface 12 to the interface 14 to be sent. The system under test 30 is electrically connected to the control unit 18 and the control unit α receives the analog command, and activates the module 16 according to the analog command to selectively connect the first access interface 12 and the second access medium. (4) Electrically coupled or separated to generate a corresponding fault. κ823!1*]Γ'^30 18 (10)' to transmit the analog command. In addition, the control unit ΐ8 14 9 —* 201020763 is similar: but not limited to Microcontroller (Micro Controller Unit, MCU). The first and second access interfaces 1 can be, but are not limited to, the SATA interface. Take the signal transmission of the "face 12 and the second access interface 14; ; can be wired or wireless transmission. Eight additional '4 with reference to the "B, 2, 3 and 4", the first access The "face 12' may include: a first signal connector 122 and a first power connector 126. The first access interface 14 may include a second connector 142 and a second power connector 146. ♦ When the connection module I6 is actuated, the first signal connector (2) and the second connector: 142 are selectively connected or disconnected, or the first power connector i26 and the power connector 146 are selectively connected. Electrically connected or separated. Wherein, when the first signal connector (2) and the second signal _ I42 _, a domain basic potential is generated. In addition, a first-side electrical unit is added to the first signal connector 122 and the second domain connector 142 to electrically couple or separate the first signal connector 122 and the second signal connector 142. Here, the relay unit can be, but is not limited to, a signal relay ©Relay). When the connection module 16 separates the first signal connector 122 from the second signal connector 142, the second signal connector 142 can be electrically connected to the first predetermined potential. Here, the first predetermined potential may be a first ground potential, a first low potential, or a first high potential. The first-ground potential is the fundamental potential of the signal is zero, the first-low potential is the potential lower than the signal basic potential, and the first-high potential is the potential higher than the signal basic potential. In addition, the first §fl connection 122 includes a first differential connector 124, and the second signal connection 201020763 header 142 includes a second differential connector 144. The first differential connector 124 corresponds to the second differential connector 144. When the connection module 16 separates the first signal connector 122 from the second signal connector 142, the first differential connector 124 and the second differential connector 144 are reversely connected. . Additionally, the first signal connector 122 includes a first differential connector 124 and the second signal connector 142 includes a second differential connector 144. The first differential connector 124 is corresponding to the second differential connector 144. When the connection module 16 separates the first signal connector 122 from the second signal connector 142, the first differential connector 124 and the second differential connector 144 are suspended. φ state. The floating state here may leave excess unused pins for the first signal connector 122 and the second signal connector 142, connect the first differential connector 124 to the floating state with the unused pin, or set the second differential. The connector 144 is connected to a suspended state connected to an unused pin. Here, the high frequency switching chip is electrically connected to electrically connect the first signal connector 122 and the second signal connector 142 to make the signal transmission rate exceed 3.0 Gbps and control the first differential connector 124 and the second differential connector 144. The connection between the signal and the pin is related to the system. The 'high frequency switching wafer can be generally, but not limited to, a DS25CP104 wafer, a DS25CP102 wafer, or a DS25CP152 wafer. The first differential connector 124 and the second differential connector 144 may further include: a positive differential signal receiver (RxP) and a negative differential signal receiver (RxN). ), p0Sitive differential signal transfer (TxP), negative differential signal transfer (201020763 ΤχΝ) and several ground pins (GND). Wherein, RxP and RxN are used to receive the differential signal 5, and TxP and TxN are used to output the differential signal; the first differential connector and the second differential connector correspond to the RxP, RxN, TxP and TxN of the first differential connector, respectively. Corresponding to RxP, RxN, TxP and TxN of the second differential connector. The reverse docking is performed by connecting TxP, TxN, RxP, and RxN of the first differential connector to RxP, RxN, TxP, and ΤχΝ of the second differential connector. In addition, when the connection module 16 is actuated, the first power connector 126 选择性 is selectively connected or disconnected from the second power source 46. Wherein, when the first signal connector 122 is coupled to the second signal connector 142, a basic potential of the power source is generated. Herein, the power control unit is electrically connected to the first power connector 126 and the second power connector 146, and the power control unit power supply connector 126 is electrically or separated from the second power connector 146. Herein, the power control unit can be generally, but not limited to, a metal oxide semiconductor (metal_〇xide semief) nduetOT MOSFET) 〇❹ wherein the first power connector 126 and the second power connector 146 are respectively included : 3.3 volt power pin, 5 volt power pin, 12 volt power pin and several ground pins (GND). Further, when the connection core group I6 separates the first power connector m from the second power connector 146, the second power connector 146 is electrically connected to the second predetermined potential. As such, the second predetermined potential may be a second ground potential, a second low potential, or a second horse potential. The second ground potential is the basic potential of the power supply is zero, the second low potential is 17 201020763 potential =: this potential, the second high potential is higher than the basic potential of the power supply. Off, (4) command to make the first access interface and the second access interface electrically divided, or according to the situation, the control host issues various kinds of irregularities, but is not used to limit the difference between the original Γ γ original power-off The control is first shown in the figure: "Fig. 5" is a flow according to an embodiment of the present invention. The first access interface electrical _ to the second ^ 八 ° ρ 令 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致 致The second access interface is electrically separated (step _._, _ fetch command, and detect whether the device can be accessed normally (step picking, directory, 1 test, picture 6), which is based on The signal short-circuit diagram of the embodiment of the present invention. Here, the step S300 may include the following real analog command to electrically connect the second differential junction, the thin, the Txp and the TXN to the first predetermined potential. And causing the signal basic potential to be equal to the first predetermined potential (step S310), wherein the _ predetermined potential may be the first ground potential, the first low potential or the first high potential. · Refer to FIG. 7 In the embodiment of the present invention, the signal detection is short. In this case, the following steps may be included for the step fiber. According to the analog command, the second differential connector, the return, the Τχρ, and the 二个[' Connected to the first pre-potential, and the signal base potential is equal to the first predetermined, potential (step Step S320), wherein the first-to-the-time can be the first-grounding, the first low-potential or the first high-potential. ι考苐8图""" is a signal short-circuit detection flow paste according to an embodiment of the present invention Here, the following implementation steps may be included for step S3 (8). According to the ❹ simulation, the third differential connector is electrically connected to the first predetermined potential, and the signal is basically connected. The potential is equal to the first predetermined potential (step S330), wherein the first-predetermined potential may be the first ground potential, the first low potential or the first high potential. The reference to Figure 9 is shown in Figure 9 The signal short-circuit detection flowchart of the embodiment. Here, the following implementation steps may be included for step S3. The second differential connector + RXP, (10), Τχρ, and ΤχΝ4 are electrically connected to the first step according to the analog command. a predetermined potential, and the signal basic potential is equal to the first predetermined potential (step S34A), wherein the first predetermined potential may be the first ground potential, the first low potential or the first high potential. 5 Green reference "Fig. 10" As shown, it is based on In the embodiment of the present invention, the following steps are performed for the step S300. The first signal connector is separated from the second signal connector according to the analog command (step S350), and the first difference is made. The connector is oppositely connected to the second differential connector (step S352), wherein the reverse pair 19 201020763 is connected to the RxP, RxN, TxP of the second differential connector corresponding to the first differential connector, ΤχΡ, ΤχΝ, RxP and RxN. Please refer to FIG. 11 , which is a flow chart of signal detection according to an embodiment of the present invention. Here, the following implementation steps may be included for step S300. The first signal connector is according to the analog command. The second signal connector is separated from the second signal connector (step S36), and the first differential connector and the second differential connector are connected to a floating state (step S362). The floating state may be to connect the TxP, TxN of the first differential connector, and the RxP, RxN, ΤχΡ and TxN pads of the second differential tap, any one or more signal pins to the unused redundant pins. To become a suspended state. Please refer to the "I2" diagram, which is a power failure detection flow paste according to an embodiment of the present invention. Here, the face leakage may include a town implementation step. Separating the first power connector from the second power connector according to the analog command (step S3·, and causing the shunting basic potential to be equal to the second predetermined wheel (step), wherein the second predetermined potential may be the second ground potential, the second low potential Or the second high potential. The fault simulation device provided according to the present invention can receive various analog faults according to the fault simulation device, and generate fault tolerance for the faults of the faulty system to be tested. Although the above-mentioned preferred embodiment of the present invention is as described above, it is not intended to limit the scope of the invention, and any skilled person can make some changes without departing from the spirit and scope of the invention. The scope of the application of this (4) shall be subject to the definition of the scope of the patent application attached to this specification. 20 201020763 [Simple Description of the Drawing] The f1 diagram is a schematic diagram of the structure according to the embodiment of the present invention. Figure 2 is a schematic diagram of an architecture according to another embodiment of the present invention. Figure 3 is a schematic diagram of a structure according to a second embodiment of the present invention. FIG. 6 is a flowchart of signal short-circuit detection according to an embodiment of the present invention. FIG. 6 is a flowchart of a signal short-circuit detection according to an embodiment of the present invention. Signal short-circuit detection flow chart. Figure 8 is a signal short-circuit detection flow chart according to an embodiment of the present invention. Figure 9 is a signal short-circuit detection flow chart according to an embodiment of the present invention. FIG. 10 is a diagram according to an embodiment of the present invention. FIG. 11 is a flow chart of signal disconnection detection according to an embodiment of the present invention. FIG. 12 is a flow chart of power supply power failure detection according to an embodiment of the present invention.
10 故障模擬裝置 12 第一存取介面 122 第一訊號接頭 124 第一差分接頭 126 第一電源接頭 14 第二存取介面 142 第一 sil號接頭 144 第二差分接頭 21 201020763 146 第二電源接頭 16 連接模組 18 控制單元 19 控制主機 20 SATA硬碟 30 待測糸統 φ 2210 fault simulation device 12 first access interface 122 first signal connector 124 first differential connector 126 first power connector 14 second access interface 142 first sil connector 144 second differential connector 21 201020763 146 second power connector 16 Connection module 18 control unit 19 control host 20 SATA hard disk 30 to be tested φ 22