CN108269606A - A kind of method and system for the storage parameter testing of eMMC chips - Google Patents

A kind of method and system for the storage parameter testing of eMMC chips Download PDF

Info

Publication number
CN108269606A
CN108269606A CN201810021777.4A CN201810021777A CN108269606A CN 108269606 A CN108269606 A CN 108269606A CN 201810021777 A CN201810021777 A CN 201810021777A CN 108269606 A CN108269606 A CN 108269606A
Authority
CN
China
Prior art keywords
emmc
chips
write
host computer
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810021777.4A
Other languages
Chinese (zh)
Other versions
CN108269606B (en
Inventor
冉亮
田维明
张志良
彭林
刘江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Jinshan Medical Technology Research Institute Co Ltd
Original Assignee
Chongqing Jinshan Medical Appliance Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chongqing Jinshan Medical Appliance Co Ltd filed Critical Chongqing Jinshan Medical Appliance Co Ltd
Priority to CN201810021777.4A priority Critical patent/CN108269606B/en
Publication of CN108269606A publication Critical patent/CN108269606A/en
Application granted granted Critical
Publication of CN108269606B publication Critical patent/CN108269606B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5604—Display of error information

Landscapes

  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention discloses a kind of method and system for eMMC storage parameter testings, this method includes：S1, host computer send write-in file and instruction to slave computer；S2, slave computer perform write instruction；S3, host computer carries out eMMC chips life performance and judges, when eMMC chips write full, if eMMC chip residue active volumes reach single detection deposit data volume, and it has been written into eMMC chip datas amount and estimates total capacity more than or equal to producer, then the eMMC chip service life meets the requirements, otherwise it is assumed that the eMMC chip service life is undesirable.When for eMMC chips are used in real-time mass data memory recorder etc product, equipment manufacturer quickly and conveniently can be detected assessment to the performance and used life of eMMC chips in advance by this method and system, the tool that can be tested as product reliability, to ensure reliability and permanent service life that product uses, different capabilities eMMC chips can be assessed.

Description

A kind of method and system for the storage parameter testing of eMMC chips
Technical field
The present invention relates to a kind of storage chip test methods, and parameter testing is stored for eMMC chips more particularly to one kind Method and system.
Background technology
EMMC chips (Embedded Multi Media Card, embedded multi-media card) are by NAND Flash, controller It is formed with standard packaging interface, wherein, NAND Flash provide memory space；Controller realizes the read-write to Flash blocks Control and management, including ECC remove wrong mechanism (Error Correcting Code), block management (Block Management), Wear leveling storage block techniques (Wear Leveling), instruction management management (Command Management), low-power consumption pipe Reason etc.；Standard packaging interface realizes the different read write commands to multi-brand NAND Flash, and unification on the user interface makes User can be absorbed in application and development, the otherness without considering Flash brands and technique.EMMC chips use BGA (Ball Grid Array Package, BGA Package) technology encapsulation, encapsulation is distributed in by array format with round or column solder joint In the following, the integrated level of eMMC chips can be increased.
EMMC chip reals are also the operation to NAND FLASH, and NAND FLASH chips are because the principle features of itself limit System, as the increase of erasing write-in number generates new bad block by continuous, lasting increased bad number of blocks will cause data to be damaged It is bad to lose, the reliability of strong influence storage data and safety.Although the master control driving in the controller of eMMC chips EMMC chip service lifes are extended by balancing the optimization algorithms such as erasing, but with the increase of erasable number, bad block is not Stopping pregnancy is given birth to, and the memory capacity and read or write speed of eMMC chips can constantly decline, the manufactory of particularly current NAND FLASH Quotient is for profit-push, the TLC or even QLC that use cost is cheap, erasable number is low, makes the service life of NAND FLASH Cause anxiety, therefore, eMMC chips in use for some time, can have that the service life expires in advance mostly.In addition, eMMC chips Because cause to replace difficult and trouble, therefore after general eMMC wafer damages, the electronic equipment of insertion is general using BGA package It scraps.
Since the more traditional storage medium of eMMC chips has great operation ease, oneself so becomes digital production in the industry for it The first choice of product, portable data storage and recording equipment.EMMC chip applications are when mobile phone, TV are when digital products, due to this A little products in use for eMMC chips, the frequency of read operation more than write operation height, so eMMC cores The service life of piece is very long, and digital product updates quickly, substantially less than the operating limit service life of eMMC chips in addition；But If by eMMC chips for portable data storage and recording equipment, during recorder particularly for recording mass data in real time, The frequency of write operation is very high, and this kind of product is very high to the complete reliability requirement of data, and a set of equipment makes It is very long with the time limit, can't frequent updating regenerate, eMMC chips because the characteristic of BGA package causes to replace difficult and trouble, because And equipment manufacturer is in deisgn product and test product, it is necessary to carry out performance to the eMMC chips of selection, reading-writing life-span is tested.
At present, it is the data hand that chip production producer provides mostly the assessment that performance and index of aging are carried out to eMMC chips Volume, relevant test verification means only have chip producer itself to know；Also senior Digit or player pass through some poles It limits test software and life test, but because plateform system is carried out for the SSD (main control chip+multi-disc NAND FLASH) of PC platforms Etc. differences, be not suitable for the assessment of eMMC chips also.Therefore, for need real-time mass data storage instrument and equipment and For the manufacturer of data recording equipment, using eMMC chips as during memory module, eMMC chips can face high-frequency and wipe Write operation, producer needs one kind, and quickly, easily method carries out eMMC chips performance and index of aging assessment.
Invention content
The present invention is directed at least solve technical problem in the prior art, especially innovatively propose one kind and be used for EMMC chips store the method and system of parameter testing.
In order to realize the above-mentioned purpose of the present invention, according to the first aspect of the invention, the present invention provides one kind to be used for The method that eMMC chips store parameter testing, including：
S1, the size and content of the write-in file of host computer setting write-in eMMC chips, sends write-in file and instruction extremely Slave computer, described instruction include write instruction；
S2, slave computer perform write instruction content, and write-in file continuously is written to eMMC chips；
Slave computer record write-in number, calculates and uploads the data volume, writing speed and the eMMC cores that have been written into eMMC chips Piece residue active volume is to host computer；
S3, host computer judge eMMC cores according to the data volume and eMMC chip residue active volumes that have been written into eMMC chips It is full whether piece is write, if eMMC chips do not write full, return to step S2；If eMMC chips have write full, progress eMMC chip life performances Judgment method is：
If eMMC chip residues active volume is more than or equal to single detection deposit data volume, and has been written into the number of eMMC chips Total capacity is estimated more than or equal to producer according to amount, then the eMMC chip service life meets the requirements, if eMMC chip residue active volumes are small Deposit data volume is detected in single, then it is assumed that the eMMC chip service life is undesirable, terminates test；
Wherein, the eMMC chips residue active volume be with repeatedly it is erasable constantly generate bad block after, eMMC chips can The capacity being normally written, slave computer are obtained in each write-in；
The data volume for having been written into eMMC chips is equal to the data volume of write-in file and the product of write-in number；
Data volume of the single detection deposit data volume to be stored in eMMC chips after test each during equipment use；
The producer estimates the total amount of data that eMMC chips are written for equipment within service life for total capacity.
When this method is proposed for eMMC chips being used in real-time data memory recorder etc product, instrument factory Family can quickly and conveniently the storage performance to eMMC chips and service life be detected assessment in advance by this method, can As the tool of product reliability test, to ensure reliability and permanent service life that product uses.This method combines The practical application scene of equipment tests the eMMC chip service life, it can be estimated that the read or write speed of different capabilities eMMC chips and Service life has versatility.
In another preferred embodiment of the present invention, the method for the step S3 replaces with：
Host computer has been written into eMMC according to the data volume and eMMC chip residue active volumes for having been written into eMMC chips, judgement Whether the data volume of chip, which reaches producer, is estimated total capacity,
If the data volume for having been written into eMMC chips, which reaches producer, estimates total capacity, and eMMC chip residue active volumes are more than Deposit data volume is detected equal to single, then the eMMC chip service life meets the requirements, otherwise it is assumed that the eMMC chip service life does not meet It is required that；Terminate test；
Total capacity, return to step S2 are estimated if having been written into eMMC chip data amounts and being not up to producer.
When having been written into eMMC chip data amounts and reaching producer and estimate total capacity, so that it may life performance judgement is carried out, without Until writing full eMMC chips, accelerate detection speed.
In the yet another preferred form of the present invention, in the step S3, judge whether eMMC chips write full side Method is：
If eMMC chip residues active volume is less than the data volume of write-in file, then it is assumed that eMMC chips have been write completely, if EMMC chip residues active volume is more than or equal to the data volume of write-in file, it is believed that eMMC chips are not write full.
This method judge eMMC chips whether write it is completely simple, the data volume of file is written as criterion, with reality Application scenarios combine, and the degree of reliability is high.
In the yet another preferred form of the present invention, in the step S3, eMMC chip ultimate lives are further included Appraisal procedure, the eMMC chips ultimate life are：
EMMC chips ultimate life=(data volume/single detection deposit data volume for having been written into eMMC chips) × equipment is deposited Store up period t2；
The equipment stores period t2For detection cycle during equipment use.
It provides eMMC chip ultimate lives and estimates computational methods, it is simple and practicable.
In the yet another preferred form of the present invention, described instruction further includes reading instruction, and institute is performed in slave computer When stating reading command content, the data having been written into eMMC chips are read, calculate reading speed, and upload in eMMC chips The data and reading speed having been written into are to host computer；
Host computer compares the data having been written into eMMC chips and write-in file, if unanimously, eMMC chips In the data having been written into it is correct, if inconsistent, the error in data having been written into eMMC chips.
The reading speed of eMMC chips is obtained, judges the correctness of the data in eMMC chips is written, grasps eMMC chips Various performance parameters, convenient for assessing the overall performance of the eMMC chips.
In the yet another preferred form of the present invention, the data volume of said write file is more than single detection deposit number According to amount.
It is convenient for whether eMMC chips write full judgement, the data volume that eMMC chips are written every time is more, increases eMMC The write-in detection zone of chip interior makes eMMC chip performances detection covering storage region wider.
In the yet another preferred form of the present invention, the data volume of said write file is detected less than or equal to single It is stored in data volume.
Make the erasable number of eMMC chips in testing not less than the erasable number of eMMC chips in duration of service, side It resits an exam the influence for examining erasable number to eMMC chip storage performances, makes test close to true service condition.
In the yet another preferred form of the present invention, in the step S2, with time interval t1In eMMC chips Middle write-in file, the time interval t1It is set by host computer.
Analog machine is detected for interval and is stored in data to eMMC chips in actual use, makes test result more accurate Really.
According to the second aspect of the invention, a kind of eMMC chip parameters test system is provided, which is characterized in that including Host computer and slave computer；
The host computer includes host computer processor, display, input unit and host computer network interface and/or upper Machine USB interface；
The display input terminal shows that output terminal is connect with host computer processor, at input unit output terminal and host computer The connection of device control signal is managed, host computer network interface first end is connect with host computer processor network input terminal, host computer USB Interface first end is connect with host computer processor USB input；
And/or the slave computer includes slave computer processor, eMMC chip modules and Network Interface Module and/or USB Interface module；
The Network Interface Module includes slave computer network interface, slave computer network interface first end and slave computer processor Network input connects, and slave computer network interface second end is connect with host computer network interface second end；
The usb interface module includes slave computer USB interface, slave computer USB interface first end and slave computer processor USB Input terminal connects, slave computer USB interface second end and host computer USB interface second end；
The eMMC chip modules include eMMC chips and the pedestal for loading eMMC chips；Have on the pedestal Have a contact being connect with each pins contact of eMMC chips, each pin of pedestal respectively with the eMMC chip testings end of slave computer processor Connection；
The host computer and slave computer carry out eMMC chips storage parameter according to the method any in claim 1-8 and survey Examination.
When for eMMC chips are used in real-time mass data memory recorder etc product, equipment manufacturer can be with Assessment is quickly and conveniently detected to the performance and used life of eMMC chips by this system in advance, it can as product By the tool of property test, to ensure reliability and permanent service life that product uses.The reality of the system bonding apparatus Application scenarios test the eMMC chip service life, it can be estimated that the read or write speed and service life of different capabilities eMMC chips, With versatility.Host computer and slave computer are carried out data transmission and are communicated by network interface or USB interface, high speed, safety, host computer Can remote control slave computer, it is without geographical constraints.EMMC chips reading speed, writing speed, longevity can be realized by display device The visualization of the test results such as life by input unit, can set write-in file size, content and other parameters, can be with The control command of input test personnel.Improve man-machine interaction.
In the yet another preferred form of the present invention, the slave computer further includes power module or by key control mould Block,
The power module outlet is connect with slave computer processor power supply input terminal；The key control module output terminal It is connect with slave computer processor key-press input end.
Power supply is provided for slave computer and can realize that booting to slave computer, reset, function are cut by key control module The operations such as change.
Description of the drawings
Fig. 1 is the present invention for the flow diagram in a specific embodiment of the method for eMMC chip parameters test；
Fig. 2 be eMMC chip parameters of the present invention test system a specific embodiment in slave computer hardware block diagram；
Fig. 3 be eMMC chip parameters of the present invention test system a specific embodiment in host computer functional block diagram.
Specific embodiment
The embodiment of the present invention is described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the present invention, it is to be understood that term " longitudinal direction ", " transverse direction ", " on ", " under ", "front", "rear", The orientation or position relationship of the instructions such as "left", "right", " vertical ", " level ", " top ", " bottom " " interior ", " outer " is based on attached drawing institutes The orientation or position relationship shown is for only for ease of the description present invention and simplifies description rather than instruction or imply signified dress It puts or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that limit of the invention System.
In the description of the present invention, unless otherwise prescribed and limit, it should be noted that term " installation ", " connected ", " connection " should be interpreted broadly, for example, it may be the connection inside mechanical connection or electrical connection or two elements, it can To be to be connected directly, can also be indirectly connected by intermediary, it for the ordinary skill in the art, can basis Concrete condition understands the concrete meaning of above-mentioned term.
Fig. 1 show the flow in a kind of a kind of embodiment of method for the test of eMMC chip parameters of the present invention Figure, in the present embodiment, this method includes：
S1, the size and content of the write-in file of host computer setting write-in eMMC chips, sends write-in file and instruction extremely Slave computer, instruction include write instruction；
S2, slave computer perform write instruction content, and write-in file continuously is written to eMMC chips；
Slave computer record write-in number, calculates and uploads the data volume, writing speed and the eMMC cores that have been written into eMMC chips Piece residue active volume is to host computer；
S3, host computer judge eMMC chips according to eMMC chip datas amount and eMMC chip residue active volumes is had been written into Whether write completely, if eMMC chips do not write full, return to step S2；If eMMC chips have been write completely, carry out eMMC chip life performances and sentence Disconnected method is：
If eMMC chip residues active volume is more than or equal to single detection deposit data volume, and has been written into the number of eMMC chips Total capacity is estimated more than or equal to producer according to amount, then the eMMC chip service life meets the requirements, if eMMC chip residue active volumes are small Deposit data volume is detected in single, then it is assumed that the eMMC chip service life is undesirable, terminates test；
Wherein, eMMC chips residue active volume be with repeatedly it is erasable constantly generate bad block after, eMMC chips can be normal The capacity of write-in, slave computer are obtained in each write-in；
The data volume for having been written into eMMC chips is equal to the data volume of write-in file and the product of write-in number；
Data volume of the single detection deposit data volume to be stored in eMMC chips after test each during equipment use；Producer Estimate the total amount of data that eMMC chips are written for equipment within service life for total capacity.
In the present embodiment, it is realized by slave computer and the hardware of eMMC chips is connected and tested, host computer is main It is that control slave computer carries out corresponding test operation, passes through network (such as ICP/IP protocol) or USB connection sum numbers between the two According to transmission.Document form corresponding with the detection data of equipment in actual use can be selected in the form or size that file is written And size, such as EXCEL file or TXT files, it is preferred that single or multiple test datas in being actually used using equipment File is as write-in file.Instruction includes write instruction, reads instruction.Single detection deposit data volume can be that equipment uses process In repeatedly test after deposit eMMC chips data volume average value or maximum value.Producer, which estimates total capacity, to exist more than equipment The total amount of data of write-in eMMC chips in service life.
In the present embodiment, writing speed for slave computer at interval of a period of time, obtain write-in data data volume, ask It is averaged, obtains writing speed.If write-in file write-in eMMC chips are expended the time by slave computer record every time, ask for being written The data volume of file and time-consuming ratio, that is, obtain writing speed.When eMMC chips are written in slave computer every time, need by The data erasing of Nand Flash memory storages in eMMC chips is clean, and obtains eMMC chip residue active volumes, is wiping In the process, bad block can be generated inside Nand Flash, therefore, as erasing times are more and more, bad number of blocks will be increasingly More, eMMC chip residues active volume (i.e. the capacity that can be normally written inside Nand Flash) will be less and less, therefore works as When eMMC chip residues active volume is less than write-in file data amount, it is believed that the eMMC chips have been write full.Single detection deposit number According to amount as eMMC chip service life whether qualified threshold value is judged, combined with actually using situation, increase the reliable of this method Property.The method for obtaining eMMC chip residue active volumes is by the way that the general residue active volume function that reads of eMMC chips is called to obtain .
In the preferred embodiment of the present invention, the method for step S3 replaces with：
Host computer has been written into eMMC according to the data volume and eMMC chip residue active volumes for having been written into eMMC chips, judgement Whether chip data amount, which reaches producer, is estimated total capacity,
If the data volume for having been written into eMMC chips, which reaches producer, estimates total capacity, and eMMC chip residue active volumes are more than Deposit data volume is detected equal to single, then the eMMC chip service life meets the requirements, otherwise it is assumed that the eMMC chip service life does not meet It is required that；Terminate test；
Total capacity, return to step S2 are estimated if having been written into eMMC chip data amounts and being not up to producer.
In the present embodiment, without wait until eMMC chips write it is full, as long as upper computer detection is to having been written into eMMC chip-counts When reaching producer according to amount and estimating total capacity, so that it may carry out life performance judgement.Host computer includes comparator, a first memory And second memory, storage producer estimates total capacity in first memory, can be stored in before the test begins, memory output terminal with Comparator first input end connects, and the data for having been written into eMMC chips of newest slave computer feedback are stored in second memory Amount, second memory output terminal connect with the second input terminal of comparator, host computer according to the output result of comparator output terminal into Row judges to have been written into eMMC chip datas amount and whether reached producer to estimate total capacity, when comparator output high level is thought to have write Enter eMMC chip data amounts and be not up to producer to estimate total capacity, when comparator output low level thinks to have been written into eMMC chip datas Amount has reached producer and has estimated total capacity.Single detection deposit data volume as judge the eMMC chip service life whether qualification threshold Value is combined with actual use situation, increases the reliability of this method.Due to increasing with the erasable number of eMMC chips, eMMC Chip residue active volume is less and less, and total capacity, eMMC chips are estimated when the data volume for having been written into eMMC chips reaches producer Remaining active volume is less than single detection deposit data volume, and eMMC chips can use surplus deficiency, and risk is larger, it is believed that eMMC chips Service life is unqualified.
In the preferred embodiment of the present invention, in step s3, judge whether eMMC chips write full method and be：
If eMMC chip residues active volume is less than the data volume of write-in file, then it is assumed that eMMC chips have been write completely, if EMMC chip residues active volume is more than or equal to the data volume of write-in file, it is believed that eMMC chips are not write full.
In the present embodiment, eMMC chips write full expression in new write-in, wipe the Nand Flash in eMMC chips After storage content, slave computer obtains the data volume that the capacity that can be normally written inside Nand Flash has been less than write-in file, nothing Method is completely written to write-in file again, then it is assumed that it has write completely, it is on the contrary, it is believed that not write full.
In the preferred embodiment of the present invention, in step s3, eMMC chips ultimate life assessment step is further included Suddenly, eMMC chips ultimate life is：
EMMC chips ultimate life=(data volume/single detection deposit data volume for having been written into eMMC chips) × equipment is deposited Store up period t2；
Equipment stores period t2For detection cycle during equipment use.
In the present embodiment, eMMC chips ultimate life is after the eMMC chips are embedded in the equipment such as recorder, without it Under his external interference, only eMMC chips self performance determine equipment service life.
In the preferred embodiment of the present invention, instruction further includes reading instruction, and the reading is performed in slave computer During command content, the data having been written into eMMC chips are read, calculate reading speed, and upload having been written into eMMC chips Data and reading speed to host computer；
Host computer compares the data having been written into eMMC chips and write-in file, if unanimously, eMMC chips In the data having been written into it is correct, if inconsistent, the error in data having been written into eMMC chips.
In the present embodiment, reading speed takes out the reading for the data having been written into for slave computer record from eMMC chips It takes, calculates the data volume of the data having been written into eMMC chips, and by the data of the data having been written into eMMC chips Amount is with reading time-consuming ratio as reading speed.Host computer carries out the data having been written into eMMC chips and write-in file Byte-by-byte comparison, if each byte is consistent, then it is assumed that the data having been written into eMMC chips are correct, if inconsistent, The error in data having been written into eMMC chips.
In the preferred embodiment of the present invention, the data volume that file is written is more than single detection deposit data volume.
In the present embodiment, the size that file is written can be multiple combinations that repeated detection is stored in data volume.
In the preferred embodiment of the present invention, the data volume that file is written is less than single detection deposit data volume.
In the present embodiment, the size that file is written can be the average value or minimum that repeated detection is stored in data volume Value.
In the preferred embodiment of the present invention, in step s 2, with time interval t1It is written in eMMC chips File, time interval t1It is set by host computer.
In the present embodiment, time interval t1It should be less than being equal to equipment storage period t2.Time interval t1It can include at least Slave computer write-in write-in file takes, and slave computer record write-in number, calculating have been written into the data volume of eMMC chips, obtain eMMC The processing of chip residue active volume takes and host computer carries out eMMC chips life performance and judges to take.
In a kind of a kind of embodiment of present invention eMMC chips storage parameter test system, system include host computer and Slave computer；
Host computer includes host computer processor, display, input unit and host computer network interface and/or host computer USB interface；
Display input terminal shows that output terminal is connect with host computer processor, input unit output terminal and host computer processor Control signal connects, and host computer network interface first end is connect with host computer processor network input terminal, host computer USB interface First end is connect with host computer processor USB input；
And/or slave computer includes slave computer processor, eMMC chip modules and Network Interface Module and/or USB interface Module；
Network Interface Module includes slave computer network interface, slave computer network interface first end and slave computer processor network Input terminal connects, and slave computer network interface second end is connect with host computer network interface second end；
Usb interface module includes slave computer USB interface, and slave computer USB interface first end is inputted with slave computer processor USB End connection, slave computer USB interface second end and host computer USB interface second end；
EMMC chip modules include eMMC chips and the pedestal for loading eMMC chips；Have on pedestal and eMMC The contact of each pins contact connection of chip, each pin of pedestal are connect respectively with the eMMC chip testings end of slave computer processor；
Host computer and slave computer carry out the storage parameter testing of eMMC chips according to any of the above-described method.
Fig. 2 show the hardware block diagram of slave computer in present embodiment, and Fig. 3 show the work(of host computer in present embodiment It can block diagram.
In the present embodiment, industrial personal computer or PC computers can be selected in host computer, and host computer processor can be computer PC master Plate.The major function that host computer is realized has：It obtains and shows the connection status with slave computer；The data of eMMC chips to be written, File is written, size, content, time-write interval t1Setting；Host computer data content is transferred to slave computer to carry out in fact When show, if the active volume of eMMC chips is shown, have been written into eMMC chip data amounts and show that reading speed shows and writes Enter speed to show；Life capability setting to be tested；Write-in or the control for reading process including starting, suspending and stop, being read Take that can individually be tested with write operation also can combined test；And the display of current task state.Display device can be LED Display screen or computer monitor, input unit can be touch screen or keyboard.
In the present embodiment, MCU can be selected in slave computer processor, including main controller and RAM etc., is responsible for entire the next Machine is controlled, the read-write operation of operation and eMMC chips；EMMC chip modules, the bottom being connect including mainboard with eMMC chips Seat and eMMC chips realize the replacement and connection of different capabilities eMMC chips.By USB cable or cable realize host computer and ICP/IP protocol can be selected in the USB connection communications of slave computer or network communication, network communication.
In the preferred embodiment of the present invention, slave computer further includes power module or key control module,
Power module outlet is connect with slave computer processor power supply input terminal；Key control module output terminal and slave computer Processor key-press input end connects.
In the present embodiment, switch power module can be selected in power module, and power supply is provided for entire circuit；Pass through button Control module realizes the operations such as booting, reset, function switch to lower computer system.
In the description of this specification, reference term " one embodiment ", " example ", " is specifically shown " some embodiments " The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description Point is contained at least one embodiment of the present invention or example.In the present specification, schematic expression of the above terms are not Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any One or more embodiments or example in combine in an appropriate manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not In the case of being detached from the principle of the present invention and objective a variety of change, modification, replacement and modification can be carried out to these embodiments, this The range of invention is limited by claim and its equivalent.

Claims (10)

  1. A kind of 1. method for eMMC storage parameter testings, which is characterized in that including：
    S1, the size and content of the write-in file of host computer setting write-in eMMC chips, sends write-in file and instruction to bottom Machine, described instruction include write instruction；
    S2, slave computer perform write instruction content, and write-in file continuously is written to eMMC chips；Slave computer record write-in number, It calculates and uploads and have been written into data volume, writing speed and the eMMC chip residue active volumes of eMMC chips to host computer；
    S3, host computer judge that eMMC chips are according to the data volume and eMMC chip residue active volumes that have been written into eMMC chips It is no to write completely, if eMMC chips do not write full, return to step S2；If eMMC chips have write full, progress eMMC chips life performance judgement Method is：
    If eMMC chip residues active volume is more than or equal to single detection deposit data volume, and has been written into the data volume of eMMC chips Total capacity is estimated more than or equal to producer, then the eMMC chip service life meets the requirements, if eMMC chip residues active volume is less than list Secondary detection deposit data volume, then it is assumed that the eMMC chip service life is undesirable, terminates test；
    Wherein, the eMMC chips residue active volume be with repeatedly it is erasable constantly generate bad block after, eMMC chips can be normal The capacity of write-in, slave computer are obtained in each write-in；
    The data volume for having been written into eMMC chips is equal to the data volume of write-in file and the product of write-in number；
    Data volume of the single detection deposit data volume to be stored in eMMC chips after test each during equipment use；
    The producer estimates the total amount of data that eMMC chips are written for equipment within service life for total capacity.
  2. 2. as described in claim 1 for the method for eMMC storage parameter testings, which is characterized in that the method for the step S3 It replaces with：
    Host computer has been written into eMMC chips according to the data volume and eMMC chip residue active volumes for having been written into eMMC chips, judgement Data volume whether reach producer and estimate total capacity,
    If the data volume for having been written into eMMC chips, which reaches producer, estimates total capacity, and eMMC chip residue active volumes are more than or equal to Single detection deposit data volume, then the eMMC chip service life meets the requirements, otherwise it is assumed that the eMMC chip service life is undesirable； Terminate test；
    Total capacity, return to step S2 are estimated if having been written into eMMC chip data amounts and being not up to producer.
  3. 3. as described in claim 1 for the method for eMMC storage parameter testings, which is characterized in that in the step S3, Judge whether eMMC chips write full method and be：
    If eMMC chip residues active volume is less than the data volume of write-in file, then it is assumed that eMMC chips have been write completely, if eMMC cores Piece residue active volume is more than or equal to the data volume of write-in file, it is believed that eMMC chips are not write full.
  4. 4. as claimed in claim 1 or 2 for the method for eMMC storage parameter testings, which is characterized in that in the step S3 In, eMMC chip ultimate life appraisal procedures are further included, the eMMC chips ultimate life is：
    EMMC chips ultimate life=(data volume/single detection deposit data volume for having been written into eMMC chips) × equipment storage week Phase t2；
    The equipment stores period t2For detection cycle during equipment use.
  5. 5. as claimed in claim 1 or 2 for the method for eMMC storage parameter testings, which is characterized in that described instruction is also wrapped Reading instruction is included, when slave computer performs the reading command content, the data having been written into eMMC chips is read, calculates and read Speed is taken, and uploads the data having been written into eMMC chips and reading speed to host computer；
    Host computer compares the data having been written into eMMC chips and write-in file, if unanimously, in eMMC chips The data having been written into are correct, if inconsistent, the error in data having been written into eMMC chips.
  6. 6. as claimed in claim 1 or 2 for the method for eMMC storage parameter testings, which is characterized in that said write file Data volume be more than single detection deposit data volume.
  7. 7. as claimed in claim 2 for the method for eMMC storage parameter testings, which is characterized in that the number of said write file It is less than or equal to single detection deposit data volume according to amount.
  8. 8. as claimed in claim 1 or 2 for the method for eMMC storage parameter testings, which is characterized in that in the step S2 In, with time interval t1File, the time interval t are written in eMMC chips1It is set by host computer.
  9. 9. a kind of system that any the method carries out eMMC storage parameter testings in 1-8 based on claim, which is characterized in that Including host computer and slave computer；
    The host computer includes host computer processor, display, input unit and host computer network interface and/or host computer USB interface；
    The display input terminal shows that output terminal is connect with host computer processor, input unit output terminal and host computer processor Control signal connects, and host computer network interface first end is connect with host computer processor network input terminal, host computer USB interface First end is connect with host computer processor USB input；
    And/or the slave computer includes slave computer processor, eMMC chip modules and Network Interface Module and/or USB interface Module；
    The Network Interface Module includes slave computer network interface, slave computer network interface first end and slave computer processor network Input terminal connects, and slave computer network interface second end is connect with host computer network interface second end；
    The usb interface module includes slave computer USB interface, and slave computer USB interface first end is inputted with slave computer processor USB End connection, slave computer USB interface second end and host computer USB interface second end；
    The eMMC chip modules include eMMC chips and the pedestal for loading eMMC chips；On the pedestal have with The contact of each pins contact connection of eMMC chips, each pin of pedestal connect respectively with the eMMC chip testings end of slave computer processor It connects；
    The host computer and slave computer carry out the storage parameter testing of eMMC chips according to the method any in claim 1-8.
  10. 10. eMMC as claimed in claim 9 stores parameter test system, which is characterized in that the slave computer further includes power supply Module or key control module,
    The power module outlet is connect with slave computer processor power supply input terminal；The key control module output terminal is under The connection of position machine processor key-press input end.
CN201810021777.4A 2018-01-10 2018-01-10 Method and system for testing storage parameters of eMMC chip Active CN108269606B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810021777.4A CN108269606B (en) 2018-01-10 2018-01-10 Method and system for testing storage parameters of eMMC chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810021777.4A CN108269606B (en) 2018-01-10 2018-01-10 Method and system for testing storage parameters of eMMC chip

Publications (2)

Publication Number Publication Date
CN108269606A true CN108269606A (en) 2018-07-10
CN108269606B CN108269606B (en) 2020-07-14

Family

ID=62773366

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810021777.4A Active CN108269606B (en) 2018-01-10 2018-01-10 Method and system for testing storage parameters of eMMC chip

Country Status (1)

Country Link
CN (1) CN108269606B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273045A (en) * 2018-09-21 2019-01-25 郑州云海信息技术有限公司 Store equipment on-line detection method, device, equipment and readable storage medium storing program for executing
CN111142889A (en) * 2019-12-30 2020-05-12 深圳佰维存储科技股份有限公司 eMMC automatic volume production method, device, storage medium and electronic equipment
CN112214339A (en) * 2020-09-03 2021-01-12 中国电力科学研究院有限公司 Method and system for testing service life of chip
CN113741820A (en) * 2021-09-18 2021-12-03 青岛海信传媒网络技术有限公司 Method for refreshing data from memory to eMMC memory and display equipment
CN117423377A (en) * 2023-12-18 2024-01-19 合肥康芯威存储技术有限公司 System and method for testing performance of memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677203B1 (en) * 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
CN105097050A (en) * 2015-08-24 2015-11-25 宁波三星智能电气有限公司 Memory service life test algorithm
CN106683709A (en) * 2016-12-28 2017-05-17 西北工业大学 Method for evaluating NOR and NAND flash memory performance
CN106935273A (en) * 2015-12-30 2017-07-07 北京京存技术有限公司 EMMC test systems and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677203B1 (en) * 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
CN105097050A (en) * 2015-08-24 2015-11-25 宁波三星智能电气有限公司 Memory service life test algorithm
CN106935273A (en) * 2015-12-30 2017-07-07 北京京存技术有限公司 EMMC test systems and method
CN106683709A (en) * 2016-12-28 2017-05-17 西北工业大学 Method for evaluating NOR and NAND flash memory performance

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273045A (en) * 2018-09-21 2019-01-25 郑州云海信息技术有限公司 Store equipment on-line detection method, device, equipment and readable storage medium storing program for executing
CN111142889A (en) * 2019-12-30 2020-05-12 深圳佰维存储科技股份有限公司 eMMC automatic volume production method, device, storage medium and electronic equipment
CN111142889B (en) * 2019-12-30 2023-03-14 深圳佰维存储科技股份有限公司 eMMC automatic volume production method, device, storage medium and electronic equipment
CN112214339A (en) * 2020-09-03 2021-01-12 中国电力科学研究院有限公司 Method and system for testing service life of chip
CN113741820A (en) * 2021-09-18 2021-12-03 青岛海信传媒网络技术有限公司 Method for refreshing data from memory to eMMC memory and display equipment
CN113741820B (en) * 2021-09-18 2023-10-03 青岛海信传媒网络技术有限公司 Method for refreshing data from memory to eMMC memory and display device
CN117423377A (en) * 2023-12-18 2024-01-19 合肥康芯威存储技术有限公司 System and method for testing performance of memory
CN117423377B (en) * 2023-12-18 2024-03-22 合肥康芯威存储技术有限公司 System and method for testing performance of memory

Also Published As

Publication number Publication date
CN108269606B (en) 2020-07-14

Similar Documents

Publication Publication Date Title
CN108269606A (en) A kind of method and system for the storage parameter testing of eMMC chips
CN106571166B (en) MT29F series NAND FLASH test aging system with customizable flow
CN104518924B (en) Automatic testing and result comparison method and system
US8880779B2 (en) Debugging a memory subsystem
CN101996121B (en) Universal serial bus (USB) port testing device and testing method
CN110459259A (en) Store test method, system and the storage medium of equipment write error error correcting capability
CN103367189B (en) Test system and test method thereof
CN102568522A (en) Hardware performance test method and device
US11828787B2 (en) Eye diagram capture test during production
US20130036255A1 (en) Testing memory subsystem connectivity
TW201843589A (en) User control of automated test features with software application programming interface (api)
CN103364650A (en) Testing system and testing method
TW201842447A (en) Test program flow control
CN116719675B (en) Hard disk wear testing method, device and medium
CN117435416B (en) Memory testing system and method
CN117012258B (en) Analysis device, method and medium for storing chip state data
CN114077509A (en) Detection method and detection device for reliability detection of flash memory chip
CN108648780A (en) A kind of memory testing system, method and storage medium
CN116560985B (en) Chip equipment test control method, upper computer, equipment and medium
CN110544505B (en) Test system and method for screening poor Die in Wafer
CN113270136A (en) Control method and control system for testing Nand-flash bad block
CN111028881B (en) Open Block testing device, method and system
CN112445670B (en) eMMC test method and device
KR20100041514A (en) Solid state drive apparatus reducing a test time and method for testing the same
Luo et al. A solid state drive architecture with memory card modules

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210922

Address after: 401120 1-1, 2-1, 3-1, building 5, No. 18, Cuiping Lane 2, Huixing street, Yubei District, Chongqing

Patentee after: Chongqing Jinshan Medical Technology Research Institute Co.,Ltd.

Address before: 401120 1 office buildings, Jinshan International Industrial City, 18 of Nei sang Road, Hui Xing street, Yubei District, Chongqing.

Patentee before: CHONGQING JINSHAN MEDICAL APPLIANCE Co.,Ltd.

TR01 Transfer of patent right