201019427 九、發明說明： -【發明所屬之技術領域】 ·· 本發明係有關於一種嵌埋半導體晶片之封裝結構及 :其製法’尤指一種盲孔能精確對位之嵌埋半導體晶片之封 ^裝結構及其製法。 【先前技術】 隨著半導體封裝技術的演進，除了傳統打線式（Wire bonding)半導體封裝技術以外，目前半導體裝置 ❹（Semiconductor device)已開發出不同的封震型態，例如 直接在一封裝基板（package substrate)中嵌埋並電性整 合一例如具有積體電路之半導體晶片，此種封裝件可縮減 整體半導體裝置之體積並提昇電性功能’遂成為一種新的 封裝趨勢。 5青參閱第1A至1G圖’係為習知之嵌埋半導體元件之 封裝結構之製法示意圖。 ❹ 如第1Α圖所示，首先，提供一基板本體1〇，該基板 本體10具有第一表面10a及第二表面1〇b，並具有貫穿 該第一表面10a及第二表面l〇b之開口 ι〇〇，且於該第一 表面l〇a及第二表面l〇b分別具有第一核心線路層ι〇ι 及第二核心線路層102，並具有複數貫穿該第一表面i〇a 及第二表面10b之導電通孔1〇3,以電性連接該第一核心 線路層101及第二核心線路層102;於該開口 1〇〇中容置 有一半導體晶片u，該半導體晶片u具有一作用面ua 及相對之非作用面Hb，且該作用面lla係具有複數電極 110970 5 201019427 墊 111。 如第1B圖所示’於該基板本體10之第—表面i〇a 及半導體晶片11之作用面118壓合第一介電層12a，又 於該基板本體10之第二表面10b及半導體晶片U之非作 用面lib壓合第二介電層12b，且使該第一介電層及 第二介電I 12b填入該開口 100中，以將該半‘體晶片 11固定於該開口 100中。 如第ic圖所示’於該第一介電層12a上以雷射鑽孔 ❿形成有對應該半導體晶片u之電極墊iu的第一開孔 120a’以露出該電極墊⑴之部份表面；於該第二介電層 =雷射鑽孔形成有對應部份之該第二核心線路層 ⑽，而弟成:t rb，以露出部份之第二核心線路層 1UZ而成為電性連接墊i〇2a。 之孔所示’於該第一介電層心、第-開孔施 之孔壁及部份之電極墊111卜形4、丄 且於該第二介電層12b、〔:第—導電層13a， 阻層14a，該第一阻層：第導電層❿上形成有第-遍，以露出部份之第-導成有複數第—開口區 ⑽上形成有第二阻層14“ 又於該第二導電層 數第二開口區！働，以露出部;^^14b並形成有複 如第1F圖所示，於該第一二導電層⑽。 14〇b中之第—導電層13& 品140a及第二開口區 木一導電層13b上分別形成 110970 6 201019427 有第一線路層15a及第二線路層15b，且於該第一開孔 120a中形成有第一導電盲孔151&，以電性連接該半導體 、晶片11之電極墊m，又於該第二開孔i2〇b中形成有第 :二導電盲孔l51b，以電性連接該電性連接墊1〇2a。 - 如第1G圖所示’移除該第一阻層14a及其所覆蓋之 第導電層13a’以露出該第一線路層i5a及第一介電層 心，並移除該第二阻層⑽及其所覆蓋之第二導電層 ⑽，以露出該第二線路層咖及第二介電層⑽。 ❿由上可知’雖該半導體晶片U嵌埋於該開口刪中， 7解決習知技術之導線連接路徑過長所產生之種種缺 = 技術中雷射鑽孔不易精確對準半導體晶片之 電極墊，通常是以一個接著一個針對每-元件逐-進行對 位2達到最佳的對位精度’因而影響製程的效率，且每 重複上述步驟，不僅成本高，更影響製程效率 進，再者，田射鑽孔易因對位偏移 ❹ 而容易造成電性失效的問題。 』千等體S曰月 孔不=雲於上述之問題，如何避免習知技術中雷射鐵 二或損害半導體晶片並影響電性功效等問題， 目則亟欲解決之課題。 耳已成為 【發明内容】 雲於上述習知技術 -種嵌埋半導體元件之封震結^之主要目的係提供 孔對準半導體晶片之電極塾之 1確度製法’能提高雷射鑽 110970 7 201019427 為達上迷目的，本發明揭露一種嵌埋 •裝結構，係包括：半導體 ：分體70件之封 千導體曰曰片’具有相對應之作用面及非 ，- ’於該作用面上設有複數電極墊，並於該作用面上 :^有鈍化層，且該鈍化層具有複數對應外露出各該電極 -墊之鈍化層開孔；第一介電層，係完整包覆該半導體晶 片且具有複數對應露出各該鈍化層開孔之第 及電鍍金屬層，係由碍於兮苗 ^ _ 於該第一介電層上的第一線路層及 各該第一開孔中的第-導電盲孔所構成，且該第 '線 ❹路層藉由該些第—導電盲孔以對應電性連接各該電極塾。 依上述之嵌埋半導體元件之封裝結構，該第一介電層 係由具有第-開孔之第二介電層、與設於該第二介電層及 半導體晶片的非作用面上的第三介電層所構成。 又依上述之嵌埋半導體元件之封裝結構，復包括金屬 層，係汉於各該電極墊、鈍化層開孔之孔壁及其周圍上， 該金屬層係可為焊塊底部金屬化（Under b卿耐 UBM)結構層。 gy’ ❹一依上述之封裝結構，第一黏著層，係設於該第二、第 -二電層之間、及第二介電層與半導體晶片之間，該第一 黏著層上具有複數第一黏著層開孔，以對應容設 導電盲孔。 或依上述之嵌埋半導體元件之封裝結構，復包括第二 黏著層’係設於該第—介電層與各該金屬層之間，且該第 二黏著層具有第二黏著層開孔，以容設該第一導電盲孔。 依上述之封襄結構，復包括第-增層結構，係設於該 110970 8 201019427 第，1電層及第-線路層上’該第一増層 •一第四介電層、設於該第四介電 ’、括至夕 〜複數設於該第四介電芦中之弟二線路層、以及 、三線路層之第二導路層及第 = = 具有複數第- 7您外露出各該弟一電性接觸墊。 β第-介半‘體（件之封裝結構，復包括於該 罾第’I電層未“第一線路層之表面上設 二並:該第一介電層中形成有複數導電通孔二3 Π:線路層與第二線路層，且於該第—介電層未設有 第一線路層之表面及第二線路層上形成有第二增Η 二增層結構係包括至少一第五介電層、設㈣ W電層上之第四線路層、以及複數設於該第五介電層中 並電性連接該第二線路層及第四線路層之第三導電盲 參孔’該第二增層結構最外層之第四線路層復具有複數第二 電性接觸塾，於該第二增層結構之最外層上設有第二防焊 層，且該第二防焊層具有複數第二防焊層開孔，以對應外 路出各該第二電性接觸墊。 本發明復包括一種嵌埋半導體元件之 係包括··提供-承載板，㈣承載板上形=== 毛層，且該第二介電層中形成有複數第一開孔，該些第一 開孔係分別對應各該電極墊，於各該第一開孔中形成有金 屬柱，於該第二介電層上接置具有相對應之作用面及非 110970 201019427 作用面之半導體晶片，於該作用面上形成有複數電極塾， •且於該作用面上形成有鈍化層’該鈍化層中形成有複數 :應外露出各該電極塾之鈍化層開孔，且令各該電極塾對應 *連接各該金屬柱；於該第二介電層與半導體晶片的非作用 -面上形成第三介電層’以將該半導體晶片包覆在第三介 層中；移除該承載板，·移除該些金屬柱，以露出各該第一 ^孔及I極墊’以及形成電鑛金屬層，該電鐘金屬層係包 形成於該第二介電層上之第一線路層、與形成於該 ❹開孔中並電性連接各該電極墊之第—導電盲孔。… 一依上述之封裝結構之製法，其中，該第二介電層與第 二介電層係相互結合而成為一第一介電層。 依上述之嵌埋半導體元件之封裝結構之製法，復包括 =各該^極塾、純化層開孔之孔壁及其周圍上形成有金屬 該金屬層對應各該金屬柱，該金聽係為焊塊底 持屬化（underb卿metallurgy，_結構層。 述之嵌埋半導體元件之封裝結構之製法，復包括 2 介電層與金屬柱上形成第—黏著層；移除該些 =包括移除該第一開孔中之第一黏著層，以形成第 -者曰開孔’且該第一黏著層係以電漿（仙應）、雷 射或反應式離子蝕刻（RIE)方式移除；。 =依上述之嵌埋半導體元件之封裝結構之製法，復包 括移除該第-開孔中之弟第一^著層厚移除該些金属柱復包 罘一黏者層，以形成第二黏著層開 ’且該第二黏著層係以電衆（Plasma)、雷射或反應式 110970 10 201019427 離子蝕刻（RIE)方式移除，而該些金屬柱係以蝕 -移除。 a々式 〜 依上述之封裝結構之製法，該第一線路層與第一導電 :盲孔之製法’係包括：於該第二介電層、第一開孔之孔壁 ‘ ”電極墊上形成導電層；於該導電層上形成阻層， 形成有複數開口區，部分之開口區對應外露出各該第/ = :匕，於該些開口區中之第一開孔中的導電層上形成該第： 導電盲孔，且於該些開口區中之第二介電層上的導電層上 1成該第—線路層；以及移除該阻層及其所覆蓋之i電 $上述之喪埋半導體元件之封裝結構之製法，復包括 ^該弟二介電層及第—線路層上形成第—增層結構，該第 一增層結構係包括至少一第介 二 Μ V ^ ^ ^ ;丨电層形成於该第四介電 m 及複數形成於該第四介電層中並電 '一2該第一線路層及第三線路層之第二導電盲孔，該第 •拯結構取外層之第三線路層上復具有複數第-電性 ，，錢該第—增層結構之最外層上形成第 第，層：成有複數第-防焊層開孔，咖^ 路出各該第一電性接觸墊。 括於= 導體元件之封裝結構之製法’復包 2電層中形成複數導電通孔，以電性連接該 = 層結構，”二二 介電層之表面上形成有第二增 / 一 θ層結構係包括至少一第五介電層、形成 110970 11 201019427 於該第五介電層上之第 八帝昆士从 線路層、以及複數形成於兮筮π -介電層中並電性連接兮當— 乂於孩第五 道帝亡π . ㈣弟—線路層及第四線路層之楚_ 、導電目孔’該第二增ΜΜ·娃Κ7、， 層之第二 :複數第二電性接觸墊，且於啄硌層上设具有 .成第二防谭層，該外層上形 孔，以對應外露出各該第二電性接觸塾。弟一防痒層開 本發明之嵌埋半導體元件之 #利用缔雪払勒L ^ Μ構及其製法，主要 :利用該電極塾上之金屬層與金屬柱可精確 = 之黏著層予以固定，最US:，介電層或外加 導體晶片之電極;之 孔不易精確對準半導體曰片極習知技術中雷射鑽 干干导體日日片之電極墊，進而損害 晶片，並影響電性功#耸μ % 半—體 /音电注功放4問題，且本發明之製法 地進行對位，進而節省萝 面積 疋叩即i衣每成本亚改善量產性， 之製法亦適用於狹窄之電極墊間距之結構。 ©【實施方式】 以下藉由特定的具體實施例說明本發明之 式，熟悉此技藝之人士可由本說明書 ' 也万 蝽銥士政n ^ 令兄a曰所揭不之内容輕易地 瞭解本發明之其他優點及功效。 [第一實施例] 一請參閱第2A圖至第2J圖，係提供本發明之嵌埋 體元件之封裝結構之第一實施例之製法。 —如第2A圖所示，提供一提供一承載板23，其上形成 有第二介電層24,且該第二介電層24中形成有複數第一 110970 12 201019427 開孔240 ’該些第一開孔240係分別對應各該電極墊2〇1， -於各該第一開孔240中形成有金屬柱25,該金屬柱25之 ，材料係可為銅（CU)、金（au)、鎳（Ni)、鎳（Ni) /金（au)、 -鎳（Νι) /鈀（Pd) /金（au)及焊接材料所組成群組之其中一 -者，該焊揍材料係可為錫（Sn)、銅（Cu) γ鉛（Pb)、_銀(Ag)、 鋅（Zn)及叙（Bi)所組成群組之其中一者；並於該第二介電 層24上接置有半導體晶片2〇，該半導體晶片2〇，係具有 相對應之作用面2〇a及非作用面20b，於該作用面2〇a上 ©形成有複數電極墊201 ’於該作用面2〇a上形成有鈍化層 21，該鈍化層21形成有複數對應外露出各該電極墊2〇1 之鈍化層開孔210，於各該電極墊2〇1、鈍化層開孔21〇 之孔壁及其周圍上形成有金屬層22;其中，該金屬層22 之材料係可為銅（Cu)、鎳（Ni)、及焊接材料所組成群組之 其中一者，該焊接材料係可為錫（Sn)、銅（Cu)、鉛（pb)、 銀（Ag)、鋅（Zn)及叙（Bi)所組成群組之其中一者；且八各 ⑩該電極墊201上之金屬層22對應連接各該金屬柱25: 如第2B、2C圖所示，於該第二介電層24與半導體曰 片20的非作用面2〇b上形成第三介電層邡，以將該半= 體晶片20包覆在第三介電層26中，如第2B圖所且 使該第二介電層24與第三介電層26係相互結合而 第一介電層2a，如第2C圖所示。 〃、一 如第2D圖所示，移除該承載板23,以露出誃八 電層2a及金屬柱25之表面。 Λ ；， 如第2Ε圖所示，以係如蝕刻方式移除該些金屬柱 110970 13 201019427 25’以露出該第一開孔240及電極塾201上之金屬層22。 ‘，弋離所7F ’以係如電漿(PlaSma)、雷射或反應 ^ X， IE)移除殘留於各該第一開孔240中之第一 --介電層2a。 示 之孔二圖所不’於該第一介電層2a、第-開孔240 之孔㈣部份之金屬層22上形成導電層27。 ，阻二：二圖所不，於該導電層27上形成阻層28，且 :二形成有複數開口區28〇,其中部分之開口區 ❹280對應外露出各該第-開孔240。 如第21圖所示’於該些開口區·中形成 】二於該些開ϋΙΐ2δ()中之第—開孔24q中的導電 形成第一導電盲孔291，並於該些開口區 之弟：：電層2a上的導電層27上形成第一線路請。 …以=:第所=除該阻層28及其所覆蓋之導電層 出該第-介電層2a及第一線路層292。 •中先圖所示’可於前述步驟中於該第-介電層％ ==;:=’並於形成該電錢金屬…同 第一介電Μ h Μ形成導電通孔3卜且於相對該 θ 2a未设有第一線路層292之表面上 線路層30,藉由該些導泰 /成第一 292與第二線路層如。电 電連接該第一線路層 電声^ 圖所示，承接第2;，圖之結構，於該第一介 s a及第一線路層292上形成第 弟-增層結…包括至少一具有複數第 110970 14 201019427 之第四介電層321a、設於該第四介電層32 la上之第三線 -路層322a、以及複數對應設於該第四介電層321a之各該 . 第四開孔320a中並電性連接該第一線路層292及第三線 : 路層322a之第二導電盲孔323a，該第一增層結構32a最 _ 外層之第三線路層322a上復具有複數第一電性接觸墊 324a，於該第一增層結構32a之最外層上形成第一防焊層 33a，且該第一防焊層33a形成有複數第一防焊層開孔 330a，以對應外露出各該第一電性接觸墊324a ;於相對 參該第一介電層2a之另一表面及第二線路層30上形成第二 增層結構32b，該第二增層結構32b係包括至少一具有複 數第五開孔320b之第五介電層321b、形成於該第五介電 層321b上之第四線路層322b、以及複數對應形成於該第 五介電層321b之各該第五開孔320b中並電性連接該第二 線路層30及第四線路層322b之第三導電盲孔323 b，該 第二增層結構32b最外層之第四線路層322b上復具有複 數第二電性接觸墊324b，於該第二增層結構32b之最外 ®層上形成第二防焊層33b，且該第二防焊層33b形成有複 數第二防焊層開孔330b，以對應外露出各該第二電性接 觸墊324b。復可包括於該第一電性接觸墊324a或第二電 性接觸墊324b上電性連接被動元件（圖未示），該被動元 件可為電阻器（Resistors)、電容器（Capacitors)或電感器 (Inductors) ° [第二實施例] 請參閱第3A圖至第3F圖，係提供本發明之嵌埋半導 15 110970 201019427 體元件之封裝結構之第二實施例之製法。 '如第3A圖所示，在如同第2A圖的結構下 、該第二介電層24與金屬柱25上形成第_黏著層％括於 如第3B圖所示，於該第一黏著層 的非作用面2〇b上形成第三介電層 曰日片20包覆在該第三介電層26中。 如第3C圖所示，移除該承載 電層24及金屬柱25之表面。 乂露出該第一介 參如第3D圖所示，移除該些金屬柱… 開孔240及電極塾2〇1上之第一黏著層以。出該第- 如第3£_示，移除各該第 :層34,使得該第-黏著…形成有複數第 移除各該第一開孔24。中之第_黏第著層= 細贴）、雷射或反應式離子㈣（_。 第3F圖所示，在如同前述之 ❹製法形成導電層27與钱金屬層29广至2;圖所不的 形成圖所示’在如同前述之第2j，與2j”圖的製法 广成另一種嵌埋半導體元件之封裝結構。 [第三實施例] =參閱第4A圖至第㈣，係提供本發明之喪埋半導 牛之封裝結構之第三實施例之製法。 該金圖所示，在如同第2A圖的結構下，復包括於 金屬柱25上形成第二黏著層35。 第4B、4C圖所7F，於該第二介電層24與半導體晶 110970 16 201019427 的非作用面2〇b上形成第三介電層26，以將該 曰曰片20包覆在第三介電層26中，如第仙圖所示； ‘、使該第二介電層24與第三介電層26係相互結合而成為一 第一介電層2a，如第4C圖所示。 . 如第4D圖所示，移除該承載板23。 如第4E圖所示，移除該些金屬柱25，以露出各該 —開孔240及電極墊2〇1上第一 ^ ^ ° 第一黏者層35，移除該些 金屬柱25之方法係可為蝕刻。 鲁如第4F圖所示，移除各該第一開孔2 著層35，令該第-獻蒌爲π + , 弟一黏 ocn 飞弟一黏者層35中形成有第二黏著層開巩 ，，移除各該第二開孔24"之第二黏著層35之方法： w 電漿（plasma)、雷射或反應式離子蝕刻（rie)。’、 ^圖所示’在如前述之第2(?至2了圖的製法形 成導電層27與電鍍金屬層29。 如第4G’圖所示，在如前述之第⑼與2r，圖的製法 _形成又一種嵌埋半導體元件之封裝結構。 括.揭露一種嵌埋半導體元件之封裝結構，係包 面20，具有相對應之作用面⑽及非作用 :該作用面2Ga上設有複數電極墊2(Π，並於今 上形成有純化層21，且 複= =外露出各該電極墊201之鈍化層開孔21。;第一 $ 層2a ’係完整包覆該半導體 „ 片2〇，且具有複數對應露 29 〇之第一開孔24°;以及電鑛金屬層 k由权於該第-介電層2a上的第—線路層292及設 110970 17 201019427 _第-開孔240中的第一導電盲孔29i所構成，該第 ，一線路層292係藉由該第一導電盲孔2_電性連接各該 - 電極墊201。 ‘ &上述之嵌埋半導體元件之封裝結構，該第-介電層 .2“糸由具有第一開孔24〇之第二介電層24、與設於該第 一介電層24及半導體晶片2〇的非作用面_上的第三介 電層2 6所構成。 X依上述之嵌埋半導體元件之封裝結構，復包括金屬 ❿層22,係設於各該電極墊2(n、鈍化層開孔21◦之孔壁及 ，、周圍上該金屬層22係為焊塊底部金屬化（㈣心卿 metallurgy, UBM)結構層。 依上述之封裝結構’復包括第—黏著層％，係設於 =第，與第三介電層24,26之間、及第二介電層％與半 體晶片20之間，該第一 ^ s 〇 >| aa 涿弟黏耆層34上具有複數第一黏著 層開孔3 4 0，以對應容設各該第一導電盲孔2 91。 •…戈I"述之钱埋半導體元件之封裝結構，復包括第二 黏著層35,係設於該第一介電層^與金屬層Μ之間， 該f二黏著層35上具有複數第二黏著層開孔35〇，以對 應容設各該第一導電盲孔291。 ，上述之封裝結構，復包括第一增層結構如，係設 於該弟一介電層2a及第-線路層⑽上，該第一增層結 構32a係包括至少一具有複數第四開孔咖之第四介電 層32h、設於該第四介電層32u上之第三線路層㈣、 以及稷數對應設於該第四介電層心之各該第四開孔 110970 18 201019427 320a中並電性連接該第一線路層292及第三線路層322a ， 之第二導電盲孔323a，該第一增層結構32a最外層之第 - 三線路層322a復具有複數第一電性接觸墊324a，復包括 ，第一防焊層33a，係設於該第一增層結構32a之最外層 上，且該第一防焊層33 a具有複數第一防焊層開孔330a， 以對應外露出各該第一電性接觸墊324a。 又依上述之嵌埋半導體元件之封裝結構，復包括第二 增層.結構32b，係該第一介電層2a未設有第一線路層292 φ之表面上，該第二增層結構32b係包括第二線路層30、 至少一具有複數第五開孔320b之第五介電層321b、設於 該第五介電層321b上之第四線路層322b、以及複數對應 設於該第五介電層321b之各該第五開孔320b中並電性連 接該第二線路層30及第四線路層322b之第三導電盲孔 323b，該第二增層結構32b最外層之第四線路層322b復 具有複數第二電性接觸墊324b，復包括第二防焊層33b， 係設於該第二增層結構32b之最外層上，且該第二防焊層 ®33b具有複數第二防焊層開孔330b，以對應外露出各該第 二電性接觸墊324b。 依上述之嵌埋半導體元件之封裝結構，復包括複數導 電通孔31，以電性連接該第一增層結構32a與第二增層 結構32b。 依上述之結構，復可包括電性連接於該第一電性接觸 墊324a或第二電性接觸墊324b上之被動元件（圖未示）， 該被動元件可為電阻器（Resistors)、電容器（Capaci tors) 19 110970 201019427 或電感器（Inductors)。 -纟發明之嵌埋半導體元件之封裝結構及其製法， 、係利用該電㈣上之金屬層與金屬柱以精確地先 :，立乂接著以具有黏性之介電層或外加之黏著層予以㊁ -疋’取後移徐該金屬柱而形成精確對準半導體晶片之電極 ^盲孔’因此可避免f知技術中雷射鑽孔不易精確對準 +導體晶片之電極塾，進而損害到半導體晶片及影響電性 功效等問題，且本發明之製法可大面積地進行對位，進而 ❹即省製造成本並改善量產性， 窄之電極墊間距之結構。林月之衣法亦適用於狹 上述實施例係用以例示性說明本發明之原理及 效，而非用於限制本發明。任何熟習此項技藝之人士^ =違背本發明之精神及範訂，對上述實施例進行修 圍所此本發明之權利保護範圍’應如後述之申請專利範 【圖式簡單説明】 導體元件之封裝結構 第1Α至1G圖係為習知之嵌埋半 及其製法之剖視示意圖； 第2A至2 J圖係為本發明之嵌埋半導體元件之封裝結 構及其製法之第—實施例之剖視示意圖； ❿圖分別為第2J圖的另一實施例； 第2:及 體元件之封裝結 其中該第3F，圖 第3A至3F圖係為本發明之嵌埋半導 構及其製法之第二實施例之剖視示意圖； 係為第3F圖的另一實施例；以及 110970 20 201019427 第4A至4G圖係為本發明之嵌埋半導體元件之封裝結 - 構及其製法之第三實施例之剖視示意圖；其中該第4G’圖 · 係為第4G圖的另一實施例。 【主要元件符號說明】 10 _基板本體 10a 第一表面 10b 第二表面 100 開口 ©l〇l 第一核心線路層 102 第二核心線路層 102a 電性連接墊 103 、 31 導電通孔 11 ' 20 半導體晶片 1 la、20a 作用面 lib、20b 非作用面 111 > 201 電極墊 w12b、24 第二介電層 12a 、 2a 第一介電層 120a ' 240 第一開孔 120b 第二開孔 13a 第一導電層 13b 第二導電層 14a 第一阻層 140a 第一開口區 21 110970 201019427 14b -140b 第二阻層 第二開口區 15a 、 292 15b 、 30 151a、291 151b、323a 21 210 參22 23 25 26 27 28 280 29 w32a 32b 320a 320b 321a 321b 322a 322b 第一線路層 第二線路層 第一導電盲孔 第二導電盲孔 純化層 鈍化層開孔 金屬層 承載板 金屬柱 第三介電層 導電層 阻層 開口區 電鍍金屬層 第一增層結構 第二增層結構 第四開孔 第五開孔 第四介電層 第五介電層 第三線路層 第四線路層 201019427 323b 第三導電盲孔 .324a 第一電性接觸墊 ” 324b 第二電性接觸墊 • 33a 第一防焊層 33b 第二防焊層 330a 第一防焊層開孔 330b 第二防焊層開孔 34 第一黏著層 .340 第一黏著層開孔 35 第二黏著層 350 第二黏著層開孔201019427 IX. Description of the invention: - [Technical field to which the invention pertains] · The present invention relates to a package structure for embedding a semiconductor wafer and a method for manufacturing the same, in particular, a method for embedding a semiconductor wafer with a blind hole capable of accurately aligning ^ Install structure and its method of production. [Prior Art] With the evolution of semiconductor packaging technology, in addition to the conventional wire bonding semiconductor packaging technology, semiconductor device 目前 (Semiconductor devices) have developed different types of sealing, such as directly on a package substrate ( The package substrate) is embedded and electrically integrated, for example, a semiconductor wafer having an integrated circuit, which can reduce the volume of the overall semiconductor device and enhance the electrical function's become a new packaging trend. 5A is a schematic diagram of a method for fabricating a package structure of a conventional embedded semiconductor device, as shown in Figs. 1A to 1G. As shown in FIG. 1 , firstly, a substrate body 1 is provided. The substrate body 10 has a first surface 10 a and a second surface 1 〇 b and has a first surface 10 a and a second surface 10 b. An opening ι, and the first surface 10a and the second surface 10b respectively have a first core circuit layer ιι and a second core circuit layer 102, and have a plurality of through the first surface i〇a The conductive vias 1 and 3 of the second surface 10b are electrically connected to the first core circuit layer 101 and the second core circuit layer 102. The semiconductor wafer u is accommodated in the opening 1 There is an active surface ua and an opposite non-active surface Hb, and the active surface 11a has a plurality of electrodes 110970 5 201019427 pads 111. As shown in FIG. 1B, the first surface of the substrate body 10 and the active surface 118 of the semiconductor wafer 11 are pressed against the first dielectric layer 12a, and the second surface 10b of the substrate body 10 and the semiconductor wafer. The non-active surface lib of U presses the second dielectric layer 12b, and the first dielectric layer and the second dielectric I 12b are filled in the opening 100 to fix the half-body wafer 11 to the opening 100. in. As shown in the figure ic, a first opening 120a' corresponding to the electrode pad iu of the semiconductor wafer u is formed on the first dielectric layer 12a by laser drilling to expose a part of the surface of the electrode pad (1) Forming a corresponding portion of the second core circuit layer (10) in the second dielectric layer=laser hole, and forming a second core circuit layer 1UZ to be electrically connected Pad i〇2a. The hole of the first dielectric layer, the first and second holes, and the electrode pad 111 are formed, and the second dielectric layer 12b, the second conductive layer 12b, the first conductive layer 13a, a resistive layer 14a, the first resistive layer: a first pass formed on the first conductive layer, the first conductive layer is formed to have a plurality of first open regions (10) formed with a second resist layer 14 The second conductive layer has a second opening area, 働, to expose the portion; ^^14b and is formed as shown in FIG. 1F, in the first two conductive layer (10). The first conductive layer 13 & The first conductive layer 15a and the second circuit layer 15b are formed in the first opening 120a, and the first conductive hole 151& The second electrode hole 51b is formed in the second opening i2〇b to electrically connect the electrical connection pad 1〇2a. Removing the first resist layer 14a and the conductive layer 13a' covered by the first resist layer 14a as shown in FIG. 1G to expose the first circuit layer i5a and the first dielectric layer core, and removing the second resistor (10) and a second conductive layer (10) covered thereon to expose the second circuit layer and the second dielectric layer (10). As can be seen from the above, although the semiconductor wafer U is embedded in the opening, the solution is known. Various defects caused by the long wire connection path of the technology. In the technology, the laser drilling is not easy to accurately align the electrode pads of the semiconductor wafer, and usually the alignment is performed one by one for each component. Accuracy' thus affects the efficiency of the process, and each time the above steps are repeated, not only the cost is high, but also the efficiency of the process is affected. Moreover, the field drilling is easy to cause electrical failure due to the alignment offset 。. Body S曰月孔不=Cloud in the above problems, how to avoid the problem of laser iron in the prior art or damage to the semiconductor wafer and affect the electrical efficacy, etc., the problem is to be solved. The ear has become [invention content] The main purpose of the above-mentioned prior art is to provide a hole-aligned semiconductor wafer electrode 塾1 determinate method to improve the laser drill 110970 7 201019427 The present invention discloses an embedded and mounted structure, which comprises: a semiconductor: a 70-piece sealed conductor piece having a corresponding action surface and a non--, and a plurality of electrode pads are disposed on the active surface. And on the active surface: a passivation layer, and the passivation layer has a plurality of passivation layer openings respectively exposing the electrode pads; the first dielectric layer completely covers the semiconductor wafer and has a plurality of corresponding exposures The first and the plated metal layer of each of the passivation layer are formed by a first circuit layer on the first dielectric layer and a first conductive hole in each of the first openings And the first 'turning circuit layer is electrically connected to each of the electrode turns by the first conductive via holes. According to the above package structure for embedding a semiconductor device, the first dielectric layer is composed of a second dielectric layer having a first opening and a second dielectric layer and a non-active surface of the semiconductor wafer. The three dielectric layers are formed. According to the above package structure for embedding a semiconductor device, a metal layer is further included on each of the electrode pad and the hole wall of the opening of the passivation layer, and the metal layer can be metallized at the bottom of the solder bump (Under b Qing resistance UBM) structural layer. According to the above package structure, the first adhesive layer is disposed between the second and second electrical layers, and between the second dielectric layer and the semiconductor wafer, and the first adhesive layer has a plurality of The first adhesive layer is opened to correspond to the conductive blind hole. Or according to the above package structure for embedding a semiconductor device, the second adhesive layer is disposed between the first dielectric layer and each of the metal layers, and the second adhesive layer has a second adhesive layer opening. The first conductive blind hole is accommodated. According to the above-mentioned sealing structure, the first layer-adding structure is provided on the first dielectric layer and the first-layer layer, and the first dielectric layer and a fourth dielectric layer are disposed on the 110970 8 201019427 The fourth dielectric ', including the eve to the evening, the plural is set in the fourth dielectric layer of the fourth dielectric reed, and the second guiding layer of the three-circuit layer and the == has a plurality of - 7 The younger one is an electrical contact pad. a β-th dielectric layer (a package structure of the device, comprising a plurality of conductive vias formed in the first dielectric layer) 3 Π: a circuit layer and a second circuit layer, and a second enhancement layer is formed on the surface of the first dielectric layer where the first circuit layer is not provided and the second circuit layer includes at least one fifth a dielectric layer, a fourth circuit layer on the (IV) W-electric layer, and a plurality of third conductive blind holes disposed in the fifth dielectric layer and electrically connected to the second circuit layer and the fourth circuit layer The fourth circuit layer of the outermost layer of the second build-up structure has a plurality of second electrical contact turns, a second solder resist layer is disposed on the outermost layer of the second build-up structure, and the second solder resist layer has a plurality of The second solder resist layer is opened to correspond to the external electrical circuit to each of the second electrical contact pads. The invention includes a system for embedding a semiconductor component, including: providing a carrier plate, and (4) carrying a plate shape === hair a layer, and a plurality of first openings are formed in the second dielectric layer, and the first openings respectively correspond to the electrode pads, respectively a metal pillar is formed in an opening, and a semiconductor wafer having a corresponding active surface and a non-110970 201019427 active surface is disposed on the second dielectric layer, and a plurality of electrodes are formed on the active surface, and a passivation layer is formed on the active surface. The passivation layer is formed with a plurality of openings: the passivation layer openings of the electrodes are exposed, and each of the electrodes is connected to each of the metal pillars; and the second dielectric layer is Forming a third dielectric layer on the non-active surface of the semiconductor wafer to encapsulate the semiconductor wafer in the third dielectric layer; removing the carrier plate, removing the metal pillars to expose the first a hole and an electrode pad and forming an electro-mineral metal layer, the metal layer of the electric clock is formed on the first circuit layer on the second dielectric layer, and is formed in the opening and electrically connected The first conductive layer of the electrode pad is formed by the above-mentioned package structure, wherein the second dielectric layer and the second dielectric layer are combined to form a first dielectric layer. The manufacturing method of the package structure of the semiconductor component, the complex includes = each a metal layer is formed on the wall of the opening of the purification layer and the metal layer corresponding to each of the metal pillars, and the gold matrix is held by the underlayer (underbqing metallurgy, _ structural layer. The embedded semiconductor component is described) The method for manufacturing a package structure comprises: forming a first adhesive layer on the dielectric layer and the metal pillar; removing the first layer includes removing the first adhesive layer in the first opening to form a first opening And the first adhesive layer is removed by plasma (synamic), laser or reactive ion etching (RIE); = according to the above-mentioned method for embedding the package structure of the semiconductor component, including removing the first - the first brother of the opening hole removes the metal pillars to form a second adhesive layer to form a second adhesive layer and the second adhesive layer is a laser, a laser Or the reaction formula 110970 10 201019427 is removed by ion etching (RIE), and the metal pillars are etched-removed. According to the above method for manufacturing the package structure, the first circuit layer and the first conductive: method for manufacturing the blind vias include: forming on the second dielectric layer, the first opening hole wall ” electrode pad a conductive layer; a resist layer is formed on the conductive layer, and a plurality of open regions are formed, and a portion of the open regions respectively expose the respective / / : 匕, formed on the conductive layer in the first opening in the open regions The first: a conductive blind via, and the first circuit layer is formed on the conductive layer on the second dielectric layer in the open regions; and the resist layer and the covered a method for fabricating a package structure of a semiconductor device, comprising: forming a first build-up structure on the second dielectric layer and the first circuit layer, the first build-up structure comprising at least one second dielectric V ^ ^ ^ ; The gate layer is formed on the fourth dielectric m and the plurality of second conductive vias formed in the fourth dielectric layer and electrically connected to the first circuit layer and the third circuit layer. The third circuit layer of the outer layer has a plurality of first-electricity, and the first layer of the first-layered structure is formed on the outer layer The first layer is formed with a plurality of first-pre-welding layer openings, and the first electrical contact pads are provided by the coffee. The method of manufacturing the package structure of the conductor element is formed in the second electrical layer of the composite component. Electrically connecting the = layer structure," the second two-dimensional layer structure is formed on the surface of the second dielectric layer, including at least one fifth dielectric layer, forming 110970 11 201019427 on the fifth dielectric layer The eighth emperor of the Upper Emperor was formed in the 兮筮π-dielectric layer from the circuit layer and the plural and electrically connected to the 兮 — 乂 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 孩 ( ( ( ( ( ( ( ( ( ( ( (楚, _, the conductive eyelet 'the second ΜΜ ΜΜ Κ Κ, 7, the second layer: a plurality of second electrical contact pads, and on the enamel layer has a second anti-tan layer, the outer layer Forming a hole to correspondingly expose each of the second electrical contacts. The anti-itch layer of the present invention utilizes the embedded semiconductor component of the present invention. The use of the snow-melting L ^ Μ structure and its preparation method is mainly: the metal layer on the electrode and the metal column can be fixed by the adhesive layer. Most US: the electrode of the dielectric layer or the external conductor chip; the hole is not easy to accurately align the electrode pad of the laser chip dry dry conductor day-day chip in the conventional semiconductor chip, thereby damaging the chip and affecting the electrical property功######################################################################################################## The structure of the electrode pad pitch. [Embodiment] Hereinafter, the formula of the present invention will be described by way of specific embodiments, and those skilled in the art can easily understand the present invention from the contents of the present specification, which is also disclosed by Wan Xi Shi Zheng. Other advantages and effects. [First Embodiment] Referring to Figs. 2A to 2J, a method of manufacturing a first embodiment of a package structure of an embedded component of the present invention is provided. - as shown in FIG. 2A, a carrier plate 23 is provided, a second dielectric layer 24 is formed thereon, and a plurality of first 110970 12 201019427 openings 240 are formed in the second dielectric layer 24 The first opening 240 corresponds to each of the electrode pads 2〇1, and a metal pillar 25 is formed in each of the first openings 240. The metal pillar 25 may be made of copper (CU) or gold (au). ), one of the group consisting of nickel (Ni), nickel (Ni) / gold (au), - nickel (Νι) / palladium (Pd) / gold (au) and welding materials, the welding material system It may be one of a group consisting of tin (Sn), copper (Cu) γ lead (Pb), _ silver (Ag), zinc (Zn), and bis (Bi); and the second dielectric layer 24 A semiconductor wafer 2 is mounted thereon, and the semiconductor wafer 2 has a corresponding active surface 2a and a non-active surface 20b. On the active surface 2a, a plurality of electrode pads 201' are formed. A passivation layer 21 is formed on the surface 2〇a, and the passivation layer 21 is formed with a plurality of passivation layer openings 210 respectively exposing the electrode pads 2〇1, and the electrode pads 2〇1 and the passivation layer openings 21〇. Formed on the wall of the hole and its surroundings The metal layer 22; wherein the material of the metal layer 22 may be one of a group consisting of copper (Cu), nickel (Ni), and a solder material, which may be tin (Sn), copper ( One of a group consisting of Cu), lead (pb), silver (Ag), zinc (Zn), and bis (Bi); and each of the metal layers 22 on the electrode pads 201 of the eight groups 10 is connected to each of the metal pillars 25: as shown in FIGS. 2B and 2C, a third dielectric layer is formed on the second dielectric layer 24 and the inactive surface 2b of the semiconductor wafer 20 to encapsulate the half-body wafer 20. In the third dielectric layer 26, as shown in FIG. 2B, the second dielectric layer 24 and the third dielectric layer 26 are bonded to each other and the first dielectric layer 2a is as shown in FIG. 2C. Then, as shown in Fig. 2D, the carrier plate 23 is removed to expose the surface of the electric layer 2a and the metal post 25. As shown in FIG. 2, the metal pillars 110970 13 201019427 25' are removed by etching, for example, to expose the first opening 240 and the metal layer 22 on the electrode stack 201. ', the 7F' is removed from the first dielectric layer 2a remaining in each of the first openings 240 by, for example, plasma (PlaSma), laser or reaction ^X, IE. The conductive layer 27 is formed on the metal layer 22 of the hole (four) portion of the first dielectric layer 2a and the first opening 240. Block 2: In the second figure, a resist layer 28 is formed on the conductive layer 27, and a plurality of open regions 28 are formed, and a portion of the open regions 280 are correspondingly exposed to the first opening-openings 240. As shown in FIG. 21, 'formed in the open areas · 2', the conductive holes in the first opening 24q of the openings 2δ() form the first conductive blind holes 291, and the brothers in the open areas The first line is formed on the conductive layer 27 on the electrical layer 2a. ...by =: the first = except the resist layer 28 and the conductive layer covered by the conductive layer 2a and the first wiring layer 292. • The first figure can be used in the first step to form a conductive via 3 in the first dielectric layer % ==;:=' and form the conductive metal via the first dielectric Μ h 且The circuit layer 30 on the surface of the first circuit layer 292 is not provided with respect to the θ 2a, and the first 292 and the second circuit layer are formed by the wires. Electrically connecting the first circuit layer to the electroacoustic circuit, as shown in FIG. 2, the structure of the figure, forming a first-generation layer on the first dielectric layer and the first circuit layer 292, including at least one having a plurality of a fourth dielectric layer 321a of the 110970 14 201019427, a third line-road layer 322a disposed on the fourth dielectric layer 32la, and a plurality of corresponding ones disposed on the fourth dielectric layer 321a. The first circuit layer 292 and the third line are electrically connected to the first circuit layer 292 and the third line: the second conductive blind hole 323a of the circuit layer 322a, and the third layer 322a of the outermost layer 32a has the first plurality The first contact layer 33a is formed on the outermost layer of the first build-up structure 32a, and the first solder resist layer 33a is formed with a plurality of first solder resist openings 330a for corresponding external exposure. Each of the first electrical contact pads 324a forms a second build-up structure 32b on the other surface of the first dielectric layer 2a and the second circuit layer 30. The second build-up structure 32b includes at least one a fifth dielectric layer 321b having a plurality of fifth openings 320b, and a fourth circuit layer 322b formed on the fifth dielectric layer 321b And a plurality of third conductive vias 323b formed in the fifth openings 320b of the fifth dielectric layer 321b and electrically connected to the second circuit layer 30 and the fourth circuit layer 322b, the second The fourth circuit layer 322b of the outermost layer of the build-up structure 32b has a plurality of second electrical contact pads 324b, and a second solder resist layer 33b is formed on the outermost layer of the second build-up structure 32b, and the second The solder resist layer 33b is formed with a plurality of second solder mask openings 330b to correspondingly expose the second electrical contact pads 324b. The passive component (not shown) may be electrically connected to the first electrical contact pad 324a or the second electrical contact pad 324b, and the passive component may be a resistor, a capacitor or a capacitor. (Inductors) ° [Second Embodiment] Referring to Figs. 3A to 3F, there is provided a method of manufacturing a second embodiment of the package structure of the embedded semiconductor half-conductor 15 110970 201019427 body element of the present invention. As shown in FIG. 3A, in the structure like FIG. 2A, the second adhesive layer 24 and the metal pillar 25 are formed on the metal pillar 25 as shown in FIG. 3B, and the first adhesive layer is formed. A third dielectric layer 20 is formed on the non-active surface 2〇b to cover the third dielectric layer 26. As shown in Fig. 3C, the surface of the carrier layer 24 and the metal post 25 is removed. The first interface is exposed as shown in FIG. 3D, and the metal pillars are removed. The opening 240 and the first adhesive layer on the electrode 塾2〇1 are removed. Except for the first - as shown in the third section, each of the first layer 34 is removed such that the first adhesive layer is formed with a plurality of first openings 24 for removing the first opening. The first _ sticky layer = fine paste), laser or reactive ion (four) (_. As shown in Fig. 3F, the conductive layer 27 and the gold metal layer 29 are formed as in the above-described tantalum method to a wide range of 2; The method of forming the second semiconductor element as shown in the above-mentioned 2j, and 2j" is widely used. [Third embodiment] = Refer to Figs. 4A to 4(4) The third embodiment of the invention discloses a package structure for a buried semi-conducting cow. The gold figure shows a second adhesive layer 35 formed on the metal post 25 under the structure as in Fig. 2A. 4C, in FIG. 7F, a third dielectric layer 26 is formed on the second dielectric layer 24 and the non-active surface 2〇b of the semiconductor crystal 110970 16 201019427 to encapsulate the germanium 20 on the third dielectric layer. 26, as shown in the first figure; ', the second dielectric layer 24 and the third dielectric layer 26 are combined to form a first dielectric layer 2a, as shown in FIG. 4C. As shown in FIG. 4D, the carrier plate 23 is removed. As shown in FIG. 4E, the metal posts 25 are removed to expose the first opening of the opening 240 and the electrode pad 2〇1. A layer of adhesive layer 35, the method of removing the metal pillars 25 can be etched. As shown in FIG. 4F, the first opening 2 is removed from the layer 35, so that the first-order is π + The second adhesive layer is formed in the adhesive layer 35, and the second adhesive layer 35 of each of the second openings 24" is removed: w plasma, thunder Shot or reactive ion etching (rie). ', ^ is shown in the figure 2 (the method of forming the conductive layer 27 and the plated metal layer 29 as shown in Fig. 4G'. As described in the foregoing (9) and 2r, the method of the invention forms another package structure for embedding a semiconductor device. The package structure of the embedded semiconductor device is disclosed, and the package surface 20 has a corresponding action surface (10) and a non-action. The active surface 2Ga is provided with a plurality of electrode pads 2 (Π, and a purification layer 21 is formed on the surface, and the passivation layer opening 21 of each of the electrode pads 201 is exposed outside; the first layer 2a' Fully encapsulating the semiconductor chip 2, and having a plurality of first openings 24° corresponding to the exposed 〇; and the electro-mineral metal layer k is entitled to the first-dielectric layer 2a The first circuit layer 292 and the first conductive hole 29i in the first opening 240 are formed by the first conductive blind hole 2_ The electrode pad 201. The above-mentioned package structure for embedding the semiconductor device, the first dielectric layer 2 is formed by the second dielectric layer 24 having the first opening 24 and A dielectric layer 24 and a third dielectric layer 26 on the non-active surface of the semiconductor wafer 2 are formed. According to the above-mentioned package structure for embedding a semiconductor device, the metal germanium layer 22 is further provided on each of the electrode pads 2 (n, the hole walls of the passivation layer opening 21, and the metal layer 22 is surrounded by The bottom of the solder bump is metallized ((4) Xinqing metallurgy, UBM) structural layer. According to the above package structure, the composite includes the first adhesive layer %, which is set between the =, and the third dielectric layer 24, 26, and Between the second dielectric layer % and the half-body wafer 20, the first layer 〇 〇 | | 耆 耆 耆 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 Conductive blind hole 2 91. The metal encapsulation structure of the buried semiconductor component, including a second adhesive layer 35, is disposed between the first dielectric layer and the metal layer, the f-adhesive The layer 35 has a plurality of second adhesive layer openings 35 〇 to accommodate the first conductive blind holes 291. The package structure includes a first build-up structure, for example, On the layer 2a and the first circuit layer (10), the first build-up structure 32a includes at least one fourth dielectric layer 32h having a plurality of fourth open cells, and is disposed on the layer The third circuit layer (4) on the four dielectric layers 32u, and the number of turns are correspondingly disposed in the fourth openings 110970 18 201019427 320a of the fourth dielectric layer and electrically connected to the first circuit layer 292 and The third conductive layer 322a, the second conductive via 323a, the third-layer 322a of the outermost layer of the first build-up structure 32a has a plurality of first electrical contact pads 324a, including a first solder resist layer 33a, The first solder resist layer 33a has a plurality of first solder mask openings 330a for correspondingly exposing the first electrical contact pads 324a. The package structure for embedding the semiconductor device further includes a second build-up layer 32b, wherein the first dielectric layer 2a is not provided with a surface of the first circuit layer 292 φ, and the second build-up structure 32b is The second circuit layer 30 includes at least one fifth dielectric layer 321b having a plurality of fifth openings 320b, a fourth circuit layer 322b disposed on the fifth dielectric layer 321b, and a plurality of corresponding interfaces. Each of the fifth openings 320b of the electrical layer 321b is electrically connected to the second circuit layer 30 and the fourth circuit layer 322b. The third conductive via hole 323b, the fourth circuit layer 322b of the outermost layer of the second build-up structure 32b has a plurality of second electrical contact pads 324b, and a second solder resist layer 33b is disposed on the second build-up layer. The second solder mask layer 33b has a plurality of second solder mask openings 330b for externally exposing the second electrical contact pads 324b. The semiconductor device package is embedded as described above. The structure includes a plurality of conductive vias 31 electrically connected to the first build-up structure 32a and the second build-up structure 32b. According to the above structure, the composite device includes a passive component (not shown) electrically connected to the first electrical contact pad 324a or the second electrical contact pad 324b, and the passive component can be a resistor (Resistors) or a capacitor. (Capaci tors) 19 110970 201019427 or Inductors. - The package structure of the embedded semiconductor component of the invention and the method of manufacturing the same, using the metal layer and the metal pillar on the electricity (4) to accurately: first, then adhere to a viscous dielectric layer or an additional adhesive layer By taking the metal pillar to form a precise alignment of the electrode of the semiconductor wafer, the blind hole can be avoided. Therefore, it is avoided that the laser drilling is difficult to accurately align the electrode of the + conductor wafer, thereby damaging The semiconductor wafer has problems affecting electrical efficacy, and the manufacturing method of the present invention can perform alignment on a large area, thereby saving manufacturing cost and improving mass productivity, and narrow electrode pad pitch structure. The invention is also intended to be illustrative of the principles and effects of the invention and is not intended to limit the invention. Any person skilled in the art ^ = contrary to the spirit and scope of the present invention, the above embodiments are modified. The scope of the present invention should be as described in the following patent application form [Simple Description] Conductor Element 1A to 1G of the package structure is a schematic cross-sectional view of a conventional embedded half and a method thereof; 2A to 2J are a package structure of the embedded semiconductor device of the present invention and a cross section of the method for manufacturing the same FIG. 2 is another embodiment of the second J-FIG.; 2: and the package of the body element, wherein the 3F, FIG. 3A to 3F are the embedded semi-conductor of the present invention and the method thereof. 2 is a cross-sectional view of a second embodiment; and is another embodiment of FIG. 3F; and 110970 20 201019427. FIGS. 4A to 4G are diagrams showing a package junction structure of an embedded semiconductor device of the present invention and a third implementation method thereof. A cross-sectional view of an example; wherein the 4G' map is another embodiment of the 4Gth image. [Main component symbol description] 10 _ substrate body 10a first surface 10b second surface 100 opening ©1 first core circuit layer 102 second core circuit layer 102a electrical connection pad 103, 31 conductive via 11 ' 20 semiconductor Wafer 1 la, 20a active surface lib, 20b non-active surface 111 > 201 electrode pad w12b, 24 second dielectric layer 12a, 2a first dielectric layer 120a '240 first opening 120b second opening 13a first Conductive layer 13b second conductive layer 14a first resistive layer 140a first open region 21 110970 201019427 14b - 140b second resistive layer second open region 15a, 292 15b, 30 151a, 291 151b, 323a 21 210 Ref 22 23 25 26 27 28 280 29 w32a 32b 320a 320b 321a 321b 322a 322b first circuit layer second circuit layer first conductive blind hole second conductive blind hole purification layer passivation layer open hole metal layer carrier plate metal column third dielectric layer conductive layer resistance Layer open area plated metal layer first build-up structure second build-up structure fourth opening fifth opening fourth dielectric layer fifth dielectric layer third circuit layer fourth circuit layer 201019427 323b third conductive blind .324a first electrical contact pad 324b second electrical contact pad • 33a first solder mask 33b second solder mask 330a first solder mask opening 330b second solder mask opening 34 first adhesive layer .340 first adhesive layer opening 35 second adhesive layer 350 second adhesive layer opening
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