201017881 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種橫向雙擴散金氧半導體結構，且 特別是有關於一種含有高矽含量介電層之橫向雙擴散金氧 半導體結構。 【先前技彳t】 Φ 功率積體電路元件由於具有耐高壓特性與較低的導通 電阻，以廣泛地應用於顯示器驅動元件、電源供應器、通 訊等領域上。 傳統的功率元件可分為橫向結構與縱向結構，橫向結 構以雙擴散金氧半導體（Lateral Double-Diffused MOS， LDMOS)為代表，縱向結構以溝槽式閘極功率電晶體為代 表’其操作原理與傳統的MOS相同，皆是利用閘極的外加 電壓，使得閘極下方表面的部分形成反轉層，進而連接源 馨 極端與没極端，於是形成通道。 維持LDMOS之臨界電壓（thresh〇ld_v〇hage，vth)的穩 定性，可提高電晶體之效能，有助於元件之操作。然而於 LDPMOS中’臨界電壓標移（drift)情形卻非常的嚴重，習 知係藉由改變閘極氧化層之摻雜濃度以改善臨界電壓飄移 的現象’但是其改善效果有限。 因此，業界亟需一種能有效改善臨界電壓標移之方法。 97011/0516-A41819-TW/final 201017881 【發明内容】 •本發明提供一種雙擴散金氧半導體結構，包括：-半 ‘體基底，-p型蟲晶層形成於該半導體基底之上·一 ? 型井區形成於該P型蟲晶層之上複數個隔離結構，形成於 該^型，區之上；-N型埋藏層形成於該p型蟲晶層中； 第同[N型井區、一第二高麼^^型井區與一高壓p型 井區職於該N型埋藏層之上，其中該高塵p型井區介於 該第型井區與該第二高壓N型井區之間；一對源 極形成於該第-高壓N型井區之上；一沒極形成於該高壓 P型井區之上’-閘極介電層形成於該第—高壓N型井區 與該第一 p型井區之上，―閘極形成於該閘極介電層之 上；以及-金屬化前介電層（Pre_metaldielectriclayer,pMD) 形成於該些源極、該閘極、該隔離結構與該汲極之上，其 中5亥金屬化岫介電層為一高矽含量之矽化物，其矽含量高 於依照化學什置組成之砍化物之；g夕含量。 。 議 本發明另提供一種雙擴散金氧半導體結構，包括：一 半導體基底；一 P型磊晶層形成於該半導體基 一 P型井區形成於該P型蠢晶層之上；複數個隔離結構形成 於該P型井區中；一 N型埋藏層形成於該p型磊晶層中； -第-高壓N型井區一第二高壓井區與第三高 型井區形成於該N型埋藏層之上；一第一高壓p型井區與 第二高壓P型井區形成於該N型埋藏層之上，其中該第二 高壓P型井區介於該第一高壓^^型井區與該第二高壓^^型 井區之間，該第二高壓p型井區介於該第二高壓N型井區 97011/0516-A41819-TW/fmal 201017881 與該第三高壓N型井區之間；一源極形成於該第一高壓P 型井區之上；一對汲極形成於該第二高壓P型井區與該第 三高壓N型井區之上；一閘極介電層形成於該第二高壓N 型井區、該第一高壓P型井區與該第二高壓P型井區之上； 一閘極形成於該閘極介電層之上；以及一金屬化前介電層 (Pre-metal dielectric layer, PMD)形成於該些源極、該閘 極、該隔離結構與該汲極之上，其中該金屬化前介電層為 一高石夕含量之石夕化物，其石夕含量高於依照化學計量組成之 ® 梦化物之矽含量。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 以下特舉出本發明之實施例，並配合所附圖式作詳細 〇 說明，而在圖式或說明中所使用的相同符號表示相同或類 似的部分，且在圖式中，實施例之形狀或是厚度可擴大， 並以簡化或是方便標示。再者，圖式中各元件之部分將以 分別描述說明之，值得注意的是，圖式中未繪示或描述之 元件，為所屬技術領域中具有通常知識者所知的形狀，另 外，特定之實施例僅為揭示本發明使用之特定方式，其並 非用以限定本發明。 本發明實施例提供一種非對稱雙擴散p -通道金氧半導 體(LD PMOS)元件，請參見第1A圖，首先提供一半導體 97011/0516-A41819-TW/final 201017881 基底100 ’例如塊狀石夕基底(buik siiicon)或絕緣層上覆;g夕基 底（silicon-on-insulator，SOI)。一 p 型磊晶層 1〇2 形成於半 導體基底100之上，其形成方法例如以硼為換質利用化學 氣相沉積製程形成一層非晶矽材料層，再對非晶矽材料層 進行固相蠢晶步驟而得。一 P型井區104形成於p型蟲晶 層102之上’其係藉由一圖案化罩幕（未顯示）配合植入p 型掺質而形成之’ P型摻質例如為硼、鎵、鋁、銦、或 上述之組合。複數個隔離結構1〇6形成於p型井區1〇4之 • 上，隔離結構1〇6的材質例如是氧化矽，其製法例如使用 熱氧化法形成場氧化層（field oxide)，或者是淺溝隔離結構 (shallow trench isolation，STI)。 一 N型埋藏層（N-doped buried layer) 108形成於P型蟲 晶層102中。N型埋藏層（N_dopedburiedlayer)108之形成 方法係利用離子植入把N型摻質引入P型磊晶層1〇2中， N型摻質例如為磷、砷、氮、銻、或上述之組合。一第一 高壓N型井區11〇與一第二高壓N型井區ι16形成於N 響型埋藏層108之上，其係藉由圖案化罩幕（未顯示）配合植 入N型摻質而形成之，接著形成一高壓p型井區112mN 型埋藏層108之上，其係藉由圖案化罩幕（未顯示）配合植 入P型摻質而形成之，其中高壓P型井區112介於第一高 壓N型井區11〇與第二高壓N型井區114之間。 一對源極區116形成於第一高壓N型井區n〇之上， 而一汲極區118形成於第二P型井區112之上。一閘極介 電層120形成於高壓p型井區112與第二高壓N型井區114 97011/0516-A41819-TW/final 8 201017881 之上，閘極介電層120包括氧化物、氮化物、氮氧化物或 高介電常數(high k)材料。形成上述閘極介電層120之方 式，包括低溫化學氣相沉積（low temperature chemical vapor deposition, LTCVD)、低壓化學氣相沉積（l〇w pressure chemical vapor deposition, LPCVD)、快速熱處理化學氣相 沉積（rapid thermal chemical vapor deposition, RTCVD)或化 學氣相沉積（chemical vapor deposition, CVD)法。一閘極 122形成於閘極介電層120之上，閘極122包括多晶矽 籲 （polysilicon)、金屬、金屬合金或金屬石夕化物。 接著沉積之結構為本發明之關鍵結構，一金屬化前介 電層（Pre-metal layer, PMD) 124形成於隔離結構106、源極 116與汲極118之上，此處需注意的是，該PMD層124為 一高矽含量之矽化物，其矽含量高於依照化學計量組成之 石夕化物之石夕含量，其包括氧化石夕、氮氧化石夕、氮化石夕或上 述之組合。 由於LDMOS後段製程中，沉積内層介電層（inter-layer ® dielectric layer，ILD)或金屬間介電層（inter-metal dielectric layer，IMD)時，使用化學氣相沉積法時，會導入大量矽烷 類分子，其會產生氫氣，再者製程清洗過程中，會導入大 量的水氣，上述製程中所產生的氫氣與水分子若擴散到載 子的通道中，會阻礙通道中載子的流通，因而造成臨界電 壓飄移（Vth shift)現象，進而影響元件的效能，且此現象在 LDPMOS中影響特別明顯。然而習知利用二氧化矽（Si〇2) 或是氮化矽（Si3N4)作為PMD層，其並無法有效阻礙氫氣或 97011/0516-A41819-TW/fmal 9 201017881 水氣之擴散，因此本發明接 以阻礙氫氣和水氣的擴散^由沉積該高料量之介電層 層作為介電 物，當沉積之介電層為氣於含有高/含量之石夕化 為（1.1〜1.5) : 2，而折射率4 ’其石夕之莫耳比例約 具有高似彳選擇比之氣切Γ ^〜1,7°右製程需要沉積 (…·^。此外，日I’其^氮之莫耳比例約為 ❿ 雜物，例如包括删、碑以::化物中可更包括-摻 沉積該高石夕含量之石夕彳!_ 積法(APCVD)或電t _ 2^包括常壓化學氣相沉 -實施例中，若要形成4 :咖積法(PECVD)。於 石夕甲烧(卿）、扣_^化層時，通人氣體之成份例如 另外尚包括通入氧氣或選握:四乙氧基减(Sl(〇C2H5)4) ’ 主要控制氧氣與切前通人爛、填、鍺等換雜物， 以得到㈣含量比之氣化^流量比約在丨.2〜12的範圍， 若依製程需要具有高為 擇通入氣狀成份包㈣甲、;!選擇tb之氮㈣時，同樣選 氧基矽烷(Si(OC2H5)4)，以=(SlH4)、矽乙烷(Sl2ii6)、四乙 或氨氣(NH3)以提供氮之來、、^石夕之來源，另外通入氮氣(N2) 驅物之流量比約在0.25〜〇 7、其中主要控制瓦氣與含石夕前 氮化石夕。 _ 5的範圍，以得到高矽含量比之 高矽含量比，能降低製程中 進而使得臨界電壓達更佳的穩定 產生之氫與水氣之影響 由於本發明之PMd層具有 97011/0516-A41819-TW/fmal 10 201017881 性。 請參見第1B圖’於PMD層124之上沉積一内層介電 層（inter-layer dielectric layer, ILD)126，其中 ild 層 126 亦 可為高矽含量之矽化物。之後再利用接觸窗製程，於源極 114與汲極116之上形成複數個金屬接觸插塞(plug)128。 請參見第1C圖，於金屬接觸插塞128之上形成一金屬 線13 0 ’之後於金屬線13 0之上沉積一金屬間介電層 (inter-metal dielectric layer，IMD) 132，其中該 IMD 層 132 ® 同樣亦可為高矽含量之矽化物。此技術人士可依實際之需 要，依前述方式沉積一或多層金屬内連線與IMD層。 請參見第1D圖’當多層金屬層完成之後，於最後之金 屬線130之上形成保護層134，此處須注意的是，保護層 同樣亦可為高矽含量之矽化物，以更有效地降低氫氣與水 氣的衫響’以k向界電壓之穩定性。 本發明另一實施例為一種對稱雙擴散P-通道金氧半導 體(LD PMOS)元件’請參見第圖，其中標號1〇〇〜1〇8 ❹之元件皆與第一實施例之元件相同，在此不再贅述。然而 本實施例與第一實施例之差異在於，一第一高壓N型井區 210、一第二高壓n型井區214與第三高壓N型井區218 形成於該N型埋藏層208之上，上述之N型井區係藉由圖 案化罩幕（未顯示）配合植入N型摻質而形成之。接著一第 一高壓P型井區212與第二高壓p型井區216形成於該N 型埋藏層208之上’上述之p型井區係藉由圖案化罩幕（未 顯示）配合植入P型摻質而形成之，其中該第一高壓P型 97011/0516-A41819-TW/fmal 11 201017881 井區212介於該第一高壓N型井區210與該第二高壓N型 井區214之間，該第二高壓P型井區216介於該第二高壓 N型井區214與該第三高壓N型井區218之間。 之後一源極220形成於第一高壓p型井區212之上， 以及一對没極222形成於第二高壓p型井區216與第三高 壓N型井區218之上。一閘極介電層224形成於第一高壓 P型井區212、第二高壓N型井區214、與第二高壓P型井 區216之上，閘極介電層224包括氧化物、氮化物、氮氧 β 化物或高介電常數材料’形成上述閘極介電層224之方 式，包括低溫化學氣相沉積（low temperature chemical vapor deposition，LTCVD)、低壓化學氣相沉積（i〇w pressure chemical vapor deposition，LPCVD)、快速熱處理化學氣相 沉積（rapid thermal chemical vapor deposition, RTCVD)或化 學氣相沉積（chemical vapor deposition, CVD)法。一閉極 226形成於閘極介電層120之上，閘極226包括多晶石夕 (polysilicon)、金屬、金屬合金或金屬矽化物 ❿ 接著沉積之結構為本發明之關鍵結構，一金屬化前介 電層（Pre-metal layer，PMD)228順應性地設置於隔離結構 106、源極220與汲極222之上，此處需注意的是，該pMD 層228為一高矽含量之矽化物，其矽含量高於依照化學計 量組成之矽化物之矽含量，其包括氧化矽、氮氧化矽、氮 化矽或上述之組合。當介電層為氧化矽時，其矽：氧之莫 耳比例約為（1.1〜1.5) . 2，而折射率約為1.5〜17。去介電 層為氮化石夕時，其中石夕：氮之莫耳比例約為(3.丨〜3 y . 4^ 97011/0516-A41819-TW/fmal 12 201017881 此外，於高矽含量之矽化物中可更包括一摻雜物，摻雜物 包括棚、磷、鍺或其結合。沉積該高矽含量之矽化物之方 法與控制氣體流罝同上述實施例，在此不再贅述。 請參見第1F圖’於pmd層228之上沉積一内層介電 層（inter-layer dielectric layer, ILD)230，其中 ILD 層 230 亦 可為高矽含量之矽化物。之後再利用接觸窗製程，於源極 220與汲極222之上形成複數個金屬接觸插塞(plug)232。 請參見第1G圖，於金屬接觸插塞232之上形成一金屬 ❹線234 ’之後於金屬線234之上沉積一金屬間介電層 (inter-metal dielectric layer, IMD)236，其中該 IMD 層 236 同樣亦可為高矽含量之矽化物。此技術人士可依實際之需 要’依前述方式沉積一或多層金屬内連線與IMD層。 凊參見第1H圖’當多層金屬層完成之後，於最後之金 屬線234之上形成保護層238，此處須注意的是，保護層 同樣亦可為高矽含量之矽化物，以更有效地降低氫氣與水 氣的影響，以提高臨界電壓之穩定性。 m 一 上述貫施例中之PMD層、ILD層、IMD層或保護層並 不偈限只沉積一層高矽含量之矽化物，另外可依製程之需 要，沉積多層高矽含量之矽化物，以更有效隔離氫氣與水 氣。 本發明之雙擴散金氧半導體結構中，其中金屬化前介 電層（PMD)由高石夕含量之石夕化物所組成，而内層介電層 (ILD)、金屬間介電層（IMD)與保護層（passivati〇n iayer)同樣 亦可由高矽含量之矽化物所組成，藉由高矽含量之石夕化物 97011/0516-A41819-TW/final 13 201017881 能有效阻擋製程中氫氣與水氣，以提高臨界電壓之穩定性。 雖然本發明已以數個較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 參 第1A~1D圖為一系列剖面圖，用以說明本發明實施例 之非對稱雙擴散金氧半導體之結構。 第1E〜1H圖為一系列剖面圖，用以說明本發明實施例 之對稱雙擴散金氧半導體之結構。 【主要元件符號說明】 100〜半導體基底 ^ 102〜P型磊晶層 104〜P型井區 106〜隔離結構 108〜N型埋藏層 110〜第一高壓N型井區 112〜高壓P型井區 114〜第二高壓N型井區 116〜源極區 118〜〉及極區 97011/0516-A41819-TW/final 14 201017881 120〜閘極介電層 12 2〜閑極 124〜PMD層 126〜ILD層 128〜金屬接觸插塞 130〜金屬線 132〜IMD層 134〜保護層 參 210〜第一高壓N型井區 212〜第一高壓P型井區 214〜第二南壓N型井區 216〜第二高壓P型井區 218〜第三南壓N型井區 220〜源極 222〜汲極 224〜閘極介電層 ❿ 226〜閘極 228〜PMD層 230〜ILD層 232〜金屬接觸插塞 234〜金屬線 236〜IMD層 238〜保護層 97011/0516-A41819-TW/final201017881 IX. Description of the Invention: [Technical Field] The present invention relates to a lateral double-diffused MOS structure, and more particularly to a lateral double-diffused MOS structure containing a high bismuth content dielectric layer. [Previous Technology t] Φ Power integrated circuit components are widely used in display drive components, power supplies, communications, etc. due to their high voltage resistance and low on-resistance. The traditional power components can be divided into a lateral structure and a vertical structure. The lateral structure is represented by a double-diffused MOS (LDMOS), and the vertical structure is represented by a trench gate power transistor. As with the conventional MOS, the applied voltage of the gate is utilized, so that the portion of the lower surface of the gate forms an inversion layer, and thus the source is connected to the extreme and not extreme, thus forming a channel. Maintaining the stability of the threshold voltage (thresh〇ld_v〇hage, vth) of the LDMOS can improve the performance of the transistor and contribute to the operation of the device. However, the 'threshold voltage drift' condition in LDPMOS is very serious, and it is known to improve the phenomenon of threshold voltage drift by changing the doping concentration of the gate oxide layer', but its improvement effect is limited. Therefore, there is a need in the industry for a method that can effectively improve the threshold voltage shift. 97011/0516-A41819-TW/final 201017881 SUMMARY OF THE INVENTION The present invention provides a double-diffused MOS semiconductor structure comprising: a semi-body substrate, on which a p-type worm layer is formed on the semiconductor substrate. The well region is formed on the P-type insect layer and has a plurality of isolation structures formed on the type and the region; the -N-type buried layer is formed in the p-type layer; the first [N-well region a second high ^^ type well area and a high pressure p type well area are disposed above the N type buried layer, wherein the high dust p type well area is between the first type well area and the second high pressure type N type Between the well areas; a pair of sources are formed on the first high-pressure N-type well region; a immersion is formed on the high-pressure P-type well region'-the gate dielectric layer is formed in the first high-pressure N-type Above the well region and the first p-type well region, a gate is formed over the gate dielectric layer; and a pre-metaldielectric layer (pMD) is formed on the source, the gate The isolation structure and the drain electrode, wherein the 5Hi metallized tantalum dielectric layer is a high tantalum content telluride, and the tantalum content is higher than the chemical composition Compound; g Xi content. . The present invention further provides a double-diffused MOS structure comprising: a semiconductor substrate; a P-type epitaxial layer formed on the semiconductor-P-well region formed on the P-type stray layer; and a plurality of isolation structures Formed in the P-type well region; an N-type buried layer is formed in the p-type epitaxial layer; - a first high-pressure N-type well region, a second high-pressure well region and a third high-type well region are formed in the N-type Above the buried layer; a first high pressure p-type well region and a second high pressure P-type well region are formed on the N-type buried layer, wherein the second high pressure P-type well region is interposed between the first high pressure type well Between the zone and the second high pressure type well region, the second high pressure p-type well region is between the second high pressure N-type well region 97011/0516-A41819-TW/fmal 201017881 and the third high pressure N-type well Between the zones; a source is formed on the first high-pressure P-well region; a pair of drains are formed on the second high-pressure P-well region and the third high-pressure N-well region; An electric layer is formed on the second high-pressure N-type well region, the first high-voltage P-type well region and the second high-voltage P-type well region; a gate is formed on the gate dielectric layer; And a pre-metal dielectric layer (PMD) formed on the source, the gate, the isolation structure and the drain, wherein the pre-metallization dielectric layer is a high-stone The content of the stone compound is higher than that of the stoichiometric composition. The above and other objects, features, and advantages of the present invention will become more fully understood from The same reference numerals are used for the same or similar parts in the drawings or the description, and in the drawings, the shape or thickness of the embodiment may be expanded. And simplified or convenient to mark. Further, portions of the various elements in the drawings will be described separately, and it is noted that elements not shown or described in the drawings are shapes known to those of ordinary skill in the art and, in addition, The embodiments are merely illustrative of specific ways of using the invention and are not intended to limit the invention. Embodiments of the present invention provide an asymmetric double-diffused p-channel metal oxide semiconductor (LD PMOS) device. Referring to FIG. 1A, a semiconductor 97011/0516-A41819-TW/final 201017881 substrate 100 is first provided, for example, a block-shaped stone eve. Substrate (buik siiicon) or insulating layer overlying; silicon-on-insulator (SOI). A p-type epitaxial layer 1〇2 is formed on the semiconductor substrate 100 by forming a layer of amorphous germanium material by a chemical vapor deposition process, for example, by boron, and then solid-phase the amorphous germanium material layer. Stupid step. A P-type well region 104 is formed over the p-type seed layer 102. The P-type dopant is formed by implanting a p-type dopant with a patterned mask (not shown) such as boron or gallium. , aluminum, indium, or a combination of the above. A plurality of isolation structures 1〇6 are formed on the p-type well region 1〇4, and the material of the isolation structure 1〇6 is, for example, ruthenium oxide, which is formed by, for example, thermal oxidation to form a field oxide layer, or Shallow trench isolation (STI). An N-doped buried layer 108 is formed in the P-type insect layer 102. The N-doped buried layer 108 is formed by ion implantation using an N-type dopant into the P-type epitaxial layer 1〇2, such as phosphorus, arsenic, nitrogen, antimony, or a combination thereof. . A first high-pressure N-type well region 11〇 and a second high-pressure N-type well region ι16 are formed on the N-type buried layer 108, and the N-type dopant is implanted by a patterned mask (not shown). Formed, a high-pressure p-type well region 112mN-type buried layer 108 is formed, which is formed by patterning a mask (not shown) with a P-type dopant, wherein the high-pressure P-type well region 112 is formed. Between the first high pressure N-type well region 11 〇 and the second high pressure N-type well region 114. A pair of source regions 116 are formed over the first high pressure N-well region n〇, and a drain region 118 is formed over the second P-well region 112. A gate dielectric layer 120 is formed over the high voltage p-well region 112 and the second high voltage N-well region 114 97011/0516-A41819-TW/final 8 201017881, and the gate dielectric layer 120 includes oxides and nitrides. , NOx or high dielectric constant (high k) materials. The manner of forming the gate dielectric layer 120 includes low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), and rapid thermal processing chemical vapor deposition. (rapid thermal chemical vapor deposition, RTCVD) or chemical vapor deposition (CVD). A gate 122 is formed over the gate dielectric layer 120, and the gate 122 includes polysilicon, a metal, a metal alloy, or a metallurgical compound. The deposited structure is a key structure of the present invention. A pre-metal layer (PMD) 124 is formed on the isolation structure 106, the source 116 and the drain 118. It should be noted here that The PMD layer 124 is a high cerium content telluride having a cerium content higher than that of the stoichiometric composition of the cerium sulphate, including oxidized stone, oxynitride, cerium nitride or a combination thereof. Due to the deposition of the inter-layer ® dielectric layer (ILD) or the inter-metal dielectric layer (IMD) in the LDMOS back-end process, a large amount of decane is introduced when chemical vapor deposition is used. Class of molecules, which will generate hydrogen, and in the process of cleaning, a large amount of water and gas will be introduced. If the hydrogen and water molecules generated in the above process diffuse into the channel of the carrier, the flow of the carriers in the channel will be hindered. Therefore, the phenomenon of threshold voltage shift (Vth shift) is caused, which in turn affects the performance of the component, and this phenomenon is particularly obvious in the LDPMOS. However, it is conventionally known that cerium oxide (Si〇2) or cerium nitride (Si3N4) is used as the PMD layer, which does not effectively hinder the diffusion of hydrogen or 97011/0516-A41819-TW/fmal 9 201017881 water and gas, and thus the present invention In order to hinder the diffusion of hydrogen and water vapor, the high-volume dielectric layer is deposited as a dielectric, and when the deposited dielectric layer is gas containing high/content, it is (1.1~1.5): 2, while the refractive index 4 'the proportion of the stone oxime molar has a high 彳 彳 selectivity than the gas cut Γ ^ ~ 1, 7 ° right process needs to be deposited (...·^. In addition, the day I' its ^ nitrogen mo The ratio of the ear is about ❿ , , , , , , 、 碑 : : : : : : : : : : : : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the case of the embodiment, in order to form a 4: grouting method (PECVD), in the case of Shi Xijia (clear), deduction layer, the composition of the gas, for example, additionally includes oxygen or a grip. :tetraethoxy reduction (Sl(〇C2H5)4) 'Mainly control the oxygen and the replacement of the rotten, filling, sputum, etc. before cutting, to obtain the (four) content ratio of the gasification ^ flow ratio is about 丨. 2~ 12 Scope, if the process needs to have a high-input gas-inducing component (four) A,;! Select tb nitrogen (four), the same choice of oxydecane (Si (OC2H5) 4), = (SlH4), 矽 ethane (Sl2ii6), tetraethyl or ammonia (NH3) to provide nitrogen, and the source of the stone, and the flow rate of nitrogen (N2) is about 0.25~〇7, which mainly controls the gas and The range of _ 5 is included in the range of 石 5 to obtain a high 矽 content ratio, which can reduce the influence of hydrogen and moisture generated in the process and thus the threshold voltage is better. The PMd layer has 97011/0516-A41819-TW/fmal 10 201017881. Please refer to FIG. 1B' to deposit an inter-layer dielectric layer (ILD) 126 over the PMD layer 124, wherein the ild layer 126 is also The germanium compound may be a germanium content. A plurality of metal contact plugs 128 are formed over the source 114 and the drain 116 by a contact window process. See FIG. 1C for the metal contact plug 128. After forming a metal line 13 0 ' thereon, an inter-metal dielectric layer (inter-metal) is deposited over the metal line 130 The dielectric layer (IMD) 132, wherein the IMD layer 132 ® can also be a germanium content of high germanium content. The person skilled in the art can deposit one or more layers of metal interconnects and IMD layers as described above. FIG. 1D'After completion of the multilayer metal layer, a protective layer 134 is formed over the last metal line 130. It should be noted here that the protective layer may also be a germanium content of high germanium content to more effectively reduce hydrogen. The sound of the shirt with the water vapor 'with k-bound voltage stability. Another embodiment of the present invention is a symmetric double-diffused P-channel metal oxide semiconductor (LD PMOS) device. Referring to the figure, the components of the reference numerals 1 〇〇 1 〇 8 ❹ are the same as those of the first embodiment. I will not repeat them here. However, the difference between this embodiment and the first embodiment is that a first high-pressure N-type well region 210, a second high-pressure n-type well region 214 and a third high-pressure N-type well region 218 are formed in the N-type buried layer 208. In the above, the N-type well region is formed by patterning a mask (not shown) and implanting an N-type dopant. A first high pressure P-type well region 212 and a second high pressure p-type well region 216 are formed on the N-type buried layer 208. The p-type well region is implanted by a patterned mask (not shown). Formed by a P-type dopant, wherein the first high-pressure P-type 97011/0516-A41819-TW/fmal 11 201017881 well 212 is interposed between the first high-pressure N-well region 210 and the second high-pressure N-well region 214 The second high pressure P-type well region 216 is interposed between the second high pressure N-type well region 214 and the third high pressure N-type well region 218. A source 220 is then formed over the first high pressure p-well 212 and a pair of gates 222 are formed over the second high pressure p-well 216 and the third high pressure N-well region 218. A gate dielectric layer 224 is formed over the first high voltage P-type well region 212, the second high voltage N-type well region 214, and the second high voltage P-type well region 216. The gate dielectric layer 224 includes oxides and nitrogen. a method of forming the gate dielectric layer 224 by a compound, a nitrogen oxide compound or a high dielectric constant material, including low temperature chemical vapor deposition (LTCVD) and low pressure chemical vapor deposition (i〇w pressure). Chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or chemical vapor deposition (CVD). A closed electrode 226 is formed over the gate dielectric layer 120. The gate 226 includes polysilicon, metal, metal alloy or metal germanide. The structure deposited next is a key structure of the present invention, a metallization. A pre-metal layer (PMD) 228 is compliantly disposed on the isolation structure 106, the source 220, and the drain 222. It should be noted that the pMD layer 228 is a high-content content. The cerium content is higher than the cerium content of the telluride according to the stoichiometric composition, and includes cerium oxide, cerium oxynitride, cerium nitride or a combination thereof. When the dielectric layer is yttrium oxide, the ratio of enthalpy: oxygen is about (1.1 to 1.5) 2. The refractive index is about 1.5 to 17. When the dielectric layer is nitrided, the ratio of nitrogen to nitrogen is about (3. 丨~3 y. 4^ 97011/0516-A41819-TW/fmal 12 201017881 In addition, the sorghum content is reduced. Further, a dopant may be included, and the dopant includes a shed, a phosphorus, a ruthenium or a combination thereof. The method of depositing the ruthenium content of the ruthenium content and the control gas flow are the same as those in the above embodiment, and will not be described herein. Referring to FIG. 1F, an inter-layer dielectric layer (ILD) 230 is deposited over the pmd layer 228, wherein the ILD layer 230 may also be a germanium content of high germanium content. A plurality of metal contact plugs 232 are formed over the source 220 and the drain 222. Referring to FIG. 1G, a metal germanium line 234' is formed over the metal contact plug 232 and then deposited over the metal line 234. An inter-metal dielectric layer (IMD) 236, wherein the IMD layer 236 can also be a germanium compound having a high germanium content. The skilled person can deposit one or more layers of metal according to the actual needs. Internal wiring and IMD layer. 凊 See Figure 1H' when multi-layer metal layer After the formation, a protective layer 238 is formed on the last metal line 234. It should be noted that the protective layer can also be a germanium content of high germanium content to more effectively reduce the influence of hydrogen and moisture to improve The stability of the threshold voltage. m. The PMD layer, ILD layer, IMD layer or protective layer in the above embodiments is not limited to depositing only one layer of germanium with a high content of germanium. In addition, multiple layers of germanium can be deposited according to the needs of the process. The content of bismuth compound to more effectively separate hydrogen and water gas. In the double-diffused MOS structure of the present invention, the pre-metallization dielectric layer (PMD) is composed of a high-stone content of the lithium, and the inner layer is dielectric. The layer (ILD), the inter-metal dielectric layer (IMD) and the protective layer (passivati〇 iayer) can also be composed of a high cerium content telluride, with a high cerium content of the lithograph 97011/0516-A41819-TW /final 13 201017881 can effectively block hydrogen and moisture in the process to improve the stability of the threshold voltage. Although the invention has been disclosed above in several preferred embodiments, it is not intended to limit the invention, in any technical field. With In general, the scope of protection of the present invention is defined by the scope of the appended claims, and the scope of the present invention is subject to the scope of the appended claims. 1A to 1D are a series of cross-sectional views for explaining the structure of an asymmetric double-diffused MOS semiconductor according to an embodiment of the present invention. FIGS. 1E to 1H are a series of cross-sectional views for explaining the symmetry of the embodiment of the present invention. The structure of double-diffused MOS. [Description of main components] 100~Semiconductor substrate ^ 102~P type epitaxial layer 104~P type well area 106~ isolation structure 108~N type buried layer 110~1st high pressure N type well area 112~high pressure P type well area 114~second high voltage N-type well region 116~source region 118~> and polar region 97011/0516-A41819-TW/final 14 201017881 120~ gate dielectric layer 12 2~ idle pole 124~PMD layer 126~ILD Layer 128 ~ metal contact plug 130 ~ metal line 132 ~ IMD layer 134 ~ protective layer reference 210 ~ first high pressure N type well area 212 ~ first high pressure P type well area 214 ~ second south pressure N type well area 216 ~ The second high-voltage P-type well region 218 to the third south-pressure N-type well region 220 to the source 222 to the drain 224 to the gate dielectric layer 226 to the gate 228 to the PMD layer 230 to the ILD layer 232 to the metal contact plug Plug 234~metal wire 236~IMD layer 238~protective layer 97011/0516-A41819-TW/final