201010021 九、發明說明： -【發明所屬之技術領域】 ' 本發明係有關於一種半導體封裝件及其製法，尤指一 種具良好散熱性之散熱型半導體封裝件及其製法。 【先前技術】 傳統導線架式半導體封裝件係於一導線架之晶片座 上接置一半導體晶片，再利用打線及封膠作業，以形成包 覆鮮線及該半導體晶片之封裝膠體；其中用以包覆晶片之 〇封裝膠體多為散熱性差之環氧樹脂（EpQxy Resin)類之材 料，因此半導體晶片於運作時所產生之熱量將無法經由封 裝膠體有效散逸至外界，造成熱量逸散效率不佳而影響到 半導體晶片之性能。 Μ參閱第1圖，為冑決前述傳統導線架式半導體封裝 件的散熱問題，業界遂發展出一種具外露晶片座之半導體 封裝件/其係將半導體晶片U湘轉Η黏置於導線架 ❹晶月座121上，再進行打線及封膠作業，以使該半 導體晶片η透料線14電性連接至該導線架12之導腳 ’並形成包覆該銲線14及半導體晶片u之封裝膠體 15’其中相較於傳統導線架式半導體封裝件最大之差里點 = Ϊ架12之晶片座121外露出該封裝膠體…以 曰：：卜：晶片座之半導體封裝件，後續即可將該具外露 +導體封裝件透過銲錫16電性連接至 =上敌並使該外露之^座⑵透過該銲錫“ J = 〜電路板17之-接地面（grmjndplane)⑺上，進而使 111015 5 201010021 該半導體晶片π運作時所產生之熱量得以透過該晶片座 • 121而傳導至該接地面171，以有效解決傳統導線架式半 .導體封裝件散熱不佳問題。該種具外露晶片座之半導體封 -裝件技術可參見美國專利第5,252,783、、 6’143’981、6, 583, 499、6, 661，083、6, 818, 973 及 6, 400, 004 號案。 然而前述具外露晶片座之半導體封裝件仍存在著些 許問題’主要係因為前述半導體晶片運作時所產生的敎量 〇傳遞路徑是經由晶片表面、晶片矽基板、銀膠、晶片座、 録錫至電路板之接地面，以進行熱量之逸散，惟該熱量逸 散途徑中所通過各元件之彼此間界面均構成影響熱量逸 散之熱阻（theorni resistance)，其中該晶片㈣基板） 之熱阻約為0.5t：/W，晶片座(主要材質為銅)之熱阻約為 銀膠之熱阻約為1(M代/w，且該熱阻⑻之 β异公式為R=L/(KA)，其中該L代表熱量通過之元件厚 ❺度’A代表熱量通過之元件㈣，κ代表導熱係數（让⑽^ c〇= vi ty)，由該計算公式中明顯可知，當L(熱量通 ^之轉厚度）愈大時，熱阻愈高，愈不利於散熱。 因此，如何有效減少半導體晶片熱量通過之元件厚 t，實即效減少熱阻，進而提升㈣體w之散熱效 量之课題為解決半導體封裝件散熱問題所亟待考 【發明内容】 有鐘於上述習知技術之缺點，本發明之主要目的係提 111015 6 201010021 供-種散熱型半導體件及其製法，得以有效減少半導 體封裝件之熱阻’進而提升散熱效率。 為達上述目的’本發明揭露—種散熱型半導體封裝 件’係包括：導線架，該導線架具有一晶片座及設於該晶 片座周圍之複數導腳；金屬層，係佈設於該晶片座上；至 少一半導體晶片’係接觸且承載於該金屬層上；銲線，電 性連接該半導體晶片及該導腳；以及封裝膠體，包覆該銲 ❹ 半導體晶片及部分導線架，並至少使該晶片座底面及 導腳部分面積外露出該封裝膠體。 s金屬層係可由複數金屬線所構成’該金屬線可經由 、、友機進行銲接作業所製得，$外該金屬線亦可經由電 f物理A積、化學沈積作業所製得’且該複數金屬線可 水平方向、垂直方向、斜向、交叉網狀、或任意排列方 ，再者該複數金屬鍊外圍所構成之面積係可選擇大於、 $於或小於半導體晶片之平面投影面積。此外，該金屬層 ❹ 複數金屬塊所排列形成。構成該金屬層之該金屬線 之線把約為η β 1 ^ 1馬0.8〜L WHS(密爾），該金屬塊之厚度約為 υ· 8十 5mils。 該半導體晶片係透過導熱黏著層黏置於該晶片座 准使該半導體晶片直接接觸該晶片座上之金屬層。 赵.^發明復揭露-種散熱型半導體封裝件之製法，係包 .提供—導線架，該導線架具有一晶片座及設於該晶片 ::圍之複數導腳;於該晶片座上佈設-金屬層；將至少 一導體晶片黏置於該晶片座上，並使該半導體晶片直接 111015 7 201010021 接觸該金屬層；電性連接該半導體晶片及該導腳；以及形 -成包覆該半導體晶片及部分導線架之封裝膠體，並至少使 該晶片座底面及導腳部分面積外露出該封裝膠體。 ‘ 該金1層之製法係可利射了線機銲接複數條金屬線 ；所形成，亦或經由電鍍、物理沈積、化學沈積等方式形成 -複數條金屬線，其中該複數金屬線可以水平方向、垂直方 :向、斜向、交叉網狀結構、或任意形式進行排列，且該複 數金屬線外圍所構成之面積係可選擇大於、等於或小於半 ❹導體晶片之平面投影面積。此外’該金屬層亦可由複數金 屬塊所排列形成。另外，該半導體晶片與該晶片座間復包 括有導熱黏著層，惟使該半導體晶片直接接觸該金屬層。 因此’本發明之散熱型半導體封裝件及其製法係在 線架之晶片座上形成由複數條金屬線（或金屬塊）所構成 之金屬層，以於該晶片座上黏著半導體晶片時，使 體晶片直接接觸該金屬線（或金屬塊）’如此相較於習知具 外露晶片座之半導體封裝件中半導 、 © 干^體日日片透過銀膠而接 ;曰曰片座上之結構，本發明透過導熱性較佳，且厚产 金屬線(或金屬塊)，將可有效減少半“ Z片運作時產生之熱量所通過元件之厚度，同時有效 …阻，進而提升半導體晶片散熱效率。 【實施方式】 以下係藉由特定的具體實施例說明本發明之 式’熟悉此技蟄之人士可由本說明書所揭示之内 瞭解本發明之其他優點與功效。 二 Π1015 8 201010021 第一實施例： ' 叫參閱弟2A至2E圖，係為本發明之散熱型半導體封 ，裝件及其製法第一實施例之示意圖。 . 如第2A圖所示，首先提供一導線架22,該導線架22 .具有一晶片座221及設於該晶片座221周圍之複數導腳 222 ° 如第2B及2B’圖所示，其中該2B，圖係為對應第2B 圖之局部上視示意圖，接著於該晶片座221上佈設一金屬 ❹層20，該金屬層20例如由複數金屬線2〇1所構成，其可 利用打線作業所使用之打線機（Wireb〇nder) 28於該晶 片座221上銲接複數金屬線2〇1，亦即，該金屬線2〇ι之 製法係透過打線機28於該導線架22之晶片座221上利用 該打線機28銲嘴先將銲線形成一球型接點2〇la(baii bond) ’再移動該打線機28銲嘴至晶片座221另一區域， 接著截斷該銲線以形成縫接銲點（stitch b〇nd) 2〇ib， 睿重覆此步驟以於該晶片座221上銲接形成複數金屬線 201。該金屬線201之材質可為金（Au)、銅（Cu)、鋁（A1) 所組群組之其中一者。構成該金屬層之該金屬線201之線 控約為0· 8〜1 · 5mi 1 s (密爾）。 該金屬線201係可如本圖式呈水平狀排列。另外，該 金屬線201亦可由利用電鍍、物理沈積、或化學沈積等方 法形成於該晶片座221上。 如第2C及2C，圖所示，其中該2C，圖係為對應第％ 圖之局部上視示意圖，再於該晶片座221上對應該些金屬 g 111015 201010021 線2 01位置塗佈一例如銀膠之導熱黏著層2 3。201010021 IX. Description of the invention: - [Technical field to which the invention pertains] The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a heat-dissipating semiconductor package having good heat dissipation and a method of fabricating the same. [Prior Art] A conventional lead frame type semiconductor package is connected to a semiconductor wafer on a wafer holder of a lead frame, and then is used for wire bonding and sealing operations to form a packaged green wire and an encapsulant of the semiconductor wafer; The encapsulating colloids coated with the wafer are mostly EpQxy Resin materials with poor heat dissipation. Therefore, the heat generated by the semiconductor wafer during operation cannot be effectively dissipated to the outside through the encapsulant, resulting in no heat dissipation efficiency. Good affects the performance of semiconductor wafers. Referring to FIG. 1 , in order to solve the heat dissipation problem of the conventional lead frame type semiconductor package, the industry has developed a semiconductor package with an exposed wafer holder/the semiconductor wafer is transferred to the lead frame. On the crystal seat 121, a wire bonding and sealing operation is performed to electrically connect the semiconductor wafer η through-wire 14 to the lead leg of the lead frame 12 and form a package covering the bonding wire 14 and the semiconductor wafer u. The colloid 15' is the largest difference from the conventional lead frame type semiconductor package. The wafer holder 121 of the truss 12 exposes the encapsulant. The semiconductor package of the wafer holder can be subsequently The exposed + conductor package is electrically connected to the upper enemy through the solder 16 and the exposed seat (2) is transmitted through the solder "J = ~ the ground plane (grmjnd plane) (7) of the circuit board 17, thereby making 111015 5 201010021 The heat generated by the semiconductor wafer π is transmitted to the ground plane 171 through the wafer holder 121 to effectively solve the problem of poor heat dissipation of the conventional lead frame type semi-conductor package. The half of the exposed wafer holder The conductor seal-mounting technique can be found in U.S. Patent Nos. 5,252,783, 6' 143 981, 6, 583, 499, 6, 661, 083, 6, 818, 973 and 6, 400, 004. There are still some problems in the semiconductor package of the wafer holder. The main reason is that the throughput of the semiconductor wafer is transmitted through the wafer surface, the wafer substrate, the silver paste, the wafer holder, and the tin to the circuit board. The ground is used for heat dissipation, but the interface between the components passing through the heat dissipation path constitutes a theorni resistance which affects the heat dissipation, wherein the thermal resistance of the wafer (four) substrate is about 0.5. t:/W, the thermal resistance of the wafer holder (mainly copper) is about 1 (M generation/w), and the β-form of the thermal resistance (8) is R=L/(KA). Where L represents the thickness of the element through which the heat passes, 'A represents the element through which heat passes (4), and κ represents the thermal conductivity (let (10)^ c〇= vi ty), which is clearly known from the calculation formula, when L (heat pass) The larger the thickness is, the higher the thermal resistance is, which is not conducive to heat dissipation. Therefore, how to effectively reduce The heat of the semiconductor chip is reduced by the thickness of the component, so that the thermal resistance is reduced, and the heat dissipation effect of the (four) body w is improved to solve the problem of heat dissipation of the semiconductor package. [Summary of the Invention] Disadvantages, the main object of the present invention is to provide a heat-dissipating semiconductor device and a method for manufacturing the same, which can effectively reduce the thermal resistance of the semiconductor package and thereby improve the heat dissipation efficiency. To achieve the above object, the present invention discloses a heat dissipation. The semiconductor package includes: a lead frame having a wafer holder and a plurality of lead pins disposed around the wafer holder; a metal layer disposed on the wafer holder; at least one semiconductor wafer 'contacting and carrying On the metal layer; a bonding wire electrically connecting the semiconductor wafer and the lead; and an encapsulant covering the solder semiconductor chip and a portion of the lead frame, and at least exposing the bottom surface of the wafer holder and the lead portion The encapsulant is encapsulated. The s metal layer can be composed of a plurality of metal wires. The metal wire can be obtained by soldering work with a friend machine, and the metal wire can also be made by electric f physical A product and chemical deposition work. The plurality of metal lines may be horizontally, vertically, obliquely, cross-web, or arbitrarily arranged, and the area formed by the periphery of the plurality of metal chains may be selected to be larger than, smaller than, or smaller than the planar projected area of the semiconductor wafer. Further, the metal layer is formed by arranging a plurality of metal blocks. The line of the metal line constituting the metal layer is about η β 1 ^ 1 horse 0.8 to L WHS (mil), and the thickness of the metal block is about υ 8 10 mils. The semiconductor wafer is adhered to the wafer via a thermally conductive adhesive layer to directly contact the semiconductor wafer with the metal layer on the wafer holder. Zhao. The invention discloses a method for manufacturing a heat-dissipating semiconductor package, which is provided by a package. The lead frame has a wafer holder and a plurality of lead pins disposed on the wafer: the wafer holder is disposed on the wafer holder a metal layer; at least one conductor wafer is adhered to the wafer holder, and the semiconductor wafer directly contacts the metal layer 111015 7 201010021; electrically connecting the semiconductor wafer and the lead; and forming the semiconductor The encapsulant of the wafer and part of the lead frame, and at least the surface of the bottom surface of the wafer holder and the portion of the lead leg are exposed to the encapsulant. The gold 1 layer manufacturing method can be used to weld a plurality of metal wires by a wire machine; or formed by electroplating, physical deposition, chemical deposition, etc. - a plurality of metal wires, wherein the plurality of metal wires can be horizontally The vertical side is aligned, diagonally, crossed, or in any form, and the area formed by the periphery of the plurality of metal lines may be selected to be larger than, equal to, or smaller than the projected area of the semi-turned conductor wafer. Further, the metal layer may be formed by arranging a plurality of metal blocks. Additionally, a thermally conductive adhesive layer is included between the semiconductor wafer and the wafer holder such that the semiconductor wafer directly contacts the metal layer. Therefore, the heat-dissipating semiconductor package of the present invention and the method for manufacturing the same are formed by forming a metal layer composed of a plurality of metal wires (or metal blocks) on the wafer holder of the wire frame to bond the semiconductor wafer to the wafer holder. The wafer is in direct contact with the metal wire (or metal block). Thus, the semiconductor package in the semiconductor package having the exposed wafer holder is connected to the semiconductor through the silver paste; the structure on the wafer holder The invention has better thermal conductivity and thick metal wires (or metal blocks), which can effectively reduce the thickness of the components passing through the heat generated by the operation of the Z-chip, and at the same time effectively resist, thereby improving the heat dissipation efficiency of the semiconductor wafer. [Embodiment] The following is a description of the present invention by way of specific embodiments. Those skilled in the art can understand other advantages and effects of the present invention as disclosed in the present specification. II 1015 8 201010021 First Embodiment : ' Refer to the drawings 2A to 2E, which is a schematic diagram of the first embodiment of the heat-dissipating semiconductor package, the package and the method for manufacturing the same according to the present invention. As shown in FIG. 2A, first provided a lead frame 22 having a wafer holder 221 and a plurality of guide pins 222° disposed around the wafer holder 221 as shown in FIGS. 2B and 2B′, wherein the 2B is a map corresponding to FIG. 2B. In a partial top view, a metal germanium layer 20 is disposed on the wafer holder 221, and the metal layer 20 is composed of, for example, a plurality of metal wires 2〇1, which can be used by a wire bonding machine (Wireb〇nder) 28 for wire bonding work. A plurality of metal wires 2〇1 are soldered to the wafer holder 221, that is, the metal wire 2〇 is manufactured by the wire bonding machine 28 on the wafer holder 221 of the lead frame 22 by using the wire bonding machine 28 tip welding. The wire forms a ball joint 2〇la(baii bond)' and then moves the wire bonder 28 to another area of the wafer holder 221, and then cuts the wire to form a stitch joint (stitch b〇nd). Ib, Rui repeats this step to solder the wafer holder 221 to form a plurality of metal wires 201. The material of the metal wires 201 may be one of a group of gold (Au), copper (Cu), and aluminum (A1). The wire control of the metal wire 201 constituting the metal layer is about 0·8~1 · 5mi 1 s (mil). The metal wire 201 is The pattern is arranged horizontally. Alternatively, the metal line 201 may be formed on the wafer holder 221 by electroplating, physical deposition, or chemical deposition. As shown in Figures 2C and 2C, wherein the 2C, The figure is a partial top view corresponding to the % figure, and a thermal adhesive layer 23 such as silver paste is applied to the wafer holder 221 corresponding to the metal g 111015 201010021 line 2 01.
• 如第2D及2D，圖所示，其中該2D，圖係為對應第2D •圖之局部上視示意圖。提供至少一半導體晶片21，該半 *導體晶片由一晶片矽基板組成，且具有相對之主動面 ；211及非主動面212,並使該半導體晶片21以其非主動面 212間隔該導熱黏著層23而接置於該晶片座221上，同 ^使該半導體晶片21直接接觸該金屬線2〇1。 如第2E圖所示，進行打線作業’利用打線機形成電 ❹性連接該半導體晶片主動面211及導腳222之銲線24。 …接著，進行封裝模壓作業，以形成包覆該銲線24、 半導體晶片21及部分導線架之封裝膠體25，並至少使該 b曰片座221底面及導腳222部分面積外露出該封裝膠體 25，以形成具外露晶片座之半導體封裝件。 透過刚述製法，本發明復揭示一種散熱型半導體封裝 件二係包括：導線架22,該導線架22具有一晶片座22ι ❹及6又於該晶片座221周圍之複數導腳222;金屬層2〇，係 佈又於該日日片座上221 ’該金屬層2〇係由複數金屬線 斤構成，至^ 一半導體晶片21，係黏置於該晶片座22 J 上且使該半導體晶片21直接接觸該些金屬線2〇1 ;銲 線24，電性連接該半導體晶片21及該導腳;以及封 夕體25、用以包覆該銲線24、半導體晶片21及部分導 線架22 ’並至少使該晶片座221底面及導腳222部分面 積外露出該封裝谬體25。 清參閱第3圖，後續即可將本發明之散熱型半導體封 111015 10 201010021 裝件透過如銲錫之導電材料26接置並電性連接 板27之外«置’並使該半導㈣裝件外露出封裝勝體 、25之晶片座221亦得以透過該例如銲錫之導電材料⑼接 .^於電路板27之接地面271，以供該半導體晶片21運作 .時所產生之熱量得以由該半導體晶片主動面2ιι'曰片石夕 基板210、金屬線2(Π、晶片座⑵、鲜錫26至該^日路板 接地面271而進行逸散，其中由於本發明透過在導線架 22之晶片座221上形成複數條金屬線2〇ι，並使該半導體 ©y 21直接接觸該金屬線2()1，如此相較於習知具外露 ，片座之半導體封裝件中半導體晶片透過銀膠而接置於 晶片座之結構，本發明透過導熱性較佳，且厚度較低，熱 阻較小之金屬線，將可減少熱量通過之元件厚度，同時有 效減少熱阻，進而提升半導體晶片之散熱效率。 弟一貫施例： 請參閱第4圖’係為本發明之散熱型半導體封裝件第 ❹二實施：之示意圖。 、 本實施例與前述實施例大致相同’主要差異在於設於 導線架之晶片座321上的金屬層亦可由複數金屬塊3〇1 所構成’以供半導體晶片31黏置於該晶片座321上，同 時接觸該些金屬塊301，該金屬塊301係可利用打線機直 接一接形成球形接點所製得，亦或透過電鑛、物理沈積、 化學沈積等方式製得。構成該金屬層之該金屬塊301之厚 度約為0.8〜1.5mils。 第三實施例： 11 111015 201010021 係為本發明之散熱型半導體封 請參閱第5A至5C圖 裝件第三實施例之示意圖 • 本實施例與前述貴祐在丨t , j k Λ ^例大致相同，主要差異在於設於 ‘ 座421上的金屬層係由複數條金屬線4〇1 2構成且相&於第2C ϋ之水平排列外，該複數條金屬 線4〇1亦可呈垂直排列（如第5Α圖所示）、斜向排列（如第 5B圖所示）、或交叉網狀排列(如第5C圖所示）。 我 t然該些複數金屬線之排列方式非以前述圖式為 ©限’亦可呈現前述排列方式之組合，或呈不規則排列。 第四實施例： 請參閱第6A及6B圖，係為本發明之散熱型半導體封 裝件第四實施例之示意圖。 本實施例與前述實施例大致相同，主要差異在於設於 導線架之晶片座5 21上的複數金屬線5 G!外圍所構成之面 積除可大於半導體晶片之平面投影面積外，亦可等於（如 第6A圖所示）或小於（如第6B圖所示）半導體晶片51之平 面投影面積。 力因此，本發明之散熱型半導體封裝件及其製法係在導 線架之晶片座上形成由複數條金屬線（或金屬塊）所構成 之金屬層，以於該晶片座上黏著半導體晶片時，使該半導 體晶片直接接觸該金屬線（或金屬塊），如此相較於習知具 外露晶片座之半導體封裝件中半導體晶片透過銀膠而接 置於晶片座上之結構，本發明透過導熱性較佳，且厚度較 低，熱阻較小之金屬線（或金屬塊），將可有效減少半導體 111015 12 201010021 ▲上述實施例僅為例示十生說明I發明之原理及其功 效’而非用於限制本發明。任何熟f此項技藝之人士料 在不違背本發明之精神及_下，對上述實_進行修飾 與變化。因此，本發明之權利保護範圍，應如後述之申請 專利範圍所列。 【圖式簡單說明】 © » 1 ®係為習知具外露晶片座之半導體封裳件示意 圖； 第2A至2E圖係為本發明之散熱型半導體封裝件及其 製法第一實施例之示意圖； 第2B’圖係為對應第2B圖之局部上視示意圖； 第2C圖係為對應第·2C圖之局部上視示意圖； 第2D’圖係為對應第2D圖之局部上視示意圖； 第3圖係為本發明之散熱型半導體封裝件接置於電 路板之不意圖； 第4圖係為本發明之散熱型半導體封裝件第二實施 例之示意圖； 第5A至5C圖係為本發明之散熱型半導體封裝件第三 實施例之示意圖；以及 第6A及6B圖係為本發明之散熱型半導體封裝件第四 實施例之示意圖。 【主要元件符號說明】 13 111015 201010021 11 半導體晶片 .12 導線架 ,121 晶片座 122 導腳 13 銀膠 14 鲜線 15 封裝膠體 16 銲錫 ©I7 電路板 171 接地面 20 金屬層 201,401,501 金屬線 201a 球型接點 201b 縫接銲點 21, 31,51 半導體晶片 210 矽基板 w211 主動面 212 非主動面 22 導線架 221,321,421,521 晶片座 222 導腳 23 導熱黏著層 24 鲜線 25 封裝膠體 201010021 26 導電材料 -27 電路板 .271 接地面 .28 打線機 .301 金屬塊 〇 ❹ 15 111015• As shown in Figures 2D and 2D, the 2D is a partial top view corresponding to the 2D map. Providing at least one semiconductor wafer 21 composed of a wafer substrate and having opposite active surfaces; 211 and an inactive surface 212, and spacing the semiconductor wafer 21 by the inactive surface 212 of the thermally conductive adhesive layer 23 is placed on the wafer holder 221 to directly contact the semiconductor wafer 21 with the metal line 2〇1. As shown in Fig. 2E, the wire bonding operation is performed to form a bonding wire 24 electrically connecting the semiconductor wafer active surface 211 and the lead pins 222 by a wire bonding machine. Then, a package molding operation is performed to form the encapsulant 25 covering the bonding wire 24, the semiconductor wafer 21 and a part of the lead frame, and at least the bottom surface of the b-pad holder 221 and the portion of the guiding leg 222 are exposed to the encapsulant. 25, to form a semiconductor package with an exposed wafer holder. The present invention discloses a heat-dissipating semiconductor package, which includes a lead frame 22 having a wafer holder 22 and a plurality of lead pins 222 around the wafer holder 221; a metal layer. 2〇, the fabric is further 221' on the day seat. The metal layer 2 is composed of a plurality of metal wires, and the semiconductor wafer 21 is adhered to the wafer holder 22 J and the semiconductor wafer is bonded. 21 directly contacting the metal wires 2〇1; a bonding wire 24 electrically connecting the semiconductor wafer 21 and the guiding pin; and a sealing body 25 for covering the bonding wire 24, the semiconductor wafer 21 and a part of the lead frame 22 'At least the bottom surface of the wafer holder 221 and the portion of the lead 222 are exposed to the package body 25. Referring to FIG. 3, the heat-dissipating semiconductor package 111015 10 201010021 of the present invention can be subsequently connected through the conductive material 26 such as solder and electrically connected to the outside of the board 27 and the semi-conductive (four) package is mounted. The wafer holder 221 of the outer package body 25 is also connected to the ground plane 271 of the circuit board 27 through the conductive material (9) such as solder for the semiconductor wafer 21 to operate. The active surface of the wafer 2 ιι' 曰 石 夕 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 A plurality of metal wires 2 〇 are formed on 221, and the semiconductor © y 21 is in direct contact with the metal wires 2 (1). Thus, the semiconductor wafer in the semiconductor package of the chip holder passes through the silver paste in comparison with the conventional one. According to the structure of the wafer holder, the present invention can reduce the thickness of the component through which the heat passes through the metal wire with better thermal conductivity and lower thickness and less thermal resistance, and at the same time effectively reduce the thermal resistance, thereby improving the heat dissipation of the semiconductor wafer. Efficiency. Example: Please refer to FIG. 4, which is a schematic diagram of the second embodiment of the heat-dissipating semiconductor package of the present invention. This embodiment is substantially the same as the previous embodiment. The main difference is that the wafer holder 321 is provided on the lead frame. The upper metal layer may also be formed by a plurality of metal blocks 3〇1 for the semiconductor wafer 31 to be adhered to the wafer holder 321 while contacting the metal blocks 301, which may be directly formed by a wire bonding machine. The spherical joint is obtained or obtained by electrowinning, physical deposition, chemical deposition, etc. The thickness of the metal block 301 constituting the metal layer is about 0.8 to 1.5 mils. Third embodiment: 11 111015 201010021 For the heat-dissipating semiconductor package of the present invention, please refer to the schematic diagram of the third embodiment of the assembly of FIGS. 5A to 5C. This embodiment is substantially the same as the above-mentioned example of 佑t, jk Λ ^, and the main difference is that it is located in the '座421 The upper metal layer is composed of a plurality of metal wires 4〇1 2 and the phase & is arranged horizontally at the second C ϋ, and the plurality of metal wires 4〇1 may also be vertically arranged (as shown in FIG. 5). Oblique alignment (such as 5B shows), or cross-mesh arrangement (as shown in Figure 5C). I have to say that the arrangement of the plurality of metal lines is not limited to the above-mentioned pattern, and may also be a combination of the foregoing arrangements, or The fourth embodiment is a schematic view of a fourth embodiment of the heat dissipation type semiconductor package of the present invention. This embodiment is substantially the same as the foregoing embodiment, and the main difference is that it is provided in FIG. 6A and FIG. The area of the plurality of metal wires 5 G! on the wafer holder 5 21 of the lead frame may be equal to or larger than (as shown in FIG. 6A) or smaller than (for example, FIG. 6B). The plane projected area of the semiconductor wafer 51 is shown. Therefore, the heat dissipation type semiconductor package of the present invention and the method for manufacturing the same are formed on a wafer holder of a lead frame to form a metal layer composed of a plurality of metal wires (or metal blocks) for bonding a semiconductor wafer to the wafer holder. The semiconductor wafer is directly in contact with the metal wire (or metal block), and the thermal transmission property of the present invention is compared with the structure in which the semiconductor wafer in the semiconductor package having the exposed wafer holder is connected to the wafer holder through the silver paste. Preferably, the metal wire (or metal block) having a lower thickness and a lower thermal resistance will effectively reduce the semiconductor 111015 12 201010021 ▲ The above embodiment is merely illustrative of the principle and effect of the invention of the invention. To limit the invention. Any person skilled in the art will be able to modify and change the above described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application to be described later. [Simple description of the drawings] © 1 1 is a schematic diagram of a semiconductor package with an exposed wafer holder; 2A to 2E are schematic views of a heat dissipation type semiconductor package of the present invention and a first embodiment thereof; 2B' is a partial top view corresponding to FIG. 2B; 2C is a partial top view corresponding to the 2C chart; 2D' is a partial top view corresponding to the 2D picture; FIG. 4 is a schematic view showing a second embodiment of the heat dissipation type semiconductor package of the present invention; FIGS. 5A to 5C are diagrams of the present invention; A schematic diagram of a third embodiment of a heat dissipation type semiconductor package; and FIGS. 6A and 6B are schematic views of a fourth embodiment of the heat dissipation type semiconductor package of the present invention. [Main component symbol description] 13 111015 201010021 11 Semiconductor wafer. 12 lead frame, 121 wafer holder 122 lead pin 13 silver glue 14 fresh wire 15 package colloid 16 solder ©I7 circuit board 171 ground plane 20 metal layer 201,401,501 metal wire 201a spherical Contact 201b splicing solder joints 21, 31, 51 semiconductor wafer 210 矽 substrate w211 active surface 212 inactive surface 22 lead frame 221, 321, 421, 521 wafer holder 222 lead 23 thermal adhesive layer 24 fresh wire 25 encapsulant 201010021 26 conductive material -27 circuit Board .271 Ground plane .28 Wire machine .301 Metal block 〇❹ 15 111015