TW201007891A - Dielectric layer above floating gate for reducing leakage current and method of forming the same - Google Patents

Abstract

A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

Description

201007891 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a non-volatile memory device. Reference is also made to the following application and is incorporated herein by reference in its entirety:

U.S. Patent Application No. _ [Summary File No. SAND-01336US0] of James Kai et al., entitled "METHOD OF FORMING DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT", was filed on the same day. [Prior Art] Semiconductor memory devices are increasingly used in various electronic devices. For example, non-volatile semiconductor memory can be used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable programmable read only memory (EEPROM) and flash memory are the most popular non-volatile semiconductor memories. A typical EEPROM and flash memory utilizes a memory cell having a floating gate. The floating gate is provided over a channel region in a semiconductor substrate. The net moving gate is separated from the channel region by a dielectric region. For example, the channel region is located in a p-well between the source region and the non-polar region. A control gate is separated from the floating gate by another dielectric region (inter-gate or polycrystalline inter-lithium dielectric). The threshold voltage of the memory cell is controlled by the amount of charge remaining on the floating gate. That is, the charge level on the floating gate determines the minimum amount of voltage that must be applied to the control gate before the memory cell conducts to allow conduction between its source and drain. 141462.doc 201007891 - Some EEPRQM and fast pg memory devices have a floating gate for storing two charge ranges and thus can be programmed/erased between the two states (eg, - binary) Memory unit). - Multi-bit or multi-state flash memory cells are implemented by identifying a plurality of different voltage ranges within the device. Each of the different threshold voltage ranges corresponds to the value of the data bits of the group. In order to achieve the correct (four) storage of the multi-state unit: the plurality of thresholds must be separated from each other so that the memory unit can be read, programmed or erased in a clear manner. Level. When stylizing a typical flash memory device, 'apply a stylized voltage to the control gate and ground the bit line 4 to the capacitance between the control gate and the floating open, thus controlling the program on the gate The voltage is combined to the gate of the gate' to cause a floating gate voltage. This floating gate voltage causes electrons to be injected from the channel into the floating gate. #电子 accumulates in the floating open pole. The floating gate becomes a negatively charged and the memory unit δ» limit voltage rises from the control gate. In order to maintain the programmed state of the memory cell, it is necessary to maintain the charge on the floating gate at any time. However, charge can leak through the polysilicon dielectric from the floating gate to the control gate 15, which is referred to as the leakage current. / In the latest flash memory technology, short stylization/erasing times and low operating voltages overcome the main obstacles to achieving high speed and density and low power operation. Therefore, it is increasingly necessary to increase the capacitive coupling between the floating gate of the memory cell and the control gate while suppressing the escape of the electronic self-floating gate to the control gate. Control gate and floating that affect the coupling ratio 14I462.doc 201007891 The capacitance between the gates depends on the thickness of the polysilicon dielectric (IPD) between the two gates and the relative permittivity or dielectric constant κ of ipd. One technology used to achieve a high coupling ratio uses a thin IPD. However, if the IPD is too thin, the leakage current can become undesirably large. As non-volatile memory structures become smaller and smaller, leakage currents are becoming more and more difficult. One cause of leakage current problems is the strength of the electric field that occurs in various parts of the IPD when a voltage is applied to the control gate. In particular, the electric field is enhanced in certain regions of the IPD, resulting in a large leakage current. Referring to Figure 1A, the electric field is strongest in the IPD 106 near the sharp corners of the floating gate 102 and the control gate 1〇4. Being close! !^ 106 The area of the rounded corner is the ratio of the electric field to 1/A, where a is the radius of curvature of the corner of the floating gate 102. It should be noted that a sharp angle corresponds to a very small radius of curvature and thus a strong electric field. To reduce the electric field strength in the IPD 106 at the corners of the floating gate 102, the radius of curvature of the top of the floating gate 102 can be increased, as depicted in Figure 1B. It should be noted that this also changes the curvature of the control gate 1〇4. The current is reduced by reducing the electric field strength. However, in order to continue to scale down the size of the device structure, the width of the floating gate 102 needs to be narrowed, as depicted in Figure 1c. It should be noted that the spheronized polysilicon floating gate 1 〇 2 extends completely across the top of the floating gate 102 of the Figure IC. The possible rounding amount of the floating gate 丨〇2 is limited by the width of the floating gate 102. That is, the maximum possible radius of curvature (A) is limited to one half of the width of the floating gate 102. It should be noted that if the width (2A) of the floating gate ι is further reduced, the maximum possible radius of curvature is further reduced. Therefore, as the size of the memory cell continues to decrease, IPD 1 〇6 Yinzhi 141462.doc 201007891 The electric field and therefore the leakage current also become more difficult to handle. • One technique for reducing the electric field forms the IPD 106 with a thin film having a high dielectric constant. However, this thin article is difficult to use and therefore undesirable. For example, a paraelectric material has a dielectric constant that is generally higher than at least two values of ceria, but several problems limit its use as a gate dielectric. One such problem is oxygen diffusion. During the high temperature process associated with semiconductor fabrication, oxygen diffuses from the IPD 106 to the interface between the IPD 1〇6 and the floating gate 102 and the control gate 104 that sandwiches the IPD 106, thus creating an undesirable degradation. The total capacitive oxide layer of the electrical system. Therefore, the effect of high dielectric constant paraelectric materials is reduced. Metal oxides are also proposed as sorghum materials for flash memory devices. Metal oxides (specifically, Oxide (Al2〇3)) have a low dew current. Moreover, metal oxides have high temperature durability for process integration. However, since such deposited high dielectric metal oxides have a non-stoichiometric composition, they tend to form large electrical defects or (d) in most dielectrics and at dielectric/semiconductor interfaces. These defects or (d) enhance the conduction through the dielectric and reduce the breakdown strength of the dielectric. Another technique used to reduce the amount of IPD 106 in the IPD of the IPD is to increase the thickness of the IPD 106. However, the increase in the thickness of the IPD 1〇6 is greater in thickness, and the capacitive coupling between the floating gate 102 and the control gate 106 is reduced, and the valley coupling, for the reasons previously discussed, unexpected. In general, increasing the thickness of the IPD 106 when the curvature radius of the field is less than the thickness of the IPD 106 or when the thickness of the IPD 106 is close to the size of the A hidden body ("feature size") often fails. SUMMARY OF THE INVENTION 141462.doc 201007891 Embodiments in accordance with the present disclosure are generally related to a non-volatile <RTI ID=0.0>> The memory cell has a dielectric cover on the floating gate. In one embodiment, the dielectric cover resides between the floating gate and a conformal IPD layer. The dielectric cover reduces leakage current between the floating gate and a control gate. The dielectric cover achieves leakage current reduction by reducing the intensity of the electric field at the top of the floating gate, in the absence of the dielectric cover for a floating gate having a narrow stem, the floating gate At the top of the pole, the electric field will be the strongest. Another embodiment is a method for making a non-volatile storage element. The mysterious method includes forming a floating gate having a top and at least two sides. A dielectric cover is formed at the top of the floating gate. An inter-gate dielectric layer is formed around at least two sides of the floating gate and over the top of the dielectric cover. A control gate is formed over the top of the floating gate, the inter-gate dielectric separating the control gate from the floating gate. • In one aspect, forming the dielectric cap includes implanting oxygen into the top of the floating gate and heating the floating gate to form a dielectric cap from the implanted oxygen and the word-forming gate formed therefrom cover. These and other objects and advantages will be more apparent from the following description of the various embodiments illustrated herein. [Embodiment] An example of a flash memory system uses a NAND structure including a plurality of floating gate transistors arranged in series between two select gates. ^ The series transistor and the selected gate are called a NAND string. 141 141462.doc 201007891 A typical architecture for a flash memory system in a NAND architecture will contain several NAND strings. For example, Figure 2 shows three NAND strings 202, 204, and 206 having one memory array of more NAND strings. Each of the NAND strings of Figure 2 includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226, and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246, and 248. Each NAND string is connected to the source line by its selection transistor (e.g., select transistor 230 and select transistor 250). A source line SGS is used to control the source side selection gate. The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., controlled by selected line SGD. In other embodiments, the selection lines do not have to be common. Word line WL3 is coupled to the control gates of memory unit 222 and memory unit 242. Word line WL2 is coupled to control gates of memory unit 224, memory unit 244, and memory unit 252. Word line WL1 is coupled to the control gates of memory unit 226 and memory unit 246. Word line WL0 is coupled to the control gates of memory unit 228 and memory unit 248. Thus, each bit line and corresponding NAND string includes a number of rows of a memory cell array. Word lines (WL3, WL2, WL1, and WL0) include a number of columns of the array. Figure 3 is a top plan view of a portion of a NAND flash memory cell array. The array includes bit line 350 and word line 352. It should be noted that Figure 3 does not show all of the other details of the flash memory unit. It should be noted that a NAND string can have fewer or more memory cells than the memory cells illustrated in Figures 2 and 3. For example, some NAND strings 141462.doc 201007891 will contain 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, and the like. The discussion herein does not limit the memory cells in a NAND string to any particular number. In addition, a word line can have more or fewer memory cells than the memory cells illustrated in Figures 2 and 3. For example, a word line can contain thousands or tens of thousands of memory cells. The discussion herein does not limit the memory cells in a word line to any particular number.

Each memory unit can store analog data or digital data. When a digital data bit is stored, the possible threshold voltage range of the memory cell is divided into two ranges, and logical data "丨" and "〇" are assigned to the two ranges. In one example of a NAND flash memory, the threshold voltage is negative after the erase of the memory cell and is defined as a logical "丨". After the stylization, the threshold voltage is the logical "Q". When the threshold power is negative and a read is attempted by applying a stagnation to the control pole, the memory unit will be turned on to indicate that the logic is being stored and when the threshold is positive and by the control gate When a 0 volt is applied to attempt a read job, the memory unit will not turn on 'this indication stores the logic 〇.

In the case of storing more than one data level, this γ A month will be able to divide the threshold voltage range into the number of breeding levels. For example, while storing four information levels (two stock levels) on the right, there will be four thresholds for the lean value of "1 1 , 10" 〇 1" and ^ 〇〇 |$|=| , Recalling the body - in an example, in the - bar except the work pressure 11 circumference. It is defined as "U" in NA Qingji. If the positive threshold voltage is used for ^ after _ voltage is negative / is 14I462.doc 201007891 data bits), there will be eight assigned data values "〇〇〇"001", "010", "〇11", The threshold voltage range of "1", "1"1, "110" and "111". The specific relationship between the data stylized into the memory unit and the threshold voltage level of the memory unit depends on the data encoding scheme employed for the units. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, the entireties of each of each of each of each of each Encoding Scheme In an embodiment, a data value is assigned to the threshold voltage ranges using a Gray code assignment scheme such that if the threshold voltage of a floating gate is erroneously shifted to its neighboring physical state, only one The bit will be affected. In some embodiments, the data encoding scheme may be changed for different word lines, the data encoding scheme may change over time, or the data bits of the random word line may be inverted or otherwise randomized to reduce data sensitivity and even Wear of the memory unit. NAND-type flash memory and related examples of operations are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Patent No. 5,57 No. 315; U.S. Patent No. 5,774,397; U.S. Patent No. 6,046,935; U.S. Patent No. 456,528; and U.S. Patent Publication No. US Pat. No. 2/3,348. The descriptions herein may also apply to other types of flash memory other than NAND, as well as other types of non-volatile memory. For example, the following patents describe NOR-type flash memories, and are incorporated herein by reference in their entirety. U.S. Patent No. 5, 〇95,344; 5,172,338; 5,890,192 141462.doc -10 - 201007891 ; and 6, 151, 248. 4A and 4B are two-dimensional block diagrams of one embodiment of a non-volatile storage element array. Figure 4 shows a cross section (cross section along the word line) of the memory array along the tangent to Figure 3. Figure 4B shows a cross section (cross section along the bit line) of one of the memory arrays along the tangent line B-B. The memory cell of Figures 4A and 4B includes a triple well (not shown) including a -P substrate, a well and a p-well. In the p-well, a number of N+ diffusion regions 444 are used as source/depolarization. Whether the N+ diffusion region is marked as a source region or a drain region is arbitrary to some extent; therefore, the source/drain region 444 can be regarded as a source region, a drain region, or both. In a NAND string, a source/drain region 444 acts as one of the memory cells and serves as one of the adjacent memory cells. A channel 446 between the source/drain regions 444. A first dielectric region 410 on channel 446 is otherwise referred to as a gate oxide. In one embodiment, the dielectric layer 410 is made of Si〇2. Other dielectric materials can also be used. On the dielectric layer 410 is a floating gate 412. The floating idler is electrically isolated/isolated from the via 446 by the dielectric layer 41A under low voltage operation associated with a read or bypass operation. The floating gate 412 is typically made of polysilicon doped with a dopant of the type; however, other conductive materials such as metals may also be used. A dielectric cover 408 is attached to the floating gate 412. A second dielectric layer 406, also referred to as an IPD 4〇6, is placed on top of the floating gate 412 and on the side of the floating gate 412. A polysilicon control gate 404 is provided on IPD 4〇6. The control gate 4〇4 may comprise an additional layer of a tungsten germanium (WSi) layer and a tantalum nitride (3) layer. A wsi layer is a lower resistance layer, and a SiN layer acts as an insulator of 141462.doc -11 - 201007891. Dielectric layer 410, floating gate 412, dielectric cap 408, IPD 406, and control gate 404 form a floating gate stack. A memory cell array will have many of these floating gate stacks. In another embodiment, a floating gate may have more or fewer components than those illustrated in Figures 4 and 4B. However, a floating gate stack is named because it contains a float. Gate and other components. Referring to Figure 4A, a shallow trench isolation (STI) structure 407 provides electrical isolation between strings of memory cells. In particular, an STI 4〇7 separates the source/drain regions of one NAND string from the next NAND string (not shown in Figure 4A). In one embodiment, 'STI 407 is filled with Si〇2. In FIGS. 4A and 4B, the floating gate has an "inverted τ" shape. That is, the floating gate has a base 412b and a stem 412a. The inverted shape helps to increase the area of portions of the floating gate 412 that coincide with the control gate 404 while allowing the floating gates 412 to be closely spaced together. In this example, one of the floating gates taken along the word line has an inverted τ shape. In another embodiment, the cross-section taken along a bit line follows a collapsed shape. For example, the floating gate in Figure 4Β will have an inverted τ shape. However, do not require the floating gate to have an inverted τ shape. In general, any floating gate having a top and sides separated by an IPD from a control gate may benefit from a dielectric cover located above the top of the floating gate. However, a floating gate having a relatively thin width in at least one direction can be more susceptible to the high electric field problem and thus can receive a greater benefit from a dielectric cover. 141462.doc •12· 201007891 The stem 412a of the floating interpole 412 is not required to have a relative mean width as illustrated in FIG. In the -# embodiment, the floating gate loyalty 412a is narrower near the bottom of the dielectric cover than the bottom of the base of the floating junction. Techniques for reducing the electric field strength in certain regions of IPD 406 are disclosed herein. One of the floating gates 412 has an arrow labeled "Top Field" which refers to the electric field in IpD 4〇6 on top of the floating gate 412. The arrow labeled "corner field" refers to the electric field in IPD 406 near the top corner of floating gate 412. In some embodiments, the electric field strength at the top of the floating gate 412 is reduced by the dielectric cap 408 such that it is less than (or at least not greater than) the electric field strength at the corners of the floating gate 412. However, the electric field at the top of the floating gate 412 is not required to be weaker than the electric field at the corner of the floating gate 412. For example, the dielectric cover 4〇8 can be used to weaken the electric field at the top of the floating gate 412 to some extent, but it is not necessary to weaken the electric field such that the electric field is weaker than the electric field at the corner of the floating gate 412. . Reducing the electric field strength at the top of the floating pole reduces the total leakage current without significantly affecting the overall efficiency. Figure 5 is a flow diagram illustrating one embodiment of a process for fabricating the memory cells of Figures 4A and 4B. Figures 6A-6J illustrate memory cells at various stages of the process. The process of Figure 5 is illustrated in relation to the reference numbers from Figure 4A and Figure 6A-6J. Figures 6A-6J illustrate a cross section along line -8 of Figure 3. In this example, a floating gate is relatively narrow when viewed in a lateral direction taken along a word line. It should be noted, however, that the principles discussed herein apply to a narrow floating gate when viewed in a cross section along the bit line or word line and bit line 141462.doc -13 - 201007891. This flow chart does not describe all implantation steps, gap filling of the etched volume between floating gate stacks, or formation of contacts, metallization, vias, and purification, as well as other portions of the fabrication process known in the art. There are many methods for fabricating a memory according to the present invention' and thus the inventors expect to use various methods other than those described by Figure 5. When the _flash memory chip will contain core memory and peripheral circuitry, the process steps of Figure 5 are intended only to describe in general terms one possible process recipe for fabricating a core memory array. Step 502 of Figure 5 includes growing a tunnel oxide layer 604 on top of a substrate 6〇2. The tunnel oxide layer 6〇4 will be used to form the gate dielectric layer 410. In step 504, a polysilicon layer 606 for forming a floating gate 412 is deposited over the oxide layer 604 using CVD, PVD, ALD, or another suitable method. In step 505, a second oxide layer 608 is grown on top of the polysilicon 6〇6. This second oxide layer 6〇8 will be used to form the dielectric cap 408. In step 506, a SiN layer is deposited over the second oxide layer 6A8. SiN can be deposited by, for example, CVD. In step 508, a photoresist is added. For example, a spacer process is used to define an amorphous germanium pattern 612. The 矽 pattern 612 is transferred to the nitride hard mask 610 in step 508. Step 5 10 includes etching the nitride hard mask 610 using an anisotropic plasma etch (i.e., 'reactive ion etching). The results of steps 502-510 are illustrated in FIG. 6A, which shows the nitride hard mask remaining after the germanium substrate 402, the first oxide layer 604, the polycrystalline layer 606, and the second oxide layer 608' Cover 610 and amorphous 矽 pattern 612. 141462.doc • 14· 201007891 After the hard mask layer 610 is pasted, the photoresist 612 is stripped in step 512 and the hard mask layer 610 can be used as a mask for etching the underlying layer. Step 514 includes etching through a portion of the second oxide layer 6〇8 and the polysilicon 606 to form a stem 412a of the floating gate 412. For each planar layer encountered, the etching can be performed using an anisotropic plasma etch with an appropriate balance between physical and chemical etching. The remaining portion of the second oxide layer 6〇8 after etching will form the dielectric cap 4〇8. Techniques for stopping etching polysilicon 606 at a suitable depth are known in the art. An example technique for stopping the etching of polysilicon can be found in the following U.S. Patent Application: U.S. Patent Application entitled "Enhanced Endp〇int Detecti〇n in Non-Volatile Memory Array Fabrication", December 19, 2007 Patent application ll/96〇, 485 and December 19, 2007, the application was named “Composite Charge Storage Structure F〇rmati〇n N〇n_

Volatile Memory Using Etch Stop Technologies, U.S. Patent Application Serial No. 1 1/960,498, the disclosure of which is incorporated herein by reference. The results of steps 512-514 are shown in the figure, which illustrates the formation of an oceanic gate stub 412a having a dielectric cover 408 thereon. In step 516, an oxide-based spacer 7〇8, such as tetraethyl vinegar (TEOS), is grown. In one embodiment, an isotropic deposition process is used. In step 518, the oxide spacers 7〇8 are etched such that the oxide spacers 7〇8 are removed from the horizontal surface rather than from the vertical surface. In one example, an anisotropic etch process is used to form sidewall oxide spacers 7〇8. The results are shown in Figure 60, which shows the side of the oxide spacer along the stem 412a of the floating gate 412 and the dielectric cover 4A8. 141462.doc 15-201007891 During or after steps 516-518, the top end of the floating interpole post 412a can be oxidized to form a "bird" on top of the floating gate polysilicon. Oxidizing the floating gate polycrystal is used to round the corner of the floating open pole 4 仏. The oxidation time and chemical reaction can change the floating gate 412a to a greater or lesser extent. The top is curved. Figure W shows the floating gate at the top of which is rounded by the "Bird" 712 on the top of the floating gate 412. Since guanine 712 includes dioxide, it can tend to act as a dielectric. Thus, in one embodiment, the bird can be considered to be a part of the electric cover. It should be noted that the bird's eye m has an effect on the total height of the floating opening and the width of the stem. Therefore, these effects should be pre-compensated early in the process. Next, in the case where the oxide spacer 708 is in the home position, a shallow trench isolation trench is formed. In step 520, the lower portion of the polysilicon 606, the first oxide layer 604, and the top of the germanium substrate 602 are etched while the oxide spacers 7〇8 are in the home position. The results are shown in Figure 61). In one embodiment, the money is etched into the substrate 602 by about .2 microns to form a shallow trench isolation (STI) region between the NAND strings, with the bottom of the trench being inside the top of the p-well. In step 522, the STI trench is filled with a spacer material 407 (eg, partially stabilized zirconia (PSZ), Si〇2 (or another suitable material)) using CVD, rapid ALD, or another method to achieve a hard mask 610. The top. In step 524, chemical mechanical polishing (CMP) or another suitable process is used to polish the spacer material 扁平ο? until it reaches the SiN 610. The green results of steps 522-524 are shown in Figure 6E. 141462.doc -16 - 201007891 Step 526 is to return the last name STI isolation material 407 and oxide spacer 708. Step 5 2 7 removes the nitride hard mask 610. These steps can be performed in either order, as illustrated by option A and option B in the flowchart. Option A will be discussed first. In step 526, the etch back STI isolation material 407 and oxide spacer 708 are prepared to deposit a polycrystalline inter-turn dielectric (IPD). The result of step 526 is shown in Figure 6F. In step 527, the SiN layer 610 is stripped. The result of this step of option A is shown in Figure 6G. If the nitride hard mask 61 is removed after etch back, the dielectric cover 408 will have a relatively flat top. In option B, nitride mask 610 is removed (step 527) prior to etch back STI material 407 and oxide spacer 708 (step 526). The result of executing option B is shown in Figure 6H. If the nitride hard mask 61 is removed prior to etch back, the dielectric cover 408 will have a relatively round top. When option b is used, the etch can have a small horizontal component and slightly etch both the oxide cap 4〇8 and the polycrystalline dream that forms the oceanic gate stub 412a. Therefore, the floating gate stem 412a should be defined wider than the last desired target width early in the process. A polycrystalline inter-turn dielectric (e.g., dielectric 406) is grown or deposited in step 528. The IPD can comprise alternating conformal layers of oxide and nitride. For example, 'oxide-nitride-oxide (ΟΝΟ) polycrystals; 5 eve dielectrics are used. In one embodiment 'IPD includes nitride-oxide-nitride oxide-nitride. The result of step 528 is shown in FIG. It should be noted that the dielectric cover 408 is depicted in Fig. 61 as having a curvature, although the curvature is not desired. 141462.doc •17· 201007891 In step 530, a control gate (word line) is deposited. Step 53 may comprise a deposition-polysilicon layer, a layer of tungsten germanium (WSi) layer and a layer of tantalum nitride (siN). When the control gate is formed, photolithography is used to form a strip pattern perpendicular to the NAND chain to form word lines that are isolated from each other. In the step 蚀刻, etching is performed using plasma etching, ion milling, ion etching by pure physical etching, or another suitable process to etch various layers and form a single word line. In step 532, an implant process is performed to form an N+ source/drain region 444. Arsenic or scale implants can be used. In one embodiment, a halo implant is also used. In some embodiments, an annealing process, such as a rapid thermal annealing (RTA), is performed. The example parameters for RTA are heated to 1 〇〇〇 Celsius for 10 seconds. 4A illustrates a cross-section of one of the memory arrays along the tangent AA of FIG. 3 after step 532 is used when option 8 is used to cause rounding on top of dielectric cover 4〇8. 4B illustrates a cross section of the memory array along the tangent & B of FIG. 3 after step 532 when option B is used. There are many alternative structures and processes for the above structures and processes, and such alternative structures and processes are still within the spirit of the invention. As in the prior NAND embodiments, an alternative method is to fabricate a memory cell from a PMOS device in which the opposite polarity bias conditions are used for various jobs as compared to existing NMOS implementations. In the above examples, the substrate is made of tantalum. However, other materials known in the art, such as gallium antimonide or the like, may also be used. Figure 7 is a graph illustrating the variation of various configuration electric fields for floating gate pole widths for non-volatile storage elements. Curve 7〇2 indicates that 14I462.doc -18- 201007891 is not used on the top of the floating gate with a dielectric single cover 408 for a floating gate similar to the floating pole depicted in Figure lc. The electric field in IPD 406. The electric field is based on a simulation and represents one of the IpDs on the tip of the arrow labeled "A" in Figure (1). It should be noted that as the width of the floating gate pole is made narrower and narrower, the strength of the electric field becomes stronger and stronger, and when the stem width is reduced by less than 200 A, the electric field strength is greatly increased. Curve 704 represents the electric field in the IPD at the top corner of the floating gate without the use of a dielectric cover 4〇8 for a floating gate similar to one of the floating gates depicted in Figure π. The electric field is based on a simulation and represents one of the left or right ipDs of the double arrow labeled "2A" in Figure 1C. It should be noted that for a given floating gate stem width, the strength of the electric field is greater at the tip of the stem (curve 7〇2) than at the corner (curve 7〇4). Point 706 represents IPD 4〇6 at the top corner of the stem post 412a of the floating gate 412 in a situation similar to the non-volatile storage element depicted in FIG. 4A using a half-spherical dielectric cover 4〇8. The electric field in the middle (marked as "corner field" in Figure 4). The floating gate 412 has a width of 1 〇〇 A. Point 708 represents the electric field in the IPD 406 at the top of the stem 412a of the floating gate 412 in the case of a non-volatile storage element similar to that depicted in Figure 4A (in Figure 4A). Marked as "top field"). It should be noted that the electric field strength at the top of the floating gate (point 7〇8) is less than the electric field strength at the corner of the floating gate (point 706). Moreover, since the electric field strength at the top of the stem 412a is small, the amount of leakage current in the region is reduced. Reducing the electric field strength at the top of the floating gate can substantially reduce the total leakage current 141462.doc •19· 201007891 without significantly affecting overall performance. It should be noted that the amount of dielectric does not increase too much when some dielectric material is added to the IPD. Therefore, the coupling between the floating idler and the control gate is not seriously affected. Moreover, the leakage current has been reduced in one of the biggest problems of the current system. Figure 8A is a flow diagram of an embodiment of a portion of a process for fabricating the memory cells of Figures 4A and 4B. Figures 9A-9E illustrate various stages of formation in accordance with the process of Figure 8A. Fig. 9 is a cross section along line a_a in Fig. 3. In this example, the floating gate is relatively narrow when viewed in cross section taken along the word line. It should be noted, however, that the principles discussed herein are applicable to a floating gate that is narrow when viewed in a cross-section taken along either a bit line or both a word line and a bit line. In the process of FIG. 8A, a dielectric cap 4〇8 is formed by implanting a material (eg, oxygen) at the top of the floating gate 412 and processing the float by a process (eg, annealing) The gate 412 is such that a dielectric cap is formed by the implanted oxygen and the polycrystalline spine of the floating gate 412. Oxygen is not required to be implanted. In one embodiment, nitrogen is implanted. The initial flow of the floating gate 412 is not illustrated in the flow chart of Figure 8A. In addition, the flow chart does not depict most implantation steps, gap filling of the buttoned volume between stacks, or formation of contacts, metal, vias, and passivation, and processes known in the art. The other part A. There are many methods for fabricating memory in accordance with the present disclosure, and thus the inventors expect that various methods other than those illustrated in Figure 8A can be used. When the flash memory chip will contain the core memory and peripheral circuitry, the process steps of Figure 8A are only intended to provide a general description of the process recipe for the fabrication of the core 'memory array 141462.doc -20- 201007891. Step 902 forms a floating gate and deposits material for the STI structure. Figure 9A shows two s-resonance units at a stage after the STI material 4〇7 has been deposited around the floating gate 412. Specifically, FIG. 9A illustrates two floating gates 412 formed on a substrate 402. A gate oxide 41 is formed between the floating gate 412 and the substrate 402. The nitride mask 91 is still at the position on the floating gate post 412a. A trench for the STI material 4?7 is etched into the substrate 402, wherein the STI material 407 fills the trench and also extends to the top of the nitride mask 610. Techniques for forming s-resonance units that reach the point depicted in Figure 9 are well known and will therefore not be discussed in detail. Step 904 is a step of implanting a material into the top surface of floating gate 412 for use as a seed material to subsequently form dielectric cap 4〇8. In this embodiment, the material is implanted through a nitride mask 910. Figure 9B illustrates the memory cell after seed material 908 has been implanted in the top of floating gate post 412 & wherein nitride mask 910 is still in place. Subsequent to the process, the seed material 908 will be treated (e.g., by heating) to form the dielectric cover 4〇8. In one embodiment, the seed material 9〇8 is oxygen. The oxygen can be implanted by a technique similar to that by means of implanted oxygen separation. SIM〇x is a technique for fabricating an upper insulator structure and a substrate by implanting a high dose of oxygen followed by high temperature annealing. For example, the SIM0X process uses oxygen ions to implant ions by selecting implanted ions. Enter a desired depth in the substrate. After the ion implantation, annealing is performed to convert the oxygen ions together with the ruthenium in the substrate into ruthenium dioxide. Using SIM〇x, a carefully controlled dioxide layer is formed which is buried in the germanium substrate. However, although SIMOX is typically used to form a buried layer of germanium dioxide at a certain depth in a substrate of 141462.doc -21 - 201007891, the present technology forms a dielectric cap 4 at the top of a floating gate 412. 8. It should be noted that the seed material 908 can be implanted through the SiN 91 by appropriate control of the implantation process. The depth and concentration can be controlled by the energy and dose of oxygen. The energy by which the ions are implanted controls the depth. The concentration of the seed material 908 may be non-uniform in the vertical direction. For example, the distribution can be approximately Gaussian. By appropriately selecting the energy for the implant material, a peak of the Gaussian distribution can be established at a surface very close to the floating gate stem 412a.

Subsequent processing steps (e.g., annealing) of implanting ions into the substrate 4?2 to form a source/drain region with one or more heels have a side effect of converting oxygen to cerium oxide. It should be noted that it is not necessary to add one step of converting the seed material 9〇8, but an additional step can be performed if necessary. The seed material 908 is not required to be oxygen. In another embodiment, the seed material 908 is nitrogen. In this case, the dielectric cover 4〇8 will be “Μ. In a real

In the embodiment, the seed material 908 comprises both oxygen and nitrogen. Other seed materials can also be used. In one embodiment, in addition to the seed material 9A8, a control material is implanted to control how the dielectric cover 4A8 is formed. The control material controls the rate at which the dielectric cap is formed during annealing. For example, argon can be implanted along with oxygen to control the rate at which ceria is formed from the seed material 908. Argon can increase the rate at which cerium oxide is formed. In one embodiment, the argon is dissipated during the step of, for example, retreating to leave little or no argon remaining. However, in some embodiments, some argon may remain after the formation of the memory cell. 141462.doc • 22- 201007891 In step 906, the SiN mask 910 is stripped. The results are shown in Figure 9Ct. In step 908, the STI material 407 is etched back. The results are shown in Figure 9D, which shows the level of etchback of STI material 407 to gate dielectric 410. In step 91, a polycrystalline inter-turn dielectric (e.g., dielectric 406) is grown or deposited. For example, an oxide-nitride-oxide (〇N〇) polycrystalline intergranular dielectric is used. The deposited IPD can be used to heat the material in the floating gate 412 to a sufficiently high temperature to at least partially form the dielectric cap 4〇8. For example, the _ 5 ' dioxide dream can begin to form and float from the implanted oxygen. The gate 412 is formed. It should be noted that some of the implanted oxygen may remain in the floating gate 412 after the IPD 406 is formed. The subsequent thermal process steps convert this oxygen to dioxide dioxide. Figure 9E shows the results after step 910. After step 41, the well-known steps can be used to form the control gate, source/drain regions and other aspects of the memory cell. In step 912, the seed material 908 is processed to form a dielectric cap 4〇8 from the seed material 9〇8 and the polysilicon at the top of the floating gate post 412a. In one embodiment of the seed crystal material oxygen, the processing of the seed material 908 is achieved by a process step that heats the seed material 908 to a temperature sufficient to implant oxygen and float. The polysilicon of the gate 412 forms si〇2. It should be noted that one or more process steps can achieve this desired effect. As previously discussed, forming the IPD 406 can at least partially achieve processing of the seed material mirror. The annealing process performed when the source/drain region is formed is an example of the process of seeding (4) 908-process. Therefore, one of the processing steps for another purpose is also used to process the seed material to form a dielectric cover 141462.doc • 23- 201007891 408. Typically, the source/drain regions are formed by implanting a substrate such as a material such as kun or phosphor. After implantation, an annealing process (eg, rapid thermal annealing (RTA)) is performed. The example parameters for RTA are heated to t just for ten seconds. This - RTA can be used to convert a majority of the seed material (eg, oxygen) to Si〇2. However, some seed material 9 (10) may remain. This residual seed material 9〇8 can be processed by a different process step. For example, the side difference oxidation process step can process the seed material 908 to at least partially form the dielectric cap 408. To achieve sidewall oxidation, the apparatus is placed in a furnace at a high temperature and with a fractional percentage of ambient oxygen to expose the surface to provide a protective layer. (4) Oxidation can also be used to round the floating gate and control the edge of the gate. It should be noted that sidewall oxidation can be performed before the formation of the source/drain regions. Figure 8B is a flow diagram illustrating one embodiment of a process for making Figure 8 and a portion of a memory cell. The process of Figure 8B is an alternative to the process of Figure 8a. Figure _9(} is a cross-section along line A_A of Figure 3, which depicts the various stages of formation in accordance with the initial steps described in the process of Figure 8B. Figure 9D-9E (in the discussion of the process of Figure 8A) It has been explained that the formation phase is later. In this example, the floating gate is relatively narrow when viewed in cross section along the word line. However, it should be noted that the principles discussed herein apply to A narrow gate floating gate is viewed along a bit line or a word line and a bit line. The process of Figure 8B begins with the formation of a floating gate and sti material in step 902, which is related to This is discussed in Figure 8A. Then, the SiN mask 910 is stripped in step 9〇4. Figure 9F illustrates the formation of the memory cell in step 〇14.doc -24-201007891 after step 9〇4 of the process of Figure 8B. The seed material for the dielectric cap 408 is implanted into the top of the floating gate stem 412a. Figure 9G depicts the result after step 926. Step 926 can be similar to implant step 904 of Figure 8A. Since the seed material 908 is directly implanted into the polysilicon of the floating gate 412 instead of passing through the S The iN mask 910 'and thus a lower implant energy can be used in step 926. In one embodiment the 'seed material is oxygen. In another embodiment, the seed material is nitrogen. In one embodiment A control material (e.g., argon) is also implanted. Step 908 is an etch back of the STI material 407. The results are shown in Figure 9D. Step 910 is the deposition of the IPD material 406 and the results are shown in Figure 。. The seed material 908 is processed in step 912 to form a dielectric cap 4〇8 from the polycrystalline spine at the top of the seed material 9〇8 and the floating gate stem 412a. Step 912 has been discussed in relation to 圊8A Figure 8C is a flow chart illustrating one embodiment of a process for fabricating the memory cell of Figure 4A and Figure 4. The process diagram of Figure 8C is substituted for one of the processes of ❿ 8B. Figure 9H- 9I is a cross-section along line AA of Figure 3, which depicts the various stages of formation in accordance with the initial steps set forth in the process of Figure 8C. Figures 9D-9E (described in the discussion of the process of Figure 8A) No later formation phase. In this example, when viewed in a cross section taken along the word line, float The gate is relatively narrow. However, it should be noted that the principles discussed herein are applicable to a floating gate that is narrow when viewed in a cross-section along either a bit line or a word line and a bit line.

The process of Figure 8C begins with the formation of floating gates 412 and 5 in step 902; material 1 407, which has been discussed in relation to Figure 8A. At step 9〇4, the SiN 141462.doc -25-201007891 mask 910 is stripped. Next, in step 944, the STI material 407 is etched back to the middle. The result of step 944 is illustrated in Figure 9H, which shows that an STI material 407 is etched down to expose a portion of the floating gate stem 412a. However, the lower portion of the floating gate stub 412a and the floating gate substrate 412b are still covered by the STI material 407. The exact depth to which the STI material 407 is etched back is not critical. In one embodiment, the etch is stopped at a point prior to reaching the floating gate substrate 412b so that it does not reach the floating gate substrate 412b when the seed material is added. It should be noted that in this embodiment, the energy from which oxygen is implanted can be kept relatively low due to the exposure of the top of the floating gate stem 412a and the implantation of oxygen only to a very shallow depth. In step 946, seed material 908 is implanted into the top of floating gate stub 412a, wherein STI material 407 is etched back to expose the side of top floating gate stem 412a. In one embodiment, the material is oxygen. In another embodiment, the material is nitrogen. In one embodiment, a material such as argon is also implanted. Figure 91 depicts the results after step 946. It should be noted that in this embodiment, a majority of the back-sliding STI is performed prior to the implantation step. In step 948, the STI material 407 is further etched back. It should be noted that when the STI material 407 is further etched back in step 948, any seed material that may have been implanted in the upper portion of the STI material 407 will be removed. Figure 9D illustrates the results after step 948. In step 910, an IPD layer 406 is deposited. Figure 9E depicts the results after deposition of the IPD layer 406. In step 912, the seed material 908 is processed to form a dielectric cap 408 from the seed material 908 and the polysilicon at the top of the floating gate post 412a. Phase 141462.doc -26- 201007891 Step 912 is discussed with respect to Figure 8A. FIG. 1 illustrates a non-volatile storage device 1010 that may include one or more memory dies or wafers 〇12. The memory die 1012 includes a memory cell array 1000 (two-dimensional or three-dimensional), control circuit 1〇2〇, and read/write circuits 1030A and 1030B. In one embodiment, various peripheral circuit-to-memory arrays The accesses of 100 〇 are implemented in a symmetrical form on opposite sides of the array to halve the density of access lines and circuits on each side. The read/write circuits 1030A and 1030B include a plurality of sensing blocks 3 (9) that allow parallel reading or programming of a memory unit page. The memory array 100 can be addressed by the prewire via the column decoders 1〇8 and 1〇4〇8 and can be addressed by the bit lines via the row decoders 1042 and 1042B. In an exemplary embodiment, a controller 1044 and one or more memory die 2 are included in the same memory device 1 (e.g., a removable memory card or package). The command and lean material are transferred between the host and controller 110 via line 1032 and between the controller and one or more memory dies 1 〇 12 via line 丨〇 34. One embodiment may include a plurality of wafers 1〇12. The control circuit 1020 cooperates with the read/write circuits 1 〇 3 及 and 1 〇 3 〇 8 to perform a memory job on the memory array 1 。. The control circuit 1 〇 2 〇 includes a state machine 1022, an on-chip address decoder 1 〇 24, and a power control module 1 026. State machine i 022 provides wafer level control of the memory job. The on-chip address decoders 1 to 24 provide an address interface for the address and decoders used by the host or a memory controller, and the decoders 1〇4〇A, 1〇4〇b, 1〇42A, and i〇42B. Convert between the hardware addresses used. The power control module 1 26 controls the power and voltage supplied to the word lines and bit lines during the memory operation. In an embodiment of 141462.doc • 27· 201007891, the power control module includes one or more charge pumps capable of generating a voltage greater than the supply voltage. In one implementation, the control circuit 1020, the power control circuit 脳, the decoder circuit 1G24, the state machine circuit 1G22, the decoder circuit 1A42A, the decoder circuit 1042B, the decoder circuit 1G4GA, and the decoder circuit B° are sold/ The combination or combination of write circuit 1030A, read/write circuits 1〇3〇6, and/or control benefit 1044 may be referred to as one or more management circuits.

Figure 11 illustrates an exemplary structure of a memory cell array face. In one embodiment, the se* memory cell array is divided into one memory cell block. For flash EEPRQM systems, the block is the erase unit: that is, each block contains the smallest number of memories that can be erased = the element I block is usually divided into pages. One page is a stylized early position. One or more data pages are typically stored in the line memory unit to store 4 solids or multiple segments. One section includes user data: additional items. Additional item data usually contains users who have been from that section

The data is calculated in sixty-one error correction code (ECC). One part of the controller (described below) calculates the ECC when the data is being programmed into the array t, and also checks the ECC when reading the data. Alternatively - choose to have the ECC and/or other additional libraries in a different page than the user's profile or even a different zone. A user data section typically has a size of 512 words corresponding to a sector within the disk drive. A large number of pages form a block, for example, from 8 pages (for example) to as many as 32, 64, 128 or ^pages. Different size blocks and configurations can also be used. A 141462.doc • 28· 201007891 In another embodiment, the bit line is divided into odd bit lines and even bit lines. In an odd/even bit line architecture, memory cells along a common word line and connected to odd bit lines are programmed at one time, while stylized along a common word line and connected to even bits at another time. The memory of the Yuan line is 70 in the morning. Figure 11 shows more details of block i of memory array 1000. Block i contains X+1 bit lines and X+1 NAND strings. Block i also includes 64 data word lines (WL0-WL63), two dummy word lines (WL d0 and WL dl), a drain side select line (SGD), and a source side select line (Sgs). One terminal of each NAND string is connected to a corresponding bit line via a drain select gate (connected to select line SGD), and the other terminal is connected to the source via a source select gate (connected to select line SGS) Polar line. Since there are 64 data sub-lines and two virtual word lines, each NAND string contains 64 data memory cells and two virtual memory cells. In other embodiments, NAND can have more or less than 64 data memory cells and two virtual memory cells. The data memory unit stores user or system data. Virtual. 拟 己 体 体 unit is usually not used to store user or system data. Some embodiments do not include a virtual memory unit. Figure 12 is divided into a core portion (referred to as a sensing module 128A) and a common one. Ρ is the individual sensing block of 1290 - block diagram. In one embodiment, there will be a separate sensing module 128A for each bit line, and a common portion 129A for a plurality of sensing modules 1280. In one example, the sensing block will include a common portion 129A and eight sensing modules 1280. Each of the sensing modules in a group will communicate with the associated common portion via a data 141462.doc -29- 201007891 bus 12 7 2 . For further details, reference is made to U.S. Patent Application Publication No. 2006/014, the entire disclosure of which is incorporated herein by reference. The sensing module 1280 includes a sensing circuit 1270 that determines whether one of the connected bit lines is conducting current above or below a predetermined threshold level. In some embodiments, sensing module 1280 includes a circuit, which is commonly referred to as a sense amplifier. Sensing module 1280 also includes a bit line latch 1282' which is used to set a voltage condition on a connected bit line. For example, the latching in the bit line latch 1282 - the predetermined state causes the connected bit line to be pulled to a state in which the specified program is disabled (e.g., Vdd). The common portion 1290 includes a processor 292, a set of data latches 1294, and an I/O interface U96 that is interposed between the set of data latches 1294 and the data bus 122. The processor 1292 performs calculations. For example, one of its functions is to store the data stored in the sensed memory unit and store the determined data in the set of data latches. The set of data latches 294 is used to store the data bits determined by the processor 1292 during a read operation. It is also used to store data bits imported from the data bus 1220 during a stylized job. The data bits that are imported represent the data that is intended to be programmed into the memory. I/O interface 1296 provides an interface between data latch 1294 and data sink 12 2 0. During reading or sensing, the system operates under the control of state machine 22, which controls the supply of different control gate voltages to the addressed unit. When the sensing module 1280 steps through various predefined control gate voltages corresponding to the various memory states supported by the memory 141462.doc 201007891, it can trip at one of the voltages and via The bus 1272 provides an output from the sensing module 128 to the processor 1292. At this time, the processor 1292 determines the resulting memory state by considering the tripping event of the sensing module and the information about the control gate voltage applied from the state machine via the input line 1293. Processor 1292 then computes one of the binary codes for the memory state and stores the resulting data bits in data latch 1294. In another embodiment of the core portion, the ❹ bit line latch 1282 serves two purposes: as one of the outputs for latching the sense module 1280, as well as one of the above. Bit line latch. It is contemplated that some embodiments will include multiple processors 292. In one embodiment, each processor 1292 will include an output line (not shown in Figure 12) to connect each of the output lines or (wired_〇R) together. In some embodiments, the output lines are inverted before being connected to the line "or" line. This configuration enables a quick determination of when the programization process is completed during the program verification process because the state machine of the receive line OR line determines when all of the bits being programmed have reached the desired level. For example, when each bit reaches its desired level, it will send a logical zero (or reversed, one data one) to the line "or" line. When all bits output a data〇 (After reversal, a data one), the state machine knows to terminate the stylization process. Embodiment 1 'State machine in which each processor is in communication with eight sensing modules may (in some embodiments) need to read a line "or" line eight or add logic to processor 1292 to accumulate correlation The result of the joint line is such that the state machine only needs to read the line "or" line once. 141462.doc -31- 201007891

During stylization or verification, the data to be stylized is stored in the set of data latches 1294 from the data bus 1212. The programming operation under state machine control includes applying a series of stylized voltage pulses (with an increased magnitude) to the control gates of the addressed memory cells. Each stylized pulse is followed by a verification process to determine if the memory cell has been programmed to the desired state. Processor 1292 monitors the verified memory state relative to the desired memory state. When the two match, the processor 1292 sets the bit line latch 1282 to cause the bit line to be pulled to a specified program suppressed state. This prohibits the unit coupled to the bit line from being further programmed, even when it is subjected to a programmed pulse applied to its control gate. In other embodiments, the processor first loads the bit line latch 1282 and the sensing circuit sets it to a disable value during the verification process.

The lean latch stack 1294 contains a stack of data drivers corresponding to one of the sensing modules. In the "item embodiment", there are 3 or another number of data latches per sensing module 128. In the embodiment, the latches are each a bit. In some embodiments (but not required), the data latches are implemented as a shift register to cause parallel data stored therein to be converted into serial data for the data bus 1220, and In a preferred embodiment, all data latches corresponding to a single memory/write block can be linked in a block shift register to make a resource or output ^... By serial transmission to the wheel-input specials, the read/write module library is arbitrarily latched in each of the H groups, and the 汇 汇 汇 ^ ^ ^ ^ Transfer or transfer of funds for the entire read/write block - shift temporary J41462.doc • 32 · 201007891 one part of the register. Additional information regarding read operations and sense amplifiers can be found in the following patents: (1) US Patent 7,196,93 1 entitled "Non-Volatile Memory And Method With Reduced Source Line Bias Errors"; (2) U.S. Patent No. 7,023,736 to "Non-Volatile Memory And Method with Improved Sensing"; (3) US Patent Application Publication No. 2005/0169082; (4) entitled "Compensating for Coupling During Read Operations of - Spring Non-Volatile Memory" US Patent No. 7,196,928; and (5) US Patent Application No. 2006/0158947, entitled "Reference Sense Amplifier For Non-Volatile Memory", issued July 20, 2006 Open case. All of the above five patent documents listed above are hereby incorporated by reference. The embodiments of the present invention have been described in detail above for the purposes of illustration and illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. According to the above teachings, many modifications and changes can be made. The embodiments were chosen to best explain the principles of the embodiments of the present invention and the application of the embodiments of the embodiments of the invention. The present invention is utilized. The scope of the invention is intended to be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A, FIG. 1B and FIG. 1C illustrate the structure of different floating gate/control gate interfaces; 141462.doc -33- 201007891 FIG. 2 is a circuit diagram of three NAND strings. The structure of a non-volatile memory device is shown in FIG. 4A and FIG. 4B as a plan view of a memory cell array. FIG. 5 is a flow chart illustrating a non-volatile memory used as a non-volatile memory. An embodiment of a process for 兀 arrays; non-swipe 6 -6 shows a portion of an array of memory cells at various stages of the process described in FIG. 5; FIG. 7 illustrates a non-volatile storage element Various configurations and a chart, FIG. 8 is a flow chart illustrating an embodiment of a process for fabricating an integrated cell array; non-volatile memory

Figure 8 is a flow chart illustrating an embodiment of a process for fabricating a non-volatile memory cell array by W M Dan w XL ;; Figure 8C is a flow diagram illustrating a process for making An embodiment of a process for a non-volatile memory cell array;

9A, 9B, 9C, 9D, and 9E illustrate the non-volatile storage elements in the various stages of the manufacturing process of FIG. 8; FIG. 9F and FIG. 9G illustrate one of the manufacturing processes in the drawings. Non-volatile storage elements in the stage; Figures 9H and 91 illustrate the non-volatile storage elements in various stages of the manufacturing process of Figure 8c; Figure 1 is a block diagram of a non-volatile memory system; 11 is a block diagram showing an embodiment of a memory array; and FIG. 12 is a block diagram showing an embodiment of a sensing block. 41462.doc -34· 201007891 ❹ [Main component symbol description] 102 Floating gate 104 Control gate 106 IPD 202 NAND string 204 NAND string 206 NAND string 220 transistor 222 memory unit 224 memory unit 226 memory unit 228 Memory unit 230 transistor 240 transistor 242 memory unit 244 memory unit 246 memory unit 248 memory unit 250 transistor 252 memory unit 300 sensing block 350 bit line 352 word line 402 矽 substrate 141462.doc • 35_ 201007891 404 406 407 408 410 412 412a 412b 444 446 602 604 606 610 708 712 908 910 1000 1010 1012 1020 1022 1024 Control Gate Second Dielectric Layer (IPD) Isolation Material Dielectric Cover Dielectric Layer Floating Gate Floating interpole pole floating gate base source region/and pole region channel 矽 substrate tunnel oxide layer polycrystalline layer nitride nitride hard mask oxide spacer "Bird" seed material nitride mask memory array Non-volatile storage device memory die control circuit state machine on-chip address decoder 141462.doc -36- 201007891

1026 Power Control Module 1030A Read/Write Circuit 1030B Read/Write Circuit 1032 Line 1034 Line 1040A Column Decoder 1040B Column Decoder 1042A Line Decoder 1042B Line Decoder 1044 Controller 1220 Data Bus 1270 Sensing Circuit 1272 Bus 1280 Core (Sense Module) 1282 Bit Line Latch 1290 Common Part 1292 Processor 1293 Input Line 1294 Data Latch 1296 I/O Interface 141462.doc -37-

Claims (1)

201007891 VII. Patent Application Range: 1. A method for forming a non-volatile storage device, the method comprising: forming a floating gate (5〇4, 514, 520' 902) having a top and at least two sides Forming a dielectric cover (5〇5, 514, 904, 912, 926, 946) at the top of the floating gate; ❹ around the at least two sides of the floating gate and the dielectric cover An inter-gate dielectric layer (528) is formed over the top of the cap; and a control (10) is formed over the top of the floating gate, the inter-dielectric layer separating the control gate from the floating gate ( 5 3 〇). 2. The method of claim 1 wherein the forming a floating open comprises forming the floating gate by a stone eve; and wherein forming the dielectric cover comprises: implanting oxygen into the top of the floating gate And heating the floating gate to form the dielectric cover from the implant after implantation of the implant and the floating gate from which the floating gate is formed. 3. The method of claim 2, wherein: forming a floating gate comprises using a hard mask; and applying the oxygen to the floating gate » λ ^ top. The sputum contains the implant through the hard cover. 4. The method of claim 2, further comprising: depositing a shallow trench isolation junction (four), leaving the material 'the isolation material surrounding the at least two sides of the driven gate; Isolating the isolation material to one of the hard masks 141462.doc 201007891 residing on the floating pole; removing the hard mask from the floating gate; wherein after removing the hard mask but after The implantation of oxygen into the top of the floating gate is performed prior to the at least two sides of the floating gate removing the isolation material. 5. The method of claim 2, further comprising: depositing an isolation material for a shallow trench isolation structure, the isolation material surrounding the sides of the floating gate; planarizing the isolation material to reside in the floating gate One of the hard masks of one of the poles; removing the hard mask from the floating gate; etch back a portion of the spacer material to expose at least a portion of the at least two sides of the floating gate; wherein in the back Oxygen implantation is performed in the top of the floating gate after etching a portion of the isolation material. 6. The method of claim 1, wherein the forming a floating gate and the forming-dielectric cover comprises: forming a polycrystalline layer for forming the floating gate; Forming an oxide layer on the dielectric cap; forming a pattern on the oxide layer; etching the oxide layer and the polysilicon based on the pattern to form the dielectric cap and the Floating gate. 7. The method of claim 6, wherein the forming the floating closed pole and forming the 141462.doc 201007891 dielectric cover further comprises: selectively oxidizing the polycrystalline, day and day used to form the floating gate 7' provides a curvature to the top of the floating gate, the oxidized portion of the polysilicon forming a portion of the dielectric cap. 8. The method of claim 1, wherein the forming a control gate further comprises forming the control gate around the at least two side surfaces of the floating gate. 9. A non-volatile storage device comprising: a floating gate (412) having a top and sides; a control gate (404) on the top and at the floating gate (412) Around the sides; an inter-gate dielectric (406, 408) between the floating gate (412) and the control gate (404), the inter-gate dielectric comprising the floating gate (412) The upper dielectric cover (4〇8) and a layer of dielectric material (4〇6) on and around the floating gate (412). 10. The device of claim 9, wherein when the floating gate and the control gate are at different voltages, an electric field is present in the inter-gate dielectric, and the dielectric cover is shaped to cause the gate The strength of the electric field in the dielectric is about the same or less than the strength of the electric field in the region of the inter-gate dielectric on the sides of the floating gate. 11. The device of claim 9, wherein the vertical thickness of the dielectric cover causes a peak of the electric field in the inter-electrode dielectric to occur at the sides of the floating gate * 12_如吻9 The device wherein the dielectric cover comprises ruthenium dioxide. 141462.doc 201007891 13. The device of claim 9, wherein the dielectric cover has a curved top. 14. The device of claim 9, wherein the top of the dielectric cover has a substantially flat top. 15. The device of claim 9, wherein the top of the dielectric cover has a curved shape having a radius of curvature, and a width of one of the portions of the floating gate closest to the dielectric cover is approximately The radius of curvature of the electric cover is twice. 141462.doc