KR20110031491A - Dielectric cap above floating gate - Google Patents

Abstract

A memory system is disclosed that includes a set of nonvolatile storage elements. Certain memory cells have a dielectric cap over the floating gate. In one embodiment, this dielectric cap is between the floating gate and the conformal IPD layer. This dielectric cap reduces the leakage current between the floating gate and the control gate. The dielectric cap achieves a reduction in leakage current by reducing the strength of the electric field at the top of the floating gate, which, in the absence of a dielectric cap for the floating gate having a narrow stem, causes the electric field to It is the largest place.

Description

Dielectric cap on floating gate {DIELECTRIC CAP ABOVE FLOATING GATE}

The present invention relates to a nonvolatile memory device.

Semiconductor memory devices are increasing in demand in various electronic devices. For example, nonvolatile semiconductor memory is used in devices such as mobile phones, digital cameras, PDAs, portable computers, and non-portable computers. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most widely used nonvolatile memory devices.

Typical EEPROMs and flash memories utilize memory cells with floating gates provided over a channel region of a semiconductor substrate. The floating gate is separated from the channel region by a dielectric region. For example, the channel region is located in the P well between the source region and the drain region. The control gate is separated from the floating gate by another dielectric such as an inter-gate dielectric or an inter poly dielectric. The threshold voltage of the memory cell is controlled by the amount of charge retained at the floating gate. In other words, the level of charge on the gate determines the minimum amount of voltage that must be applied to the control gate before the memory cell is turned on so that the source and drain are conductive.

In some EEPROM and flash memory devices, the floating gate stores two ranges of charge so that the memory cell can write or erase two states (such as a binary memory cell). Multi-bit or multi-state flash memory cells are implemented by identifying multiple distinct threshold voltage ranges within one device. Each distinct threshold voltage range corresponds to predetermined values for the set of data bit values. In order to achieve correct data storage of multi-state memory cells, multiple ranges of threshold voltage levels are separated from each other with sufficient margin so that the level of the threshold voltage of the memory cell can be unambiguously read, programmed or erased. Should be.

When programming a typical flash memory device, a program voltage is applied to the control gate and the bit line is grounded. By capacitive coupling between the control gate and the floating gate, the program voltage at the control gate is coupled to the floating gate to cause the voltage of the floating gate. The floating gate voltage causes electrons to be injected from the channel into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell increases when viewed from the control gate. In order to maintain the programmed state of the memory cell, the amount of charge on the floating gate needs to be maintained over time. However, charge can leak from the floating gate to the control gate through the interpoly dielectric, and this current is called leakage current.

In recent flash memory technologies, short program and erase times and low operating voltages present major challenges to achieve high speed, high density, and low power operation. Thus, there is an increasing need to increase the capacitive coupling between the floating gate and the control gate of a memory cell, while at the same time increasing the need to block electrons from escaping from the floating gate to the control gate. The capacitance between the floating gate and the control gate, which affects the coupling ratio, is the thickness of the interpoly dielectric (hereinafter referred to as 'IPD') between the two gates and the relative permittivity or dielectric constant K of the IPD. Determined by One way to create a high coupling rate is to use a thin IPD, but when using too thin IPD, the leakage current becomes undesirably large.

The smaller the nonvolatile memory structure is, the more difficult the leakage current becomes. One source of leakage current is the strength of the electric field in various parts of the IPD when voltage is applied to the control gate. In particular, in certain areas of the IPD, the strength of the electric field increases, in which case a greater leakage current occurs. 1A, the electric field is strongest at IPD 106 near the sharp edges of floating gate 102 and control gate 104. When A is the radius of curvature of the floating gate 102, if the area near the edge of the IPD 106 is rounded, the intensity of the electric field is proportional to 1 / A. Note that sharp edges have a very small radius of curvature, which results in a stronger electric field.

In order to reduce the intensity of the electric field at the IPD 106 at the corner of the floating gate 102, the radius of curvature on top of the floating gate 102 can be increased as shown in FIG. 1B. Note that the curvature of the control gate 104 also changes in this case. By reducing the strength of the electric field, the leakage current is reduced. However, in order to reduce the size of the device structure, it is preferable to reduce the width of the floating gate 102 as shown in FIG. 1C. Note that, in FIG. 1C, the top portion of the polysilicon floating gate 102 must also be rounded. The possible range when rounding the floating gate 102 is limited by the width of the floating gate 102. In other words, the maximum possible radius of curvature A is limited to half the width of the floating gate 102. Note that as the width 2A of the floating gate 102 is further reduced, the maximum possible radius of curvature is also reduced. Therefore, as the feature size of the memory cell continues to decrease, the electric field and therefore leakage current in the IPD 106 becomes more difficult to handle.

One way to reduce the strength of the electric field is to form the IPD 106 into a thin film having a high dielectric constant. However, such a film is not preferable because it is difficult to work. For example, paraelectric materials have dielectric constants at least twice that of silicon dioxide, but there are some problems that limit their use as gate dielectrics. One problem is oxygen diffusion. Oxygen diffuses from the IPD 106 to the interface of the IPD 106 and the floating gate 102 and the interface of the IPD 106 and the control gate 104 during the high temperature process of the semiconductor manufacturing process. To lower the overall capacitance of the dielectric. Therefore, the influence of high dielectric constant dielectric material is reduced.

Metal oxides, which are used in flash memory devices, have also been proposed as materials having high K values. The use of metal oxides, especially Al ₂ O ₃ , makes the leakage current small. In addition, metal oxides have high temperature resistance in process integration. However, the deposited metal oxides of the high dielectric constant have a non-stoichiometric composition, which is likely to cause electrical defects or traps in the bulk of the dielectric and at the interface between the dielectric and the semiconductor. These bonds or traps increase the conduction through the dielectric, reducing the dielectric breakdown strength.

Another way to reduce the electric field in the IPD is to increase the thickness of the IPD 106. However, increasing the thickness of the IPD 106 tends to reduce the capacitive coupling between the floating gate 102 and the control gate 106, which is undesirable as discussed above. Generally, when the radius of curvature is smaller than the thickness of the IPD 106 or when the thickness of the IPD 106 reaches the feature size of the memory cell, the thickness of the IPD 106 tends not to increase.

Embodiments as disclosed herein are briefly related to the fabrication techniques of nonvolatile memory cells and nonvolatile memory cells. The memory cell has a dielectric cap over the floating gate. In one embodiment, a dielectric cap is positioned between the floating gate and the conformal IPD layer. The dielectric cap reduces the amount of leakage current generated between the floating gate and the control gate. When the stem portion of the floating gate is narrow, the electric field is generated most strongly on the top of the floating gate. By placing the dielectric cap on the top of the floating gate, the electric field is reduced to reduce the amount of leakage current.

Yet another embodiment is a method of manufacturing a nonvolatile memory device. The manufacturing method includes forming a floating gate having a top and at least two sides. The dielectric cap is formed on top of the floating gate. An inter-gate dielectric layer is formed around the top of the dielectric cap and at least two sides of the floating gate. The control gate is formed over the floating gate and is separated from the floating gate by an inter-gate dielectric layer.

In one aspect, forming the dielectric cap includes implanting oxygen at the top of the floating gate and heating the floating gate to form a dielectric cap from the implanted oxygen and the silicon on which the floating gate is formed.

These and other objects and advantages will appear more clearly from the following detailed description, which sets forth various embodiments with reference to the drawings.

1A, 1B, and 1C show the structure of different floating gate / control gate interfaces.
2 is a circuit diagram of three NAND strings.
3 illustrates a structure of a nonvolatile memory device.
4A and 4B are top views of a portion of a memory cell array.
5 is a flow chart describing one embodiment of a process for manufacturing a nonvolatile memory cell array.
6A-6J illustrate a portion of a nonvolatile memory cell array in the various process steps described in FIG. 5.
7 is a graph showing the intensity of an electric field according to various configurations of a nonvolatile memory device.
8A is a flow chart describing one embodiment of a process for manufacturing a nonvolatile memory cell array.
8B is a flow chart illustrating one embodiment of a process for fabricating a nonvolatile memory cell array.
8C is a flow diagram illustrating one embodiment of a process for fabricating a nonvolatile memory cell array.
9A, 9B, 9C, 9D and 9E illustrate nonvolatile memory devices at various stages of the fabrication process of FIG. 8A.
9F and 9G illustrate a nonvolatile memory device at one stage of the fabrication process of FIG. 8B.
9H and 9I illustrate nonvolatile memory devices at various stages of the fabrication process of FIG. 8C.
10 is a block diagram of a nonvolatile memory system.
11 is a block diagram illustrating one embodiment of a memory array.
12 is a block diagram illustrating an embodiment of a sense block.

One example of a flash memory system uses a NAND structure, which includes multiple gate transistors arranged in series between two select gates. The series transistors and the select gate are called a NAND string. A typical structure of a flash memory system using a NAND structure includes several NAND strings. For example, FIG. 2 shows three NAND strings 202, 204, and 206 of a memory array having many NAND strings. Each NAND string of FIG. 2 includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246 and 248. Each NAND string is connected to a source line by a select transistor, in which the select transistors 230 and 250 play a role. The select line SGS is used to control the select gate on the source side. Several NAND strings are connected to each bit line by select transistors 220 and 240 controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be shared. The word line WL3 is connected to the control gates of the memory cells 222 and 242. The word line WL2 is connected to the control gates of the memory cells 224, 244 and 252. The word line WL1 is connected to the control gates of the memory cells 226 and 246. Word line WL0 is connected to the control gates of memory cells 228 and 248. As shown in the figure, each bit line and each NAND string constitute a column of a memory cell array, and word lines WL3, WL2, WL1, and WL0 constitute a row of the array.

3 is a plan view of a portion of a NAND flash memory cell array. In this array, the bit lines 350 and word lines 352 are included. It should be noted that Figure 3 does not show every detail of the flash memory cell.

Note that one NAND string may have fewer or more memory cells than shown in FIGS. 2 and 3. For example, a NAND string may have as many memory cells as 8, 16, 32, 64, or 128. What is discussed here is not limited to the specific number of memory cells that can be in one NAND string. In addition, one word line may include fewer or more memory cells than those shown in FIGS. 2 and 3. Likewise, what is discussed herein is not limited to the specific number of memory cells that can have in one word line.

Each memory cell can store data values in the form of analog or digital. When storing one bit of digital data, the range of possible threshold voltages of the memory cell is divided into two, each of which is assigned logical data "1" and "0". For example, for a NAND flash memory, the threshold voltage is negative when the memory cell is erased to correspond to the logic value "1", and the threshold voltage is positive when the logic value is "0" programmed. When the threshold voltage is negative and the memory cell is read by applying 0 volts to the control gate, the memory cell is turned on to indicate that logic 1 is stored. When the threshold voltage is positive and the memory cell is read by applying 0 volts to the control gate, the memory cell is not turned on to indicate that the logic value 0 is stored.

In the case of storing multiple data levels, the range of possible threshold voltages is divided by the number of data levels. For example, if you want to store four levels of information, that is, two bits of data, you will need four ranges of threshold voltages corresponding to data values "11", "10", "01", and "00." . Taking a NAND flash memory as an example, after erasing a memory cell, it has a negative threshold voltage, which corresponds to a logic value "11". Positive threshold voltage values are used to store data values of "10", "01", and "00". To store eight levels of information, that is, three bits of data, the data values "000", "001", "010", "011", "100", "101", "110", and "111" A range of eight threshold voltages will be required.

The specific relationship between the data value programmed in the memory cell and the threshold voltage value of the memory cell is determined according to the data encoding method employed in the memory cell. For example, US Pat. No. 6,222,762 and US Patent Application Publication No. 2004/0255090, both incorporated herein by reference, describe various data encoding methods used in multi-state flash memory cells. In one embodiment, even if the threshold voltage of the floating gate is accidentally shifted to a neighbor state value, the data values are assigned to the range values of the threshold voltage according to the gray code so that the influence can be limited to 1 bit. can do. In another embodiment, the data encoding method may be different for each word line, the data encoding method may change over time, invert the data bit values for any word line, or the sensitivity and the memory cell for the data pattern. It can also be set arbitrarily to reduce wear.

Examples of NAND-type flash memory and its operation are described in U.S. Pat. It is described in the heading. As discussed herein, the present invention can be applied to other types of nonvolatile memories as well as other types of flash memories. For example, NOR type flash memories are described in US Pat. Nos. 5,095,344, 5,172,338, 5,890,192, and 6,151,248, all of which are incorporated herein by reference.

4A and 4B show two-dimensional block diagrams of an embodiment of a portion of an array of nonvolatile memory elements. FIG. 4A shows a cross section of a memory array taken along line A-A (ie, taken along a word line). FIG. 4B illustrates a cross section of the memory array taken along line B-B of FIG. 3 (ie, taken along the bit line). Although not shown in FIGS. 4A and 4B, triple wells including a P substrate, an N well, and a P well are included. N + diffusion region 444 serving as source and drain is in the P well. The source / drain region 444 may be considered as a source region, a drain region, or both, since the N + diffusion region is somewhat arbitrary whether to be a source region or a drain region. The source / drain region 444 is a source of a memory cell in one NAND string, but serves as a drain to neighboring memory cells.

The channel 446 is located between the source / drain regions 444. Above the channel 446 is a first dielectric layer 410, labeled gate oxide. In one embodiment, the dielectric layer 410 is made of SiO ₂ and other dielectric materials may be used. Floating gate 412 is positioned over dielectric layer 410. The floating gate is electrically isolated from the channel 446 by the dielectric layer 410 under low voltage operating conditions, such as read or bypass operation. Floating gate 412 is usually made of poly-silicon doped with an n-type dopant, but a conductive material such as metal may be used. Dielectric cap 408 is positioned over floating gate 412. A second dielectric layer 406 is positioned around the top and sides of the floating gate 412, labeled inter-poly dielectric (IPD). A polysilicon control gate 404 is positioned over the IPD 406. The control gate 404 may additionally include a tungsten silicide (WSi) layer and a silicon nitride (SiN) layer. The WSi layer is a low electrical resistance layer, while the SiN layer acts as an insulator.

One floating gate stack consists of dielectric layer 410, floating gate 412, dielectric cap 408, IPD 406, and control gate 404. The memory cell array will have many of these floating gate stacks. In one embodiment, a floating gate stack may have fewer or more components than shown in FIGS. 4A and 4B because a floating gate stack is named because it includes other components as well as floating gates. .

In FIG. 4A, shallow trench isolation (STI) structure 407 electrically isolates strings of memory cells. In particular, the STI 407 separates the source / drain regions of one NAND string from the source / drain regions of a neighboring string, although not shown in FIG. 4A. In one embodiment, the STI 407 is filled with SiO ₂ .

4A and 4B, the floating gate has an inverted T shape. That is, the floating gate has a base portion 412b and a stem portion 412a. The inverted T shape helps to increase the area of the portion of the floating gate 412 that coincides with the control gate 404 while keeping the floating gates 412 close to each other. In this example, the cross section of the floating gate along the word line has an inverted T shape. In another embodiment, the cross-sectional inverted T-shape of the floating gate may be formed along the bit line. For example, the floating gate of FIG. 4B may have an inverted T shape. In general, a floating gate, having a top and sides and separated from the control gate by the IPD, may be advantageous if the floating gate has a dielectric cap on top of the floating gate, particularly if the floating gate has a relatively thin width in at least one direction. It may be susceptible to problems due to the strong electric field in the field, so using dielectric caps in these cases can be a great benefit.

The floating gate stem portion 412a need not have a relatively uniform width as shown in FIG. 4A. In an alternative embodiment, the floating gate stem portion 412a may be shaped to have a narrower width in the vicinity of the dielectric cap than in the vicinity of the floating gate base portion 412b.

The technique disclosed herein is directed to reducing the intensity of an electric field in a particular region of the IPD 406. An arrow labeled "upper field" indicates an electric field generated within IPD 406 on top of floating gate 412 and an arrow labeled "edge electric field" indicates IPD 406 near the top edge of floating gate 412. ) Refers to the electric field generated within In one embodiment, the strength of the electric field at the top of the floating gate 412 may be reduced due to the dielectric cap 408 such that it is less than or at least not greater than the strength of the electric field at the corners of the floating gate 412. However, it is not a requirement that the strength of the electric field at the top of the floating gate 412 be weaker than the strength of the electric field at the corner portion. For example, the dielectric cap 408 may serve to reduce the strength of the electric field at the top of the floating gate 412 but need not be weaker than the strength of the electric field at the corners of the floating gate 412. will be. Reducing the strength of the electric field at the top of the floating gate can reduce the overall amount of leakage current without significantly affecting overall performance.

 FIG. 5 is a flow chart describing one embodiment as part of the process of manufacturing the memory cells shown in FIGS. 4A and 4B. 6A-6J illustrate memory cells at various stages of the fabrication process. The process of FIG. 5 is described with reference to FIGS. 4A and 4B and with reference to FIGS. 6A-6J. 6A-6J illustrate cross-sectional views taken along line A-A of FIG. 3. In this example, the width of the floating gate is relatively narrow in the cross section along the word line, but the principle discussed here is that even when the width of the floating gate is narrow in the cross section when viewed along both the bit line and both the bit line and the word line. Note that it applies.

In this flowchart, all implant steps, a gap fill of the etched space between the floating gate stack, a contact formation, a metallization step, a via formation, The passivation step as well as other well known steps in the manufacturing process are not described. There are many methods for manufacturing a memory according to the present invention, and thus other inventions can be made in consideration of various methods besides the method described in FIG. The flash memory chip may include a core memory and a peripheral circuit, but the process shown in FIG. 5 is merely intended to describe, in general terms, one possible process recipe for manufacturing the core memory.

Step 502 of FIG. 5 includes forming a tunnel oxide layer 604 over the silicon substrate 602. Tunnel oxide layer 604 will be used to form gate dielectric layer 410. In step 504, the polysilicon layer 606 used to form the floating gate 412 is deposited over the oxide layer 604 using CVD, PVD, ALD or other suitable method. In operation 505, a second oxide layer 608 is formed on the polysilicon 606. The second oxide layer 608 will be used to form the dielectric cap 408. In step 506 a SiN layer is deposited over the second oxide layer 608. The SiN layer can be deposited by a method such as CVD. In step 508, a photoresist is added. For example, the amorphous silicon pattern 612 is defined using a spacer process. The silicon pattern 612 is transferred to a nitride hard mask 610 in step 508. Step 510 includes etching the nitride hard mask using anisotropic plasma etching, such as reactive ion etching. After step 502 to step 510, the silicon substrate 402, the first oxide layer 604, the polysilicon layer 606, the second oxide layer 608, and the nitride hard mask may remain as shown in FIG. 6A. 610 and amorphous silicon pattern 612 are shown.

After etching the hard mask layer 610 and removing the photoresist 612 in step 512, the hard mask layer 610 may be used as a mask for etching the layers below it. Step 514 includes etching the second oxide layer 608 and a portion of the polysilicon 606 to form the stem portion 412a of the floating gate 412. The etching of this step can be performed using anisotropic plasma etching with a suitable balance between physical and chemical etching for each planar layer. The portion of the second oxide layer remaining after etching forms the dielectric cap 408. Techniques for stopping the etching so that the polysilicon 606 is at an appropriate depth are well known. Techniques for stopping etching are described in U.S. Patent Application No. 11 / 960,485, filed Dec. 19, 2007, and "Composite Charge," entitled "Enhanced Endpoint Detection in Non-Volatile Memory Array Fabrication," which is incorporated herein by reference in its entirety. Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies, "US patent application Ser. No. 11 / 960,498, filed Dec. 19, 2007. The result after the step 512 to the step 514 is shown in Figure 6b is formed in the shape having a dielectric cap 408 on top of the floating gate stem portion (412a).

In step 516, an oxide spacer 708 such as tetraethyl orthosilicate (TEOS) is formed. In one embodiment, an isotropic deposition process is used. In step 518, the oxide spacer 708 is etched so that it is removed only in the horizontal plane but in the vertical plane. In one embodiment, an anisotropic etching process is used to form the oxide spacer sidewalls 708. The result is shown in FIG. 6C where an oxide spacer 708 is formed around the side of the floating gate stem portion 412a and the dielectric cap 408.

The end portion of the floating gate stem portion 412a may be oxidized during or after the step 516 to 518 to cause a bird's beak on the floating gate poly. When the floating gate polysilicon is oxidized, the edge of the upper portion of the floating gate stem 412a is rounded. Changing the oxidation time and reaction well can make the degree of curvature of the upper portion of the floating gate stem portion 412a larger or smaller. Referring to FIG. 6J, it can be seen that a buzz beak 712 is formed at the upper portion of the floating gate 412 so that its end is rounded. The buzz beak 712 is made of silicon dioxide and may therefore tend to act as a dielectric. It should be noted that the buzz beak 712 may affect the overall height of the floating gate and the width of the stem portion. Therefore, these effects must be compensated for earlier in the process.

The oxide spacer 708 is then left to form trenches for shallow trench isolation (hereinafter referred to as STI). In operation 520, the lower portion of the polysilicon 606, the first oxide layer 604, and the upper portion of the silicon substrate 602 are etched while leaving the oxide spacer 708 intact. The etched result is shown in FIG. 6D. In one embodiment, the trench is etched to a depth of approximately 0.2 microns inside the substrate 602 to form an STI between the NAND strings, with the bottom of the trench located within the top of the P well.

In step 522, the STI trenches are filled with an insulator 407, such as partially stabilized zirconia (PSZ) or SiO ₂ , to the top of the hard mask 610 using CVD, rapid ALD, or other methods. In step 524, the insulator 407 is polished and flattened to the SiN 610 using chemical mechanical polishing (CMP) or other suitable process. Figure 6e shows the result after the step 524 to step 524.

In step 526, the STI insulator 407 and the oxide spacer 708 are etched back. In step 527, the nitride hard mask 610 is removed. Steps 526 and 527 can be performed in any order, labeled as option A and option B. Option A will be described first. In step 526, the STI insulator 407 and the oxide spacer 708 are etched back in preparation for depositing an inter-poly dielectric (IPD). 6F shows the result after the step 526.

In step 527, the SiN layer 610 is peeled off. 6G shows the result after going through option A. Removing the nitride hard mask 610 after etch back causes the top of the dielectric cap 408 to be relatively flat.

In option B, the nitride mask 610 is removed 527 prior to the step 526 of etching back the STI insulator 407 and the oxide spacer 708. 6H shows the result after performing option B. Removing the nitride hard mask 610 before etching back makes the top of the dielectric cap 408 relatively rounded. When using option B, the etching may have some horizontal component and both the polysilicon and the oxide cap 408 forming the floating gate stem portion 412a may be etched in small portions so that the floating gate stem portion (from the beginning of the process) 412a) should be slightly wider than the final target.

Step 528 forms or deposits an interpoly dielectric, such as dielectric 406. This dielectric may include a conformal layer, in which oxides and nitrides alternate. For example, an oxide nitride oxide (ONO) interpoly dielectric is used. In one embodiment, the IPD consists of nitride-oxide-nitride-oxide-nitride. The result after step 528 is shown in FIG. 6I. Note that although dielectric cap 408 is depicted in FIG. 6I as having curvature, curvature is not necessarily required.

In step 530, a control gate (word line) is deposited. Step 530 may include depositing a polysilicon layer, a tungsten silicide (WSi) layer, and a silicon nitride (SiN) layer. When forming the control gate, photolithography is used to pattern the strips perpendicular to the NAND chain so that the word lines are separated from each other. Step 530 is performed using a purely physical etching method such as plasma etching, ion milling, ion etching or another suitable process to etch the various layers to form individual word lines.

In operation 532, an implant process is performed to make the N + source / drain region 444. Arsenic or phosphorous implants may be used. In one embodiment, a halo implant is also used. In another embodiment, a heat treatment process such as rapid thermal anneal (hereinafter, referred to as 'RTA') is performed. An example of an RTA parameter is a method of heating to 1000 degrees Celsius for 10 seconds.

4A shows a cross-section taken along line A-A of FIG. 3 after step 532 when rounding the top of dielectric cap 408 using option B. FIG. 4B is a cross-sectional view taken along line B-B of FIG. 3 after step 532 in the case of using option B.

In addition to the structures and processes described above, there are many alternative structures and processes that fall within the spirit of the present invention. One alternative method in the conventional NAND type is to manufacture a memory cell with a PMOS with a bias condition of opposite polarity compared to that implemented with conventional NMOS. In the previous example, the substrate is made of silicon, but other materials well known in the art, such as gallium arsenide, may also be used.

7 is a graph showing the intensity of an electric field as a function of the width of the floating gate stem in various configurations of non-volatile memory elements. Curve 702 shows the intensity of the electric field occurring within IPD 406 directly above the floating gate without using a dielectric cap for a floating gate similar to FIG. 3. The intensity of the electric field was calculated based on the simulation and represents the intensity of the electric field at the point in the IPD above the end of the arrow labeled “A” in FIG. 1C. Note that the narrower the floating gate stem portion, the greater the intensity of the electric field. In addition, the intensity of the electric field increases rapidly when the stem portion width is less than 200 angstroms.

Curve 704 shows the intensity of the electric field in the IPD of the corner of the top of the floating gate without using the dielectric cap 408 for a floating gate similar to FIG. 1C. The intensity of the electric field was calculated based on the simulation and represents the intensity of the electric field at the point in the IPD to the right or left of the double arrow labeled "2A" in FIG. 1C. Note that for a given floating gate stem width, the field strength is greater at the stem portion (curve 702) than at the corner portion (curve 704).

Point 706 is the IPD of the upper corner portion of the floating gate stem portion 412a, which is labeled " edge edge electric field " of FIG. 4A when using a hemispherical dielectric cap 408 similar to the nonvolatile memory element shown in FIG. 4A. The intensity of the electric field at 406 is shown. Floating gate 412 is 100 angstroms wide.

Point 708 represents the electric field generated at the top of the IPD 406 at the top of the floating gate stem portion 412a, which is labeled " top electric field " in FIG. 4A when using a dielectric cap 408 similar to the nonvolatile memory device shown in FIG. 4A. It represents the strength of. Note that the strength of the electric field at the end of the floating gate (point 708) is less than the strength of the electric field at the edge of the floating gate (point 706). In addition, since the intensity of the electric field at the top of the stem portion 412a is reduced, the amount of leakage current in that area is also reduced.

Reducing the field strength above the floating gate can significantly reduce the amount of total leakage current without significantly affecting overall performance. Note that some dielectric material was added to the IPD but the overall amount of dielectric did not increase much. Therefore, the coupling between the floating gate and the control gate is not severely affected. However, the amount of leakage current where the leakage current is most problematic is reduced.

FIG. 8A is a flow diagram illustrating one embodiment of a portion of the memory cell fabrication process illustrated in FIGS. 4A and 4B. 9A-9E show the shape of a memory cell at various stages of FIG. 8A. 9A to 9E illustrate a cross section taken along line A-A of FIG. 3. In this example, the floating gate has a relatively narrow shape when viewed from a cross section along the word line, but the principle discussed herein is a width when viewed from a cross section along the bit line or along both the bit line and the word line. It should be noted that this can be applied even in narrow cases.

In the process shown in FIG. 8A, a process such as annealing is performed to implant a material such as oxygen on top of the floating gate 412 and to form a dielectric cap 408 from the implanted oxygen and polysilicon of the floating gate 412. Treating the floating gate 412 to form the dielectric cap 408. The material to be implanted does not necessarily have to be oxygen. In one embodiment, nitrogen is implanted.

In the process of FIG. 8A, the initial steps used to form the floating gate 412 are not shown. In addition, most of the initial steps, gap fill of the etched portions between the stacks, formation of contacts, metallization, via formation, passivation steps, as well as other well-known parts of the manufacturing process are not shown in this flowchart. There are many methods for manufacturing a memory in accordance with the present invention and can be invented in consideration of various methods besides the method described in FIG. 8A. The flash memory chip has a core memory and peripheral circuits, but the process of Figure 8A describes one possible process recipe for the manufacture of a core memory array in general terms.

Step 902 is to form a floating gate and deposit a material for the STI structure. 9A shows two memory cells in a step after STI material 407 is deposited around floating gate 412. Specifically, FIG. 9A shows two floating gates 412 formed on the substrate 402. Gate oxide 410 was formed between floating gate 412 and substrate 402. The nitride mask 910 has not yet been removed over the floating gate stem portion 412a. After etching into the substrate 402 to make an STI trench, the trench is filled with the STI material 407 to the top of the nitride mask 610. Techniques for forming memory cells up to the steps shown in FIG. 9A are well known and will not be discussed in detail here.

Step 904 is implanting material from the top of the floating gate 412 to serve as a seed material to form the dielectric cap 408 later. In this embodiment, the material is implanted through nitride mask 910. 9B shows the memory cell after implanting the seed material 908 from the top of the floating gate stem portion 412a with the nitride mask 910 in place. In a later process, the seed material 908 is subjected to a treatment such as heat treatment to form the dielectric cap 408. In one embodiment, the seed material 908 is oxygen. When implanting oxygen, a technique similar to separation by implanted oxygen (SIMOX) can be used. SIMOX is a technology for fabricating silicon-on-insulator (SOI) structures and substrates by implanting a large amount of oxygen and performing a high temperature heat treatment. For example, the SIMOX process selects ion implantation energy to implant oxygen ions to the desired depth of the silicon substrate. After implanting the ions, heat treatment is performed to convert oxygen ions into silicon dioxide together with the silicon in the substrate. The silicon dioxide layer was carefully controlled and formed embedded in the silicon substrate using SIMOX. However, SIMOX is typically used to make a layer of silicon dioxide embedded at a certain depth of the substrate, while the present technology forms a dielectric cap 408 over the floating gate 412.

It should be noted that the seed material 908 may be implanted through the SiN 910 with appropriate control of the implant process. Depth and concentration can be controlled by energy and oxygen dose. Depth is controlled by the energy at which ions are implanted. The concentration of seed material 908 may not be uniform when viewed in the vertical direction. For example, the distribution of concentrations may be close to a Gaussian, whereby the peaks of the Gaussian distribution can be formed very close to the surface of the floating gate stem 412a by appropriately selecting the energy used when implanting.

After implanting ions into the substrate 402 to form source / drain regions, side effects such as oxygen conversion to silicon dioxide occur during later steps such as heat treatment. Note that additional steps may be performed if desired, but it is not necessary to add the step of converting the seed material 908.

Seed material 908 need not necessarily be oxygen. In other embodiments, the seed material 908 is nitrogen. In this case the dielectric cap 408 will be SiN. In one embodiment, the seed material 908 includes both oxygen and nitrogen. Other seed materials may also be used.

In one embodiment, a control material is implanted in addition to the seed material 908 to control the formation of the dielectric cap 408. As a control material, the rate at which the dielectric cap 408 is formed during the heat treatment may be controlled. For example, argon may be implanted with oxygen to control the rate at which silicon dioxide is formed from the seed material 908. Argon here can increase the rate at which silicon dioxide is formed. In one embodiment, argon is blown off during a step such as heat treatment so that little or no argon remains. In other embodiments, some argon remains after the memory cells are formed.

In operation 906, the SiN mask 910 is peeled off. The results are shown in Figure 9c. In step 908, the STI material 407 is etched back. The result is shown in FIG. 9D, showing that the STI material 407 is etched back to the height of the gate dielectric 410.

In step 910, an interpoly dielectric such as dielectric 406 is formed or deposited. In one example, an oxide nitride oxide (ONO) interpoly dielectric is used. Depositing the IPD may serve to heat the material in the floating gate 412 to a temperature high enough to at least partially form the dielectric cap 408. For example, silicon dioxide may begin to form from the silicon implanted with the silicon on which the floating gate 412 is formed. Note that some of the implanted oxygen may remain in the floating gate 412 even after the IPD 406 is formed. In later high temperature processes this oxygen may be converted to silicon dioxide. 9E shows the result after step 910. After step 910, well-known steps may be used to form the control gate, source / drain regions, and other portions of the memory cell.

In step 912, the seed material 908 is processed to form a dielectric cap 408 from polysilicon over the seed material 908 and the floating gate stem portion 412a. In one embodiment where oxygen is the seed material, the seed material is processed by a process step of heating the seed material 908 to a sufficiently high temperature to form SiO2 from the implanted oxygen and polysilicon of the floating gate 412. 908 is processed. It should be noted that one or more process steps may be passed to achieve this result. As discussed above, the seed material 908 may be processed at least in part in forming the IPD 406.

The heat treatment performed when forming the source / drain regions is an example of a process step of treating the seed material 908. As such, processing steps to be performed for other purposes serve to treat the seed material to form the dielectric cap 408. Source / drain regions are usually formed by implanting a material such as arsenic or phosphorus onto a substrate. After implantation, a heat treatment process such as RTA is performed. An example of an RTA parameter is a method of heating to 1000 degrees Celsius for 10 seconds. The RTA may convert most of the seed material such as oxygen into SiO ₂ . However, some of the seed material 908 may remain. The seed material 908 thus left may be processed by other process steps. For example, seed material 908 may be processed to form dielectric cap 408 at least partially in a sidewall oxidation process step. During sidewall oxidation, they are placed in a hot furnace and react with some of the surrounding oxygen gas to oxidize the exposed surface, which acts as a protective layer. Sidewall oxidation can also be used to round the edges of the floating gate and the control gate. Note that sidewall oxidation can be performed prior to forming the source / drain regions.

FIG. 8B is a flow chart describing one embodiment of a portion of the process of manufacturing the memory cells shown in FIGS. 4A and 4B. The process of FIG. 8B is an alternative to the process of FIG. 8A. 9F through 9G are cross-sectional views taken along the line A-A of FIG. 3, showing the state of the memory cells formed following the initial steps of the process described in FIG. 8B. 9D-9E illustrate the state of the memory cell formed later in the process, as discussed previously in the process of FIG. 8A. In this example, the floating gate has a relatively narrow shape when viewed from a cross section along the word line, but the principle discussed herein is a width when viewed from a cross section along the bit line or along both the bit line and the word line. It should be noted that this can also be applied in narrow cases.

The process of FIG. 8B has already been discussed in connection with FIG. 8A and begins with forming the floating gate and STI material at step 902. Then, in step 904, the SiN mask 910 is peeled off. FIG. 9F illustrates the formation of a memory cell after step 904 in the process of FIG. 8B.

In step 926, the seed material 908 for forming the dielectric cap 408 is implanted over the floating gate stem portion 412a. 9G shows the result after step 926 is complete. Step 926 may be similar to step 904 of FIG. 8A. However, less implant energy may be used in step 926 because the seed material 908 is implanted directly into the polysilicon of the floating gate 412 instead of through the SiN mask 910. In one embodiment the seed material is oxygen and in another embodiment the seed material is nitrogen. In one embodiment, a control material such as argon is also implanted.

In step 908, the STI material 407 is etched back and the results are shown in FIG. 9D. In step 910, IPD material 406 is deposited, the result of which is shown in FIG. 9E. In step 912, the seed material 908 is processed to form a dielectric cap 408 from polysilicon over the seed material 908 and the floating gate stem portion 412a. Step 912 has been discussed with respect to FIG. 8A.

FIG. 8C is a flow chart describing one embodiment of a portion of the process for fabricating the memory cell shown in FIGS. 4A and 4B. The process of FIG. 8C is an alternative to the process of FIGS. 8A and 8B. 9H-9I illustrate a memory cell formed in accordance with the initial steps of the process described in FIG. 8C, taken along line A-A of FIG. 3. 9D-9E, which have already been discussed in the process of FIG. 8A, show memory cells formed later in the process. In this example, the floating gate has a relatively narrow shape when viewed from a cross section along the word line, but the principle discussed herein is a width when viewed from a cross section along the bit line or along both the bit line and the word line. It should be noted that this can also be applied in narrow cases.

The process of FIG. 8C has already been discussed with respect to FIG. 8A and begins with forming the floating gate 412 and STI material 407 at step 902. In step 904, the SiN mask 910 is peeled off.

Next, in step 944, the STI material 407 is partially etched back. The results after step 944 are shown in FIG. 9H where the STI material 407 is etched down to expose only a portion of the floating gate stem portion 412a. However, the lower portion of floating gate stem portion 412a and floating gate base portion 412b are still covered by STI material 407. The exact depth to etch back the STI material 407 is not critical. In one embodiment, the etch stops at any point prior to descending to the floating gate base 412b so as not to touch the floating gate base 412b when the seed material is added. Note that in this embodiment, since the upper portion of the floating gate stem portion 412a is exposed and oxygen only needs to be implanted to a very shallow depth, the energy when implanting oxygen can be kept relatively low.

In operation 946, the seed material 908 is implanted onto the floating gate stem 412a while the STI material 407 is etched back and the side surfaces of the floating gate stem 412a are exposed. In one embodiment, the seed material is oxygen. In another embodiment, the seed material is nitrogen. In one embodiment, a control material such as argon is also implanted. 9I shows the result after step 946. Note that in this embodiment, most of the STI etch back is performed prior to the implant step.

In step 948, the STI material 407 is further etched back. Note that further seeding of the STI material 407 at this stage will remove any seed material that may have been implanted on top of the STI material 407. 9D shows the result after the step 948. In step 910, an IPD layer 406 is deposited. 9E shows the results after depositing the IPD layer 406.

In step 912, the seed material 908 is processed to form a dielectric cap 408 from polysilicon over the seed material 908 and the floating gate stem portion 412a. Step 912 has already been discussed with respect to FIG. 8A.

10 illustrates a nonvolatile memory device 1010 that may include one or more memory dies or chips 1012. The memory die 1012 includes a two-dimensional or three-dimensional memory cell array 1000, a control circuit 1020, and read / write circuits 1030A and 1030B. In one embodiment, access to the memory array 1000 by several peripheral circuits may be implemented symmetrically on opposite sides of the array, reducing the density of access lines and circuits on each side by half. The read / write circuits 1030A and 1030B include multiple sense blocks 300 to read or program one page of memory cells in parallel. The memory array 1000 may be addressed by the bit lines via the row decoders 1040A and 1040B and the word lines and the column decoders 1042A and 1042B. In a typical embodiment, the controller 1044 is included in the same memory device 1010 (eg, a removable storage card or package) that includes one or more memory dies 1012. Commands and data between the host and the controller are passed over line 1032 and between the controller and one or more memory dies 1012 over line 1034. In one embodiment, it may be implemented to include several chips 1012.

The control circuit 1020 performs memory operations on the memory array 1000 in cooperation with the read / write circuits 1030A and 1030B. The control circuit 1020 includes a state machine 1022, an on-chip address decoder 1024, and a power control module 1026. State machine 1022 controls memory operations at the chip level. On-chip address decoder 1024 provides an address interface that translates an address used by a host or memory controller into a hardware address used by decoders 1040A, 1040B, 1042A, 1042B. The power control module 1026 controls power and voltage provided to word lines and bit lines during memory operations. In one embodiment, the power control module 1026 includes one or more charge pumps capable of producing a voltage greater than the supply voltage.

In one embodiment, the control circuit 1020, power control circuit 1026, decoder circuit 1024, state machine circuit 1022, decoder circuits 1042A, 1042B, 1040A, 1040B, read / write circuits 1030A, 1030B. Any combination of controller 1044 may be represented by one or more managing circuits.

11 illustrates a typical structure of the memory cell array 1000. In one embodiment, the memory cell array is divided into M memory cell blocks. As is common with flash EEPROM systems, blocks are units of erase. That is, each block has the minimum number of memory cells that are erased together. Each block is usually divided into several pages. One page is a unit of programming. Typically one or more pages of data are stored in one row of memory cells. One page may have more than one sector. One sector includes user data and overhead data. The overhead data generally includes an error correction code (hereinafter referred to as 'ECC') calculated from the user data of the sector. One part of the controller calculates the ECC when data is programmed into the memory array and checks the ECC when read from the memory array. ECC, other overhead data, and all of these are stored on different pages, even different blocks, than the associated user data. The user data sector generally has 512 bytes depending on the sector size of the magnetic disk drive. One block is made up of a large number of pages, for example from 8 pages to 32, 64, 128 pages or more. Other sizes of blocks and arrangements may also be used.

In another embodiment, the bit lines are divided into odd bit lines and even bit lines. In an odd / even bit line structure, memory cells connected to a common word line and an odd bit line are programmed at a time, and memory cells connected to a common word line and an even bit line are programmed at a time.

11 illustrates the i-th block of the memory array 1000 in detail. Block i includes 64 word lines WL0-WL63, two dummy word lines WL_d0 and WL_d1, a drain side select line SGD and a source side select line SGS. One end of each NAND string is connected to the corresponding bit line via a drain select gate and the other end is connected to a source line via a source select gate. Since there are 64 data word lines and two dummy word lines, each NAND string includes 64 memory cells and two dummy memory cells. In another embodiment, the NAND string may have more or fewer memory cells than 64 data memory cells and two dummy memory cells. The data memory cell can store user data or system data. Dummy memory cells are generally not used to store user data or system data. In some embodiments, dummy memory cells are not included.

FIG. 12 shows a block diagram of an individual sense block 300 divided into a core portion and a common portion 1290, referred to as a sense module 1280. In one embodiment, each bit line may have a separate sense module 1280 and one share unit 1290 for a plurality of sense module sets. For example, one sense block includes one share unit 1290 and eight sense modules 1280. Each sense module will communicate with the associated share via data bus 1272 as a group. For further details, see US Patent Application Publication No. 2006/0140007, which is incorporated herein by reference in its entirety.

The sense module 1280 is comprised of a sense circuit 1270 that determines whether the current value being conducted in the connected bit line is above or below a predetermined threshold. In some embodiments, sense module 1280 includes circuitry, commonly referred to as a sense amplifier. Sense module 1280 includes a bit line latch 1282 used to set the voltage condition of the connected bit line. For example, the predetermined state latched in bit line latch 1282 results in the bit line connected to the latch being locked to a program inhibit state, such as Vdd.

The sharer 1290 includes a processor 1292, a series of data latches 1294, and an input / output interface 1296 that couples the data latches and the data bus 1220. Processor 1292 performs the calculation. For example, one of its functions is to sense and determine data stored in a memory cell and store the data in a series of data latches. The series of data latches 1294 is used to store the data bits determined by the processor 1292 during a read operation. It is also used to store data bits received from the data bus 1220 during program operation. The data received from the data bus is data to be programmed in the memory. Input / output interface 1296 provides an interface between data latch 1294 and data bus 1220.

The operation of the system is controlled by state machine 1022, which controls to supply different control gate voltages to the addressed cells during read or sense operations. Stepwise application of various predetermined control gate voltages corresponding to the various memory states supported by the memory causes the sense module 1280 to trip one of these voltages to the processor 1292 via the data bus 1272. Export the output. The processor 1292 then determines that the sense module has tripped and determines the resulting memory state in consideration of information about the control gate voltage applied from the state machine via input line 1293. The data bit values resulting from encoding the binary code for the memory state are then stored in the data latches 1294. In another embodiment, the core portion serves a dual role as a bit line latch as well as a latch for latching the output of the sense module 1280.

In some implementations, multiple processors 1292 are expected to be included. In one embodiment each processor 1292 includes one output line although not shown in FIG. 12 and each output line will be coupled together to a wired-OR. In another embodiment, the output lines are inverted before coupling to the connection OR. This configuration allows the state machine receiving the concatenation line to determine whether all the bits being programmed have reached the desired level, allowing for a quick determination of when the programming process is completed during the program verification process. . For example, when each bit reaches the desired level value, a logic value '0' (or inverted logic value '1') is sent out to the concatenation logical sum. When all the bits send out data 0 (or inverted data 1), the state machine knows that it should end the program process. In embodiments where each processor communicates with eight sense modules, the result of the associated bit lines may be that the state machine may need to read the concatenation line eight times or the state machine needs to read the concatenation line only once. Logic circuitry that accumulates values may be added to the processor 1292.

During the program or verify process, data to be programmed is stored in the series of data latches 1294 from the data bus 1220. The programming task consists of a series of programming voltage pulses controlled by the state machine and applied to the control gate of the addressed memory cell. Each programming pulse is followed by a process of verifying that the programmed memory cell has been programmed to the desired state. The processor 1292 observes the verified memory state with respect to the desired memory state. If the two states match, the processor 1292 sets the bit line latch 1282 so that the bit line is held in a state for program prohibition. This prevents the memory cell connected to the bit line from being programmed anymore even if programming pulses are applied to the control gate of the memory cell. In another embodiment, the processor initially loads an initial value into bit line latch 1282 and the sense circuit sets the bit line latch to a program inhibit value during the verify process.

Data latch stack 1294 has a stack of data latches corresponding to each sense module. In one embodiment, there are three to five (or another number) of data latches per sense module 1280. In one embodiment, the latches are each one bit. In other embodiments, this is not necessarily the case, but may be implemented as a shift register such that parallel data stored for data bus 1220 is converted to serial data and serial data is converted to parallel data. do. In a preferred embodiment, all data latches corresponding to read / write blocks of a memory cell may be connected together to form a block shift register so that one block of data can be inputted and outputted by serial transmission. Specifically, the banks of read / write modules are aligned so that each data latch can serially shift data through the data bus, just as a series of data latches are part of one shift register for the entire read / write block.

Additional information on read operations and sense amplifiers can be found in (1) US Patent No. 7,196,931 "Non-Volatile Memory And Method With Reduced Source Line Bias Errors", and (2) US Patent No. 7,023,736 "Non-Volatile Memory And Method with Imporved Sensing ", (3) US Patent Application Publication No. 2005/0169082, (4) US Patent No. 7,196,928" Compensating for Coupling During Read Operations of Non-Volatile Memory ", (5) published July 20, 2006 See US Patent Application Publication No. 2006/0158947, "Reference Sense Amplifier For Non-Volatile Memory." The five patent documents listed above are incorporated herein by reference in their entirety.

The foregoing detailed description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The above described embodiments best explain the principles of the present invention and its practical application, and thus best illustrate the present invention in various embodiments and with various modifications for the particular use now contemplated by those skilled in the art. It is chosen to make good use of it. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (15)

Forming (504, 514, 520, 902) a floating gate having a top and at least two sides;
Forming a dielectric cap on the floating gate (505, 514, 904, 912, 926, 946);
Forming (528) an inter-gate dielectric layer over the dielectric cap and around at least two sides of the floating gate; And
Forming a control gate over the floating gate,
And wherein the inter-gate dielectric layer separates the floating gate and the control gate. The method of claim 1,
Forming the floating gate comprises forming a floating gate from silicon;
Forming the dielectric cap,
Implanting oxygen on top of the floating gate; And
Heating the floating gate to form a dielectric cap from the implanted oxygen and the silicon on which the floating gate is formed. The method of claim 2,
Forming the floating gate comprises using a hard mask; And
Implanting oxygen over the floating gate comprises implanting oxygen through the hard mask. The method of claim 2,
Depositing an insulating material for a shallow trench isolation (STI) structure, wherein the insulating material surrounds at least two sides of the floating gate;
Planarizing the insulating material to a level of a hard mask over the floating gate; And
Removing the hard mask from above the floating gate,
Implanting oxygen on top of the floating gate is performed after removing the hard mask and before removing the insulating material from at least two sides of the floating gate. . The method of claim 2,
Depositing an insulating material for a shallow trench isolation (STI) structure, wherein the insulating material surrounds at least two sides of the floating gate;
Planarizing the insulating material to a level of a hard mask over the floating gate;
Removing the hard mask from above the floating gate; And
Etching back a portion of the insulating material to expose at least a portion of at least two sides of the floating gate,
Implanting oxygen on top of the floating gate is performed after etching back a portion of the insulating material. The method of claim 1,
Forming the floating gate and forming the dielectric cap,
Forming a polysilicon layer used to form the floating gate;
Forming an oxide layer over the polysilicon layer to be used for the dielectric cap;
Forming a pattern on the oxide layer; And
Etching the oxide layer and the polysilicon layer based on the pattern to form the dielectric cap and the floating gate. The method according to claim 6,
Forming the floating gate and forming the dielectric cap selectively oxidize the polysilicon layer used to form the floating gate to provide curvature on top of the floating gate. Further comprising the step of,
Wherein the oxidized portion of the polysilicon layer forms part of the dielectric cap. The method according to any one of claims 1 to 7,
Forming the control gate further comprises forming the control gate around at least two sides of the floating gate. A floating gate 412 having a top and sides;
A control gate (404) over the floating gate (412) and around the sides of the floating gate; And
Inter-gate dielectrics 406 and 408 between the floating gate 412 and the control gate 404,
The inter-gate dielectric includes a dielectric cap 408 over the floating gate 412, and a dielectric material layer 406 over the floating gate 412 and around the floating gate. store. The method of claim 9,
When different voltages are applied to the floating gate and the control gate, an electric field is present in the intergate dielectric, and the dielectric cap is a region of the intergate dielectric on the sides of the floating gate in which the strength of the electric field in the intergate dielectric is A nonvolatile memory device, characterized in that it is formed to be approximately equal to or less than the strength of an electric field in the body. The method according to claim 9 or 10,
And, due to the thickness in the vertical direction of the dielectric cap, a peak value of the intensity of the electric field in the inter-gate dielectric occurs at the sides of the floating gate. The method according to any one of claims 9 to 11,
And the dielectric cap comprises silicon dioxide. The method according to any one of claims 9 to 12,
And said dielectric cap has a curved top. 14. The method according to any one of claims 9 to 13,
And an upper portion of the dielectric cap has a substantially flat upper portion. 14. The method according to any one of claims 9 to 13,
The upper portion of the dielectric cap has a curved shape with a radius of curvature, wherein the width of the portion of the floating gate closest to the dielectric cap is about twice the radius of curvature of the dielectric cap. Volatile Memory.

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