JP5558464B2 - Dielectric layer on floating gate to reduce leakage current - Google Patents

Description

  The present invention relates to a nonvolatile memory.

  Semiconductor memories are becoming more commonly used in various electronic devices. For example, non-volatile semiconductor memories are used in mobile phones, digital cameras, personal digital assistants, mobile computers, non-mobile computers, and other devices. Electrically erasable and rewritable read only memory (EEPROM) and flash memory are the most popular nonvolatile semiconductor memories.

  Typical EEPROM and flash memory employ a memory cell with a floating gate provided on a channel region in a semiconductor substrate. The floating gate is separated from the channel region by a dielectric region. For example, the channel region is aligned with the p-well between the source region and the drain region. The control gate is separated from the floating gate by another dielectric region (intergate dielectric or interpoly dielectric). The threshold voltage of the memory cell is controlled by the amount of charge held on the floating gate. That is, the charge level on the floating gate determines the minimum amount of voltage to be applied to the control gate before the memory cell is turned on to allow conduction between the source and drain of the memory cell.

  Some EEPROM and flash memories have a floating gate that is used to store two charge ranges, so that the memory cell is writable / erasable between two states (eg, Binary memory cells). Multi-bit or multi-state flash memory cells are implemented by specifying multiple distinct threshold voltage ranges within the device. Each threshold voltage range corresponds to a predetermined value for a set of data bits. To achieve proper data storage for multi-state cells, multiple ranges of threshold voltage levels are sufficient to allow the memory cell levels to be read, written, or erased in a well-defined manner Should be separated from each other.

  When writing to a typical flash memory device, a write voltage is applied to the control gate and the bit line is grounded. Due to capacitive coupling between the control gate and the floating gate, the write voltage on the control gate is coupled to the floating gate, inducing a floating gate voltage. The floating gate voltage injects electrons from the channel into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged, and the threshold voltage of the memory cell increases as viewed from the control gate. In order to maintain the written state of the memory cell, the charge on the floating gate needs to be maintained for a long time. However, charge can leak from the floating gate to the control gate through the interpoly dielectric, referred to as leakage current.

  In modern flash memory technology, short write / erase times and low operating voltages are major barriers that must be solved to achieve high speed and high density and low power operation. Thus, it is becoming increasingly necessary to increase capacitive coupling between the floating gate and the control gate of a memory cell and at the same time prevent electrons from escaping from the floating gate to the control gate. The capacitance between the control gate and the floating gate that affects the capacitive coupling ratio depends on the thickness of the interpoly dielectric (IPD) between the two gates and the relative permittivity of the IPD, that is, the dielectric constant K. One approach to achieving a high coupling ratio is to use a thin IPD. However, if the IPD is very thin, the leakage current can be undesirably high.

  As nonvolatile memory structures become thinner, leakage current becomes a more difficult problem. One reason for this leakage current problem is the strength of the electric field that occurs in various parts of the IPD when a voltage is applied to the control gate. Specifically, the electric field is strengthened in certain areas of the IPD, resulting in greater leakage current. Referring to FIG. 1A, the electric field is strongest at IPD 106 proximate to the acute corners of floating gate 102 and control gate 104. In the region close to the corner of the IPD 106 marked with a circle, the magnitude of the electric field is proportional to 1 / A when A is the curvature deformation of the corner of the floating gate 102. The acute corner portion corresponds to a very small radius of curvature, and therefore the electric field is strong.

  In order to reduce the strength of the electric field in the IPD 106 at the corner of the floating gate 102, the radius of curvature at the top of the floating gate 102 can be increased, as shown in FIG. 1B. This increase also changes the curvature of the control gate 104. By reducing the strength of the electric field, the leakage current is reduced. However, in order to further reduce the size of the device structure, it is desirable to reduce the width of the floating gate 102 as shown in FIG. 1C. The roundness of the polysilicon floating gate 102 extends across the entire top of the floating gate 102 of FIG. 1C. The amount of rounding of the floating gate 102 can be limited by the width of the floating gate 102. That is, the maximum radius of curvature (A) can be limited to half the width of the floating gate 102. When the width (2A) of the floating gate 102 is further reduced, the maximum curvature radius is further reduced. Thus, as the processing size of the memory cell is further reduced, it becomes more difficult to handle the electric field in the IPD 106 and thus the leakage current.

  One way to reduce the electric field is to form the IPD 106 using a thin film having a high dielectric constant. However, such membranes are difficult to handle and are therefore undesirable. For example, paraelectrics typically have a dielectric constant that is at least two orders of magnitude greater than that of silicon dioxide, but several problems limit the use of paraelectrics as gate dielectrics. One such problem is oxygen diffusion. During the high temperature process associated with semiconductor manufacturing, oxygen diffuses from the IPD 106 to the interface between the IPD 106 and the floating gate 102 and control gate 104 sandwiching the IPD 106, resulting in the overall dielectric system. An undesirable oxide layer is formed that reduces the capacitance. Therefore, the influence of the high dielectric constant paraelectric is reduced.

Metal oxides have also been proposed as high K materials for flash memory devices. A metal oxide, specifically, aluminum oxide (Al ₂ O ₃ ) has a small leakage current. In addition, metal oxides have high temperature durability for process integration. However, because the deposited high dielectric metal oxide has non-stoichiometric compounds, it tends to have large electrical defects or traps in the majority of the dielectric and at the dielectric / semiconductor interface. These defects or traps increase the conductivity through the dielectric and reduce the dielectric breakdown strength.

  Another approach to reducing the electric field within the IPD is to increase the thickness of the IPD 106. However, increasing the thickness of the IPD 106 tends to reduce capacitive coupling between the floating gate 102 and the control gate 106 and is undesirable for the reasons described above. In general, an increase in the thickness of the IPD 106 tends to fail when the radius of curvature is less than the thickness of the IPD 106 or when the thickness of the IPD 106 approaches the size of the memory cell (processing dimension).

  The disclosed embodiments generally relate to non-volatile memory cells and techniques for manufacturing memory cells. The memory cell has a dielectric cap on the floating gate. In one embodiment, the dielectric cap is between the floating gate and the conformal IPD layer. The dielectric cap reduces leakage current between the floating gate and the control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate where the electric field is strongest when there is no dielectric cap for the floating gate with a narrow stem.

  Another embodiment is a method of manufacturing a non-volatile storage element. The method includes forming a floating gate having an upper portion and at least two sides. A dielectric cap is formed on top of the floating gate. An intergate dielectric layer is formed over the dielectric cap around at least two sides of the floating gate. A control gate is formed on top of the floating gate, and an intergate dielectric layer separates the control gate from the floating gate.

  In one aspect, forming the dielectric cap includes injecting oxygen into the top of the floating gate, and heating the floating gate to form the dielectric cap from the implanted oxygen and the silicon in which the floating gate is formed. Including the step of.

  These and other objects and advantages will become more apparent from the following description in which various embodiments are set forth in conjunction with the drawings.

It is a figure which shows the structure of various floating gate / control gate interfaces. It is a figure which shows the structure of various floating gate / control gate interfaces. It is a figure which shows the structure of various floating gate / control gate interfaces. It is a circuit diagram which shows three NAND strings. It is a figure which shows the structure of a non-volatile memory device. It is a top view of a part of a memory cell array. It is a top view of a part of a memory cell array. 3 is a flowchart illustrating one embodiment of a process for manufacturing a nonvolatile memory cell array. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. FIG. 6 shows a portion of a non-volatile memory cell array at various stages of the process described in FIG. It is a graph which shows the electric field with respect to various structures of a non-volatile memory element. 3 is a flowchart illustrating one embodiment of a process for manufacturing a nonvolatile memory cell array. 3 is a flowchart illustrating one embodiment of a process for manufacturing a nonvolatile memory cell array. 3 is a flowchart illustrating one embodiment of a process for manufacturing a nonvolatile memory cell array. FIG. 8B illustrates a non-volatile memory element at various stages in the manufacturing process of FIG. 8A. FIG. 8B illustrates a non-volatile memory element at various stages in the manufacturing process of FIG. 8A. FIG. 8B illustrates a non-volatile memory element at various stages in the manufacturing process of FIG. 8A. FIG. 8B illustrates a non-volatile memory element at various stages in the manufacturing process of FIG. 8A. FIG. 8B illustrates a non-volatile memory element at various stages in the manufacturing process of FIG. 8A. It is a figure which shows the non-volatile memory element in the step of the manufacturing process of FIG. 8B. It is a figure which shows the non-volatile memory element in the step of the manufacturing process of FIG. 8B. FIG. 8D illustrates a non-volatile storage element at various stages in the manufacturing process of FIG. 8C. FIG. 8D illustrates a non-volatile storage element at various stages in the manufacturing process of FIG. 8C. 1 is a block diagram of a nonvolatile memory system. 1 is a block diagram illustrating one embodiment of a memory array. It is a block diagram which shows one Embodiment of a sense block.

  One embodiment of a flash memory system utilizes a NAND structure that includes placing a plurality of floating gate transistors in series between two select gates. The transistor in series and the selection gate are called a NAND string. A typical structure for a flash memory system using a NAND string structure includes a plurality of NAND strings. For example, FIG. 2 shows three NAND strings 202, 204, and 206 of a memory array having multiple NAND strings. Each NAND string in FIG. 2 includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226, and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246 and 248. Each NAND string is connected to the source line by a select transistor (eg, select transistor 230 and select transistor 250) of the NAND string. The selection line SGS is used to control the source side selection gate. Various NAND strings are connected to each bit line by select transistors 220, 240, etc. controlled by select line SGD. In other embodiments, the selection lines need not be common. Word line WL 3 is connected to the control gates for memory cell 222 and memory cell 242. Word line WL 2 is connected to control gates for memory cell 224, memory cell 244, and memory cell 252. Word line WL 1 is connected to the control gates for memory cell 226 and memory cell 246. Word line WL 0 is connected to the control gates for memory cell 228 and memory cell 248. As shown, each bit line and each NAND string constitutes a column of an array of memory cells. Word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array.

  FIG. 3 is a plan view of a portion of an array of NAND flash memory cells. The array includes bit lines 350 and word lines 352. Note that FIG. 3 does not show all other details of the flash memory cell.

  Note that the number of memory cells included in the NAND string may be increased or decreased from the number shown in FIGS. For example, some NAND strings include 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, and the like. The description herein is not limited to any particular number of memory cells in a NAND string. In addition, the word line can have a number of memory cells that are more or less than the number shown in FIGS. For example, a word line can include thousands or tens of thousands of memory cells. The description herein is not limited to a specific number of memory cells in a word line.

  Each memory cell can store data (analog or digital). When storing 1-bit digital data, the range of possible threshold voltages of the memory cell is divided into two ranges assigned logical data “1” and “0”. In one embodiment of a NAND flash memory, after a memory cell is erased, the threshold voltage is negative and is defined as a logic “1”. The threshold voltage after writing is positive and is defined as logic “0”. When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell is turned on to indicate that a logic 1 is stored. When the threshold level is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell does not turn on, indicating that a logic zero is stored.

  When storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information (2-bit data) are stored, there are four threshold voltage ranges assigned to data values “11”, “10”, “01”, and “00”. In one embodiment of a NAND memory, the threshold voltage after an erase operation is negative and is defined as “11”. The positive threshold voltage is used for data states of “10”, “01” and “00”. When 8-level information (or state) (for example, 3-bit data) is stored, data values “000”, “001”, “010”, “011”, “100”, “101”, “110” There are eight threshold voltage ranges assigned to "" and "111".

  The specific relationship between the data written to the memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. For example, US Pat. No. 6,222,762 and US Patent Application Publication No. 2004/0255090, both incorporated herein by reference, provide various data encodings for multi-state flash memory cells. It describes the method. In one embodiment, the data value is assigned to the threshold voltage range using Gray code assignment so that only one bit is affected if the floating gate threshold is erroneously shifted to an adjacent physical state. In some embodiments, the data encoding scheme can be changed for different word lines to reduce data pattern sensitivity and further memory cell consumption, and the data encoding scheme can change over time. Or data bits for random word lines may be inverted or otherwise randomized.

  NAND flash memories and related examples of their operation are incorporated herein by reference, US patent / patent application: US Pat. No. 5,570,315, US Pat. No. 5,774. 397, US Pat. No. 6,046,935, US Pat. No. 6,456,528, and US Patent Application Publication No. 2003/0002348. The description herein can be applied not only to other types of flash memories in addition to NAND, but also to other types of nonvolatile memories. For example, the following patents, US Pat. Nos. 5,095,344, 5,172,338, 5,890,192, and 6,151,248, describe NOR flash memories. , Which are hereby incorporated by reference in their entirety.

  4A and 4B are two-dimensional block diagrams of one embodiment of a portion of an array of non-volatile storage elements. FIG. 4A shows a cross section of the memory array (cross section along the word line) along the section line AA of FIG. FIG. 4B shows a cross section of the memory array (cross section along the bit line) taken along section line BB in FIG. The memory cell of FIGS. 4A and 4B includes a triple well (not shown) comprising a p-substrate, an n-well and a p-well. Within the p-well is an n + diffusion region 444 that serves as a source / drain. Since the n + diffusion region 444 is called a source region or a drain region is somewhat free, the source / drain region 444 can be considered as a source region, a drain region, or both. In a NAND string, the source / drain region 444 serves as a source for one memory cell and serves as a drain for an adjacent memory cell.

A channel 446 exists between the source / drain regions 444. Above channel 446 is a first dielectric area 410, sometimes referred to as gate oxide. In one embodiment, dielectric layer 410 is made of SiO _2. Other dielectric materials can also be used. Above the dielectric layer 410 is a floating gate 412. The floating gate is electrically isolated / isolated from the channel 446 by the dielectric layer 410 under low voltage operating conditions associated with read or bypass operation. Floating gate 412 is typically made of polysilicon doped with an n-type dopant, but other conductive materials such as metals could be used. Above the floating gate 412 is a dielectric cap 408. Around the top and sides of the floating gate 412 is a second dielectric layer 406, sometimes referred to as IPD 406. Above the IPD 406 is a polysilicon control gate 404. The control gate 404 can include additional layers of a tungsten silicide (WSi) layer and a silicon nitride (SiN) layer. The WSi layer is the lower resistance layer, while the SiN layer serves as an insulator.

  The dielectric layer 410, the floating gate 412, the dielectric cap 408, the IPD 406, and the control gate 404 constitute a floating gate stack (floating gate stack). An array of memory cells has many such floating gate stacks. In other embodiments, the number of components that the floating gate stack has may increase or decrease from the floating gate stack shown in FIGS. 4A and 4B, but the floating gate stack includes floating gates in addition to other components. So called this way.

Referring to FIG. 4A, a shallow trench isolation (STI) structure 407 provides electrical isolation between strings of memory cells. Specifically, the STI 407 separates the source / drain region (not shown in FIG. 4A) of one NAND string from the next NAND string. In one embodiment, STI407 is filled with SiO _2.

  In FIGS. 4A and 4B, the floating gate has an “inverted T” shape. That is, the floating gate has a base 412b and a stem 412a. The inverted T shape helps to increase the area of the portion of the floating gate 412 that coincides with the control gate 404 and allows the floating gates 412 to spatially approach each other. In this embodiment, the cross section of the floating gate along the word line has an inverted T shape. In another embodiment, an inverted T shape appears along a cross section along the bit line. For example, the floating gate in FIG. 4B may have an inverted T shape. However, the floating gate does not necessarily have an inverted T shape. In general, a floating gate with top and sides separated from the control gate by the IPD may benefit from a dielectric cap over the top of the floating gate. However, floating gates that have a relatively thin width in at least one direction are more susceptible to high field problems in the IPD and may therefore benefit more from the dielectric cap.

  It is not essential that the stem 412a of the floating gate 412 has a relatively uniform width, as shown in FIG. 4A. In other embodiments, the floating gate stem 412a may be narrower near the dielectric cap 408 than the lower portion near the floating gate base 412b.

  Techniques for reducing the electric field strength in certain areas of the IPD 406 are disclosed herein. One of the floating gates 412 has an arrow labeled “Upper Electric Field” that refers to the electric field in the IPD 406 above the top of the floating gate 412. The arrow labeled “Corner Electric Field” refers to the electric field in IPD 406 proximate the upper corner of floating gate 412. In some embodiments, the dielectric cap 408 causes the electric field strength at the top of the floating gate 412 to be smaller (or at least not larger) than the electric field strength at the corner of the floating gate 412. Reduced. However, it is not necessary that the electric field at the top of the floating gate 412 is weaker than the electric field at the corner of the floating gate 412. For example, the dielectric cap 408 may serve to slightly weaken the electric field at the top of the floating gate 412, but it is not necessary to weaken the electric field so that it is weaker than the electric field at the corner of the floating gate 412. Reducing the field strength at the top of the floating gate can reduce the overall leakage current without significantly affecting the overall performance.

  FIG. 5 is a flowchart describing one embodiment of a portion of a process for manufacturing the memory cell of FIGS. 4A and 4B. 6A-6J show the memory cells at various stages of the process. The process of FIG. 5 is described along the reference from FIGS. 4A and 4B and FIGS. 6A to 6J show a cross section taken along line AA of FIG. In this embodiment, the floating gate is relatively narrow when viewed in a section along the word line. However, the principles discussed herein can be applied to narrow floating gates when viewed in cross-section along bit lines or both word lines and bit lines.

  This flowchart describes all the implantation steps, gap filling with etched capacitance between floating gate stacks, or other parts of the well-known manufacturing process in addition to contact formation, metallization, vias, and passivation. Not what you want. Since the memory according to the invention can be manufactured in many ways, the inventor believes that various methods other than the method described by FIG. 5 can be used. Although the flash memory chip includes a core memory and peripheral circuitry, the process steps of FIG. 5 are generally intended to describe only one possible process strategy for the manufacture of a core memory array.

  Step 502 of FIG. 5 includes growing a tunnel oxide layer 604 on top of the silicon substrate 602. Tunnel oxide layer 604 is used to form gate dielectric layer 410. In step 504, the polysilicon layer 606 used to form the floating gate 412 is deposited on the oxide layer 604 using CVD, PVD, ALD, or other suitable method. In step 505, a second oxide layer 608 is grown on top of polysilicon 606. This second oxide layer 608 is used to form the dielectric cap 408. Step 506 deposits a SiN layer on the second oxide layer 608. This SiN can be deposited, for example, by CVD. In step 508, a photoresist is added. For example, the amorphous silicon pattern 612 is defined using a spacer process. In step 508, the silicon pattern 612 is transferred to a nitride hard mask. Step 510 includes etching the nitride hard mask 610 using anisotropic plasma etching (eg, reactive ion etching). The results of steps 502-510 result in a silicon substrate 402, a first oxide layer 604, a polysilicon layer 606, a second oxide layer 608, a nitride hard mask 610 remaining after etching, and an amorphous silicon pattern. 6A is shown in FIG.

  After etching the hard mask layer 610, in step 512, the photoresist 612 is stripped and the hard mask layer 610 can be used as a mask to etch the underlying layer. Step 514 includes etching through the second oxide element 608 and a portion of the polysilicon 606 to form the stem 412a of the floating gate 412. Etching can be performed using anisotropic plasma etching with the proper balance between physical and chemical etching for each impacted flat layer. A portion of the second oxide 608 remaining after etching forms a dielectric cap 408. Techniques for stopping the polysilicon 606 etch at an appropriate depth are well known. An exemplary technique for stopping polysilicon etching is filed on December 19, 2007 and is entitled “Enhanced Endpoint Detection in Non-Volatile Memory Array Fabric”, US patent application Ser. No. 11 / 960,485, US Patent Application No. 11/960, filed December 19, 2007, with the name “Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies”. Are also incorporated herein by reference. The result of steps 512-514 is depicted in FIG. 6B showing the formation of a floating gate stem 412a with a dielectric cap 408 on top.

  In step 516, an oxide-based spacer 708 such as tetraethylorthosilicate (TEOS) is grown. In one embodiment, an isotropic deposition process is used. In step 518, the oxide spacer 708 is etched so that it is removed from the horizontal surface rather than the vertical surface. In one embodiment, an anisotropic etch process is used to form sidewall oxide spacers 708. This result is illustrated in FIG. 6C where oxide spacers 708 are represented along the sidewalls of stem 412a and dielectric cap 408 of floating gate 412.

  During or after steps 516-518, the tip of floating gate stem 412a can be oxidized to form a "bird's beak" on top of the floating gate poly. The oxidation of the floating gate polysilicon helps to round the corners at the top of the floating gate stem 412a. Changing the oxidation time and chemistry can cause the top of the floating gate stem 412a to bend at a larger or smaller angle. FIG. 6J shows a floating gate having a top rounded by a “bird's beak” 712 above the floating gate 412. Bird's beak 712 contains silicon dioxide and therefore tends to serve as a dielectric. Thus, in one embodiment, bird's beak 712 can be considered to be part of a dielectric cap. Note that the bird's beak 712 can affect the overall height and stem width of the floating gate. Therefore, such effects should be compensated for early in the process flow.

  Next, shallow trench isolation trenches are formed using oxide spacers 708 in place. Step 520 etches the lower portion of polysilicon 606, first oxide layer 604, and top of silicon substrate 602 using oxide spacers 708 in place. The result is shown in FIG. 6D. In one embodiment, the etch is up to about 0.2 microns into the substrate 602 to create a shallow trench isolation (STI) area between the NAND strings, with the bottom of the trench being the top of the p-well. On the inside.

In step 522, with insulating material 407 such as partially stabilized zirconia (PSZ), SiO ₂ (or another suitable material) up to the top of hard mask 610 by using CVD, high speed ALD or another method. Fill STI trench. In step 524, the insulating material 407 is polished flat until SiN 610 is reached using chemical mechanical polishing (CMP) or another suitable process. The results of steps 522-524 are shown in FIG. 6E.

  Step 526 etches back STI insulating material 407 and oxide spacer 708. Step 527 removes the nitride hard mask 610. These steps can be performed in either order, as indicated by option A and option B in the process flow. Option A will be described first. Step 526 etches back STI insulating material 407 and oxide spacer 708 in preparation for depositing an interpoly dielectric (IPD). The result of step 526 is shown in FIG. 6F.

  In step 527, the SiN layer 610 is stripped. The result of this step for option A is shown in FIG. 6G. The dielectric cap 408 has a relatively flat top when the nitride hard mask 610 is removed after etch back.

  In Option B, the nitride mask 610 is removed (step 527) prior to the etch back of the STI material 407 and oxide spacer 708 (step 526). The execution result of option B is shown in FIG. 6H. The dielectric cap 408 has a relatively rounded top when the nitride hard mask 610 is removed prior to etch back. When using Option B, the etch has a small horizontal component and may slightly etch both the oxide cap 408 and the polysilicon that forms the floating gate stem 412a. Thus, early in the process, the floating gate stem 412a should be defined to be wider than the final desired target width.

  In step 528, an interpoly dielectric (eg, dielectric 406) is grown or deposited. The IPD may include alternating conformal layers of oxide and nitride. For example, an oxide-nitride-oxide (ONO) interpoly dielectric is used. In one embodiment, the IPD includes nitride, oxide, nitride, oxide, nitride. The result of step 528 is shown in FIG. 6I. Note that although dielectric cap 408 is shown in FIG. 6I as having curvature, curvature is not essential.

  In step 530, a control gate (word line) is deposited. Step 530 includes depositing a polysilicon layer, a tungsten silicide (WSi) layer, and a silicon nitride (SiN) layer. When forming the control gates, photolithography is used to create a pattern of strips that are perpendicular to the NAND column to form word lines that are isolated from each other. In step 530, plasma etching, ion milling, ion etching, which is purely physical etching, or another suitable process is performed to etch the various layers and form individual word lines. The

  In step 532, the implantation process is performed to create n + source / drain regions 444. Arsenic implantation or phosphorus implantation can be used. In one embodiment, halo implantation can also be used. In some embodiments, an annealing process such as rapid thermal annealing (RTA) is performed. An exemplary parameter for RTA is heating to 1000 degrees Celsius for 10 seconds.

  FIG. 4A shows a cross section of the memory array along section line AA of FIG. 3 after step 532 when option B is used to round the top of the dielectric cap 408. FIG. 4B shows a cross section of the memory array along section line BB of FIG. 3 after step 532 when option B is used.

  There are many alternative embodiments to the structures and processes described above within the spirit of the invention. As with existing NAND embodiments, an alternative embodiment is to manufacture memory cells from PMOS devices with reverse polarity bias conditions for various operations compared to existing NMOS implementations. In the above embodiment, the substrate is made of silicon. However, other known materials such as gallium arsenide can also be used.

  FIG. 7 is a graph showing the electric field as a function of floating gate stem width for various configurations of non-volatile storage elements. Curve 702 represents the electric field in IPD 406 just above the top of the floating gate when not using a dielectric cap 408 for a floating gate similar to the floating gate shown in FIG. 1C. The electric field is determined based on the simulation and represents a point in the IPD that is above the tip of the arrow, referred to as “A” in FIG. 1C. Note that the field strength increases as the width of the floating gate stem is narrowed. Furthermore, the strength of the electric field increases significantly when the stem width is reduced to 200 angstroms.

  Curve 704 represents the electric field in the IPD at the upper corner of the floating gate without using a dielectric cap 408 for the floating gate similar to the floating gate shown in FIG. 1C. The electric field is determined based on the simulation and represents a point in the IPD that is either left or right of the double arrow, referred to as “2A” in FIG. The electric field strength for a given floating gate stem width is greater than the corner (curve 704) at the stem tip (curve 702).

  Point 706 is at the upper corner of stem 412a of floating gate 412 (referred to as the “corner field” in FIG. 4A) when using a hemispherical dielectric cap 408 similar to the non-volatile storage element shown in FIG. 4A. An electric field in the IPD 406 is expressed. Floating gate 412 has a width of 100 angstroms.

  Point 708 is within IPD 406 on top of stem 412a of floating gate 412 (referred to as “corner field” in FIG. 4A) when using a dielectric cap 408 similar to the non-volatile storage element shown in FIG. 4A. Express the electric field. Note that the electric field strength at the tip of the floating gate (point 708) is less than the electric field strength at the corner of the floating gate (point 706). Furthermore, since the electric field strength at the top of the stem 412a is reduced, the amount of leakage current in this region is reduced.

  By reducing the strength of the electric field at the top of the floating gate, the overall leakage current may be substantially reduced without significantly affecting the overall performance. Note that the overall amount of dielectric does not increase significantly while some dielectric material is added into the IPD. Thus, the coupling between the floating gate and the control gate is not significantly affected. Furthermore, leakage current has been reduced in areas where this was the biggest problem.

  FIG. 8A is a flowchart describing one embodiment of a portion of a process for manufacturing the memory cell of FIGS. 4A and 4B. 9A-9E show various stages of formation by the process of FIG. 8A. 9A-9E show cross sections along line AA in FIG. In this embodiment, the floating gate is relatively narrow when viewed in a section along the word line. However, it should be noted that the principles discussed herein can be applied to narrow floating gates when viewed in cross-section along both bit lines or word lines and bit lines.

  In the process of FIG. 8A, dielectric cap 408 is implanted with a material such as oxygen on top of floating gate 412 such that dielectric cap 408 is formed by the implanted oxygen and polysilicon of floating gate 412. It is formed by processing the floating gate 412 by a process such as annealing. It is not essential that the material be oxygen implanted. In one implementation, nitrogen is implanted.

  The flowchart of FIG. 8A does not show the initial steps used to form the floating gate 412. In addition, the flowchart shows other parts of the known manufacturing process in addition to most implant steps, gap filling with etched volume between stacks, or contact formation, metallization, vias, and passivation. Absent. Since there are many ways of manufacturing a memory according to the present disclosure, the inventors believe that various methods other than the method described by FIG. 8A can be used. A flash memory chip includes a core memory and peripheral circuitry, and the process steps of FIG. 8A are intended only as a general explanation of one possible process strategy for the manufacture of a core memory array.

  Step 902 is to form a floating gate and deposit material for the STI structure. FIG. 9A shows two memory cells at a stage after the STI material 407 has been deposited around the floating gate 412. In particular, FIG. 9A shows two floating gates 412 formed on a substrate 402. Gate oxide 410 is formed between floating gate 412 and substrate 402. The nitride mask 910 is still in place over the floating gate stem 412a. A trench for the STI material 407 is etched into the substrate 402 so that the STI material 407 fills the trench and further extends to the top of the nitride mask 610. The method of forming the memory cell up to the position shown in FIG. 9A is well known and will not be described in detail.

  Step 904 is the step of injecting material into the top surface of the floating gate 412 to serve as a seed material later to form the dielectric cap. In this embodiment, material is implanted through the nitride mask 910. FIG. 9B shows the memory cell after the seed material 908 has been implanted into the top of the floating gate stem 412a using the nitride mask 910 still in place. Later in the process, seed material 908 is processed (eg, with heat) to form dielectric cap 408. In one embodiment, seed material 908 is oxygen. Oxygen may be implanted using a technique (SIMOX) similar to oxygen implantation separation. SIMOX is a technique for manufacturing a silicon-on-insulator structure and a substrate by injecting a large amount of oxygen and continuing high-temperature annealing. For example, the SIMOX process implants oxygen ions into a silicon substrate at a desired depth by selecting the energy at which the ions are implanted. After ion implantation, annealing is performed with silicon in the substrate to convert oxygen ions to silicon dioxide. Using SIMOX, a carefully controlled layer of silicon dioxide is embedded in the silicon substrate. However, although SIMOX is typically used to form a buried layer of silicon dioxide at a depth in the substrate, this approach forms a dielectric cap 408 on top of the floating gate 412.

  Seed material 908 can be implanted through SiN 910 by appropriate control of the implantation process. Depth and concentration can be controlled by the energy and amount of oxygen. The energy at which ions are implanted controls the depth. The concentration of the seed material 908 may be non-uniform in the vertical direction. For example, the distribution may approximate a Gaussian distribution. By appropriate selection of the energy used to inject the material, the Gaussian distribution peak can be defined very close to the surface of the floating gate stem 412a.

  One or more subsequent process steps, such as annealing followed by implanting ions into the substrate 402 to form source / drain regions, have the side effect of converting oxygen to silicon dioxide. Note that adding the step of converting seed material 908 can perform additional steps as needed, but is not essential.

  The seed material 908 is not required to be oxygen. In another embodiment, seed material 908 is nitrogen. In this case, the dielectric cap 408 is SiN. In one embodiment, seed material 908 contains both oxygen and nitrogen. It is possible to use further seed materials.

  In one implementation, in addition to the seed material 908, a control material is implanted to control how the dielectric cap 408 is formed. The control material may control the rate at which the dielectric cap 408 forms during annealing. For example, argon can be implanted with oxygen to control the rate at which silicon dioxide is formed from seed material 908. Argon can increase the rate at which silicon dioxide is formed. In one implementation, the argon is expelled during a step such as annealing so that little or no argon remains. However, in some implementations, some argon may remain after the memory cell is formed.

  In step 906, the SiN mask 910 is stripped. The result is shown in FIG. 9C. In step 908, the STI material 407 is etched back. This result is shown in FIG. 9D, which shows that the STI material 407 has been etched back to the level of the gate dielectric 410.

  In step 910, an interpoly dielectric (eg, dielectric 406) is grown and deposited. For example, an oxide-nitride-oxide (ONO) interpoly dielectric is used. Depositing the IPD may help to heat the material in the floating gate 412 to a sufficiently high temperature to at least partially form the dielectric cap 408. For example, silicon dioxide may begin to be formed from implanted oxygen and silicon from which floating gate 412 is formed. Note that some implanted oxygen may remain in floating gate 412 after formation of IPD 406. A later thermal process step may convert this oxygen to silicon dioxide. FIG. 9E represents the result after step 910. After step 410, well-known steps can be used to form control gates, source / drain regions, and other aspects of memory cells.

In step 912, the seed material 908 is processed to form a dielectric cap 408 from the seed material 908 and the polysilicon on top of the floating gate stem 412a. In embodiments where the seed material is oxygen, the treatment of the seed material 908 is by a process step that heats the seed material 908 to a sufficiently high temperature to form SiO ₂ from the implanted oxygen and the polysilicon of the floating gate 412. Realized. Note that one or more process steps can achieve this desired effect. As described above, forming the IPD 406 can at least partially implement the processing of the seed material 908.

The annealing performed when forming the source / drain regions is one example of process steps for processing the seed material 908. Thus, process steps performed for another purpose may be equally useful for treating the seed material to form the dielectric cap 408. Typically, the source / drain regions are formed by implanting a material such as arsenic or phosphorus into the substrate. After the implantation, an annealing process (eg, rapid thermal annealing (RTA)) is performed. An exemplary parameter for RTA is heating up to 1000 degrees Celsius in 10 seconds. Such RTA can be useful for converting most of the seed material (eg, oxygen) to SiO ₂ . However, some seed material 908 may remain. This remaining seed material 908 may be processed by various process steps. For example, the sidewall oxidation process step may process the seed material 908 to at least partially form the dielectric cap 408. Due to sidewall oxidation, the device is placed in a high temperature furnace with a small percentage of ambient oxygen gas so that the exposed surface oxidizes and provides a protective layer. Sidewall oxidation can also be used to round the edges of the floating gate and the control gate. Note that sidewall oxidation may be performed prior to forming the source / drain regions.

  FIG. 8B shows a flowchart describing a portion of the process of manufacturing the memory cell of FIGS. 4A and 4B. The process of FIG. 8B is another example of the process of FIG. 8A. 9F-9G, which are cross-sections along line AA in FIG. 3, illustrate the stage of formation according to the initial steps described in the process of FIG. 8B. FIGS. 9D-9E (already described in the process discussion of FIG. 8A) show the later stages of formation. In this embodiment, the floating gate is relatively narrow when viewed in a cross section along the word line. However, it should be noted that the principles discussed herein can be applied to narrow floating gates when viewed in cross-section along both bit lines or word lines and bit lines.

  The process of FIG. 8B begins with the formation of the floating gate and STI material 407 in step 902 already described in FIG. 8A. Next, the SiN mask 910 is removed at step 904. FIG. 9F shows memory cell formation after step 904 of the process of FIG. 8B.

  In step 926, seed material 908 for dielectric cap 408 is implanted on top of floating gate stem 412a. FIG. 9G shows the result after step 926. Step 926 may be similar to injection step 904 of FIG. 8A. However, since the seed material 908 is implanted directly into the polysilicon of the floating gate 412 rather than through the SiN mask 910, the implantation energy used in step 926 may be lower. In one embodiment, the seed material is oxygen. In another embodiment, the seed material is nitrogen. In one embodiment, a control material such as argon is also injected.

  Step 908 etches back the STI material 407 and the result is already shown in FIG. 9D. Step 910 deposits IPD material 406, the result of which is already shown in FIG. 9E. In step 912, the seed material 908 is processed to form a dielectric cap 408 from the seed material 908 and the polysilicon on top of the floating gate stem 412a. Step 912 has already been mentioned in connection with FIG. 8A.

  FIG. 8C is a flowchart describing one embodiment of a portion of the process of manufacturing the memory cell of FIGS. 4A and 4B. The process of FIG. 8C is another example of the process of FIGS. 8A and 8B. FIGS. 9H-9I, taken along line AA in FIG. 3, illustrate the stage of formation according to the initial steps described in the process of FIG. 8C. FIGS. 9D-9E (already described in the reference to the process of FIG. 8A) show the stages after formation. In this embodiment, the floating gate is relatively narrow when viewed in a section along the word line. However, the principles discussed herein can be applied to a narrow floating gate when viewed in a cross section along a bit line or both a word line and a bit line.

  The process of FIG. 8C begins with the formation of the floating gate and STI material 407 in step 902 already discussed with respect to FIG. 8A. In step 904, the SiN mask 910 is stripped.

  Next, the STI material 407 is partially etched back at step 944. The result of step 944 is shown in FIG. 9H, which represents that the STI material 407 has been etched down to expose a portion of the floating gate stem 412a. However, the lower portion of the floating gate stem 412a and the floating gate base 412b are still covered by the STI material 407. The exact depth at which the STI material 407 is etched back is not critical. In one embodiment, the etch is stopped at a point before reaching the floating gate base 412b so that when the seed material is added, the etch does not reach the floating gate base 412b. In this embodiment, the top of the floating gate stem 412a is exposed and oxygen is implanted only to a very shallow depth, so that the energy when oxygen is implanted may be kept relatively low. Please be careful.

  In step 946, seed material 908 is implanted on top of floating gate stem 412a and STI material 407 is etched back to expose the sides of floating gate stem 412a at the top. In one embodiment, the material is oxygen. In another embodiment, the material is nitrogen. In one embodiment, a control material such as argon is injected as well. FIG. 9I shows the result after step 946. Note that in this implementation, most of the STI etchback is performed prior to the implantation step.

  In step 948, the STI material 407 is further etched back. Note that seed material that may have been implanted into the upper portion of STI material 407 is removed when STI material 407 is further etched back in step 948. FIG. 9D shows the result after step 948. In step 910, an IPD layer 406 is deposited. FIG. 9E shows the result after depositing the IPD layer 406.

  In step 912, the seed material 908 is processed to form a dielectric cap 408 from the seed material 908 and the polysilicon on top of the floating gate stem 412a. Step 912 has already been discussed with respect to FIG. 8A.

  FIG. 10 illustrates a non-volatile storage element 1010 that may include one or more memory dies or memory chips 1012. Memory die 1012 includes an array (two-dimensional or three-dimensional) 1000 of memory cells, a control circuit 1020, and read / write circuits 1030A and 1030B. In one embodiment, access to the memory array 1000 by various peripheral circuits is performed in a symmetric fashion on the opposite side of the array, thus reducing access line and circuit density by half on each side. . Read / write circuits 1030A and 1030B include a plurality of sense blocks 300 that allow pages of memory cells to be read or written in parallel. Memory array 100 is addressable by word lines through row decoders 1040A and 1040B, and is addressable by bit lines through column decoders 1042A and 1042B. In an exemplary embodiment, controller 1044 is included in the same memory device 1010 (eg, a removable storage card or package) as one or more memory dies 1012. Commands and data are transferred between the host and controller 1044 via line 1032 and between the controller and one or more memory dies 1012 via line 1034. In one embodiment, a plurality of chips 1012 can be included.

  Control circuit 1020 cooperates with read / write circuits 1030A and 1030B to perform memory operations on memory array 1000. The control circuit 1020 includes a state machine 1022, an on-chip address decoder 1024, and a power control module 1026. The state machine 1022 provides chip level control of memory operations. On-chip address decoder 1024 provides an address interface that translates between addresses used by the host or memory controller and hardware addresses used by decoders 1040A, 1040B, 1042A and 1042B. The power control module 1026 controls the power and voltage supplied to the word lines and bit lines during memory operation. In one embodiment, the power control module 1026 includes one or more charge pumps that can produce a voltage greater than the supply voltage.

  In one embodiment, control circuit 1020, power control circuit 1026, decoder circuit 1025, state machine circuit 1022, decoder circuit 1042A, decoder circuit 1042B, decoder circuit 1040A, decoder circuit 1040B, read / write circuit 1030A, read / write circuit 1030B And / or one or any combination of the controllers 1044 may be referred to as one or more management circuits.

  FIG. 11 shows an exemplary structure of the memory cell array 1000. In one embodiment, the array of memory cells is divided into M blocks of memory cells. As is common in flash EEPROM systems, a block is a unit of erase. That is, each block contains a minimum number of memory cells that are erased together. Each block is typically divided into a certain number of pages. A page is a unit of writing. One or more pages of data are typically stored in one row of memory cells. A page can store one or more sectors. The sector includes user data and overhead data. Overhead data typically includes an error correction code (ECC) calculated from user data in a sector. A portion of the controller (described below) calculates the ECC when data is being written into the array and further checks the ECC when data is being read from the array. In an alternative embodiment, ECC and / or other overhead data is stored on a different page or even a different block from the related user data. The sector of user data is typically 512 bytes corresponding to the size of the sector in the magnetic disk drive. A number of pages from 8 pages up to, for example, 32, 64, 128 or more form a block. Different sized blocks and arrangements can be used as well.

  In another embodiment, the bit lines are divided into odd bit lines and even bit lines. In odd / even bit line architecture, memory cells connected to odd bit lines along a common word line are written at some point, while memory connected to even bit lines along a common word line The cell is written at another time.

  FIG. 11 shows further details of block i of memory array 1000. Block i includes X + 1 bit lines and X + 1 NAND strings. The block i further includes 64 data word lines (WL0 to WL63), two dummy word lines (WL_d0 and WL_d1), a drain side selection line (SGD), and a source side selection line (SGS). . One terminal of each NAND string is connected to the corresponding bit line via a drain select gate (connected to select line SGD) and the other terminal has a source select gate (connected to select line SGS). Connected to the source line. Since there are 64 data lines and 2 dummy word lines, each NAND string includes 64 data memory cells and 2 dummy memory cells. In other embodiments, a NAND string can have an increased or decreased number of memory cells, not limited to 64, and an increased or decreased number of dummy memory cells, not limited to two. The data memory cell can store user data or system data. Dummy memory cells are typically not used to store user data or system data. Some embodiments do not include dummy memory cells.

  FIG. 12 is a block diagram of individual sense blocks 300 divided into a core portion called a sense module 1280 and a common portion 1290. In one embodiment, there is a separate sense module 1280 for each bit line and one common portion 1290 for a set of multiple sense modules 1280. In one embodiment, the sense block includes one common portion 1290 and eight sense modules 1280. Each sense module in the group communicates with the associated common part via the data bus 1272. For further details, see US Patent Application Publication No. 2006/0140007, which is hereby incorporated by reference in its entirety.

  The sense module 1280 includes a sense circuit 1270 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. In some embodiments, sense module 1280 includes a circuit commonly referred to as a sense amplifier. The sense module 1280 further includes a bit line latch 1282 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 1282 results in the connected bit line being drawn into a state that specifies write inhibit (such as Vdd).

  The common portion 1290 includes a processor 1292, a data latch set 1294, and an input / output interface 1296 coupled between the data latch set 1294 and the data bus 1220. The processor 1292 performs the calculation. For example, one of the functions of the processor is to determine the data stored in the sensed memory cell and store the determined data in a set of data latches. Data latch set 1294 is used to store data bits determined by processor 1292 during a read operation. The data latch set is also used to store data bits imported from the data bus 1220 during a write operation. The imported data bits represent the write data that is to be written to the memory. Input / output interface 1296 provides an interface between data latch 1294 and data bus 1220.

During reading or sensing, the operation of the system is under the control of a state machine 1022 that controls the application of various control gate voltages to the addressed cell.
When the state machine passes through various predetermined control gate voltages corresponding to various memory states supported by the memory, the sense module 1280 may trip at one of these voltages and the output may be The signal is supplied from the sense module 1280 to the processor 1292 via the bus 1272. At this point, the processor 1292 determines the resulting memory state by considering the sense module trip event (s) and information regarding the control gate voltage applied via the input line 1293 from the state machine. The processor then calculates the binary encoding of the memory state and causes the resulting data bits to be stored in the data latch 1294. In another embodiment of the core portion, the bit line latch 1282 serves a dual role as both a latch that latches the output of the sense module 1280 and a bit line latch as further described above.

  Some embodiments are expected to include multiple processors 1292. In one embodiment, each processor 1292 includes an output line (not shown in FIG. 12) such that each output line is integrally wired-ORed. In some embodiments, the output line is inverted before being connected to the wired OR line. This configuration allows the same state machine that receives the wired-OR line to determine when all the bits being written have reached the desired level, so that during the write verification process, the time at which the write process ends can be quickly determined. Make decisions. For example, when each bit reaches the desired level of this bit, a logical zero for this bit is sent on the wired OR line (or data 1 is inverted). When all bits output data 0 (or when data 1 is inverted), the state machine knows that the write process should be terminated. In embodiments where each processor communicates with 8 sense modules, the state machine (in some embodiments) requires the wired OR line to be read 8 times, or the state machine can read the wired OR line. Logic is added to the processor 1292 to accumulate the associated bitline results so that it only needs to be read once.

  During writing or verification, the data to be written is stored from the data bus 1220 into the data latch set 1294. The write operation includes a series of write voltage pulses that are applied (increase in magnitude) to the control gate of the addressed memory cell under the control of a state machine. Each write pulse is followed by a verification process to determine if the memory cell has been written to the desired state. The processor 1292 monitors the verified memory state relative to the desired memory state. When both match, the processor 1292 sets the bit line latch 1282 to result in the bit line being drawn to a state that specifies write inhibit. This setting prohibits further writing even if the cell connected to the bit line receives a write pulse at the control gate. In other embodiments, the processor first loads the bit line latch 1282 and the sense circuit sets the bit line latch to a prohibited value during the verification process.

  Data latch stack 1294 contains a stack of data latches corresponding to the sense module. In one embodiment, there are 3-5 (or another number) data latches per sense module 1280. In one embodiment, each latch is one bit. In some implementations (although not essential), the data latch is a shift register so that parallel data stored therein is converted to serial data for the data bus 1220 and vice versa. As implemented. In one preferred embodiment, all data latches corresponding to a read / write block of m memory cells form a block shift register so that a block of data can be input or output by serial transfer. , Can be connected together. Specifically, a bank of read / write modules has a data bus as if each one of the bank's data latch sets is part of a shift register for the entire read / write block. Is adapted to shift data into or out of the data bus in sequence.

  Additional information regarding read operations and sense amplifiers can be found in (1) US Pat. No. 7,169,931, “Non-Volatile Memory And Method Reduced Source Line Bias Errors” and (2) US Pat. No. 7,023,736. No., “Non-Volatile Memory And Method Improved Sensing”, (3) U.S. Patent Application Publication No. 2005/0169082, and (4) U.S. Pat. Non-Volatile Memory ”and (5) US Patent Application Publication No. published on July 20, 2006. 2006/0158947, “Reference Scene Amplifier For Non-Volatile Memory”. All five patent documents listed immediately above are incorporated by reference in their entirety.

  The foregoing detailed description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments best elucidate the principles and practical applications of the embodiments of the invention, so that those skilled in the art will understand the invention in various embodiments and the specific uses contemplated. Is selected to allow the most efficient use with various modifications that are suitable for the above. The scope of the invention is intended to be defined by the matters recited in the claims.

Claims (14)

Forming a floating gate (504, 514, 520, 902) having an upper portion and at least two sides;
Forming a dielectric cap on the upper portion of the floating gate (505, 514, 904, 912, 926, 946), wherein forming the dielectric cap on the upper portion of the floating gate comprises: Implanting the material and a second material into the top of the floating gate, the second material controlling the formation of the dielectric cap;
Forming an intergate dielectric layer around the at least two sides of the floating gate and over the top of the dielectric cap (528);
Forming a control gate over the top of the floating gate and around the at least two sides of the floating gate (530), wherein the intergate dielectric layer separates the control gate from the floating gate; The step (530) of
A method of forming a non-volatile memory device. Forming the floating gate includes forming the floating gate from silicon;
The step of forming the dielectric cap includes
Implanting oxygen as the first material into the upper portion of the floating gate;
Heating the floating gate to form the dielectric cap from the implanted oxygen and silicon in which the floating gate is formed;
The method of claim 1 comprising: Forming the floating gate includes using a hard mask;
The method of claim 2, wherein implanting oxygen into the top of the floating gate comprises implanting oxygen through the hard mask. Depositing an insulating material for a shallow trench isolation structure surrounding the at least two sides of the floating gate;
Planarizing the insulating material to the level of a hard mask present on the floating gate;
Removing the hard mask from above the floating gate;
Further comprising
The step of injecting oxygen into the upper portion of the floating gate is performed after the step of removing the hard mask and before the step of removing the insulating material from the at least two sides of the floating gate. The method according to claim 2. Depositing an insulating material for shallow trench isolation surrounding the side of the floating gate;
Planarizing the insulating material to the level of a hard mask overlying the floating gate;
Removing the hard mask from above the floating gate;
Etching back a portion of the insulating material to expose at least a portion of the at least two sides of the floating gate;
Further comprising
The method of claim 2, wherein implanting oxygen into the top of the floating gate is performed after etching back a portion of the insulating material. The step of forming the floating gate and the step of forming the dielectric cap include
Forming a layer of polysilicon used to form the floating gate;
Forming an oxide layer used to form the dielectric cap on the polysilicon;
Forming a pattern on the oxide layer;
Etching the oxide layer and the polysilicon based on the pattern to form the dielectric cap and the floating gate;
The method of claim 1 comprising: The step of forming the floating gate and the step of forming the dielectric cap include
The polysilicon used to form the floating gate is selectively provided such that a curvature is provided on the top of the floating gate and an oxidized portion of the polysilicon forms part of the dielectric cap. The method of claim 6, further comprising oxidizing.   8. The method according to any one of claims 1 to 7, wherein forming the control gate further comprises forming the control gate around the at least two sides of the floating gate. A floating gate (412) having top and sides;
A control gate (404) above and around the top of the floating gate (412);
A dielectric cap (408) between the floating gate (412) and the control gate (404) and over and around the floating gate (412) An intergate dielectric (406, 408) comprising a layer of material (406), wherein the dielectric cap (408) transfers a first material and a second material to the top of the floating gate (412). The inter-gate dielectric (406, 408) formed by implantation into
With
An electric field exists in the intergate dielectric when the floating gate and the control gate are at different voltages, and the dielectric cap is the strength of the electric field in the intergate dielectric at the top of the floating gate. Is a non-volatile memory device that is shaped to be equal to or lower than the strength of the electric field in the intergate dielectric region in contact with the side of the floating gate.   The apparatus of claim 9, wherein a vertical thickness of the dielectric cap causes a peak of the electric field in the intergate dielectric to the side of the floating gate.   11. A device according to any one of claims 9 or 10, wherein the dielectric cap comprises silicon dioxide.   12. A device according to any one of claims 9 to 11, wherein the dielectric cap has a curved upper portion.   12. Apparatus according to any one of claims 9 to 11 wherein the dielectric cap has a substantially flat top.   The top of the dielectric cap has a curvilinear shape with a radius of curvature, and the width of the portion of the floating gate closest to the dielectric cap is approximately twice the radius of curvature of the dielectric cap; Device according to any one of claims 9 to 12.

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