TW201007744A - Non-volatile memory with adaptive setting of state voltage levels and the method therefor - Google Patents

Abstract

A non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

Description

201007744 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a memory device. The name of this application and the co-transfer in the application together with the application is "Method for Adaptive Setting of State Voltage Levels in

Non-Volatile Memory, U.S. Patent Application Serial No. </RTI> (file number SAND-01301US0), which is incorporated herein by reference. [Prior Art] The use of semiconductor memory in various electronic devices has become popular. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable programmable read-only memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. In contrast to conventional full-featured EEPROMs, in the case of flash memory (also a type of EEPROM), the contents of the entire memory array or the contents of a portion of the memory can be erased in one step. Both conventional EEPROM and flash memory utilize a floating gate that is positioned above and insulated from one of the channel regions of the semiconductor substrate. The floating gate is positioned between the source region and the drain region. The control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage (VTH) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate to permit conduction between the source and the drain of the transistor before the transistor is turned on is controlled by the charge level on the floating gate. 139679.doc 201007744 Some EEPROM and flash memory devices have floating gates for storing two charge ranges, and therefore, the memory device can be programmed between two states (eg, erased state and stylized state). / erase. Since each memory element can store a data bit, this flash memory device is sometimes referred to as a binary flash memory device. By convention, a memory that stores one bit per cell is called a "single-level. cell" (SLC) memory and stores more than one bit per cell. The memory is called a "multi-level cell" (MLC). )Memory. For example, when each MLC s memory element can be placed in four discrete charge bands corresponding to four distinct threshold voltage ranges, the memory element can store two data bits. yuan. Typically, the stylized voltage VPGM applied to the control gate during the stylization operation is applied as a series of pulses whose magnitude increases with time. In one possible approach, the magnitude of the pulse increases with each successive pulse by a predetermined step size (e.g., 0.2 V to 0.4 V). The VPGM can be applied to the control gate of the flash memory component. The verification operation is performed during the period between the stylized pulses. That is, the stylized level of each component in the group of parallelly programmed components is read between successive stylized pulses to determine that it is equal to 'the wandering is greater than the verify bit of the component being stylized. quasi. For multi-state flashing, the array of elements can be verified by performing a verification step for each state of the component to determine if the component has reached its data-associated verification level. For example, δ, a multi-state memory element that stores data in four states may require verification operations on three comparison points. In addition, when staging a EEPROM or flash memory device (such as, in contrast, the reverse flash memory device in the 139679.doc 201007744 string), the vPGM is typically applied to the control gate and the bit line is grounded, thereby Electrons from a channel of a cell or memory element (eg, a storage element) are caused to be injected into the floating gate. When electrons accumulate at the floating gate t, the floating gate becomes negatively charged and the threshold voltage of the memory element is raised to cause the memory element to be considered to be in a programmed state. U.S. Patent No. 6,859,397, entitled "Source Side Self Boosting Technique for Non-Volatile Memory", and U.S. Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory" (issued February 3, 2005) Find out more about this stylization; the entire contents of these are incorporated herein by reference. Further, a read reference voltage is applied to a set of storage elements to be read during a read operation and a determination is made as to which read reference voltage causes the storage element to become conductive. The read reference voltage is set to allow for the storage of the data status of the component. However, the voltages used during stylization, verification, and reading are typically fixed and do not account for the fact that the threshold voltage distribution can vary. For example, the threshold voltage distribution can be varied due to problems such as Pr〇gram disturb. The result of 'fixed stylization, verification and read voltages results in non-optimal performance. SUMMARY OF THE INVENTION The present invention provides a non-volatile storage system that sets, for example, voltage levels for writing, reading, and verifying operations to optimize performance. In one embodiment, a storage system includes: a plurality of storage elements 139679.doc 201007744 respective collections of non-volatile storage elements; a non-volatile storage location; and a control circuit. The at least one control circuit: a) measuring the respective threshold voltage distributions of the respective sets of non-=, and b) determining the voltage soil of each of the non-volatile storage elements based on the respective threshold coating cloth The individual collections of voltages in the respective sets σ纟 are customized for individual collections of non-volatile storage elements, c) stored in non-volatile storage locations—the collections are called non-volatile after storage. Storage location ❿ ❿ !: at least one of the respective sets of voltages, and the at least one of the respective sets of voltages « perform at least one of the respective sets of non-volatile storage elements Into the operation. In another embodiment, a storage system includes: a non-volatile collection of non-volatile storage elements; a non-volatile storage location; and a circuit of =g. The at least-control circuit: a) measuring respective threshold voltage distributions of respective sets of non-volatile storage τ, wherein the measuring comprises writing the data to respective sets of non-volatile storage elements, b) based on A separate collection of voltages for each of the individual collections of the non-volatile storage elements of the cloth. The individual collections of voltages are customized for the respective collection of non-volatile storage of 7L pieces. Each of the stored voltages in the non-volatile storage location, + collection port and d), after storage, at least one of the respective sets of voltages obtained from the non-volatile storage locations, and the respective sets of voltages used The at least one of the ones accesses at least one of a respective one of the non-volatile storage elements. Another embodiment includes a collection of independent memory devices. Each of the individual memory devices includes: non-volatile storage S-- or a plurality of individual collections, 139679.doc 201007744::: the storage component is a multi-level storage component; - each non-volatile == body control Circuit. The at least-control circuit: (4) the amount of wt non-volatile storage π pieces of the - or more of the individual = other limited power distribution, (b) based on individual perspective determination of non-volatile storage elements - each (four) The respective voltages of the respective non-volatile storage elements of the combined voltage are stored in respective non-volatile storage locations' and (4) in the respective sets of voltages obtained at the stored η volatile storage locations And the at least one of the respective sets of voltages is used to perform one: and:: the one or more individual sets of the volatility storage element = the operation of the t Each individual collection of volatile storage elements is customized and varies among independent memory devices. Memories include a collection of independent memory devices. Each-different D, non-volatile storage elements - or multiple individual collections, storage / 1 storage storage elements are multi-level storage elements; - each non-volatile, and at least one control circuit. The at least-control circuit (4) the one or more of the non-volatile storage elements in the device:::- or a plurality of respective power-limiting distributions, including measuring data The threshold (4) of the volatile storage element determines a respective set of voltages for each respective set of non-volatile storage elements' (4) stores respective sets of voltages for each respective set of non-volatile storage elements. Among the respective non-volatile storage locations, and (4) the ones of the respective sets of voltages obtained from the respective non-volatile storage locations after storage, and the at least one of the respective sets of voltages used 139679 .doc 201007744 2 Take the one or more individual collections of non-volatile storage elements. In addition, the respective sets of = are for each individual set of non-volatile storage elements, are morphological, and vary among independent memory devices. = (4) methods, systems, and computer or processor readable storage devices for performing the methods provided herein. [Embodiment]

The present invention provides a non-volatile storage system that sets, for example, voltage levels for writing, reading, and verifying operations to optimize performance. An example of a memory system suitable for use in the practice of the present invention uses an inverse flash memory structure that includes a plurality of transistors arranged in series between two selected open electrodes. The series connected transistor and the selected gate are referred to as inverse and string. Figure 丄 is a top view showing the opposite. Figure 2 is its equivalent circuit. FIG. 2 and the reverse series depicted in FIG. 2 include four transistors 1〇〇, 1〇2, 1〇4 connected in series and sandwiched between the first selection gate 12〇 and the second selection gate 122, and 1〇6. The gate 120 is gated to the bit line 126 and the string connection is selected. The gate 122 is gated to the source line 128 and connected in series. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 1 〇〇, 102, 1 〇 4 and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate ioofg. The transistor 102 includes a control gate 102C and a floating gate 102FG. The transistor includes a control gate i〇4CG and a floating gate i〇4FG. The transistor 106 includes a control gate 106CG and a floating gate i〇6FG. The control gate l〇〇CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 139679.doc 201007744 is connected to the word line WL1, and the control gate 1〇6cg is connected to the word line WL0. The control gate can also be provided as part of the word line. In one embodiment, transistors 100, 102, 104, and 106 are each a storage element, which is also referred to as a memory unit. In other embodiments, the storage element can comprise a plurality of transistors or can be different from the storage elements depicted in Figures 2 and 2 . The gate 120 is selected to be connected to the select line sgd (dip gate selection gate). Select gate 丨22 to connect to select line SGS (source select gate). Figure 3 is a circuit diagram depicting three inverses and strings. A typical architecture using a reverse flash memory system will include several inverses and strings. For example, three inverses _32〇, 34〇, and 360 are shown in an array of memories with many inverse strings. Each of the strings includes two selection gates and four storage elements. Although four storage elements are illustrated for simplicity, for example, modern reverse strings can have up to thirty-two or sixty-four storage elements. For example, the reverse string 320 includes select gates 322 and 327 and storage elements 323 to 326. The reverse string 340 includes select gates 342 and 347 and storage elements 343 to 346. The reverse string 360 includes a select gate. 362 and 367 and storage elements 363 to 366. Each of the inverse strings is connected to the source line by its selection gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The various reverse strings 32 〇, 34 〇 and 36 连接 are connected to the respective bit lines 321, 341 and 361 by selecting the selection transistors of the gates 322, 342, 362 and the like. The drain selection line Sgd controls these selection transistors. In other embodiments, the selection lines do not necessarily need to be common in the opposite, i.e., different selection lines may be provided for different inverse strings. Word line WL3 is coupled to the control gates of storage elements 323, 343 and 363. Word line 139679.doc 201007744

WL2 is coupled to the control gates of storage elements 324, 344, and 364. Word line WL1 is coupled to the control gates of storage elements 325, 345, and 365. Word line WL〇 is coupled to the control gates of storage elements 326, 346, and 366. As can be seen, 'each bit line and each of the other columns and rows containing the array or set of storage elements. The word lines (WL3, WL2, WL1, and WL0) contain the array or set of columns. Each word line connects the control gate of each of the storage elements in the column. Alternatively, the control gate can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line. Each storage element can store data. For example, when storing a bit of digital data, the range of possible threshold voltages of the storage elements is divided into two ranges, and logical data "丨" and "〇" are assigned to the two ranges. In one example of a reverse type flash memory, Vth is negative after erasing the storage element and is defined as a logical ri". Vth is positive after the stylized operation and is defined as a logical "Q". When Vth is negative and an attempt is made to read, storing 7L will turn "on" to indicate that the logic "丨" is being stored. When Vth is positive and an attempt is made to read, the Her element will not be turned on, and (5) will store the logic "〇". The storage element can also have multiple levels of information, such as multiple digits of digits. In this case, the range of the Vth value is divided into the number of data levels. For example, if information on four materials is available, there will be four VTH ranges assigned to the data values "..., "~, "... and the factory core. In the case of the inverse type memory - in the instance, The erase operation is negative and is defined as "U". The positive Vth value is used for the states of "ι〇", "〇ι", and "(10)". The material that is programmed into the storage element and the element; the specific relationship between the threshold voltage range of the cattle I39679.doc •11· 201007744 depends on the information coding scheme used for the storage element. Various data encoding schemes for multi-state flash storage elements are described, for example, in U.S. Patent No. 6,222,762, and U.S. Patent No. 7,237,074, the disclosure of each of each of Examples of reciprocal and type flash memory and their operation are provided in U.S. Patent Nos. 5,386,422, 5,57,315, 315, M4M35, 6,456,528 and M22. Each of these patents is incorporated herein by reference. ❹ When stylizing (4) the storage element, 'apply a staging voltage to the control gate of the storage element' and ground the bit line associated with the storage element. The electrons from the channel are injected into the floating idler. When electrons accumulate in the floating gate, the floating_ becomes negatively charged and the Vth of the storage element rises. To apply a programmed voltage to the control gate of the program element being programmed, the stylized voltage is applied to the appropriate word line. As described above, one of the storage elements of each of the strings shares the same word line. For example, when the storage element 324 of Figure 3 is programmed, the programmed voltage will also be applied to the control gates of the storage elements 344 and 364. Unselected storage elements 344 and 364 are subject to stylized interference. Stylized interference occurs when an unselected storage element on the same word line is inadvertently programmed as a selected storage element due to the relatively high stylized voltage applied to the selected word line. Figure 4 depicts a cross-sectional view of a reversed string formed on a substrate. This view is simplified and not drawn to scale. The reverse string 400 includes a source side selection gate 4〇6, a drain side selection gate 424, and eight storage elements 139679.doc • 12-201007744 pieces 408, 410, 412, 414 formed on the substrate 49A. 416, 418, 420, and 422 ° A number of source/drain regions (one of which is source/drain region 430) are provided on either side of each storage element and select gates 406 and 424. In one method, the substrate 490 uses a triple well technique that includes a p-well region 492 within the n-well region 494, which in turn is within the p-type substrate region 496. The reverse string and its non-volatile storage elements can be formed at least partially on the ρ well region. In addition to the bit line 426 having the potential of VBL, a source supply line 404 having a potential of V SOURCE is also provided. Voltage may also be applied to the p-well region 492 via terminal 402 and to the n-well region 494° via terminal 403. During the read operation, a control gate voltage VCG is provided on the selected word line (WL3 in this example), WL3 is associated with storage element 414 and other storage elements not shown. In addition, the control gate that remembers the storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend via control gates of storage elements 408, 4 10, 412, 4 14 , 416 , 41 8 , 420 , and 422 , respectively. φ In a possible arrangement, the read turn-on voltage VREAD is applied to the remaining word lines associated with the inverse string 400. VsGS and VsGD are applied to select gates 406 and 424, respectively. - Figure 5 depicts a block of storage elements. In an example implementation, the inverse flash EEPROM can be partitioned into 1,024 blocks. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest unit of the storage element that is simultaneously erased. In this example, in each block, there are 4,256 rows corresponding to the bit lines BL0, BL1, ..., BL4255. In an embodiment called the All-Band Line (ABL) architecture, it is possible to read and program operations 139679.doc -13 - 201007744 = select all the bit lines of a block and simultaneously program the edges Ugly as a sub-line and connected to the storage element of any bit line. , , ^ The real wealth storage component provided by (4) is connected to the string, and there is a data word line _ to hungry 7. The reverse string can also be a dummy storage element and associated word line. In other embodiments, there are eight or more (four) storage elements. The data record unit can store user or system data. Virtually remember the user or system data. (10) The body μ is normally stored such that the Φ mother and the string-terminal are connected to the selection via the no-pole (connected to the selection; = connected to the corresponding bit line, and the other terminal is connected to the gate via the source (connected to the select gate) The pole source line SGS) is connected to the common source 5〇5. Therefore, the common source 5〇5 is coupled to each-reverse and string. φ In an embodiment called a parity structure, bit lines are divided An even-numbered bit line (BLe) and an odd bit line (BL〇). In this case, the storage elements along the common word line and connected to the odd bit lines are programmed at one time, while stylized along another time. Common word lines and connected to storage elements of even bit lines. In each block, 'divide the lines into even lines and odd lines. During configuration of one of the read and program operations, select Μ% of the storage at the same time. The selected storage element has the same word line and is thus part of the common entity page. Therefore, 'the 532-bit data of a logical page can be simultaneously read or programmed, and the memory block is _block Stores at least eight logical pages. In this example, the physical page and the logical page are In the same way, but in general this is not required. For example, a physical page can include multiple logical pages. A logical page is usually a minimum of 139679.doc -14- 201007744 collection of simultaneously written (stylized) storage elements. For multi-state storage elements, when each storage element stores two data bits (where each of these two bits is stored on a different page), one block stores sixteen logical pages. Use blocks and pages of other sizes. • For fox or parity architectures, the storage element can be erased by raising the p-well to the erase voltage (for example, 20 V) and grounding the word line of the selected block. The polar and bit lines are floating. Each time a block can be erased, or • H (four) memory device is erased every time a number of blocks. The floating gate of the electronic self-storage component is transferred to P Well area to make the Vth of the storage element negative. In the read and verify operation, select the gate (SGD and SGS) to connect to the 2.5V to 4.5 V range and the unselected word line rises to Read the turn-on voltage vREAD (usually at 4 5 乂 to 6 v van Medium voltage) to operate the transistor as a turn-on gate. The selected word line is connected to a voltage, and the level of the voltage is specified for each read and verify operation to determine the associated memory cell. Still below this level. For example, in the read operation of two quasi-storage components, the selected word line can be grounded so that Vth is detected to be still 0 V. In the verification operation, for example - and 5, the selected word line is connected to V to verify that VTH has reached • at least 88 V. The source and P wells are at 0 V. Pre-charge the selected positioning line to (eg A level of 0.7 V. If Vth is higher than the read or verify level on the word line, the potential level of the bit line associated with the storage element of interest maintains a high level due to the non-conductive storage element. On the other hand, if Vth is lower than the read or verify level' then the potential level of the associated bit line is reduced to a low level 139679.doc -15· 201007744 (eg, less than 0.5 v) 'because the conductive storage element makes place Yuan line discharge. Thus, in a possible implementation, the voltage comparator sense amplifier connected to the bit line can detect the state of the storage element. As with stylization, read operations can be performed on a per-page basis. Many details of the erase, read, and verify operations described above are performed in accordance with techniques known in the art. Because of &amp;, those skilled in the art can make many variations in the details explained. Other erase, read and verify techniques known in the art can also be used. Figures 6a through & are related to how the stylized interference can change the threshold distribution of the non-volatile storage elements - and is a procedure for solving this problem. Figure 6a depicts the initial threshold voltage distribution and corresponding verify and read voltages for a set of non-volatile storage elements. The threshold voltage of the storage element is the lowest voltage that changes the channel state from the non-conductive state to the conductive state when applied to the control gate of the storage element. The amount of negative charge trapped in the floating gate affects this voltage: the more charge, the higher the threshold voltage of the cell: The most common type of multi-level cell (MLC) type device uses four charge levels in the floating gate ( Including zero charge), so the four voltage levels can represent the state, whereby the MLC storage element stores two data bits. Generally, he is. Use 2&quot; voltage levels to represent each stored component paste. Newer devices are expected to use eight or more voltage levels. The use of a large number of bits per storage element allows the flash device to be generated at high data densities and thereby reduce the overall cost per flash device. Note that the multi-level data storage and the multi-bit data storage for use in a NROM device, for example, have a multi-bit data storage device that respectively corresponds to a charge level corresponding to 0 or 1. . For example, Α ^ 0 ’ 139679.doc • 16- 201007744 When the MLC storage element stores two data bits, the multi-level data storage relates to the range of charge levels corresponding to 00, 01, 10 and 11. A read operation in an MLC device with four states uses three reference voltage levels, an MLC device with eight states uses seven reference voltage levels, and, in general, stores # bits per cell (its The device of the y state representation uses a reference voltage level for the read operation. In Figure 6a, the graph includes a x-axis representing the threshold voltage and a y-axis representing the number of storage elements. The example MLC device includes eight states (state 〇 to state 7), associated verify voltages 至^ to ^7, and associated read voltages VRjVR7. As each storage element is programmed to the desired voltage group, the distribution of each state is relatively narrow. In addition, the respective reference voltage (e.g., ▽ to %7) used to read the storage element is between the voltage groups, typically just above the previous distribution&apos;, e.g., Vri is in a state. Between the state and the state, just above the distribution of state 0, Yu is between state 丨 and state 2, just above the distribution of state 1, and so on. ▲ As mentioned, 'programmed interference can cause significant changes in the threshold voltage distribution. Stylized interference is inadvertently programmed to be unselected on the line due to the relatively high stylized voltage applied to the selected word line. 7C pieces are selected as: 7L days appear. Stylized interference thus tends to raise the limit voltage A outside, and the lowest state (eg, erase state) tends to rise to the maximum and can therefore be used as a storage element - the process that has been experienced in the set: The worst-case indicator of the amount of disturbance. For the flash memory device; the amount of the read-and-write interference is between different memory devices - between different blocks within the device, and even within the same block = 139679.doc - 17- 201007744 Significant changes between lines. In order to ensure optimal performance of all memory devices in terms of reliability (eg, a minimum number of errors), it is necessary to maintain stylized interference at similar levels or voltage levels (eg, verify and/or read) for all devices. The actual value of the stylized interference that is adapted to a particular device, block, and/or word line. A technique for controlling stylized interference and for matching stylized interference to verify and/or read voltage levels is provided herein. More specifically, the technique customizes the verification and/or read voltage levels used to access a collection of storage elements. Figure 6b depicts the threshold voltage distribution of a set of non-volatile storage elements undergoing stylized interference. The read reference voltages vR1 through Vr7 are depicted to be the same as the read reference voltage in Figure 6a. Here, the lower state threshold voltage distribution is wider and upshifted due to stylized interference than the distribution shown in Figure 6a. Stylized interference is usually significant for low voltage states, while the upper state is generally not compromised by stylized interference. Note that the distribution of adjacent data states may also overlap under some conditions. Here, it can be seen that if the same § selling voltage of Fig. 6a is used to read the data state represented in Fig. 6b, a read error (in this example, at least for the read voltages vR1 to vR5) can be generated. The lower threshold voltage distribution overlaps each of the read voltages Vri through vR5. In contrast, in this example, the lower threshold voltage distribution does not overlap the read voltages Vr6 and VR7. In addition, the effect of stylized interference can be different for different sets of storage elements. For example, the threshold voltage distribution of different sets of storage elements can vary, such as at device, block, and/or word line levels. Therefore, if the same, fixed set of read voltages is used, this situation can result in a non-optimal junction 139679.doc 201007744 Poor Cat 1 causes an error during a read operation. In addition, other factors such as the number of temperature changes - / / erase cycles, and the storage in the block - such as based on the relative position of the storage element pair and the source or the drain of the string can affect the stylization interference. The measurement of the threshold voltage distribution of the near ^6c _6b and the setting of the corresponding read voltage. «The actual threshold distribution procedure involves reading the hidden device in an independent read operation, wherein the number of read operations is based on the resolution of the distribution measurement: if, for example, the memory device uses eight states, It means that for every bit of storage, and each state requires a resolution of ten points, a read operation is performed for each of the seventy-nine threshold levels. In Fig. ^, the Y mother point represents a read point, and the solid line is the same as the solid line in Fig. 6b. A histogram may be provided 'where the height of each bin indicates the number of storage elements in which the threshold dust is in the range specified by the column. The most appropriate read level for a given set of storage elements can be determined, for example, as the minimum between adjacent states. When there is a range of minimum values, the most appropriate read level between the two data states may be just above the distribution of the lower of the two states. Here 'the read level Wr5 has been shifted to the best level relative to the level of the map' and Vr6 and Vr7 have not changed. ^ If the read level of Figure 6b is used, a substantial read error will result. . In general, it is necessary to place the read level as close as possible to the previous level to allow the maximum data retention shift. In general, the "predicted voltage distribution" of a set of storage elements is involved in the storage element. The range of the voltage limit is divided into a plurality of sub-ranges, and 139679.doc -19- 201007744 then the respective number of occurrences of the storage elements in each sub-amp; surrounds the storage in the set of storage elements All or only the appearance of the °P knife is counted. It is also possible to count only the occurrences of the sub-ranges - part W^ &lt; multiple sub-ranges, and extrapolate the results to other sub-ranges. In the method, an on-line evaluation of the programmatic interference of the current device, the block and/or the word line, and a voltage level setting of the evaluated stylized interference are provided, and may be, for example, based on block-by-block measurement. The actual stylized interference that is made into the memory device can be matched between the voltage level setting (the reading and checking voltage of different data states) and the stylized interference measured for the block. These "match per block" voltage level settings can then be used for subsequent stylization and read operations. In order to deal with stylized interference, the verification voltage or the read voltage or both must be modified. The value of the stylized interference can be defined as the width of the threshold voltage distribution of the erased n in one of the pages of all data states. The material recorded to this page includes a representation of all possible data statuses. According to the coffee correction ability, the threshold voltage distribution can be considered to reach a specific percentile of the unit. The stylized interference value can be obtained by randomly staging the batting material, for example, to the memory device, then reading the threshold voltage distribution of all data states and considering the width of the erased state. The preset voltage level setting can be used for this stylization. Once the width of the erased threshold voltage distribution is obtained, it can be determined that the voltage level of the remaining data state is set to exist. There are two methods for calculating the voltage level, that is, "fixed short mustard U疋枉忒"Interference" and "fixed voltage window" methods. Both methods have the same principle. 139679.doc -20· 201007744 Section -' identifies the voltage window available for all data states except the erase state. The available voltage window can be defined as the erasing state t "end" (the rightmost) electric dust (example #, stylized interference value) and the highest can be 2" proof dust (which is Vv7 when there are eight data states) Distance between • • The press window is defined as starting at the lowest (leftmost) voltage of the erased state. Second, the window between the data states is proportional to the relative data retention shift of these states. The data retention shift for a particular component of a block (eg, write/erase cycle) and the given retention time depend on the threshold voltage of the storage component. The higher the threshold voltage, the greater the shift. This dependence, the quantitative characteristics are technical and can be obtained, for example, by testing and/or theoretical calculations. The division of the available voltage window between data states can be based on these characteristics. Second, based on the above, the read level and the verify level of each state are determined. The difference between the two above methods is as follows. In the fixed stylized interference method, the stylized interference value is tuned to a predetermined fixed value by modifying the voltage window (e.g., by modifying the highest data state of the voltage level). Stylized interference is caused by a stress that is induced by the high stylized voltage applied to the word line during stylization on the storage element in the erased state. In addition, when the stylized voltage applied to the word line is high (such as when • the selected storage element is being programmed to the highest data state), the stylized interference is more like this, by changing the highest data state. The verification level controls the stylized interference. An iterative procedure can be implemented to obtain the desired stylized interference value. For example, if the stylized interference is too high, the highest data type I can be lowered. Next, stylized interference is determined, for example, by determining the threshold voltage distribution to determine if it is close to the desired level. If the stylized interference is still too high, the verification level of the highest data status can be lowered again. Note that the verify levels for all states can be related to each other and to the available voltage window by a known function that is linear or non-linear. For example, due to the higher data retention loss of the higher state, the verification level is usually set such that the higher state provides a relatively larger interval than the lower state. Therefore, the entire voltage window is known to calculate the read voltage or verify the voltage. In the fixed voltage window method, the verification level of the highest data state remains fixed at the preset value, resulting in stylized interference as measured. It may vary between word lines, between blocks, and/or between devices. The variable stylized interference value can result in a variable state width for the remainder of the data state. In the example method, the process of adjusting the electromigration level setting may be performed at the manufacturing stage of the memory device or after the memory has been transported to the end user. In addition, the adjustment can be repeated at different times if needed. Or this adjustment can only be performed once for the life of the memory device. In fact, as the ❿:memory device undergoes an additional stylized_erase cycle, the stylized interference is mitigated so that subsequent adjustments may not be needed. r two &quot; and ° 'once the device is transported to the end user, different events (such as temperature changes, through many μ. ^ m .. #化化循环, from the last written capital, provide two quantities of time Etc.) This trigger can be triggered. For this purpose - a tracking component and / or program. In the method, you can use the storage method at the wire. (2) The memory device t. When the block is a ghost: the adjusted (4) value is stored in the address for stylization or reading 139679.doc 22· 201007744 'These block specific values can be advanced—stepped for extraction and used in normal operation of the memory device. m port is in the method, such as at the time of manufacture, can be stored in the memory device. A set of pieces determines read and/or verify • Degenerate set-times. Each time a read or program operation is performed, voltage = . 纟 can be stored in a non-volatile storage location in the memory device and subsequently Access. For other details, see Figures 9a-9e and U). ❿ Figure 7 (10) Burst 7 (8) of the programmed voltage and verify voltage. The pureness of the stylized voltage is increased in a stepwise manner, for example, starting with a program having a amplitude of VPGM1 (four) 705, followed by a programmed pulse 710 having an amplitude of VPGM2, a stylized pulse 715 having an amplitude of VpGM3, and the like. After the mother-stylized pulse, a series of verify voltages Vvi through ~ are applied, as depicted by waveforms 720, 725, and 730. Such verification voltages can be customized for the m-components of the storage elements, as discussed in connection with Figures 6a through &amp;豢 The voltage can also be customized without the use of non-swing components. Figure 8a depicts green using a series of write or program voltages during stylization. For the sake of clarity, the intermediate verify voltage is omitted. As mentioned, the write voltage generally begins at the initial level Vpgm• and increases in amplitude according to the step size until all the storage elements have been programmed to their respective states or reach the final voltage VPGM-FINAL (both The earliest of them). In the method or multiple write voltage parameters can be customized for the particular set of storage elements. For example, if the threshold voltage distribution of one of the storage elements with a lower state indicates that the threshold voltage of these states is mainly above the value of the pre-139679.doc • 23· 201007744 period, or the width of the threshold distribution is larger than expected A high width can be inferred that the stylized effect is stronger than the average effect. Under these conditions, the write voltage is reduced by lowering VPGM-1NITIAL and/or step size. In some cases, the pulse at the maximum allowable vpgm_final or at a lower level may be repeated. A similar adjustment can be made if the stylized effect is weaker than the average effect on one of the set of storage elements, e.g., as all storage elements are programmed to their respective states. Such adjustments may include increasing VPGM-_AL, step size, and/or maximum allowable VpGMF. It should be noted that the step size directly affects the width of the distribution state, so that if the width of each distribution is wider than the average width, the step size can be reduced, and if the width of each distribution is narrower than the average width, then the controller can be X Increasing the step size (for example) to achieve a faster program. Figure 8b depicts data including write, verify, and read voltages that are customized for different sets of non-volatile storage elements. As mentioned, the write, verify, and/or read voltages can be thinned out for different sets of storage elements. The optimum voltage for each set of storage elements can be determined and stored for subsequent use. For example, the voltages of a particular memory device, a block word line, and/or a group of word lines in the memory device can be stored in a non-volatile storage location of the memory device. &quot; The first - 隹 h h T ^ V 丨 不 不 不 不 不 不 不 不 不 不 不 不 不 不 不 T 不 T T T T T T T T T T T T T T T T T T T T T T T T T T T T Voltage. In addition, one or more of the U tables are: the set step size and an AL. Each of these three variables can be tailored (10) for different sets of storage elements. r). Similarly, W2 (eg, among 139679.doc 201007744 - or more: Set &amp; VpGM. Bribe, step d employment. FINAL) represents the write voltage of the second set of storage elements (set 2) ,

Vn-2 or the like represents a verification voltage of the second set of storage elements, and VR2-2 or the like represents a read voltage. In general, VpGMi (for example, a program indicating that R1 is one or more of each of two), a vpgm._al of a set i, a step size, and a VPGM_ FINAL, and the like, represents a program that stores the ith set (set i) of the component. The voltage is VV1-i, Vvu, etc., which represent the verification voltage of the third set of storage elements, and %ii, Vju-i, etc. represent the read voltage. Figure 9a depicts a procedure for determining the voltage of a set of non-volatile storage elements. Step 900 includes a start-program to obtain a set of voltages (e.g., read, verify, and/or write voltages) of a set of non-volatile storage elements. The set may represent, for example, a storage element associated with one or more particular word lines in a block having a plurality of word lines, associated with a particular block in a memory device having a plurality of blocks The storage element's or the storage element associated with the entire particular memory device. Step 9.2 includes a method for staging the set of non-volatile storage elements by random test data. Test data should include all data status. For example, this test data may be available when the memory: is subjected to testing at the manufacturing site prior to shipping. After the memory device has been transported, 1 no test data is available: the existing user data can be alternatively programmed. User data can also be sewn so that it can indicate the status of all data in a relatively uniform manner. For example, a child in a location of a memory device (such as a given block) may be copied to another location, such as including a particular set of storage elements for which the read/verify voltage will be determined Another part of the block. , 139679.doc •25- 201007744 After step 9〇2, you can follow one of the two paths. In the first path, step 904 includes determining the threshold voltage distribution of the storage elements, for example, by performing a read operation (as depicted in Figure 6c) with different incremental voltage threshold levels. In general, this can involve determining all data types and limiting their distribution. Step 906 includes determining a set of voltages based on the threshold electrical waste distribution. For example, a set of read voltages can be determined based on the minimum value of the threshold voltage distribution, as in Figure 6. (4) The window is pressed to determine a set of verification voltages. For example, the power window can be determined from the threshold voltage distribution and the function of the desired relative spacing is provided between the verify voltages within the constraints of the entire dust window to determine the verify voltage. Step W2 includes storing the set of identification voltages in a non-volatile storage location. For example, the data of the set of voltages can be stored in the memory device to obtain the storage element t from which the power limiting M is distributed. By way of example, such storage elements may be storage elements that do not store user data. In the - method, the data is stored in the storage element from which the block's threshold voltage distribution is obtained. In another method, the data is stored in the word line to obtain the storage element Φ from which the distribution of the dust is limited. # __ y^ In the case of the device, the non-volatile storage location used by the controller of the memory device can be used. Other locations are also available. In the 'Step 908' section, a threshold voltage distribution is determined for the set of storage elements for a data state that is less than all data states. For example, it is possible to determine the distribution of the erased state. As mentioned, the upper edge of the threshold voltage distribution of the erased state can be used to measure the level of stylized interference' because this state is most susceptible to stylized interference. The state m optimal read level can be determined based on the upper edge, and the optimal read bit of the remaining state can be determined based on the known relationship between the read levels of the states 139679.doc • 26-201007744 quasi. That is, the formula for correlating the optimal read level of state i (i &gt; 2) with the best read level of state 1 can be used. It is also possible to determine the threshold voltage knife&apos; for the set of storage elements for a plurality of data states (e.g., for state and state 2) and to associate this state with other states. For example, a formula that correlates the best read level of state i (i &gt; 3) to the best beta sell level of state 1 and state 2 can be used. These formulas can be obtained from theoretical relationships and/or experimental test results. Step 91 〇 thus includes determining a set of voltages based on a threshold voltage distribution of data states that are less than all data states. Further, the material of the set of voltages can be expressed in any manner. Figure 8b, previously discussed, provides a possible example. In some cases, the identifier of the set of storage elements can also be used, as depicted (e.g., set 1, 2, ..., i). For example, the controller can have a storage location that stores a different set of electrical waste for each of the respective devices, or a different set of voltages for the groups of blocks in the device. In this case, the identifier of the set of storage elements can be associated with each set of voltages. In other cases, the location of the set of voltages is used as the identification of the storage element to which the voltage is applied. For example, a set of voltages stored in the block may be applied to the block or voltage stored in the word line. A set of can be applied to the word line. In another example, several sets of voltages of different blocks are stored in a block. In this case, an identifier may be required to associate the block with its corresponding set of voltages. In some cases, several sets of voltages may be stored such that their relative position in the storage location identifies the storage element to which the voltage is applied. For example, the first position in the storage location may correspond to 139679.doc • 27- 201007744, the first block, and the second position in the storage location may correspond to the second block, 匕, or the storage location may be at In the block, wherein the first location in the storage location may correspond to a first word line or a set of word lines in the rabbit, and the second location in the storage location corresponds to the second word line or a word in the block A collection of lines, and so on. The absolute value of the voltage can be stored, or an offset value representing one of the self-valued reference sets or the offset from the single &amp; apostrophe value can be stored. Alternatively, data for directly controlling the circuit can be used, such as binary code words for input to digital analog converters. In any event, this technique is understood to mean that the techniques provided in the set of voltages advantageously do not require the use of reference storage elements for additional storage elements that are changed in order to track the device's already shifted L limit. The purpose is to store non-user data. The reference storage item exceeds the storage element of the stored user data and consumes additional space in the memory device. The reference storage element is usually read "on the fly" so that the adjustment occurs whenever the -page data is read. In this case there is no _ set of stored voltages in the non-volatile storage locations for subsequent use. In addition, the reference storage element generally does not involve measuring the threshold voltage distribution. By using the storage element 'for the storage element m (for example, referring to the storage element to measure the voltage of the second non-heavy 4 set of the storage element), the technique provided in the spit storage: = for the use voltage And the same set of stored readings is taken, the measurement is performed and the electric sensation is determined. Fig. 9bH is used for the user who uses the silent voltage to determine the non-volatile (four) memory element determined by the program of Fig. 9a. Procedure for data. 139679.doc -28. 201007744 In the method, after the memory device has been transported to the user, that is, after each device has been installed and the device has been installed in the host system used by the user' Access may occur. Step 92 includes an operation to initiate a set of non-volatile storage elements (eg, stylize, verify, or read a step Μ) to include a set of voltages obtained from a non-volatile storage location. Step 924 includes &amp; A collection of power &amp; access to the user data of the collection of non-volatile storage components. This access may include stylization/verification or reading. Figure 9 (; Determining multiple non-volatile storage elements a process of combining voltages. As mentioned, the voltage can be different for a different set of storage elements included in a single memory device and among different memory devices, similar to those in Figure 9a. Step 93 includes selecting one or more sets of non-volatile storage elements in the memory device. Step 932 includes initiating the program to obtain a corresponding set of voltages. Step 934 includes programming the non-random test data. The set of volatile storage elements. Step 936 includes determining a threshold voltage distribution of the one or more sets of non-volatile storage elements. Step 938 includes determining a set of voltages based on the threshold voltage distribution, step 94, including Storing a respective set of voltages of the currently selected one or more sets of non-volatile storage items in a non-volatile storage location. At decision step 942, if there is a next set of storage elements in the memory device, The program then continues at step 930 to select one or more sets below the non-volatile storage element. If no storage element is present in the memory device The next set, the program continues at decision step 946. If, for example, in a manufacturing environment in which a plurality of memory devices are analyzed, there is a memory device below the decision voltage, then the program proceeds at step 93 at step 139679. .doc -29 - 201007744 continued. If there is no next memory device at step 946, the program ends at step 948. For example, each pass through the program may involve obtaining a word line, word line of the storage element. a collection of blocks, blocks, or a collection of voltages of one of the blocks. For example, a given set of voltages can be applied to a storage element of a set of individual word lines or word lines, or to a particular area. A collection of blocks or blocks. Furthermore, it is noted that when determining, for example, multiple sets of voltages for writing, verifying, and/or reading, each set can be applied to a different group of storage elements. For example, a set of zeros of verify voltages can be obtained for the entire memory device, while different sets of read voltages are obtained for different blocks in the memory device. Multiple passes can be performed serially or simultaneously through the program. Figure 10 depicts a procedure for accessing a plurality of sets of user profiles of non-volatile health care entities using predetermined voltages determined by the process of Figure 9c. The step blue includes selecting one or more sets of non-volatile storage elements in the memory device. Steps 1002 through 1006 generally correspond to steps 920 through 924 of Figure 9b, respectively. Step 1002 includes initiating an operation (e.g., 'programming, verifying, or reading) the one or more sets of non-volatile storage elements. Step · Includes obtaining a corresponding set of voltages from non-volatile storage locations. The step brain includes accessing the user profile of the one or more sets of non-volatile storage elements using a respective set of voltages. This access can include stylization/verification or read_. At the decision step, if there is a next set of storage elements to be accessed in the memory device, then the program continues at step 1000, wherein _ or more of the non-volatile storage elements in the memory device are selected set. At decision step _, if there is no next set of storage 139679.doc 201007744 files to be accessed in the memory device, the program ends at step 1010. As before, each pass through the program may involve obtaining a collection of voltages, word lines, sets, blocks, or blocks of storage elements, and accessing the corresponding dependent elements. A given set of voltages can be applied to a collection of storage elements of a line or word line, or to a collection of individual blocks or blocks. Multiple passes can be performed serially or simultaneously through the program. The ® 11 is a block diagram of an array of counter-flash storage elements, such as those shown in Figures 1 and 2, which are opposite to the flash storage elements. Along each line, the bit line is coupled to the terminal of the associated reverse and the gateless select gate. For example, bit line 1106 is coupled to a non-polar terminal 1126 that is opposite to the drain select 115 of the drain. Along the opposite column, the source line 11〇4 can be connected to all of the source terminals 1128 of the source select open of the string. An example of the operation of the inverse array and its operation as part of a memory system is found in U.S. Patent Nos. 5,570,315, 5,774,397, and 6,46,935. The array of storage elements is divided into a number of storage element blocks. For the fast flash EEPR〇M system is common, the block is the unit of erasing. That is, each block contains - the smallest number of storage elements that have been erased. Each block is usually divided into a number of pages. The page is a stylized unit. - or multiple data - 1 is usually stored in the column of storage elements. - The page can be stored - or multiple zones _ @. The section includes user data and additional item information. The additional item data usually includes an error correction code calculated from the user data of the segment (10). When the data is being programmatically programmed into the array, one of the controllers (described below) calculates the coffee and when the data is being read from the array. The controller also checks the ECC. Alternatively, the ECC and/or other additional items may be stored in a different page or even a different block from the user profile of 139679.doc -31- 201007744. One of the sections of user data is typically 512 bytes, which corresponds to the size of the extent in the disk drive. The additional item data is usually an additional 16 to 20 bytes. A large number of pages form a block from 8 pages (for example) up to any of 32, 64, 128 or more pages. In some embodiments, a column of the inverse string contains a block. - Figure 12 depicts a summary of the host controller and memory devices in the storage system. The memory device alone can also be considered a storage system. The storage element 1205 can be provided in a memory device 12, which has its own controller 1210 for performing operations such as stylization/verification and reading. The memory device can be formed, for example, on a removable memory card or USB flash drive that is inserted into a host device such as a laptop, digital camera, personal digital assistant (PDA), digital audio player, or mobile phone. . The host device can have its own controller 1225 for interacting with the memory device (e. g., reading or writing user data). For example, when the data is retrieved, the host controller can send a command to the memory device' to indicate the address of the user data to be retrieved. The memory device controller converts these commands into command signals that can be interpreted and executed by the control circuitry in the memory device. The controller 210 can also include non-volatile storage locations (2) 5 for storing a plurality of sets of voltages (as previously discussed) and for users to read (4) writes to or read from the memory array. The buffer of the data is recorded. The host controller can be considered to be an entity that is external or external to the memory device. For example, the memory device can include one or more memory dies and the host controller can be in the one or more memory dies - 32. 201007744, discussed in connection with FIG. = loading: reading data from the storage element and making it

Take the command. In the possible method, the memory device is stroked and informs the host controller when another life/host control 11 responds by reading data from the buffer 11 and sends:: 7 to the memory device. Read data from another address. Example —° ’ can read data one by one. The host control can process the read data to determine the threshold voltage distribution of the storage elements of the memory device. In another method. The control circuit of the hidden device determines the distribution of the dust. Additional details of example embodiments of memory devices are provided below. 8. A redundant memory system comprising: an integrated circuit chip comprising a controller 1210' and/or a plurality of integrated circuit chips each comprising a memory array and associated control, input/output and status Machine circuit. The memory device can be embedded as part of the host system or can be included in a memory card that can be inserted into the mating socket of the host system in a decimate manner. The card may include the entire memory device, or a controller with associated peripheral circuitry and a memory array may be provided for the individual card. Figure 13 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1396 having read/write circuits for reading and programming a page of memory elements in parallel, in accordance with an embodiment of the present invention. Memory device 1396 can include one or more memory die 1398. The memory die 1398 includes a two-dimensional array of storage elements 1400, a control circuit 131A, and a read/write circuit. "In some embodiments, the array of storage elements can be three-dimensional. The memory array 14 can be borrowed from the word line via the column decoder 1330 and the bit line via the row decoder by 139679.doc -33 - 201007744 The addressing/writing circuit 1365 includes a plurality of sensing blocks 〇〇3〇〇 and allows for parallel reading or programming of a page of storage elements. Typically, the controller 135 is coupled to the one or more memory cells. The granules 1398 are included in the same memory device 1396 (eg, a 'removable memory card). Commands and data are transmitted between the host and the controller 135A via line 132 and transmitted to the controller and the one or more via line 1321. Memory die between 1398.

Control circuit 1310 cooperates with read/write circuit 1365 to perform a memory operation on memory array 1100. Control circuit 1310 includes state machine 1312

b曰 On-chip address decoder 丨3丨4 and power control module 丨3丨6. The state machine i3 i 2 provides wafer level control of the memory operation. The on-chip address decoder 1314 provides an address interface between the address used by the host or the 6-replica controller and the hardware address used by the decoder 丨3 3 . Power control module 13 16 controls the power and voltage supplied to the word lines and bit lines during memory operation. For example, power control module 13 16 can provide a control gate read voltage to a selected word line and provide a read turn-on voltage to an unselected word line for use during a read operation and for use in determining A threshold voltage distribution of a collection of storage elements. The power control module (3) (4) provides a voltage sweep to the selected word line. Power control module 1316 can include (10) such as one or more digital analog converters for this purpose. In this case, the control circuit can generate a voltage sweep without the need for an external test device (e.g., outside of the memory cell 1398). This situation is advantageous 'because it allows a voltage sweep to be generated at any time, including when the memory device is manufactured, when the end user has occupied the memory device. 139679.doc -34- 201007744 In addition, the body device 1396 can include circuitry for determining the threshold voltage of the storage element so that it can be used without the need for an external test device or an external host. This procedure is performed internally within the body grain J398. This situation is / for the benefit of the purpose of allowing the threshold voltage distribution to be determined at any time without external preparation. In some implementations, some of the components of Figure 13 can be combined. Set in various categories. One or more of the components except the storage element array 11 • can be considered as management or control circuits. For example, - or a plurality of government or control circuits may include control circuit 1310, state machine 1312, damper 1314/136G, power control 1316, sense block i, read, write circuit 1365' control Either or a combination of the device 135A, the host controller 1399, and the like. The data stored in the memory array is read by the row decoder 〇 36 且 and output to the external 经由 line via the data I/O line and the data input/output buffer i352. The stylized material to be stored in the memory array is input to the data input/output buffer (10) via the external ι/〇 line. The command data for controlling the memory device is input to the controller 1350. The command data tells the quick message what kind of operation is requested. The input command is transmitted to the control circuit 1310. The state machine 1312 can output the status of the memory device, such as ready to go or pass/fail. When the memory device is busy, it cannot receive new read or write commands. A data storage location 1354, similar to the storage location 丨 21 5 of Figure 12, may also be provided in conjunction with the controller 1350. In another-possible configuration, the non-volatile memory system can use dual-column / 139679.doc • 35· 201007744 to play decoders and read/write circuits. In this case, access to the array by various peripheral circuits is performed symmetrically on opposite sides of the memory array such that the density of access lines and circuitry on each side is halved. The foregoing embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and its application, and thus, The invention is utilized optimally. The scope of the invention is intended to be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of a reverse and a string; FIG. 2 is an equivalent circuit diagram of the reverse and string of FIG. 1; FIG. 3 is a block diagram of an array of inverse flash memory elements; Figure 5 depicts a block of storage elements; Figure 1 depicts the initial threshold voltage distribution of the non-volatile storage elements and the corresponding verification and read voltages; Figure 6b depicts the stylization The threshold voltage distribution of one of the non-volatile storage elements of the interference; Figure 6c depicts the measurement of the threshold voltage distribution of Figure 6b and the setting of the corresponding read voltage. Figure 7 depicts a burst of stylized voltage and verify voltage; Figure 8 &amp; Green can be used during stylization of the 'series of writing or stylized electricity 139679.doc •36- 201007744

Figure 9b depicts a

Figure 8 b depicts the circle of the person who writes, (4), and reads the electric H. (4): The trace is used to determine the set of non-volatile storage components. a program for accessing a user data of a non-volatile library element by a predetermined voltage determined by the program of FIG. %; a program for depicting a non-volatile material cell pressure; A block diagram U for storing user data of a plurality of sets of non-volatile storage elements using a predetermined voltage determined by the routine of FIG. 9C is a block diagram of an array of inverse flash storage elements; FIG. 12 depicts a host A summary of the controller and memory devices is a block diagram of a single column/row decoder and a read/write circuit memory system. Soap depletion [main component symbol description] too transistor 100CG control gate 100FG floating gate 102 transistor! 〇 2CG control pole 102FG ocean gate 104 transistor 104CG control gate 139679.doc -37- 201007744 104FG floating Gate 106 transistor 106CG control gate 106FG floating gate 120 first selection gate 120CG control gate 122 second selection gate 122CG control gate 126 bit line 128 source line 320 opposite string 321 bit line 322 Select Gate 323 Storage Element 324 Storage Element 325 Storage Element 326 Storage Element 327 Select Gate 340 Reverse String 341 Bit Line 342 Select Gate 343 Storage Element 344 Storage Element 345 Storage Element 139679.doc 38- 201007744 φ 346 Storage Element 347 Select gate 360 and string 361 bit line 362 Select gate 363 Storage element 364 Storage element 365 Storage element 366 Storage element 367 Select gate 400 Reverse string 402 Terminal 403 Terminal 404 Source supply line 406 Source side selection Gate 408 storage element 410 storage element 412 storage element 414 storage Element 416 storage element 418 storage element 420 storage element 422 storage element 424 drain side selection gate 139679.doc • 39. 201007744 426 bit line 430 source/nothing area 490 substrate 492 P well area 494 η well area 496 ρ Substrate Area 505 Common Source 700 Burst 705 Stylized Pulse 710 Stylized Pulse 715 Stylized Pulse 720 Waveform 725 Waveform 730 Waveform 1100 Storage Element Array / Memory Array 1104 Source Line 1106 Bit Line 1126 汲 Extreme 1128 Source Extreme 1150 anti-string 1200 memory device 1205 storage element / non-volatile storage element 1210 controller 1215 non-volatile storage location / storage location 139679.doc -40- 201007744 1220 buffer memory / buffer 1225 controller 1300 sense Block 1310 Control Circuit 1312 State Machine 1314 On-Chip Address Decoder * 1316 Power Control Module / Power Control 1320 Line 1321 Line 1330 Column Decoder 1350 Controller / Control Circuit 1352 Data Input / Output Buffer 1354 Data Storage Location / Non-volatile storage location 1360 lines of decoding 1365 Read/write circuit φ 1396 Memory device 1398 Memory die 1399 Host controller. BLO bit line BL1 Bit line BL2 Bit line BL3 Bit line BL4 Bit line BL5 Bit line 139679.doc - 41 - 201007744 BL6 bit line BL7 bit line BL4252 bit line BL4253 bit line BL4254 bit line BL4255 bit line SGD select line / drain select gate / select gate immersion line / drain select line / select Gate SGS Select Line/Source Select Gate/Select Gate Source Line/Select Gate Vbl Bit Line Potential VcG Control Gate Voltage V pgm-i Storage Element Set 1 Write Voltage V PGM-2 The write voltage of the set of storage elements 2 VpGM-i The set voltage of the set of storage elements i V PGMl amplitude VpGM2 amplitude V PGM3 amplitude V pgm-final final voltage VpgM-INITIAL initial level VR] read voltage / read reference Voltage Vri-i Read voltage Vri-2 Read voltage VR1.i Read voltage 139679.doc -42- 201007744 VR2 Read voltage/read reference voltage Vr2-1 Read voltage V R2-2 Read voltage V R2 -i read voltage VR3 read voltage / Read reference voltage V R4 Read voltage / Read reference voltage ' VR5 Read voltage / Read reference voltage 瘫 VR6 Read voltage / Read reference voltage Vr7 Read voltage / Read reference voltage V read Read turn-on voltage V SOURCE source supply line potential V TH threshold voltage Vvi verify voltage Vvi-1 verify voltage Vvi-2 verify voltage reference Vv l -i verify voltage V V2 verify voltage v V2-1 verify voltage V V2-2 verify voltage. Vv2-i verification voltage Vv3 verification voltage VY4 verification voltage VV5 verification voltage VV6 verification voltage 139679.doc -43- 201007744

Vv7 verify voltage V'ri read level V'r2 read level V'R3 read level V'r4 read level V'R5 read level WLO word line / data word line WL1 word line / data Word Line WL2 Word Line/Data Word Line WL3 Word Line/Data Word Line WL4 Word Line/Data Word Line WL5 Word Line/Data Word Line WL6 Word Line/Data Word Line WL7 Word Line/Data Word Line 139679.doc -44-

Claims (1)

201007744 VII. Patent application scope: 1. A method for a cylinder-based memory device, i includes · $ Measure the memory device to make the non-volatile storage component (10) Pro... etc. Non-piece: One base: The respective thresholds are used to determine a respective set of inks (Vpg(6), Vvi_") of the respective sets of non-volatile storage elements, and the respective sets of Φ-Heil are for non-volatile storage elements. The customized result σ is in the -non-volatile material position (1354) of the blanket voltage; and /, after the storage, the voltage is obtained from the non-volatile storage location, etc. At least one of the respective sets of the respective subsets of the electric dust are used to perform a write operation involving at least one of the respective sets of non-volatile storage elements. 2. The method of claim 1, wherein: the measurement, the determination, and the storing are performed by transporting the memory device to a maximum, the user's occurrence at the manufacturing site, and the obtaining and the performing This write operation occurs after the device is shipped to the end user. 3. The method of claim 1 or 2, wherein: the voltage (VpGM.i, the different sets are determined for different blocks of the non-volatile storage element in the memory device, each of the non-volatile storage elements A block is erasable independently of the other regions of the non-volatile storage element 139679.doc 201007744. 4. The method of claim 1 or 2, wherein: the different sets of voltages are for the memory device Non-volatile storage elements are determined by different groups of non-volatile storage elements: non-volatile storage elements: each-block is independent of other blocks of non-volatile storage elements and is divided by I's per-group - or a plurality of blocks, and - each block in the group uses the same set of voltages. 5 - The method of claim 1 or 2, wherein: the different sets of voltages (4) are non-volatile in the memory device The different groups of word lines of the shackle are smashed, each group contains one or more word lines. 6. The method of claim 1, wherein: the measurement, the determination, the storage,兮Media β —必必卜(10) The acquisition and the execution of the The operation takes place after the memory device is transported from one location to the last. The user is removed. The method of claim 1 or 2, wherein the non-volatile storage element is involved You can execute a plurality of writes of the respective collections (4) by using the respective sets of electricity. 8. If you want to use the method of item 1 or 2, where: The material: the non-volatile material components are Each time the measurement is stored, the test capital is stored: the non-volatile library component stores the user after the write operation. 9. The method of claim 1 or 2, which: 139679.doc 201007744 The voltages include The method of claim 1 or 2, wherein: the voltages comprise a write voltage. 11. The method of claim 1 or 2, wherein: the non-volatile storage location is in the memory In a body device. 12. A storage system comprising: a respective collection of non-volatile storage elements (1205), the non-volatile storage elements being multi-level storage elements; a non-volatile storage location (1354); At least - control circuit (10) 0), the at least one control Circuit: 2 each of the respective sets of volatile storage components: the non-volatile storage element of the mother of the non-volatile storage elements - the respective set of electro-printed coffee, D Each of the individual collections, for each of the non-volatile storage elements, is customized[ θ stored in the non-volatile storage location, each set, and d) After the storing, obtaining at least one of the respective sets of the electric dust, the at least one of the individual collection orders, and the respective sets of the storage elements of the electric house At least - the second step and the non-volatile storage 13. As in the storage system of claim 12, the Yin:,,, and the operation. The at least - control circuit determines that the non-volatile storage of the electrical house of the different blocks of the component is independent of the non-volatile storage: the non-volatile storage component is erased. 15. The storage system of claim 12, wherein: the at least one control circuit determines a different group of blocks of the non-volatile storage element in the storage system. Different sets of voltages, non-volatile storage, each block is erasable independently of other blocks of the non-volatile storage element, each group containing one or more blocks, and a group Each block in the group uses the same set of voltages. The storage system of claim 12, wherein: the at least one control circuit determines a different set of voltages of different groups of word lines of the non-volatile storage element in the storage system, each group comprising one or more words line. 139679.doc -4-