KR101606168B1 - Non-volatile multilevel memory with adaptive setting of reference voltage levels for program, verify and read - Google Patents

Abstract

A non-volatile memory device is accessed using voltages that customize portions of the device, such as blocks and word lines of the device and / or non-volatile storage elements. Accessing may include programming, verifying, or reading. By customizing the voltages V _pgtn , V _V , performance can be optimized, including addressing changes in the threshold voltage caused by program confusion. In one approach, other sets of storage elements in a memory device are programmed with random test data. The threshold voltage distribution is determined for different sets of storage elements. The set of voltages V _pgm , V _V is determined based on the threshold voltage distribution and stored in a non-volatile storage location for later use to access other sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use to access data by the end user.

Description

VOLATILE MULTILEVEL MEMORY WITH ADAPTIVE SETTING OF REFERENCE VOLTAGE LEVELS FOR PROGRAM, VERIFY AND READ WITH HAVING APPLE SETTINGS OF REFERENCE VOLTAGE LEVELS FOR PROGRAM,

The present invention relates to a memory device.

Semiconductor memory is more commonly used in various electronic devices. For example, a non-volatile semiconductor memory may be used in various applications such as cellular telephones, digital cameras, personal digital assistants (PDAs), mobile computing devices, Devices, non-mobile computing devices, and other devices. Electrically Erasable and Programmable Read Only Memory (EEPROM) and flash memory are among the most common non-volatile semiconductor memories. Along with the flash memory, the contents of the EEPROM, the contents of the entire memory array, or portions of the memory can also be erased in one step, unlike the traditional, full-featured EEPROM have.

Conventional EEPROMs and flash memories use floating gates which are located above the channel region in the semiconductor substrate and isolated from the channel region. The floating gate is located between the source and drain regions. A control gate is provided over the floating gate and is insulated from the floating gate. Thus, the threshold voltage (V _TH ) of the formed transistor is controlled by the amount of charge held in the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

Some EEPROM and flash memory devices have floating gates that are used to store two ranges of charges. Thus, the memory element may be programmed / erased between two states, e. G., An erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory device can store one bit of data.

Traditionally, memories storing one bit per cell are called " single level cell "(SLC) memories and memories storing more than one bit per cell are called" multi level cell " . For example, when each MLC memory element can be located in one of four discrete charge bands that correspond to four distinct threshold voltage ranges, 2-bit data can be stored.

Conventionally, the program voltage V _PGM is applied to the control gate while the program operation is applied with successive pulses increasing in magnitude over time. In one possible way, the magnitude of pulses, such as, for example, 0.2 V to 0.4 V, is increased with each successive pulse by a predetermined step size. V _PGM may be applied to the control gates of the flash memory devices. During periods (periods) between program pulses, verify operations are performed. That is, the programming level of each element of the parallel programmed group elements is read between successive programming pulses to determine whether the element has been programmed equal to or greater than the verification level. For arrays of multi-state flash memory devices, the verify step may be performed for each state of the device to determine whether or not the device has reached its data-related verify level. For example, a multi-state memory element capable of storing data in four states may be a request to perform verify operations for three compare points.

Also, when programming a flash memory device, such as a NAND flash memory device, in an EEPROM or NAND string, it is typically necessary to float the electrons in the cell or memory element, V _PGM , which causes the gate to be implanted, is applied to the control gate and the bit line is grounded. When electrons accumulate in the floating gate, the floating gate is charged negatively and the threshold voltage of the memory element rises. As a result, the memory element is considered to be in the programmed state. More information about such programming can be found in U.S. Patent No. 6,859,397 entitled " Source Side Self-Boosting Technique For Non-Volatile Memory "and U. S. Patent Publication No. 2005/0024939 entitled" Detecting Over Programmed Memory " February 3); Both of which are incorporated herein by reference in their entirety.

Also, during a read operation, read reference voltages are applied to the set of storage elements to be read, and a determination is made that the read reference voltage causes the storage element to conduct. The read reference voltages are set to allow the data states of the storage elements to be distinguished.

However, the voltages used during programming, verification, and reading are generally fixed and do not take into account the fact that the threshold voltage distribution can vary. For example, the threshold voltage distribution can be varied due to issues such as program disturb. As a result, the use of fixed programming, verification, and read voltages results in non-optimized performance.

The present invention provides a non-volatile storage system that sets voltage levels, such as write, read, and verify operations, to optimize performance.

In one embodiment, the storage system includes separate sets of non-volatile storage elements that are multi-level storage elements, a non-volatile storage location, and at least one control circuit. Said at least one control circuit comprising: a) measuring respective threshold voltage distributions for respective sets of said non-volatile storage elements; b) Determining a separate set of voltages for a respective set of elements, a separate set of voltages customizing a separate set of the non-volatile storage elements, and c) applying a respective set of voltages to the non-volatile storage location Volatile storage location; and d) after said storing, obtaining at least one of the discrete sets of voltages at said non-volatile storage location, and using at least one of the discrete sets of voltages, And performs a write operation including one.

In another embodiment, the storage system includes separate sets of non-volatile storage elements, non-volatile storage locations, and at least one control circuit, which are multi-level storage elements. The at least one control circuit comprising: a) measuring individual threshold voltage distributions for the respective sets of non-volatile storage elements, the measuring comprising writing data to the individual sets of non-volatile storage elements; ) A separate set of voltages for respective sets of respective non-volatile storage elements, based on the individual threshold voltage distributions, a separate set of voltages customizing a separate set of non-volatile storage elements, and c) At a non-volatile storage location, each set of voltages; and d) after said storing, obtaining separate sets of at least one voltages at the non-volatile storage location, and using at least one To access the separate sets of non-volatile storage elements of the non-volatile storage elements.

Another embodiment includes a set of separate memory devices. Each discrete memory device comprises discrete sets of one or more non-volatile storage elements, discrete non-volatile storage locations, and at least one control circuit. The non-volatile storage elements are multi-level storage elements. Wherein the at least one control circuit is configured to: (a) measure one or more individual threshold voltage distributions for the respective sets of the one or more non-volatile storage elements in the memory device; and (b) (C) storing a separate set of voltages for a respective set of respective non-volatile storage elements in the respective non-volatile storage location; and (d) After said storing, obtaining separate sets of at least one of the voltages at the respective non-volatile storage location and performing a write operation comprising separate sets of the at least one non-volatile storage elements using the at least one respective set of voltages do. In addition, the individual sets of voltages are customized to a respective set of respective non-volatile storage elements, and vary among the individual memory devices.

Another embodiment includes a set of individual memory devices. Each discrete memory device comprises discrete sets of one or more non-volatile storage elements, discrete non-volatile storage locations, and at least one control circuit. The non-volatile storage elements are multi-level storage elements. Wherein the at least one control circuit is configured to: (a) measure one or more individual threshold voltage distributions for the respective sets of the one or more non-volatile storage elements in the memory device, (B) determining a discrete set of voltages for a respective set of respective non-volatile storage elements based on the discrete threshold voltage distribution, and (c) Volatile storage elements; (d) after said storing, acquiring separate sets of at least one voltages at the respective non-volatile storage location; and for each of the at least one voltage The individual sets of one or more non-volatile storage elements The process. In addition, the individual sets of voltages are customized to a respective set of respective non-volatile storage elements, and vary among the individual memory devices.

Corresponding methods, systems and computer- or processor-readable storage devices for performing the methods provided herein are provided.

1 is a top view of a NAND string.
2 is an equivalent circuit diagram of the NAND string of FIG.
3 is a block diagram of an array of NAND flash storage elements.
4 is a cross-sectional view of a NAND string formed on a substrate.
Figure 5 shows a block of storage elements.
6A is a diagram illustrating an initial threshold voltage distribution of a set of non-volatile storage elements having corresponding verify and read voltages.
6B is a diagram illustrating the threshold voltage distribution of a set of non-volatile storage elements experiencing program confusion.
6C is a diagram illustrating the measurement of the threshold voltage distribution of FIG. 6B and the setting of the corresponding read voltages.
7 shows a pulse train of programming voltages and verify voltages.
Figure 8A is a diagram illustrating successive write or program voltages that may be used during programming.
Figure 8B illustrates data including write, verify, and read voltages that customize different sets of non-volatile storage elements.
9A is a diagram illustrating a process for determining voltages for a set of non-volatile storage elements.
FIG. 9B illustrates a process for accessing user data in a set of non-volatile storage elements using predetermined voltages determined by the process of FIG. 9A. FIG.
9C illustrates a process for determining voltages for multiple sets of non-volatile storage elements.
Figure 10 is a diagram illustrating a process for accessing multiple sets of non-volatile storage elements user data using predetermined voltages determined by the process of Figure 9c.
11 is a block diagram of an array of NAND flash storage elements.
12 is a diagram showing the outline of a host controller and a memory device.
Figure 13 is a block diagram of a non-volatile memory system using single row / column decoders and read / write circuits.

The present invention provides a non-volatile storage system that sets voltage levels, such as write, read, and verify operations, to optimize performance.

One example of a memory system suitable for implementing the present invention employs a NAND flash memory architecture that includes arranging multiple transistors in series between two select gates. The series transistors and select gates are quoted in the NAND string. 1 is a top view of a NAND string. Fig. 2 is an equivalent circuit of Fig. The NAND string shown in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 connected in series, which are connected between the first select gate 120 and the second select gate 122 . Select gate 120 couples the NAND string to bit line 126. Select gate 122 couples the NAND string to source line 128. The select gate 120 is controlled by applying appropriate voltages to the control gate 120CG. Select gate 122 is controlled by applying appropriate voltages to control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 has a control gate 102CG and a floating gate 102FG. The transistor 104 has a control gate 104CG and a floating gate 104FG. The transistor 106 has a control gate 106CG and a floating gate 106FG. Control gate 104CG is connected to word line WL1 and control gate 106CG is connected to word line WL2 and control gate 102CG is connected to word line WL2, Is connected to the word line WL0. The control gates may also be provided as part of the word lines. In one embodiment, the transistors 100, 102, 104, and 106 are also respective storage elements, also referred to as memory cells. In other embodiments, the storage elements may comprise multiple transistors or may differ from those shown in Figures 1 and 2. Select gate 120 is connected to a select line SDG (drain select gate). Select gate 122 is connected to select line SGS (source select gate).

3 is a circuit diagram showing three NAND strings. A general architecture for a flash memory system using a NAND architecture may include a plurality of NAND strings. For example, three NAND strings 320, 340, and 360 are shown in a memory array having more NAND strings. Each NAND string includes two select gates and four storage elements. Although four storage elements are shown schematically, modern NAND strings can have, for example, up to 32 or 64 storage elements.

For example, NAND string 320 includes select gates 322 and 327 and storage elements 323 to 326, and NAND string 340 includes select gates 342 and 347 and storage elements < RTI ID = 0.0 > 343 through 346, and NAND string 360 includes select gates 362 and 367 and storage elements 363 through 366. Each NAND string is coupled to a source line by its select gates (e.g., select gates 327, 347 or 367). The selection line SGS is used to control the source side selection gates. The various NAND strings 320,340 and 360 are connected to the individual bit lines 321,341 and 361 by select transistors at select gates 322,342 and 362, These select transistors are controlled by a drain select line SGD. In other embodiments, the select lines need not necessarily be common between the NAND strings; That is, other select lines may be provided to other NAND strings. The word line WL3 is connected to the control gates for the storage elements 323, 343 and 363. Word line WL2 is connected to the control gates for storage elements 324, 344, Word line WLl is connected to control gates for storage elements 325, 345, The word line WL0 is connected to the control gates for the storage elements 326, 346 and 366. As can be seen, each bit line and individual NAND string includes an array or set of storage elements. The word lines WL3, WL2, WL1, WL0 comprise the rows of the array or set. Each word line connects the control gates of each storage element in a row. Alternatively, the control gates may be provided by the word lines themselves. For example, word line WL2 provides the control gates for storage elements 324,344, and 364. In practice, there may be thousands of storage elements in a word line.

Each storage element may store data. For example, when storing one bit of digital data, the range of possible threshold voltages (V _TH ) of the storage element is divided by two ranges assigned to logical data "1" and "0 ". In one embodiment of the NAND type flash memory, V _TH has a negative value and is defined as a logic "1 " after the storage element is erased. After program operation, V _TH has a positive value and is defined as logic "0 ". When V _TH is attempted to read with a negative value, the storage element will be turned on to indicate the stored logic "1 ". When V _TH is positive and a read operation is attempted, the storage element will not turn on to indicate the stored logic "0 ". The storage element may also store multiple levels of information, e.g., multiple bits of digital data. In this case, the range of the V _TH value is divided by the number of levels of the data. For example, if four levels of information are stored, there may be four V _TH ranges assigned with data values "11", "10", "01" and "00" In one embodiment of the NAND type memory, V _TH after erase operation is negative and is defined as "11 ". Positive V _TH values are used as "10 "," 01 ", and "00" states. The specific relationship between the threshold voltage ranges of the device and the data programmed into the storage device depends on the data encoding scheme applied to the storage devices. For example, U.S. Patent No. 6,222,762 and U.S. Patent No. 7,237,074, which are incorporated herein by reference, describe various data encoding schemes for multi-state flash storage devices.

Examples related to NAND type flash memories and their operation are provided in U.S. Patent Nos. 5,386,422, 5,570,315, 6,046,935, 6,456,528, and 6,522,580, each of which is incorporated herein by reference .

When programming the flash storage element, the program voltage is applied to the control gate of the storage element, and the bit line associated with the storage element is grounded. Electrons in the channel are injected into the floating gate. When the electrons are accumulated in the floating gate, the floating gate is charged negatively and the V _TH of the storage element is raised. To apply the program voltage to the control gate of the storage element being programmed, the program voltage is applied to the appropriate word line. As discussed above, one storage element in each NAND string shares the same word line. For example, when programming the storage element 324 of FIG. 3, the program voltage may also be applied to the control gates of the storage elements 344, 364. Unselected storage elements 344 and 364 are referred to as program disturb. Program disruption occurs when an unselected storage element on the same word line, such as a selected storage element, is unintentionally programmed due to application of a relatively high program voltage to the selected word line.

4 is a cross-sectional view of a NAND string formed on a substrate. The figures are simplified and are not drawn to scale. The NAND string 400 includes a source side select gate 406, a drain side select gate 424 and eight storage elements 408, 410, 412, 414, 416, 418, 420, and 422, respectively. A plurality of source / drain regions are provided on either side of each storage element and the selection gates 06, 424, in one example where the source drain region 430 is present. In one approach, the substrate 490 is a triple-well technology comprising a p-well region 492 in an n-well region 494, which in turn is in a p-type substrate region 496. [ . The NAND string and its non-volatile storage elements may be at least partially formed on the p-well region. A source supply line 404 having a potential V _SOURCE is further provided to the bit line 426 having a potential V _BL . Voltages may also be applied to the p-well region 492 through terminal 402 and to n-well region 494 via terminal 403. [

During a read operation, a control gate voltage (V _CG ) is provided on the selected word line, e.g., WL3, associated with the storage element 414 and other storage elements not shown. It also recalls so that the control gate of the storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7 may be individually extended through the control gates of storage elements 408, 410, 412, 414, 416, 418, 420 and 422 can do. A read pass voltage (V _READ ) is applied to the remaining word lines associated with the NAND string 400 in one possible manner. V _SGS and V _SGD are applied to select gates 406 and 424, respectively.

Figure 5 shows a block of storage elements. In one example implementation, the NAND flash EEPROM may be divided into 1024 blocks. The data stored in each block can be erased simultaneously. In one embodiment, the block is the smallest unit of storage elements that are simultaneously erased. In this example, in each block there are 4256 columns corresponding to bit lines (BL0, BL1, ..., BL4255). In one embodiment, which is referred to in the all bit line (ABL) architecture, all bit lines of a block can be selected simultaneously during read and program operations, and are connected to any bit line The storage elements can be programmed simultaneously.

In one example provided, eight storage elements are connected in series to form a NAND string, and there are eight data word lines (WL0 to WL7). The NAND string may also include word lines associated with dummy memory cells. In other embodiments, the NAND strings may have more or fewer numbers than the eight data storage elements. Data memory cells may store user or system data. Dummy memory cells are typically not used to store user or system data.

One terminal of each NAND string is connected to the corresponding bit line through a drain select gate (connected to the select gate drain line SGD) and the other terminal is connected to the select gate source line SGS. And is connected to a common source 505 through a source select gate. Thus, the common source 505 is connected to each NAND string.

In one embodiment, the bit lines, quoted in an odd-even architecture, are divided into even bit lines (BLe) and odd bit lines (BLo). In this case, the storage elements connected to the odd bit lines passing through the common word line are programmed at one time (at the same time), while the storage elements connected to the even bit lines after the common word line are programmed at different times at another time. In each block, the rows are divided into even rows and odd rows.

During one configuration of read and program operations, 4256 storage elements are selected at the same time. The selected storage elements have the same word line, and thus are part of a common physical page. Therefore, 532 bytes of data, which also form a logical page, can be simultaneously read or programmed, and one block of memory can store at least eight logical pages. In this example, the physical page and the logical page are the same, but generally this is not required. For example, a physical page may include multiple logical pages. A logical page is typically the smallest set of storage elements that are used (programmed) simultaneously. For multi-state storage elements, when each storage element stores two bits of data, one block stores sixteen logical pages. Here, each of the two bits is stored in a different page. Other sizes of blocks and pages may also be used.

For ABL or the odd-even architecture, the storage elements can be erased by raising the p-well to an erase voltage (e.g., 20V) and grounding the word lines of the selected block. The source and bit lines are floated. Erasing can be performed in one block at a time or in some flash memory devices in several blocks at a time. Electrons are moved from the floating gates of the storage elements to the p-well region. As a result, V _TH of the storage elements becomes negative.

In the read and verify operations, the select gates (SGD and SGS) are connected to a voltage ranging from 2.5V to 4.5V, and the unselected word lines are connected to the read pass Rises to the voltage V _READ (typically a voltage ranging from 4.5V to 6V). The selected word line is connected to a voltage and the level of the voltage is specified for each read and verify operation, in order to determine if the V _TH of the storage element of interest is higher or lower than this level. For example, in a read operation for a two-level storage element, the selected word line may be grounded. As a result, it is detected whether V _TH is higher than 0 V or not. In a verify operation for a two-level storage element, the selected word line is connected to, for example, 0.8V. As a result, it is verified whether V _TH has reached at least 0.8V or not. The source and p-well are about 0V. The selected bit lines are pre-charged to a level of, for example, 0.7V. If V _TH is higher than the read or verify level at the word line, the potential level of the bit line associated with the storage element of interest remains at a high level due to the non-conductive storage element. On the other hand, if V _TH is lower than the read or verify level, the potential level of the bit line of interest is lower than the read or verify level because the conductive storage element discharges the bit line, ). In one possible implementation, the state of the storage element may be detected thereby by a voltage comparator sense amplifier coupled to the bit line. As with programming, read operations can be performed on a per-page basis.

Many details of the erase, read and verify operations described above are performed by techniques known in the art. Accordingly, many of the details described can be varied by one skilled in the art. Other erase, read, and verify techniques known in the art may also be used.

Figures 6A-6C illustrate how program disruption can change the threshold voltage distribution of a set of non-volatile storage elements and describe a process for handling such issues. 6A is a diagram illustrating an initial threshold voltage distribution of a set of non-volatile storage elements having corresponding verify and read voltages. The threshold voltage of the storage element is the lowest voltage that changes the channel state from a non-conducting state to a conducting state when applied to the control gate of the storage element. This voltage is affected by the amount of negative charge clogged in the floating gate. : The more the charge, the higher the threshold voltage of the cell.

The most common types of Multi Level Cell (MLC) -type devices use four charges in the floating gate, including a zero charge. Here, the state is represented by four voltage levels, and thus the MLC storage element stores two bits of data. In general, N bits per storage element can be represented using 2 ^N voltage levels. New devices are expected to use more than eight voltage levels. Using a greater number of bits per storage element allows the production of flash devices to have a higher data density, thus reducing the overall cost per flash device. It should be noted that multi-level data storage is distinct from multi-bit data storage as used in some NROM devices. Such multi-bit data storage includes charge levels corresponding to 0 or 1, respectively. Multi-level data storage includes a range of charge levels corresponding to 00, 01, 10 and 11 when the MLC storage element stores, for example, two bits of data.

A read operation in an MLC device with four states uses three reference voltage levels, and an MLC device with eight states uses seven reference voltage levels and is generally referred to as a 2 ^N state The device storing N bits per cell uses 2 ^N -1 reference voltage levels for read operations.

In Figure 6A, the graph includes an x-axis representing the threshold voltage and a y-axis representing the number of storage elements. In one example, the MLC device includes eight states from state 0 to state 7, associated with verify voltages V _V1 to V _V7 and associated with read voltages V _R1 to V _R7 . The distribution for each state is relatively narrow because each storage element is programmed with the desired voltage group. Also, the corresponding reference voltages for reading the storage elements, e.g., V _R1 to V _R7, are generally between the voltage groups, just above the previous distribution. For example, V _R1 may be between state 0 and state 1, just above the distribution of state 0, and V _R2 may be between state 1 and state 2, just above the distribution of state 1, and so on.

As mentioned, program confusion can cause serious changes in the threshold voltage distribution. Program disruption occurs when unselected storage elements in the same word line, such as the selected storage element, are unintentionally programmed due to application of a relatively high program voltage to the selected word line. Thus, program confusion tends to raise the threshold voltage of the storage element. Also, the lowest state, e. G., The erase state, tends to rise the highest and can therefore serve as a worst case indicator of the amount of program confusion experienced in the set of storage elements. Measurements performed in flash memory devices show that the amount of program disruption varies considerably between different memory devices, between other blocks in the same device, and even between other word lines in the same block. To maintain program confusion at a similar level for all devices, or to maintain voltage levels at a specific device, block, and / or level, to ensure maximum performance of all memory devices in reliability (e.g., the smallest number of errors) It is desirable to adapt to the actual value of the program confusion in the word line. Techniques are provided to control program confusion and to match program confusion to verify and / or read voltage levels. More generally, the technique customizes the verify and / or read voltage used to access the set of storage elements.

6B is a diagram illustrating the threshold voltage distribution of a set of non-volatile storage elements experiencing program confusion. The read reference voltages V _R1 through V _R7 shown are the same as in FIG. 6A. Here, the threshold voltage distribution for the low states is widened and shifted upward compared to the distribution shown in FIG. 6A due to program confusion. While program disruption has great significance in low voltage states, generally upper states do not suffer from program confusion. It should be noted that distributions for adjacent data states may also overlap in some cases. Here, it can be seen that the same read voltages of FIG. 6A are used in this example to read the data states shown in FIG. 6B, at least for the read voltages V _R1 to V _{R 5} , have. Each of the read voltages V _R1 to VR ₅ is overlapped by a low threshold voltage distribution. In contrast, the read voltages V _R6 to VR ₇ are not overlapped by a low threshold voltage distribution in this example.

Also, the effects of program disruption may be different for different sets of storage elements. For example, the threshold voltage distributions of different sets of storage elements may vary, such as at the device, block and / or word line level. Thus, in the same case, where a fixed set of read voltages is used, this may result in non-optimal results, such as causing errors during read operations. In addition, the relative location of the storage elements in the block, such as those based on the temperature changes and the number of programming / erase cycles, and the proximity of the storage element in the source or drain of the NAND string, You can give.

6C is a diagram illustrating the measurement of the threshold voltage distribution of FIG. 6B and the setting of the corresponding read voltages.

The process of measuring the actual threshold distribution involves reading the memory device in separate read operations. Where the number of read operations is based on the desired resolution of the distribution measurement. For example, if the storage device uses eight states representing three bits per storage element, and a resolution of ten points per state is desired, then read operations may be applied to each of the 79 voltage threshold levels . In Fig. 6C, each dot represents a read point, and the solid line is the same as in Fig. 6B. A histogram may be provided in which the height of each bin represents the number of storage elements whose threshold voltage is in the range specified by the bin. The most suitable read level for a given set of storage elements can be determined, for example, with minimum values between adjacent states. When there is a range of minimum values, the most appropriate read level between two data states can be directly over the lowest distribution of the two states. Here, the read level (V 'to V _{R1' R5)} is on the other hand is in proportion to the levels of Figure 6b shifts to the optimum level, V _{R6 R7} and V are not changed. If the read levels of FIG. 6B are used, substantial read errors will result. In general, it is also desirable to keep the read level close to the previous level to allow a maximum data retention shift.

In general, acquiring the "threshold voltage distribution" of a set of storage elements involves dividing the range of threshold voltages of the storage elements into multiple sub-ranges, Lt; / RTI > It is possible to count occurrences of all or only a portion of the storage elements in the set of storage elements. It is possible to count occurrences of only a subset of the sub-ranges, for example, one or more sub-ranges, and to estimate the result for the other sub-ranges.

In one approach, an on-line evaluation of the program confusion for the current device, block and / or word line, and adjustment of the voltage level settings for the evaluated program confusion are provided. The actual program confusion of each fabricated memory device may be measured, for example, on a block-by-block basis, and the match may be determined by voltage level settings (read and verify voltages ) And the program confusion measured for such a block. Such "matched-per-block" voltage level settings may be used in subsequent program and read operations. To deal with program confusion, it must modify the verify voltages, the read voltages, or both.

The program confusion value can be defined as the width of the threshold voltage distribution in the erased state in the page for all existing data states. That is, the data programmed into the page includes an indication of all possible data states. The threshold voltage distribution may be considered to any percentage of the cells, depending on the ECC correction capabilities. The program confusion value can be obtained, for example, by randomly programming the data in the memory device and then reading the threshold voltage distribution of all data states and considering the width of the erased state. Default voltage level settings can be used for such programming.

Once the width of the erase level threshold voltage distribution is obtained, the voltage level settings for the remaining data states can be determined. There can be two ways to calculate the voltage levels. That is, there may be a "fixed program disturb" scheme and a "fixed voltage window" scheme. The two schemes have the same principle.

First, we identify the voltage window available for all data states except the erased state. When there are eight data states, the available voltage window is the highest (most right) voltage of the erased state (e.g., the program disturbance value) and the highest possible data state of V _V7 possible data state). Further, the voltage window can be defined to start at the lowest (leftmost) voltage of the erased state.

Second, we proportionally divide this window between data states into a relative data hold shift of these states. The data retention shift and the given retention time of the storage elements for any conditions of the block (e.g., write / erase cycling) depend on the storage element threshold voltage - the higher the threshold voltage, It gets bigger. The positive properties of this dependency are technical features and can be obtained, for example, by testing and / or theoretical calculations. The division of the available voltage window between data states may be subject to these properties.

Third, we determine the read and verify levels for each state based on the above. The difference between the two mentioned schemes is as follows. In a fixed program confusion scheme, the program confusion value is adjusted to a predetermined fixed value by modifying the voltage window, e.g., by modifying the verify voltage level of the highest data state. The program confusion phenomenon is caused by the stress caused to the storage elements in the erased state by the high programming voltage applied to the word line during programming. Also, when the programming voltage applied to the word line is high, such as when the selected storage element is programmed to the highest data state, the program confusion is high. This means that the program confusion can be controlled by changing the verification level of the highest data state. The iterative procedure can be implemented to obtain the desired program confusion value. For example, if the program confusion is too high, we can reduce the verify level of the highest data state. The program confusion is then determined again, for example, by determining the threshold voltage distribution to determine that it is close to the desired level. If the program confusion is still too high, we can reduce the verification level of the highest data state again.

It should be noted that the verification levels of all states may be correlated by known voltage windows with known functions that are linear or non-linear. For example, due to the higher data retention loss of the highest states, the verification levels are typically set to provide space for states that are lower than space for relatively higher states. Thus, once the full voltage window becomes known, we can calculate the read or verify voltages.

In the fixed voltage window scheme, the verify level of the highest data state has the same program confusion as measured, which can vary from word line to word line, from block to block, and / or from device to device, Respectively. The changeable program confusion value can result in a changeable state width for the remaining data states.

The procedure for adjusting the voltage level settings may be performed at the manufacturing stage of the memory device, or may be performed after the memory device has been delivered to the end user, in the illustrative ways. Also, if desired, adjustments can be repeated at different times. Alternatively, the adjustment may be performed only once during one lifetime of the memory device. Indeed, program confusion is reduced each time the memory device experiences additional program-erase cycles. As a result, subsequent adjustments may not be necessary.

For example, if a device is delivered to an end user, the adjustment may be triggered by other events, such as temperature changes, passing of multiple programming cycles, passing of arbitrary time since the data was last written, and so on. Appropriate tracking components and / or processes are provided for this purpose. In one approach, the adjusted voltage values may be stored in the memory device for each device block using a reliable programming method similar to the storage of flash internal parameters in a ROM fuse. When a block is programmed or addressed to be read, such block-specific values can be retrieved and used for normal operation of the memory device.

Thus, in one approach, customized sets of read and / or verify voltages can be determined for a set of storage elements in a memory device, such as in a manufacturing process. The set of voltages may be stored in a non-volatile storage location in the memory device and then accessed each time a read or programming operation is performed. Additional details are shown in Figures 9a-9c and 10.

7 shows a pulse train 700 of programming voltages and verify voltages. The program voltages increase in size in a step wise manner. For example, the program voltages may be programmed starting with program pulses 705 having a magnitude of V _PGM1 followed by program pulses 710 having a magnitude of V _PGM2 , such as program pulses 715 having a magnitude of V _PGM3 , . After each program pulse, successive verify voltages V _V1 through V _V7 are applied, as indicated by waveforms 720, 725 and 730. These verify voltages can be customized to a given set of storage elements as discussed in connection with Figures 6A-6C.

The write voltages may also be customized to other sets of non-volatile storage elements. Figure 8A is a diagram illustrating successive write or program voltages that may be used during programming. Intermediate verify voltages are omitted for clarity. As noted earlier, all storage elements to their the corresponding or programmed with the state or the last voltage V _{PGM -} until it reaches the last of the two is _FINAL dog, typically writing voltages in the initial level, V _{PGM -} Start at _INITIAL and increase in size according to the step size. In one approach, one or more write voltage parameters may be customized to a particular set of storage elements. For example, if the threshold voltage distribution of a set of storage elements having low states indicates that the threshold voltage for such states is higher than expected or the width of the threshold distribution is greater than expected, It can be concluded that it is stronger than that. In these cases, we can reduce the write voltages by reducing V _{PGM - INITIAL} and / or step size. In some cases, the pulses at the maximum allowable V _{PGM - FINAL} or lowest levels may be repeated. Similar adjustments can be made if the programming effect is weaker than the average for a set of storage elements, for example when V _PGM-FINAL is reached before all storage elements are programmed to their corresponding states. Such adjustments may include increasing V _{PGM - FINAL} , step size and / or maximum allowable V _{PGM - FINAL} . It should be noted that the step size directly affects the width of the distribution states. As a result, the step size may decrease if the width of each distribution is wider than the average, and the step size may increase, for example, to reach programming faster if the width of each distribution is narrower than the average have.

8B is a diagram illustrating data including write, verify, and read voltages that customize different sets of non-volatile storage elements. As noted, write, verify, and / or read voltages may be customized with different sets of storage elements. Optimal voltages for each set of storage elements may be determined and stored for subsequent use. For example, in a memory device, voltages for a particular memory device, a block word line, and / or a group word line may be stored in a non-volatile storage location of the memory device. Here, the set 1, the voltage for writing the first set of storage elements are represented as V _{PGM -1,} verify voltages are denoted by _{V1 -1} V, _-2 V _V2, and so on, read voltages V _{R1 -1} , V _{R2 -2} , and so on. In addition, V _{PGM -1} may be represented by one or more of V _{PGM - INITIAL} , step size and V _{PGM - FINAL} for set 1. Each of these three variables can be tailored to different sets of storage elements. Similarly, write voltages for the second set of storage elements, which are set 2, are represented by V _{PGM -2} (e.g., for set 2, one or more V _{PGM - INITIAL} , step size, and V _{PGM - FINAL} , The verify voltages for the second set of storage elements are labeled V _{V2 -1} , V _{V2 -2} , etc., and the read voltages are labeled V _{R1 -2} , V _{R2 -2} , and so on. In general, the set of i, the programming voltage for the i-th set of storage elements being represented by V _{PGM -i,} etc. (for example, more than one set for the i V _{PGM - INITIAL,} the step size, and, V _{PGM - FINAL} ), while the verify voltages for the i-th set of storage elements are labeled V _{V1 -i} , V _{V2 -i} , etc., and the read voltages are labeled V _{R1 -i} , V _{R2 -i} , .

Figure 9A illustrates a process for determining voltages for a set of non-volatile storage elements. Step 900 includes initiating a process for obtaining a set of voltages (e.g., read, verify and / or write voltages) for a set of non-volatile storage elements. The set may include storage elements associated with one or more particular word lines in a block having multiple word lines, storage elements associated with a particular block in a memory device having multiple blocks, or storage elements associated with the entire particular memory device can do. Step 902 includes, in one manner, programming a set of non-volatile storage elements having random test data. The test data should include all data states. For example, such test data may be available when the memory device experiences testing at a manufacturing site prior to delivery. If no test data is available after the memory device is delivered, then the existing user data may be programmed instead. User data can also be scrambled. As a result, all data states are displayed relatively evenly. For example, user data residing at one location of a memory device, such as one given block, may be copied to another location, such as another block containing a particular set of storage locations for which the read / verify voltages are to be determined .

After step 902, either one of the two paths can be performed. In the first path, step 904 includes determining the threshold voltage distribution of the set of storage elements by performing read operations on other increasing voltage threshold levels, for example, as shown in Figure 6C . Generally, this may include determining the threshold voltage distribution of all data states. Step 906 includes determining a set of voltages based on the threshold voltage distribution. For example, the set of read voltages may be determined based on the minimum value of the threshold voltage distribution, as shown in Figure 6C. The set of verify voltages may be determined based on the voltage window. For example, a voltage window can be determined from a threshold voltage distribution, and verify voltages can be determined from a function that provides a desired relative space between verify voltages within the constraints of the overall voltage window. Step 912 includes storing data identifying a set of voltages in a non-volatile storage location. For example, data of a set of voltages may be stored in storage elements in a memory device from which a threshold voltage distribution is obtained. These may be, for example, storage elements that do not store user data. In one approach, the data is stored in storage elements of the block from which the threshold voltage distribution is obtained. In another approach, the data is stored in the storage elements of the word line from which the threshold voltage distribution is obtained. Alternatively, a non-volatile storage location used by the controller of the memory device may be used. Other positions may also be used.

In the second path, step 908 includes determining a threshold voltage distribution of the set of storage elements that is less than all data states. For example, the threshold voltage distribution of the erased state can be determined. As mentioned, the upper edge of the threshold voltage distribution in the erased state can be used to measure the level of program disruption, since such conditions are most susceptible to program disturbances. The optimal read level for state 1 may be determined based on this upper edge and the optimal read levels for the remaining states may be determined based on a known relationship between read levels for states. That is, the formula can be used to relate the optimal read level for state i (i > 2) to the optimal read level for state one. It may also be possible to determine the threshold voltage distribution of a set of storage elements for multiple data states, such as for states 1 and 2, and it may be possible to associate them with other states. For example, the formula can be used to relate the optimal read level for state i (i > 3) to the optimal read levels for states 1 and 2. Such formulas can be obtained from theoretical relationships and / or empirical test results. Thus, step 910 includes determining a set of voltages based on a lower threshold voltage distribution than all data states.

Also, the data of the set of voltages may be displayed in any manner. Figure 8b discussed above provides one possible example. Also, the identifier of the storage elements may be used in some cases, as shown by (e.g., set 1, 2, ..., i). For example, the controller may have a storage location for storing a different set of voltages for each block in the corresponding device, or for groups of blocks in the device. In this case, the identifier of the set of storage elements may be associated with each set of voltages. In other cases, the location of the set of voltages serves as an identifier for the storage elements that apply the voltages. For example, a set of voltages stored in a block may be applied to the block, or a set of voltages stored in a word line may be applied to the word line. In another example, the sets of voltages of different blocks are stored in one block, in which case the identifier may be needed to relate the block to its corresponding set of voltages. In some cases, sets of voltages may be stored so that their relative positions at the storage location identify the storage elements to which to apply the voltages. For example, the first location in the storage location may correspond to the first block, while the second location in the storage location may correspond to the second block, and so on. Alternatively, the storage location may be within a block. Wherein the first location in the storage location may correspond to a set of word lines in a first word line or block while the second location in the storage location may correspond to a set of word lines in a second word line or block, And so on.

In addition, the absolute values of the voltages may be stored, or offset values may be stored to indicate offsets in a reference set of values or a single reference value. Alternatively, data used to directly control the voltage circuit may be used, such as a binary code word to be input to the digital-to-analog converter. In any case, such data is understood to represent a set of voltages.

The technique advantageously provided here does not require the use of reference storage elements. Such reference storage elements are additional storage elements that store non-user data to track threshold voltage changes experienced by the device. Reference storage elements consume additional space in the memory device beyond the range of storage elements that store user data. Reference storage elements typically read "on the fly ". As a result, adjustments occur each time a page of data is read. In this case, there is no storage of a set of voltages in a non-volatile storage location for later use. Also, reference storage elements generally do not include measuring threshold voltage distributions. For reference storage elements, the measurements proceed in one set of storage elements, for example reference storage elements, for use in determining the second voltages, which is a non-overlapping set of storage elements. In contrast, in the case of the technique provided here, measurements are made and voltages determined for the same set of storage elements subsequently accessed using voltages.

FIG. 9B illustrates a process for accessing user data in a set of non-volatile storage elements using predetermined voltages determined by the process of FIG. 9A. FIG. In one approach, access occurs after the memory device is delivered to the user. That is, access occurs after the device is manufactured and installed in the host system used by the user. Step 920 includes initiating an operation (e.g., program, verify, or read) for the set of non-volatile storage elements. Step 922 includes acquiring a set of voltages at a non-volatile storage location. Step 924 includes accessing the user data for a set of non-volatile storage elements using a set of voltages. Such accessing may include programming / verifying or reading.

9C illustrates a process for determining voltages for multiple sets of non-volatile storage elements. As mentioned, the voltages can be customized into different sets of storage elements, including within a single memory device and between different memory devices. Many steps are similar to the steps in FIG. 9A. Step 930 includes selecting one or more sets of non-volatile storage elements in the memory device. Step 932 includes starting a process for obtaining a corresponding set of voltages. Step 934 includes programming a set of non-volatile storage elements having random test data. Step 936 includes determining a threshold voltage distribution for the one or more sets of non-volatile storage elements. Step 938 includes determining a set of voltages based on the threshold voltage distribution. Step 940 includes storing a corresponding set of voltages for the set of one or more non-volatile storage elements currently selected in the non-volatile storage location. In decision step 942, if there is a next set of storage elements in the memory device, the process continues with step 930, where the next set of one or more non-volatile storage elements is selected. If there is no next set of storage elements in the memory device, the process continues with decision step 946. [ If there are next memory devices for which voltages are to be determined, such as in a manufacturing environment where multiple memory devices are analyzed, the process continues at step 930. [ If at step 946 the next memory device is not present, then the process ends at step 948.

For example, each path through a process may include obtaining a set of voltages, a set of word lines, a block, or a set of blocks of storage elements. For example, a given set of voltages may be applied to a set of storage elements or word lines of an individual word line, or may be applied to a separate block or set of blocks. It should also be noted that when multiple sets of voltages are determined, e.g., writing, verifying and / or reading, each set may be applied to another group of storage elements. For example, one set of verify voltages may be obtained for the entire memory device, while the other sets of read voltages are obtained for the other blocks in the memory device. The multipaths through the process can be performed continuously or simultaneously.

Figure 10 is a diagram illustrating a process for accessing multiple sets of non-volatile storage elements user data using predetermined voltages determined by the process of Figure 9c. Step 1000 includes selecting one or more sets of non-volatile storage elements in the memory device. Steps 1002 to 1006 individually correspond to steps 920 to 940 of FIG. 9B. Step 1002 includes initiating an operation (e.g., program, verify, or read) for one or more sets of non-volatile storage elements. Step 1004 includes obtaining a corresponding set of voltages at a non-volatile storage location. Step 1006 includes accessing the user data for one or more sets of non-volatile storage elements using a corresponding set of voltages. Such accessing may include programming / verifying or reading. At decision step 1008, if there is a next set of storage elements for access in the memory device, the processor continues with step 1000, where the next set of one or more non-volatile storage elements is selected in the memory device. In decision step 1008, if there is no next set of storage elements for access in the memory device, then the process ends at step 1010. [

As before, each path through the process may include obtaining a set of voltages, a set of wordlines, a block, or a set of blocks, of the storage elements, and the corresponding storage elements have. A given set of voltages may be applied to a set of storage elements or word lines of an individual word line or may be applied to a separate block or set of blocks. The multipaths through the process can be performed continuously or simultaneously.

Figure 11 is a block diagram of an array of NAND flash storage elements, such as that shown in Figures 1 and 2. Along each column, the bit line is connected to the drain terminal of the drain select gate for the associated NAND string. For example, bit line 1106 is coupled to the drain terminal 1126 of the drain select gate for NAND string 1150. Along a row of NAND strings, the source line 1104 may connect all the source terminals 1128 of the source select gates of the NAND strings. Examples of NAND architecture arrays and their operation as part of a memory system can be found in U.S. Patent Nos. 5,570,315, 5,774,397, and 6,046,935.

The array of storage elements divides the storage elements into a large number of blocks. As is common for flash EEPROM systems, a block is a unit of erase. That is, each block includes a minimum number of storage elements that are erased together. Each block is generally divided into a plurality of pages. A page is a unit of programming. Pages of one or more data are typically stored in one row of storage elements. A page may store one or more sectors.

Sectors include user data and overhead data. Generally, the overhead data includes an error correction code (CEE) calculated from the user data of the sector. When data is programmed in the array, a portion of the controller (described below) calculates the ECC and also verifies the ECC when the data is read from the array. Alternatively, the ECCs and / or other overhead data are stored in different pages or even in different blocks than the user data they are associated with.

The sector of the user data corresponds to the size of the sector in the magnetic disk drives, and is generally 512 bytes. The overhead data is typically an additional 16 to 20 bytes. A large number of pages form a block between, for example, 32, 64, 128, or more pages in eight pages. In some embodiments, a row of NAND strings includes a block.

12 is a schematic diagram of a host controller and a memory device in a storage system; Also, the memory device may be considered to be a storage system alone. The storage elements 1205 may be provided in a memory device 1200 having its own controller 1210 to perform operations such as programming / verifying and reading. A memory device may be a removable memory card inserted into a host device such as, for example, a laptop computer, a digital camera, a personal digital assistant (PDA), a digital audio player or a mobile phone, card or a USB flash drive. The host device may have a controller 1225 for interacting with the memory device, such as for reading or writing user data. For example, when reading data, the host controller may send instructions to a memory device that indicates the address of the user data to be searched. The memory device controller converts such instructions into memory device controllers, which can be interpreted and executed by the control circuitry in the memory device. The controller 1210 also includes a nonvolatile storage location 1215 for storing sets of voltages and a buffer memory 1220 for temporarily storing user data written to or read from the memory array, . ≪ / RTI > A host controller can be considered to be an entity external to (outside) a memory device or external to a memory device. The memory device may include, for example, one or more memory dies, discussed in conjunction with FIG. 13, and the host controller may be outside one or more memory dies.

The memory device responds to the read command by reading the data in the storage elements and making it available on the host controller. In one possible way, the memory device stores the read data in the buffer 1220 and notifies the host controller when the data can be read. The host controller responds by reading the data from the buffer and sends another instruction to the memory device to read the data at the other address. For example, data can be read page by page. The host controller may process the read data to determine a threshold voltage distribution of the storage elements of the memory device. In another approach, the control circuitry of the memory device determines the threshold voltage distribution. Further, detailed embodiments of the memory device are provided below.

A typical memory system includes an integrated circuit chip and one or more integrated circuit chips. Here, the integrated circuit chip includes a controller 1210. Wherein the one or more integrated circuit chips each include control, input / output, and state machine circuits associated with the memory array. The memory device may be embedded as part of the host system or may be included in a memory card that may be removably inserted into a mating socket of the host system. Such a card may include an entire memory device, or a controller and memory array with associated peripheral circuits may be provided to individual cards.

Figure 13 is a block diagram of a non-volatile memory system using single row / column decoders and read / write circuits. The diagram illustrates a memory device 1396 having read / write circuits for reading and programming pages of storage elements in parallel in accordance with an embodiment of the present invention. The memory device 1396 may include one or more memory dies 1398. The memory die 1398 includes a two-dimensional array of storage elements 1400, a control circuit 1310, and read / write circuits 1365. In some embodiments, the array of storage elements may be three dimensional (3D). The memory array 1400 can be addressed by word lines via a row decoder 1330 and addressed by bit lines via a column decoder 1360. Read / write circuits 1365 include multiple sense blocks 1300, which allow pages of storage elements to be read or programmed in parallel. In general, the controller 1350 is included in the same memory device 1396 (e.g., a removable storage card), such as one or more memory dies 1398. The instructions and data are transferred between the host and the controller 1350 via lines 1320 and between the controller and the one or more memory die 1398 via lines 1321. [

The control circuit 1310 cooperates with the read / write circuits 1365 to perform memory operations in the memory array 1100. Control circuitry 1310 includes a state machine 1312, an on-chip address decoder 1314, and a power control module 1316. State machine 1312 provides chip-level control of memory operations. The on-chip address decoder 1314 provides the address interface between the host or memory controller used therein to the hardware address used by the decoders 1330 and 1360. A power control module 1316 controls the power and voltages supplied to the word lines and bit lines during memory operation. For example, the power control module 1316 may be used during read operations to provide a control gate read voltage to the selected word line and to set the read pass voltages to an unselected word line Lt; / RTI > The power control module 1316 may also provide a voltage sweep to the selected word line. The power control module 1316 may, for example, include one or more digital-to-analog converters for this purpose. In this case, the control circuit can generate a voltage sweep outside the memory die 1398, for example, without the need for an external test device. This is advantageous because, when the end user owns the memory device, it allows to generate a voltage sweep at any time, including after the manufacture of the memory device. In addition, the memory device 1396 may include circuitry for determining the threshold voltage distribution of the storage elements. As a result, this process can be performed internally within the memory die 1398, without requiring an external test device or an external host. This is advantageous because it allows to determine the threshold voltage distribution at any time without an external device.

In some embodiments, some of the components of FIG. 13 may be combined. In various designs, one or more of the components (alone or in combination), other than the storage element array 1100, may be considered as management or control circuitry. For example, one or more management or control circuits may include control circuitry 1310, state machine 1312, decoders 1314/1360, power control 1316, sense blocks 1300, read / write circuits 1365, a controller 1350, a host controller 1399, and so on, or any combination thereof.

Data stored in the memory array is read out by a column decoder 1360 and output to external I / O lines through a data I / O line and a data input / output buffer 1352. Program data to be stored in the memory array is input to the data input / output buffer 1352 through external I / O lines. The command data for controlling the memory device is input to the controller 1350. [ The instruction data informs the flash memory which operation is required. The input command is sent to the control circuit 1310. State machine 1312 may output the state of the memory device, such as READY / BUSY or PASS / FAIL. When the memory device is busy, it can not receive new read or write commands.

Similar to the storage location 1215 of FIG. 12, a data storage location 1354 may also be provided in connection with the controller 1350.

In another possible configuration, the non-volatile storage system may utilize dual row / column decoders and read / write circuits. In this case, access to the memory array by various peripheral circuits is implemented in a symmetric fashion on the opposite side of the array. As a result, the density of access lines and circuitry on each side is reduced by half.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It should also be understood that the above detailed description is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above description. The described embodiments are chosen to best explain the principles of the invention, and practical applications of the invention by the described embodiments may be implemented in various embodiments in the art, And various modifications of the present invention. But are considered within the scope of the invention as defined by the claims appended hereto.

Claims (20)

A method of configuring a memory device,
Measuring individual threshold voltage distributions for individual sets of non-volatile storage elements (1205) in the memory device; and the non-volatile storage elements are multi-level storage elements;
Determining a respective set of voltages (V _PGM-i , V _{V1 -i} , V _R1-i ) for each discrete set of non-volatile storage elements based on the discrete threshold voltage distribution; Is customized for a respective set of non-volatile storage elements;
Storing data representing a respective set of voltages in a non-volatile storage location (1354);
The method of claim 1, further comprising: after the storing, obtaining data of at least one of the discrete sets of voltages from the non-volatile storage location; and using data of at least one of the discrete sets of voltages, Performing a write operation associated with at least one set of discrete sets of volatile storage elements; And
Determining a programming effect for each set of non-volatile storage elements,
The voltages comprising write voltages comprising at least one of an initial program voltage and a step size,
Wherein a write voltage is reduced for a set of non-volatile storage elements in which the programming effect predominates over the average. The method according to claim 1,
Wherein the measuring step measures an amount of program disturb of each set,
Wherein the determining step is performed based on an amount of the program disruption. 3. The method of claim 2,
Wherein the amount of program disruption is based on a width of the threshold voltage distribution in an erased state on a page in which all data states are present. The method according to claim 1,
The measuring step, the determining step, and the storing step may be performed at a manufacturing facility, before the memory device is delivered to an end user,
Wherein the obtaining and performing the write operation are performed after the device is delivered to the end user. 5. The method according to any one of claims 1 to 4,
Different sets of voltages (V _PGM-i , V _V1-i , V _R1-i ) are determined for different blocks of non-volatile storage elements in the memory device,
Wherein each block of non-volatile storage elements is erasable independently of other blocks of non-volatile storage elements. 5. The method according to any one of claims 1 to 4,
Wherein different sets of voltages are determined for different groups of word lines of non-volatile storage elements in the memory device,
Wherein each group comprises one or more word lines. 5. The method according to any one of claims 1 to 4,
The sets of voltages comprising at least one of a read voltage and a verify voltage,
Wherein the sets of voltages are determined using a fixed program disturb approach in which the verify voltage level of the highest data state is modified. 8. The method of claim 7,
Wherein the verify voltage level of the highest data state is decreased when the amount of program disruption is greater than a desired program disturb value. 5. The method according to any one of claims 1 to 4,
The sets of voltages comprising at least one of a read voltage and a verify voltage,
Wherein the sets of voltages are determined using a fixed voltage window approach in which the verify voltage level of the highest data state is fixed. 5. The method according to any one of claims 1 to 4,
Wherein the measuring step measures a threshold voltage distribution comprising a plurality of data states for each set. As a storage system,
Separate sets of non-volatile storage elements 1205 and the non-volatile storage elements are multi-level storage elements;
A non-volatile storage location 1354; And
At least one control circuit (1350)
Said at least one control circuit comprising:
a) measuring individual threshold voltage distributions for respective sets of non-volatile storage elements;
b) determining a respective set of voltages (V _PGM-i , V _{V1 -i} , V _R1-i ) for each individual set of non-volatile storage elements based on said individual threshold voltage distribution, Are customized for a respective set of non-volatile storage elements,
c) storing, at the non-volatile storage location, data representative of each set of voltages,
d) after storing the data, obtaining data of at least one of the discrete sets of voltages from the non-volatile storage location, and using data of at least one of the discrete sets of voltages, Performing a write operation associated with at least one of the discrete sets of non-volatile storage elements,
The sets of voltages comprising at least one of a read voltage and a verify voltage,
Wherein the sets of voltages are determined using a fixed voltage window scheme in which the verify voltage level of the highest data state is fixed. 12. The method of claim 11,
Wherein the at least one control circuit determines a programming effect for each set of non-volatile storage elements,
The voltages comprising write voltages comprising at least one of an initial program voltage and a step size,
Characterized in that the write voltage is reduced for a set of non-volatile storage elements whose programming effects predominate over the average. 12. The method of claim 11,
Wherein the at least one control circuit measures the amount of program disruption in each set,
Wherein determining a separate set of voltages is performed based on an amount of the program disruption. 14. The method of claim 13,
Wherein the amount of program confusion is based on a width of the threshold voltage distribution in an erased state on a page in which all data states are present. 15. The method according to any one of claims 11 to 14,
Volatile storage elements in the storage system and different groups of blocks of non-volatile storage elements in the storage system, and a plurality of non-volatile storage elements in the storage system, Gt; of the at least one of the different groups of < / RTI > 15. The method according to any one of claims 11 to 14,
Wherein said measuring measures a threshold voltage distribution comprising a plurality of data states for each set. As a storage system,
Separate sets of non-volatile storage elements 1205 and the non-volatile storage elements are multi-level storage elements;
A non-volatile storage location 1354; And
At least one control circuit (1350)
Said at least one control circuit comprising:
a) measuring individual threshold voltage distributions for respective sets of non-volatile storage elements;
b) determining a respective set of voltages (V _PGM-i , V _{V1 -i} , V _R1-i ) for each individual set of non-volatile storage elements based on said individual threshold voltage distribution, Are customized for a respective set of non-volatile storage elements,
c) storing, at the non-volatile storage location, data representative of each set of voltages,
d) after storing the data, obtaining data of at least one of the discrete sets of voltages from the non-volatile storage location, and using data of at least one of the discrete sets of voltages, Performing a write operation associated with at least one of the discrete sets of non-volatile storage elements,
The sets of voltages comprising at least one of a read voltage and a verify voltage,
Wherein the sets of voltages are determined using a fixed program confusion scheme in which the verify voltage level of the highest data state is modified. 18. The method of claim 17,
Wherein the verify voltage level of the highest data state is reduced when the amount of program disruption is greater than a desired program confusion value. delete delete

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