JP2011519110A - Non-volatile multi-level memory with adaptive setting of reference voltage for programming, verification and reading - Google Patents

Abstract

The non-volatile storage device is accessed using a voltage customized for the device and / or part of the device (such as a block of non-volatile storage elements or a word line). This access process may include a programming process, a verification process, or a read process. By customizing the voltages (V _pgtn-i , _V V), performance can be optimized including accommodating for threshold voltage changes caused by program disturb. In one approach, different sets of storage elements in the storage device are programmed with random test data. A threshold voltage distribution is identified for different sets of storage elements. A set of voltages (V _PGM , V _V ) is identified based on the threshold voltage distribution and stored in a non-volatile storage location for later use in accessing different sets of storage elements. The set of voltages can be specified at the time of manufacture for later use by the end user to access the data.

Description

  The present invention relates to a memory device.

  Semiconductor memories are becoming more commonly used in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal digital assistants, mobile computers, non-mobile computers, and other devices. Electrically erasable / writable read only memory (EEPROM) and flash memory are the most widespread nonvolatile semiconductor memories. In flash memory, as with some types of EEPROM, the contents of the entire memory array or a portion of the memory can be erased in one step, unlike a normal full-featured EEPROM.

Ordinary EEPROM and flash memory employ a floating gate that is disposed on a channel region in a semiconductor substrate and is insulated from the channel region. The floating gate is disposed between the source region and the drain region. A control gate that is insulated from the floating gate is provided on the floating gate. The threshold voltage (V _TH ) of the formed transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate to turn on the transistor and conduct between the source and drain is controlled by the charge level on the floating gate.

  Certain EEPROM and flash memory devices have a floating gate that is used to store two ranges of charge, and therefore the storage element is in two states: an erased state and a programmed state. , The program / erase is performed. Such flash memory devices are sometimes referred to as binary flash memory devices because each storage element can store 1-bit data.

  In general, a memory that stores one bit per cell is called a single level cell (SLC) memory, and a memory that stores two or more bits per cell is called a multi-level cell (MLC) memory. For example, each MLC memory element can store 2-bit data by taking one of four different charge bands corresponding to four different threshold voltage ranges.

Normally, the program voltage _VPGM applied to the control gate in the program operation is applied as a series of pulses that increase in magnitude over time. As one approach, the pulse magnitude is increased by a predetermined step size of, for example, 0.2-0.4V for each successive pulse. V _PGM is applied to the control gate of the flash memory device. A verification operation is performed during the period between program pulses. That is, the program level of each element in the element group programmed in parallel is read between successive pulses and whether the element is equal to or greater than the verification level programmed. Determined. In an array of multi-state flash memory elements, verification processing is performed for each element state to determine whether the element has reached a verification level corresponding to data. For example, a multi-state storage element that can store data in any of four states requires verification operations at three comparison points.

Further, when programming a NAND string of a flash memory device, such as an EEPROM or NAND flash memory device, typically a V _PGM is applied to the control gate and the bit line is grounded, thereby allowing the cell or Electrons are injected from the channel of the memory element (ie, the storage element) into the floating gate. When electrons are accumulated in the floating gate, the floating gate is charged to a negative value, the threshold voltage of the memory element is increased, and the memory element is programmed. Further information on such programming can be found in US Pat. No. 6,859,397 entitled “Source Side Self Boosting Technique For Non-Volatile Memory” and February 3, 2005 entitled “Detecting Over Programmed Memory”. This is disclosed in US Patent Publication No. 2005/0024939 published in Japan. The contents of both documents are incorporated herein by reference in their entirety.

  Further, during the read operation, a plurality of read reference voltages are applied to the set of read memory elements, and a determination is made as to which read reference voltage causes the memory elements to conduct. The plurality of read reference voltages are set so that the data states of the storage elements can be distinguished.

  However, the voltages used for programming, verification, and reading are usually fixed, and no consideration is given to the possibility that the threshold voltage distribution may vary. For example, the threshold voltage distribution may vary due to problems such as program disturb. This can result in inadequate performance due to fixed programming, verification, and use of read voltages.

  The present invention provides a non-volatile storage system that sets voltage levels for write, read, verify operations, etc. to optimize performance.

  In one embodiment, the storage system comprises each set of non-volatile storage elements that are multi-level storage elements, a non-volatile storage location, and at least one control circuit. At least one control circuit (a) measures each threshold voltage distribution for each set of non-volatile memory elements, and (b) non-volatiles for each set of non-volatile memory elements based on each threshold voltage distribution. Identify each set of voltages customized for each set of storage elements, (c) store each set of voltages in a non-volatile storage location, and (d) perform non-volatile storage after performing the storage process described above. At least one of each set of voltages is obtained from a position and a write operation is performed on at least one of each set of non-volatile storage elements using at least one of the aforementioned sets of voltages.

  In another embodiment, the storage system comprises each set of non-volatile storage elements that are multi-level storage elements, a non-volatile storage location, and at least one control circuit. The at least one control circuit (a) measures a respective threshold voltage distribution for each set of non-volatile storage elements (this measurement includes writing data to each set of non-volatile storage elements); b) Based on each threshold voltage distribution, for each set of non-volatile memory elements, identify each set of voltages customized for each set of non-volatile memory elements, and (c) set each set of voltages to non-volatile (D) after performing the storage process described above, after obtaining at least one of the voltage sets from the non-volatile storage position and using at least one of the voltage sets described above Accessing at least one of each set of non-volatile storage elements.

  Another embodiment comprises a set of individual storage devices. Each storage device includes one or more sets of non-volatile storage elements that are multi-level storage elements, each non-volatile storage location, and at least one control circuit. At least one control circuit (a) measures each threshold voltage distribution for one or more sets of non-volatile memory elements included in the memory device, and (b) non-volatile memory based on each threshold voltage distribution. Identify each set of voltages for each set of elements, (c) store each set of voltages for each set of non-volatile storage elements in their respective non-volatile storage locations, and (d) perform the storage process described above Thereafter, at least one of the sets of voltages is obtained from a non-volatile storage location and one or more sets of each set of non-volatile storage elements is obtained using at least one of the aforementioned sets of voltages. To access. Furthermore, each set of voltages is customized for each set of non-volatile storage elements and varies with the individual storage device.

  In another embodiment, a separate set of storage devices is provided. Each storage device includes one or more sets of non-volatile storage elements that are multi-level storage elements, each non-volatile storage location, and at least one control circuit. The at least one control circuit (a) measures one or more threshold voltage distributions for each of one or more sets of nonvolatile storage elements of the storage device, and (b) based on each threshold voltage distribution. Identify a set of voltages for each set of non-volatile storage elements; (c) store each set of voltages for each set of non-volatile storage elements in a respective non-volatile storage location; and (d) store the foregoing After performing the processing, at least one of the sets of voltages is obtained from a non-volatile storage location, and at least one of the sets of non-volatile storage elements is each Obtained from non-volatile storage location. Further, each set of voltages is customized for each set of non-volatile storage elements and varies between individual storage devices.

  Corresponding methods, systems and computer or processor readable storage devices can also be provided that perform the methods provided herein.

It is a top view of a NAND string. FIG. 2 is an equivalent circuit diagram of the NAND string of FIG. 1. 1 is a block diagram of an array of NAND flash storage elements. FIG. It is sectional drawing of the NAND string provided in the board | substrate. A block of storage elements is shown. An initial threshold voltage distribution of a set of nonvolatile memory elements and corresponding verification and read voltages are shown. 2 shows a threshold voltage distribution of a set of nonvolatile memory elements that are subjected to program disturb. FIG. 6b shows the measurement of the threshold voltage distribution and the corresponding setting of the read voltage. Shows a series of pulses of program and verify voltages. A series of write or program voltages available during programming is shown. Data including write, verify, and read voltages customized for each set of nonvolatile memory elements is shown. 1 represents a process for identifying the voltage of a set of non-volatile storage elements. 9a illustrates a process of accessing user data in a set of non-volatile storage elements using a predetermined voltage specified by the process of FIG. 9a. 4 represents a process for identifying voltages of a plurality of sets of nonvolatile memory elements. 9c illustrates a process of accessing user data of multiple sets of non-volatile storage elements using a predetermined voltage specified by the process of FIG. 9c. 1 is a block diagram of an array of NAND flash storage elements. FIG. It is a figure showing the outline of a host controller and a storage device. 1 is a block diagram of a non-volatile storage system using a single row / column decoder and read / write circuitry.

  The present invention provides a non-volatile storage system that sets voltage levels for write, read, verify operations, etc. to optimize performance.

  An example of one storage system suitable for applying the present invention uses a NAND flash memory structure in which a plurality of transistors are arranged in series between two select gates. The transistor in series and the select gate are called a NAND string. FIG. 1 is a top view of one NAND string. FIG. 2 is an equivalent circuit diagram thereof. The NAND string shown in FIGS. 1 and 2 is connected in series and includes four transistors 100, 102, 104, and 106 sandwiched between a first select gate 120 and a second select gate 122. The select gate 120 opens and closes the connection to the bit line 126 of the NAND string. The select gate 122 opens and closes the connection to the source line 128 of the NAND string. The select gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The select gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each transistor 100, 102, 104, 106 includes a control gate and a floating gate. The transistor 100 includes a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. Yes. The control gate may be configured as part of the word line. In one embodiment, each of transistors 100, 102, 104, 106 is a storage element and may be referred to as a memory cell. In another embodiment, the storage element may comprise a plurality of transistors or may be different from the embodiment shown in FIGS. The select gate 120 is connected to a selection line SGD (drain selection gate). The select gate 122 is connected to a selection line SGS (source selection gate).

  FIG. 3 is a circuit diagram of three NAND strings. A typical architecture of a flash memory system using a NAND structure includes a plurality of NAND strings. For example, three NAND strings 320, 340, 360 in a memory array with many NAND strings are shown. Each NAND string includes two selection gates and four storage elements. Although four storage elements are illustrated briefly, modern NAND strings can have, for example, up to 32 or 64 storage elements.

  For example, the NAND string 320 includes selection gates 322 and 327 and storage elements 323 to 326, the NAND string 340 includes selection gates 342 and 347 and storage elements 343 to 346, and the NAND string 360 includes the selection gate 362, 367 and storage elements 363 to 366. Each NAND string is connected to the source line by its own select gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The NAND strings 320, 340, 360 are connected to the bit lines 321, 341, 361 by selection transistors such as selection gates 322, 342, 362, respectively. These selection transistors are controlled by a drain selection line SGD. In other embodiments, the select line need not be common to multiple NAND strings. That is, different selection lines may be connected to different NAND strings. The word line WL3 is connected to the control gates of the storage elements 323, 343, and 363. The word line WL2 is connected to the control gates of the storage elements 324, 344, and 364. The word line WL1 is connected to the control gates of the storage elements 325, 345, and 365. The word line WL0 is connected to the control gates of the storage elements 326, 346, and 366. Thus, each bit line and each NAND string comprises an array or a set of storage element columns. A word line (such as WL3, WL2, WL1, WL0) comprises the array or set of rows. Each word line connects the control gates of the respective storage elements included in the row. Alternatively, the control gate may be configured by the word line itself. For example, word line WL2 provides a control gate for storage elements 324, 344, 364. In practice, there can be thousands of storage elements in one word line.

Each storage element can store data. For example, when storing 1-bit digital data, the available threshold voltage (V _TH ) range of the storage element is divided into two ranges to which logical data “1” and “0” are assigned. In an example of a NAND type flash memory, the V _TH becomes negative after the storage element is erased, and is defined as logic “1”. The V _TH after the program operation is positive and is defined as logic “0”. If V _TH is negative and a read is attempted, the storage element is turned on indicating that a logic “1” is stored. When V _TH is positive and a read operation is attempted, the storage element is not turned on, indicating that a logic “0” is stored. The storage element can also store information at a plurality of levels such as digital data of a plurality of bits. In this case, the range of _VTH values is divided into the number of data levels. For example, if four levels of information are stored, there are four _VTH ranges assigned to data values “11”, “10”, “01”, and “00”. In an example of a NAND type memory, the V _TH after the erase operation becomes negative and is defined as “11”. Positive _VTH values are used for the "10", "01" and "00" states. The specific relationship between the data written to the storage element and the threshold voltage range of the element depends on the data encoding scheme employed for the storage element. For example, US Pat. No. 6,222,762 and US Pat. No. 7,237,074, incorporated herein by reference in their entirety, describe various data codes for multi-state flash storage elements. Explains the conversion method.

  Relevant examples of NAND type flash memory and its operation are described in US Pat. Nos. 5,386,422, 5,570,315, 5, respectively, each incorporated herein by reference. 774, 397, 6,046,935, 6,456,528, and 6,522,580.

When programming a flash storage element, a program voltage is applied to the control gate of the storage element and the bit line connected to the storage element is grounded. Electrons are injected from the channel into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged, V _TH of the storage element is raised. In order to apply a program voltage to the control gate of the storage element being programmed, the program voltage is applied on the appropriate word line. As described above, one storage element in each NAND string shares the same word line. For example, when programming the storage element 324 of FIG. 3, the program voltage is also applied to the control gates of the storage elements 344 and 364. Unselected storage elements 344 and 364 may be subject to program disturb. Program disturb occurs when an unselected storage element on the same word line as the selected storage element is unintentionally programmed by applying a relatively high program voltage to the selected storage element.

FIG. 4 shows a cross-sectional view of the NAND string formed on the substrate. The diagram is simplified and not to scale. The NAND string 400 includes a source side selection gate 406, a drain side selection gate 424, and eight storage elements 408, 410, 412, 414, 416, 418, 420 and 422 formed on the substrate 490. A plurality of source / drain regions (an example is a source / drain region 430) is formed on both sides of each storage element and select gates 406 and 424. In one approach, the substrate 490 employs triple well technology, with a p-well region 492 formed in the n-well region 494, which is formed in the p-type substrate region 496. The NAND string and its nonvolatile memory element are at least partially formed on the p-well region. The potential of _{V BL} is a bit line 426 is supplied, the potential of _{V SOURCE} is supplied to the source supply line 404. A voltage is applied to n-well region 494 through terminal 403, and a voltage is applied to p-well region 492 through terminal 402.

During the read process, the control gate voltage V _CGR is applied to the selected word line (in this example, WL3) associated with the storage element 414 and other storage elements not shown. Note that the control gate of the storage element can be configured as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend through the control gates of storage elements 408, 410, 412, 414, 416, 418, 420, and 422, respectively. Please note that. In one possible scheme, the read pass voltage V _READ is applied to the remaining word lines associated with the NAND string 400. V _SGS and V _SGD are applied to the selection gates 406 and 424, respectively.

  FIG. 5 shows a block of the storage element. In one embodiment, the NAND flash EEPROM can be partitioned into 1024 blocks. Data stored in each block can be erased simultaneously. In the embodiment, a block is the smallest unit of memory elements that can be erased simultaneously. In this example, there are 4,256 columns corresponding to bit lines BL0, BL1,..., BL4255 in each block. In one embodiment, referred to as an all bit line (ABL) architecture, all bit lines of the block are selected simultaneously during read and programming operations. Storage elements along a common word line and connected to any bit line are programmed simultaneously.

  In the illustrated example, eight storage elements are connected in series to form a NAND string. There are eight data word lines WL0-WL7. The NAND string may further include a dummy storage element and a corresponding word line. In other embodiments, the NAND string may have more or less than eight data storage elements. The data memory cell can store user data or system data. The dummy memory cell is not normally used for storing user data or system data.

  One terminal of each NAND string is connected to the corresponding bit line via a drain select gate (connected to the select gate drain line SGD), and another terminal (connected to the select gate source line SGS). ) It is connected to the common source 505 via the source selection gate. That is, the common source 505 is connected to each NAND string.

  In one embodiment, referred to as an odd-even architecture, the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In this case, the storage element groups along the common word line and connected to the odd bit lines are programmed at the same time, and the storage element groups along the common word line and connected to the even bit lines have different timings. Are programmed at the same time. In each block, the columns are divided into even columns and odd columns.

  During one configuration of read and programming operations, 4,256 storage elements are selected simultaneously. The selected storage elements have the same word line and are part of a common physical page. Accordingly, 532 bytes of data forming one logical page can be simultaneously read or programmed, and one block of memory can store at least eight logical pages. In this example, the physical page and the logical page are the same, but generally this is not essential. For example, the physical page may include a plurality of logical pages. A logical page is usually the smallest set of storage elements that are written (programmed) simultaneously. In the case of a multi-state storage element, if each storage element stores 2 bits of data and each of these 2 bits is stored on a separate page, one block stores 16 logical pages. Other sized blocks and pages can also be used.

In either the ABL architecture or the odd-even architecture, the storage element can be erased by raising the p-well to an erase voltage (eg, 20V) and grounding the word line of the selected block. The source line and bit line are floated. The erase process is performed once for a block or, for some flash memory devices, for a small number of blocks. Electrons from the floating gates of the storage elements transferred into p- well region, V _TH of the storage elements becomes negative.

For read and verify operations, the select gates (SGD and SGS) are connected to a voltage in the range of 2.5-4.5V, and the unselected word lines are read pass voltages (typically in the range of 4.5-6V). The voltage is raised to V _READ , thereby operating the transistor as a pass gate. The selected word line is connected to a voltage at a level specified for each read and verify operation, and it is determined whether the V _{TH of} the connected storage element is above or below that level. For example, in a read operation of a two-level storage element, the selected word line may be grounded to detect whether _VTH is greater than 0V. In a verify operation of a two-level storage element, for example, to V _TH to verify whether it has reached at least 0.8 V, the selected word line may be connected to 0.8V. 0V is applied to the source and p-well. The selected bit line is precharged to a level such as 0.7V. When V _TH is greater than the word line read or verify level, the potential level of the bit line associated with the subject storage element is maintained at a high level because the storage element is not conducting. On the other hand, if V _TH is smaller than the read or verify level, the potential level of the target bit line is lowered to a low level (for example, 0.5 V, etc.) because the storage element conducts and discharges the bit line. Decrease. Thus, in one possible embodiment, the state of the storage element can be detected by a voltage comparator detection amplifier connected to the bit line. Similar to programming, read operations can be performed on a page-by-page basis.

  The details of the erase, read and verify operations described above are performed according to conventional known techniques. Thus, many of the details described can be varied by one skilled in the art. Other erase, read and verify techniques may be used.

  FIGS. 6a-c illustrate how program disturb can change the threshold voltage distribution of a set of non-volatile storage elements and a process for addressing this issue. FIG. 6a represents the initial threshold voltage distribution of a set of non-volatile storage elements and the corresponding verify and read voltages. The threshold voltage of the storage element is the lowest voltage that, when applied to the control gate of the storage element, changes the channel state from a non-conductive state to a conductive state. This voltage is affected by the amount of negative charge trapped in the floating gate. The greater the amount of charge, the higher the threshold voltage of the cell.

The most common multi-level cell (MLC) type device is configured such that the state can be represented by four voltage levels using four charge quantities of the floating gate including zero charge. Therefore, the MLC storage element stores 2-bit data. In general, N bits per storage element can be represented by 2 ^N voltage levels. More modern devices are expected to use 8 or more voltage levels. By increasing the number of bits per storage element, a flash device having a high data density can be manufactured, and the overall unit cost of the flash device can be reduced. Note that multi-level data storage is distinct from multi-bit data storage used in NROM devices and the like. Such multi-bit data storage uses charge levels corresponding to 0 or 1, respectively. Multi-level data storage uses, for example, charge level ranges corresponding to 00, 01, 10, and 11 when the MLC storage element stores 2-bit data.

In a read operation of an MLC device having four states, three reference voltage levels are used. A read operation of an MLC device having 8 states uses 7 reference voltage levels. In general, a device that stores N bits per cell represented by 2 ^N states uses 2 ^N-1 reference voltage levels for the read operation.

In FIG. 6a, the graph has an x-axis representing the threshold voltage and a y-axis representing the number of storage elements. The illustrated MLC device has eight states 0 to 7, corresponding verification voltages V _{V1 to} V _V7 , and read voltages V _{R1 to} V _R7 . The distribution of each state is relatively narrow, and each storage element is programmed to a desired voltage group. Further, for example, the reference voltage corresponding to the reading of the storage elements such as V _{R1 to} V _R7 is located between these voltage groups, and is a little higher than the previous distribution. For example, _VR1 is a value between state 0 and state 1, which is slightly higher than the distribution of state 0. _VR2 is a value between state 1 and state 2 and is slightly higher than the distribution of state 1.

  As described above, the program disturb may greatly change the threshold voltage distribution. Program disturb occurs when an unselected storage element on the same word line as the selected storage element undergoes unintentional programming because a relatively large program voltage is applied to the selected word line. . That is, the program disturb tends to increase the threshold voltage of the storage element. Further, for example, the lowest state, such as the erased state, is most likely to be raised, thus providing a worst-case indicator of the amount of program disturb experienced by a set of storage elements. Measurements made on flash memory devices show that the amount of program disturb varies widely from one storage device to another, from different blocks in the same device, or from different word lines in the same block. To ensure the best performance of all storage devices (eg, minimum error count), keep program disturb at a similar level on all devices, or (verification and Preferably, the (or read) voltage level is adapted to the actual value of the program disturb for a given device, block and / or word line. The techniques provided below are for controlling program disturb and for matching program disturb to verify and / or read voltage levels. More generally, this technique customizes the verification and / or read voltage levels used to access the set of storage elements.

FIG. 6b represents the threshold voltage distribution of a set of non-volatile storage elements that are undergoing program disturb. The read reference voltages V _{R1 to} V _R7 shown are the same as those shown in FIG. 6a. Compared to the distribution shown in FIG. 6a, here, the threshold voltage distribution in a lower state is wider because of program disturb, and the distribution is shifted to a higher one. Program disturb is prominent mainly in a low voltage state, and generally a higher state is less likely to cause a failure due to program disturb. In some examples, adjacent data state distributions may overlap. Here, if the same read voltage as shown in FIG. 6a is used to read the data state shown in FIG. 6b, at least the read voltages V _{R1 to} V _R5 in this example will cause a read error. It is understood that this can happen. Each read voltage V _{R1 to} V _R5 overlaps with the lower threshold voltage distribution. Conversely, the read voltages V _R6 and V _R7 in this example do not overlap with the lower threshold voltage distribution.

  In addition, the effect of program disturb may vary from one set of storage elements to another. For example, the threshold voltage distributions for different sets of storage elements may differ on a device, block, and / or word line basis. Thus, when the same fixed read voltage is used, this may cause an inappropriate result such as an error during the read operation. In addition, other factors can affect program disturb, such as temperature changes, the number of program / erase cycles, and the relative position of the storage element within the block, such as the proximity of the storage element to the source or drain of the NAND string. is there.

  FIG. 6c shows the measurement of the threshold voltage distribution of FIG. 6b and the corresponding read voltage setting.

The actual threshold distribution measurement process includes a process of reading the storage device in a separate read operation. Here, the number of read operations varies depending on the required resolution of distribution measurement. For example, if the storage device uses 8 states as 3 bits per storage element and a resolution of 10 points is required per state, a read operation is performed for each of 79 voltage threshold levels. . In FIG. 6c, each point represents a read point, and the solid line is similar to that of FIG. 6b. A histogram is provided in which the height of each bin represents the number of storage elements whose threshold voltage is within the range specified by that bin. For example, the read level most appropriate for any set of storage elements can be specified as the minimum value between adjacent states. If there is a minimum width, the most appropriate read level between the two data states can be a little higher than the lower of the two states. Here, the read levels V ′ _{R1 to} V ′ _R5 are shifted to the optimum level with respect to the level of FIG. 6b, while V _R6 and V _R7 are not changed. If the read level of FIG. 6b is used, an actual read error can occur. In general, it is preferred that the read level be as close as possible to the previous level in order to allow the maximum data retention shift.

  In general, acquiring the “threshold voltage distribution” of a set of storage elements is a process of dividing the threshold voltage range of the storage elements into a plurality of subranges and then counting the number of occurrences of the storage elements in each subrange. Including. The expression of all or some of the memory elements in a set of memory elements may be counted. It is also possible to count only the expression for a part of a subrange (for example, one or a plurality of subranges, etc.), and predict other subranges from the result.

  In one approach, on-line evaluation of current device, block, and / or wordline program disturb and adjustment of voltage level settings for the evaluated program disturb can be performed. The actual program disturb of each manufactured storage device can be measured, for example, on a block-by-block basis, with the voltage level setting (for read and verify voltages for different data states) and the program disturb measured in that block. And can be adapted. This "block adapted" voltage level setting can be used in subsequent program and read operations. To address program disturb, the verify voltage and / or read voltage must be modified.

  The value of program disturb can be defined as the width of the threshold voltage distribution in the erased state in a page where all data states exist. That is, the data programmed into the page contains a representation of all possible data states. The threshold voltage distribution can be considered as a predetermined percentage of cells depending on the ECC correction capability. The program disturb value can be obtained by, for example, randomly programming data in the storage device, reading the threshold voltage distribution of all data states, and specifying the width of the erase state. Default voltage level settings can be used for this programming.

  Once the width of the erase level threshold voltage distribution is obtained, the voltage level settings for the remaining data states are determined. There are two approaches for calculating the voltage level: a “fixed program disturb” method and a “fixed voltage window” method. Both of these approaches have the same principle.

First, identify available voltage windows for all data states except the erased state. The available voltage window is between the “edge” (rightmost) voltage of the erased state and the verification voltage of the highest data state (V _V7 for 8 data states). Can be defined by distance. The voltage window can also be defined as starting from the lowest voltage (leftmost) in the erased state.

  Second, the window is divided for each data state at a rate corresponding to the relative data holding shift of the data state. The data retention shift of the storage element in a particular situation in the block (eg, a write / erase cycle) and the predetermined retention time depend on the threshold voltage of the storage element, and the shift increases as the threshold increases. This dependent quantitative characteristic is technically specific and can be obtained, for example, by testing and / or theoretical calculations. The division between the data states of the available voltage window may be performed according to such characteristics.

  Third, based on the above, the read level and verification level for each state are determined. The difference between the above two approaches is as follows. In the fixed program disturb scheme, the program disturb value is adjusted to a predetermined fixed value by modifying the voltage window (eg, by modifying the verification voltage level of the highest data state). The program disturb phenomenon is caused by stress applied to the erased storage element by a high program voltage applied to the word line during programming. In addition, program disturb is higher when the program voltage applied to the word line is high, such as when the selected storage element is programmed to the highest data state. This means that program disturb can be controlled by changing the verification level of the highest data state. An iterative process may be used to obtain the desired program disturb value. For example, if the program disturb is too high, the verification level of the highest data state can be reduced. Then, the program disturb can be determined again (for example, by determining the threshold voltage distribution) to determine whether it is close to the desired level. If the program disturb is still too high, the verification level of the highest data state can be reduced again.

  Note that the verification levels of all states are related to each other by known functions, linear or nonlinear, and available voltage windows. For example, because the loss of data retention is greater at higher conditions, the verification level is generally set to have a relatively large space for the higher state than for the lower state. Thus, once the overall voltage window is known, the read or verify voltage can be calculated.

  In the fixed voltage window method, the highest level of verification remains fixed at the default value, which may cause program disturb, which may vary between word lines, blocks, and / or devices, but this is measured Is done. Since the program disturb value changes, the state width of the remaining data state also changes.

  In the illustrated approach, the process of adjusting the voltage level setting may occur during the manufacturing stage of the storage device, or after the storage device is shipped to the end user. Further, if necessary, the adjustment may be repeated at different occasions. Alternatively, the adjustment may be performed only once during the lifetime of the storage device. Indeed, since program disturb decreases as the storage device goes through additional program / erase cycles, subsequent adjustments may not be necessary.

  For example, after a device is shipped to an end user, adjustments are triggered by different timings, such as a temperature change, a program cycle is performed a predetermined number of times, or a predetermined time has elapsed since the last data write. May be. Appropriate tracking components and / or processes are provided for this purpose. In one approach, the adjusted voltage value can be stored in a storage device for each device block using a reliable programming technique similar to storing flash internal parameters in a fuse ROM. Values specific to these blocks can be obtained and used in normal operation of the storage device when the block is designated for programming or reading.

  Thus, in one approach, customized read and / or verify voltages can be specified at one time for a set of storage elements of a storage device, such as during manufacturing. The set of voltages can be stored in a non-volatile storage location within the storage device and subsequently accessed each time a read or programming operation is performed. See FIGS. 9a-9C and FIG. 10 for details.

FIG. 7 shows a pulse train 700 of program and verify voltages. For example, the programming voltage may be set for each step size, such as a program pulse 705 having an amplitude of V _PGM1 , followed by a program pulse 710 having an amplitude of V _PGM2 , then a program pulse 715 having an amplitude of V _PGM3 , and so on. The size will be increased. After each program pulse, verification voltages of V _{V1 to} V _V7 are applied as represented by waveforms 720, 725, and 730. These verification voltages can be customized for any of the storage element sets described in connection with FIGS.

The write voltage can also be customized for different sets of non-volatile storage elements. FIG. 8a represents a series of write or program voltages available during programming. Intermediate verification voltages are omitted for clarity. As described above, the write voltage starts from the initial level V _PGM-INITIAL and is programmed for each step size until the storage elements are programmed to their respective states or reach the final voltage V _PGM-FINAL. The amplitude increases. In one approach, one or more write voltage parameters can be customized for a particular set of storage elements. For example, if the threshold voltage distribution of a set of storage elements in a low state indicates that many of the threshold voltages in such a state are greater than expected or the width of the threshold distribution is higher than expected, the programming effect We can conclude that is stronger than average. In such a case, the write voltage can be lowered by reducing _VPGM-INITIAL and / or the step size. In some examples, the maximum allowable _VPGM-FINAL or lower level pulses may be repeated. Similar if the programming effect of a set of storage elements is weaker than average, for example, if _VPGM-FINAL has been reached before all storage elements are programmed to their respective states Adjustments can be made. Such adjustments include increasing V _PGM-INITIAL , step size, and / or maximum allowable V _PGM-FINAL . Since the step size directly affects the width of the distribution state, the step size can be reduced if the width of each distribution is wider than the average, and if the width of each distribution is narrower than the average Note that the step size can be increased. For example, this allows faster programming.

FIG. 8b shows data including write, verify and read voltages customized for different sets of non-volatile storage elements. As described above, the write, verify and / or read voltages can be customized for different sets of storage elements. The optimum voltage for each storage element can be determined and stored for subsequent use. For example, the voltages for a particular storage device, block wordline and / or group of storage device wordlines can be stored in a non-volatile storage location of the storage device. Here, the write voltage for the first set of memory elements “set 1” is represented by V _PGM-1 , the verification voltage is represented by V _V1-1 , V _V2-1, etc., and the read voltage is V _R1-1 , It is represented by _VR2-1 etc. Further, _VPGM-1 may represent one or more of set 1, _VPGM-INITIAL , step size, and _VPGM-FINAL . Each of the three variables may be adapted for a different storage element. Similarly, the write voltage of the second set of storage elements “set 2” is represented by V _PGM-2 (eg, representing one or more of V _PGM-INITIAL , step size and V _PGM-FINAL of set 2). The verification voltage is represented by V _V2-1 , V _V2-2, etc., and the read voltage is represented by V _R1-2 , V _R2-2, etc. In general, the program voltage of the i-th set of storage elements “set i” is represented by V _PGM-i (eg, representing one or more of V _PGM-INITIAL , step size and V _PGM-FINAL of set i). The verification voltage is represented by V _V1-i , V _V2-i, etc., and the read voltage is represented by V _R1-i , V _R2-i, etc.

  FIG. 9a represents a process for determining the voltage of a set of non-volatile storage elements. Step 900 begins a process for obtaining a set of voltages (eg, read, verify, and / or write voltages) for a set of non-volatile storage elements. This set includes, for example, storage elements associated with one or more specific word lines in a block having a plurality of word lines, storage elements associated with a specific block in a storage device having a plurality of blocks, Alternatively, a storage element associated with an entire specific storage device can be represented. In one approach, at step 902, a set of non-volatile storage elements is programmed with random test data. Test data should include all data states. For example, such test data can be utilized when the storage device is tested at the manufacturing site prior to shipment. After the storage device is shipped, if the test data is not available, the existing user data may be programmed instead. User data may be scrambled to represent all data states relatively uniformly. For example, user data residing in a given location on a storage device, such as an arbitrary block, is copied to another location, eg, another block containing a specific set of storage elements for which a read / verify voltage is to be determined. Can.

  After step 902, one of two passes is performed. In the first pass, in step 904, for example, the threshold voltage distribution of a set of storage elements is specified by performing a read operation at different increased voltage threshold levels as shown in FIG. 6c. In general, this involves determining the threshold voltage distribution for all data states. In step 906, a set of voltages is identified based on the threshold voltage distribution. For example, a set of read voltages may be determined based on the minimum value of the threshold voltage distribution, as shown in FIG. 6c. A set of verification voltages may be determined based on a voltage window. For example, the voltage window can be identified from the threshold voltage distribution, and the verification voltage can be determined by a function that provides the desired relative space between the verification voltages within the constraints of the overall voltage window. In step 912, data identifying the set of voltages is stored in a non-volatile storage location. For example, voltage set data can be stored in a storage element of a storage device that has obtained a threshold voltage distribution. These storage elements do not store user data, for example. In one approach, data is stored in the storage element of the block from which the threshold voltage distribution is obtained. In another approach, the data is stored in the storage elements of the word line from which the threshold voltage distribution is obtained. Alternatively, a non-volatile storage location used by the controller of the storage device may be used. Other positions may be used.

  In the second pass, step 908 identifies a threshold voltage distribution for a set of storage elements that is less than all data states. For example, the threshold voltage distribution in the erased state is specified. As described above, since the erase state is most sensitive to program disturb, the level of program disturb can be measured using the upper edge of the threshold voltage distribution in this state. The appropriate read level for state 1 can be determined based on this upper edge, and the appropriate read level for the remaining states can be determined based on a known relationship between the read levels of the states. That is, a function that associates an appropriate read level of state i (i> 2) with an appropriate read level of state 1 can be used. It is also possible to specify a threshold voltage distribution of a set of storage elements for a plurality of data states, such as states 1 and 2, and associate these with other states. The function may, for example, associate an appropriate read level for state i (i> 3) with an appropriate read level for states 1 and 2. Such functions can be obtained from logical relationships and / or empirical test results. For this reason, in step 910, a set of voltages is determined based on the threshold voltage distribution of a smaller number of states than all data states.

  Further, the voltage set data may be represented in any manner. FIG. 8b described above shows one case. In some cases, a set of storage element identifiers (eg, sets 1, 2,..., Etc.) may be used, as shown. For example, the controller may have a storage location that stores a different set of voltages for each block of the corresponding device, or for a group of blocks within the device. In this case, the identifier of the set of storage elements may be associated with each set of voltages. In other cases, the position of a set of voltages serves as an identification element for a storage element to which a voltage is applied (eg, a set of voltages stored in a block is applied to that block, and a word A set of voltages stored on a line is what is applied to that word line.) In another embodiment, a set of voltages for different blocks may be stored in one block. In this case, an identification element is required to associate a block with a corresponding set of voltages. In some cases, the set of voltages may be stored to identify the storage elements to which they are applied by their relative position at the storage location. For example, the first position of the storage position may correspond to the first block, the second position of the storage position may correspond to the second block, and the like. Alternatively, the storage location may be in a block, where the first location of the storage location corresponds to the first word line or set of word lines in the block, and the second location of the storage location is the second word line. Alternatively, it may be configured to correspond to a set of word lines in the block.

  Moreover, the absolute value of a voltage may be memorize | stored and the offset value showing the offset from the set of the voltage used as a reference | standard, or a single reference value may be memorize | stored. Alternatively, for example, data used to directly control the voltage circuit such as a binary code word input to the digital-analog converter may be stored. In any case, such data is understood as representing a set of voltages.

  The technique provided herein has the advantage of not requiring the use of a reference storage element, which is an additional storage element that stores non-user data for the purpose of tracking threshold voltage changes experienced by the device. The reference storage element occupies extra space in the storage device in addition to the storage element for storing user data. The reference storage element is typically read “in operation” so that adjustments are made each time a page of data is read. In this case, the set of voltages is not stored in a non-volatile storage location for later use. Further, in general, the reference storage element does not measure the threshold voltage distribution. In the reference storage element, a measurement is performed on a set of storage elements, such as a reference storage element, for use in determining the voltage of the second non-overlapping set of storage elements. Conversely, in the technique provided herein, measurements are taken and voltages are determined for the same set of storage elements that are subsequently accessed using voltages.

  FIG. 9b represents a process for accessing user data in a set of non-volatile storage elements using voltages predetermined by the process of FIG. 9a. In one approach, the access process may occur after the storage element is shipped to the user. That is, it may be after the device is manufactured and installed in the host system used by the user. In step 920, an operation (eg, program, verify, or read) is started for a set of non-volatile storage elements. In step 922, a set of voltages is obtained from the non-volatile storage location. In step 924, the set of voltages is used to access user data in a set of non-volatile storage elements. Such access may include programming / verification or reading.

  FIG. 9c represents a process for determining voltages for multiple sets of non-volatile storage elements. As described above, the voltage can be customized for different sets of storage elements within a single storage device or between different storage devices. Many of these steps are similar to those of FIG. 9a. In step 930, one or more sets of non-volatile storage elements in the storage device are selected. In step 932, the process of obtaining a corresponding set of voltages begins. In step 934, the set of non-volatile storage elements is programmed with random test data. In step 936, the threshold voltage distribution of one or more sets of nonvolatile memory elements is identified. In step 938, a set of voltages is identified based on the threshold voltage distribution. In step 940, a set of voltages corresponding to the currently selected set or sets of non-volatile storage elements is stored in a non-volatile storage location. At decision step 942, if the next storage element is present in the storage device, the process proceeds to step 930 to select the next set or sets of non-volatile storage elements. If the next storage element is not present in the storage device, the process proceeds to decision step 946. For example, when multiple storage devices are being analyzed in the manufacturing environment and there is a next storage device that needs to be identified, the process proceeds to step 930. If the next storage device does not exist at step 946, the process ends at step 948.

  For example, in each pass in the above process, a set of voltages may be obtained for a word line, a set of word lines, a block, or a set of blocks of storage elements. For example, any set of voltages may be applied to a single word line or set of word line storage elements, or a single block or set of block storage elements. Further, for example, if multiple sets of voltages are specified for writing, verifying, and / or reading, each set can be applied to a different group of storage elements. For example, while one set of verification voltages for the entire storage device can be obtained, different sets of read voltages may be obtained for different blocks within the storage device. A plurality of passes included in the process may be performed continuously or in parallel.

  FIG. 10 represents a process of accessing user data of multiple sets of non-volatile storage elements using voltages predetermined by the process of FIG. 9c. In step 1000, one or more sets of non-volatile storage elements in the storage device are selected. Steps 1002 to 1006 generally correspond to steps 920 to 924 of FIG. 9b, respectively. In step 1002, an operation (eg, program, verify, or read) for one or more sets of non-volatile storage elements is initiated. In step 1004, a corresponding set of voltages is obtained from the non-volatile storage location. In step 1006, the set of voltages is used to access user data in one or more sets of non-volatile storage elements. Such access may include programming / verification or reading. At decision step 1008, if the next storage element to be accessed exists in the storage device, the process proceeds to step 1000 where the next set or sets of non-volatile storage elements in the storage device are selected. . If at decision step 1008 there is no next set of storage elements in the storage device, the process ends at step 1010.

  As before, each pass in the above process takes a set of voltages for one word line, one set of word lines, one block, or one set of blocks of storage elements and accesses the corresponding storage element. May be. Any set of voltages may be applied to a single word line or a set of word line storage elements, or a single block or set of blocks. A plurality of passes included in the process may be performed continuously or in parallel.

  FIG. 11 is a block diagram illustrating an array of NAND flash storage elements, for example as shown in FIGS. Along each column, a bit line is connected to the drain terminal of the drain select gate of the associated NAND string. For example, the bit line 1106 is connected to the drain terminal 1126 of the drain select gate of the NAND string 1150. Along each row of the NAND string, a source line 1104 may be connected to all the source terminals 1128 of the source select gate of the NAND string. An example of a NAND architecture array and its operation as part of a storage system is shown in US Pat. Nos. 5,570,315, 5,774,397, 6,046,935.

  The array of storage elements is divided into a number of storage element blocks. As is often seen in flash EEPROM systems, a block is a unit of erase. That is, each block includes the minimum number of storage elements that are erased at one time. Each block is generally divided into a plurality of pages. A page is a unit of programming. One or more pages of data are typically stored in a row of storage elements. A page can store one or more sectors. The sector includes user data and overhead data. Overhead data generally includes an error correction code (ECC) calculated from the user data for that sector. Some of the controllers (described below) calculate an ECC when data is programmed into the array and check this when data is read from the array. Alternatively, ECC and / or other overhead data may be stored on a different page or different block than the user data to which it pertains.

  The sector of user data is generally 512 bytes and corresponds to the sector size of the magnetic disk drive. Overhead data is generally an additional 16-20 bytes. For example, a large number of pages such as 8 pages to 32, 64, and 128 pages constitute a block. In some embodiments, one row of NAND strings has blocks.

  FIG. 12 shows an overview of the host controller of the storage device of the storage system. A storage device can be regarded as a storage system by itself. The storage element 1205 is provided in a storage device 1200 having its own controller 1210 for performing program / verify and read operations. The storage device may be formed on a removable memory card or USB flash drive that is inserted into a host device such as a laptop computer, digital camera, personal digital assistant (PDA), digital audio player or mobile phone, for example. Good. The host device includes its own controller 1225 for interoperating with the storage device, such as reading or writing user data. For example, when reading data, the host controller can send a command specifying the address of user data to be acquired to the storage device. The storage device controller converts such commands into command signals that can be interpreted and processed by control circuitry within the storage device. The controller 1210 may also include a non-volatile storage location 1215 that stores a set of voltages and a buffer memory 1220 that temporarily stores user data that is written (or read) to the memory array, as described above. Good. The host controller can be considered a component external or external to the storage device. The storage device may include, for example, one or more memory dies, and the host controller may be provided external to the one or more memory dies as described with reference to FIG. Good.

  The storage device responds to the read command by reading data from the storage element and making it available to the host controller. In one possible approach, the storage device stores the read data in the buffer 1220 and notifies the host controller when the data can be read. The host controller responds by reading the data from the buffer and sends another command to the storage device for reading the data from yet another address. For example, data may be read for each page. The host controller may process the read data to identify the threshold voltage distribution of the storage elements of the storage device. In another approach, the control circuit of the storage device may identify the threshold voltage distribution. A more detailed embodiment of the storage device will be described below.

  A typical storage system includes an integrated circuit chip that includes a controller 1210 and one or more integrated circuit chips that each include a memory array and associated control, input / output, and state machine circuits. The storage device may be incorporated as a part of the host system, or may be provided in a memory card that can be inserted into and removed from a corresponding socket of the host system. Such a card may include all of the storage devices, or a controller, a memory array, and associated peripheral circuitry may be provided on a separate card.

  FIG. 13 is a block diagram of a non-volatile storage system using a single row / column decoder and read / write circuitry. In this figure according to an embodiment of the invention, the storage device 1396 includes a read / write circuit for reading and programming pages of storage elements in parallel. Storage device 1396 includes one or more memory dies 1398. The memory die 1398 includes a two-dimensional array of storage elements 1400, a control circuit 1310, and a read / write circuit 1365. In some embodiments, the array of storage elements may be three dimensional. The storage array 1400 can be specified by word lines through the row decoder 1300 and can be specified by bit lines through the column decoder 1360. The read / write circuit 1365 includes a plurality of sense blocks 1300 and allows pages of storage elements to be read or programmed in parallel. In general, the controller 1350 is provided in the same storage device 1396 as one or more memory dies 1398 (eg, a removable storage card). Commands and data are transmitted between the host and controller 1350 via line 1320 and between the controller and one or more memory dies 1398 via line 1321.

  The control circuit 1310 performs a storage operation on the memory array 1100 in cooperation with the read / write circuit 1365. The control circuit 1310 includes a state machine 1312, an on-chip address decoder 1314, and a power control module 1316. The state machine 1312 enables control of storage operation at the chip level. On-chip address decoder 1314 provides an address interface between those used in the host or memory controller and the hardware addresses used by decoders 1330 and 1360. The power control module 1316 controls the power supply and the voltage supplied to the word line and bit line during the storage operation. For example, the power control module 1316 applies a control gate read voltage to a selected word line and applies a read pass voltage to a non-selected word line for use during a read operation, and a threshold for a set of storage elements. The voltage distribution can be specified. The power control module 1316 can apply a voltage sweep to the selected word line. The power control module 1316 may comprise, for example, one or more digital-to-analog converters for this purpose. In this case, the control circuit can generate a voltage sweep without the need for external test equipment such as, for example, outside the memory die 1398. This is advantageous in that a voltage sweep can be generated at any time after the storage device is manufactured or after the end user obtains the storage device. Further, the storage device 1396 may include a circuit for identifying the threshold voltage distribution of the storage element, so that this process does not require external test equipment or an external host, etc. Can be done. This is advantageous in that the threshold voltage distribution can be specified at any time without the need for external equipment.

  For some applications, several configurations of FIG. 13 can be combined. In various designs, one or more configurations other than the storage element array 1100 can be single or combined into a management circuit or a control circuit. For example, the one or more management circuits or control circuits include any of the control circuit 1310, state machine 1312, decoder 1314/1360, power control 1316, sense block 1300, read / write circuit 1365, controller 1350, host controller 1399, etc. One or a combination of these may be provided.

  Data stored in the memory array is read by the column decoder 1360 and output to the external I / O line via the data I / O line and the data input / output buffer 1352. Program data stored in the memory array is input to the data input / output buffer 1352 via an external I / O line. Command data for controlling the storage device is input to the controller 1350. The command data notifies the flash memory of what operation is requested. The input command is transmitted to the control circuit 1310. The state machine 1312 can output a memory status such as READY / BUSY or PASS / FAIL. If the storage device is busy, no new read or write commands can be received.

  The data storage location 1354 may be provided connected to the controller 1350, similar to the storage location 1215 of FIG.

  In another possible embodiment, the non-volatile storage system may use dual row / column decoders and read / write circuits. In this case, access to the memory array from various peripheral circuits is performed in a symmetrical form on both sides of the array. This can reduce the density of access lines and circuits on each side in half.

  The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many variations and modifications are possible in light of the above teaching. The described embodiments best describe the invention and its practical application, so that those skilled in the art will be able to use the various embodiments and various modifications to suit the particular use intended. It was chosen to make the best use of the present invention. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (15)

A method of configuring a storage device, comprising:
Measuring each threshold voltage distribution for each set of non-volatile storage elements (1205) that are multi-level storage elements in the storage device;
Identifying each set of voltages (V _PGM-i , V _V1-i ) customized for each set of non-volatile storage elements for each set of non-volatile storage elements based on each threshold voltage distribution When,
Storing each set of voltages in a non-volatile storage location (1354);
After the storing step, obtaining at least one of each set of voltages from a non-volatile storage location;
Performing a write operation on at least one of each set of non-volatile storage elements using the at least one of each set of voltages;
A method comprising:   The measuring step, the identifying step, and the storing step are performed at a manufacturing site before the storage device is shipped to an end user, and the obtaining step and the writing operation are performed. The method of claim 1, wherein the method is performed after the storage device is shipped to the end user. Different voltage sets (V _PGM-i , V _V1-i ) are specified for different blocks of the nonvolatile memory element of the memory device, and each block of the nonvolatile memory element is independent of the other blocks of the nonvolatile memory element. The method according to claim 1 or 2, wherein the method is erasable.   Different sets of voltages are identified for different groups of non-volatile storage element blocks of the storage device, each block of non-volatile storage elements being erasable independently of other blocks of the non-volatile storage element, The method according to claim 1 or 2, comprising one or more blocks, wherein each block in a group uses the same set of voltages.   The method according to claim 1 or 2, wherein different sets of voltages are identified for different groups of word lines of non-volatile storage elements of the storage device, each group comprising one or more word lines.   The step of measuring, the step of specifying, the step of storing, the step of acquiring, and the step of executing the write operation are performed after the storage device is shipped from a manufacturing site to an end user. The method as described in any one of -5.   The method according to claim 1, wherein a plurality of write operations are performed on each set of non-volatile storage elements using each set of voltages. The nonvolatile memory element stores test data at the stage of the measuring step,
The method according to claim 1, wherein the nonvolatile memory element stores user data after the writing operation.   The method according to claim 1, wherein the voltage includes a verification reference voltage.   The method according to claim 1, wherein the voltage includes a write voltage.   The method according to claim 1, wherein the non-volatile storage location is in a storage device. A storage system,
Each set of non-volatile storage elements (1205) that are multi-level storage elements;
A non-volatile storage location (1354);
At least one control circuit (1350),
The at least one control circuit comprises:
(A) measuring each threshold voltage distribution for each set of nonvolatile memory elements;
(B) Based on each threshold voltage distribution, for each set of non-volatile storage elements, a respective set of voltages (V _PGM-i , V _V1-i ) customized for each set of non-volatile storage elements. Identify,
(C) store each set of voltages in a non-volatile storage location;
(D) after performing the storing process, obtaining at least one of each set of voltages from a non-volatile storage location and using the at least one of each set of voltages to generate a non-volatile storage element A write operation is performed for at least one of each set of
Storage system. The at least one control circuit identifies different voltage sets (V _PGM-i , V _V1-i ) for different blocks of non-volatile storage elements of the storage system, and each block of the non-volatile storage elements is non-volatile The storage system of claim 12, wherein the storage system is erasable independently of other blocks of the storage element.   The at least one control circuit identifies different sets of voltages for different groups of non-volatile storage element blocks of a storage system, each block of non-volatile storage elements being independent of other blocks of non-volatile storage elements. 13. The storage system of claim 12, wherein each group comprises one or more blocks, and each block within a group uses the same set of voltages.   13. The at least one control circuit identifies different sets of voltages for different groups of word lines of non-volatile storage elements of a storage system, each group comprising one or more word lines. The storage system described in 1.

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