TW201005898A - Window-type semiconductor stacked structure and the forming method thereof - Google Patents

Window-type semiconductor stacked structure and the forming method thereof Download PDF

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Publication number
TW201005898A
TW201005898A TW97128054A TW97128054A TW201005898A TW 201005898 A TW201005898 A TW 201005898A TW 97128054 A TW97128054 A TW 97128054A TW 97128054 A TW97128054 A TW 97128054A TW 201005898 A TW201005898 A TW 201005898A
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Taiwan
Prior art keywords
wafer
substrate
back surface
adhesive layer
active
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TW97128054A
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Chinese (zh)
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TWI401777B (en
Inventor
Hung-Tsun Lin
Cheng-Ting Wu
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW97128054A priority Critical patent/TWI401777B/en
Publication of TW201005898A publication Critical patent/TW201005898A/en
Application granted granted Critical
Publication of TWI401777B publication Critical patent/TWI401777B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

A chip stacked structure includes a substrate having a front side and a reverse side, and an opening penetrated through the substrate; a first chip having an active surface and a back surface, and the active surface of first chip is faced downward to attach on the reverse side of the substrate by first adhesive layer, and portion of reverse side of first chip is to be exposed; a second chip having an active surface and a back surface, and the active surface of the second chip is faced upward and attached on the back surface of the substrate by a second adhesive layer; a first wire is electrically connected the active surface of first chip and the back surface of the substrate; a second wire is electrically connected the active surface of second chip and the front surface of the substrate; a first encapsulated body is encapsulated the first chip, first adhesive layer, a first wire, and the reverse side of the substrate; a second encapsulated body is encapsulated the second chip, second adhesive layer, a second wire, the portion of the back surface of the first chip, and the portion of front side of the substrate; and a conductive component is disposed on the front side of the substrate.

Description

201005898 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝結構及其方法，特別是有關於一種具有開口 之基板之晶粒堆疊封裝結構及其封裝方法。 【先前技術】 具有開口之基板之半導體封裝結構係為較先進之封裝技術，其特徵在於: 在基板上形成至少一個貫孔(opening)，且允許晶片設置且覆蓋住基板之貫 ® 孔，並藉由穿過貫孔之打線接合之導線與基板電性連接。此種設置的方式可 有效的縮短打線接合之導線之長度，藉此在基板及晶片之間形成電性連接。 習知的具有開口之基板之封裝結構如第1圖所示，其中基板100具有一上表 面及一下表面且具有一開口 102貫穿基板10(^接著，一晶片12〇以主動面 (未在圖中表示)朝下的方式且其主動面上的焊墊122係曝露於基板1〇〇之開 口 102緊接著’複數條導線130以打線接合(b〇ndingWires)的方式經由基板 100之開口 102連接至曝露於開口 1〇2之晶片12〇之焊墊122，藉此電性連 接基板100之下表面與晶片120之主動面。接著，一封裝體14〇藉由印刷的 參 方式形成在基板100的下表面上用以包覆導線130以及將基板1〇〇之開口 102密封住。 然而，由於在封裝體140(尤其是藉由樹脂材料(仿如materjai)所形成之 封裝體140)及與封裝體140接觸之晶片12〇之間的熱膨脹係數(CTE， coefficient of thermal expansion)之不匹配，在高溫的條件下，例如封裝體14〇 之固化(curing)步驟或是後續的熱循環步驟，特別是在晶粒12〇的部份因為 來自於封裝體140的熱應力(thermal stress)會產生晶粒崩裂(chip_crack)的問 題，而相對於較長且較大尺寸的晶粒來說，其可靠度以及良率都會降低。 此外，在封裝體140的形成過程中，其焊線接合之導線會與樹脂材料以模 201005898 流的方式形成雜體時_，使得會有祕的問題。 【發明内容】 鑒於以上的問題’本卿的主要目的在於提供__種彻具開口之基板 進行晶粒之堆疊，藉以減少整個晶姆疊結構之封裝厚度。 根據上述之目的’轉_露_種晶⑽疊結構，包含:―基板，具有 -正面及-背面且分別配置有—線路佈局及具有—開口貫穿基板；一第一 晶片，具有-主動面及-背面，其中第—晶片之主動面朝下且經由一第BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure and a method thereof, and more particularly to a die stack package structure having an open substrate and a package method therefor. [Prior Art] A semiconductor package structure having an open substrate is a more advanced packaging technology, characterized in that at least one opening is formed on the substrate, and the wafer is allowed to be disposed and covers the through hole of the substrate, and The wire is electrically connected to the substrate by a wire bonded through the through hole. This arrangement can effectively shorten the length of the wire bonding wire, thereby forming an electrical connection between the substrate and the wafer. The package structure of the conventional open substrate is as shown in FIG. 1 , wherein the substrate 100 has an upper surface and a lower surface and has an opening 102 extending through the substrate 10 (ie, a wafer 12 〇 is active surface (not shown) In the downward direction, the pads 122 on the active surface are exposed to the opening 102 of the substrate 1 and then the plurality of wires 130 are connected via the opening 102 of the substrate 100 in a manner of wire bonding (b〇nding Wires). The pad 122 exposed to the opening 12 of the wafer 1 is electrically connected to the lower surface of the substrate 100 and the active surface of the wafer 120. Then, a package 14 is formed on the substrate 100 by means of printing. The lower surface is used to cover the wire 130 and seal the opening 102 of the substrate 1. However, due to the package 140 (especially the package 140 formed by a resin material (like materjai)) The coefficient of thermal expansion (CTE) between the wafers 12 that are in contact with the package 140 is not matched, and under high temperature conditions, such as a curing step of the package 14 or a subsequent thermal cycle step, especially The portion of the die 12 turns because of the thermal stress from the package 140, which causes chip cracking, and the reliability of the die with respect to the longer and larger die. In addition, in the formation process of the package body 140, the wire bonding wire may form a hybrid with the resin material flowing in the manner of the mold 201005898, so that there is a problem of the secret. The above problem 'The main purpose of this Qing dynasty is to provide __ a substrate with an opening for stacking the crystal grains, thereby reducing the package thickness of the entire eutectic structure. According to the above purpose, the _ _ _ seed crystal (10) stacked structure The method includes: a substrate having a front surface and a back surface and respectively disposed with a line layout and an opening through the substrate, and a first wafer having an active surface and a back surface, wherein the active surface of the first wafer faces downward and One

黏著層將第曰曰片之部份背面貼附在基板之背面上，並曝露出未被第一 黏著層覆蓋之第-晶片之部份背面；第二晶片，具有—主動面及一背面， 其中第二晶片之主動面朝上，且經由—第二黏著層將第二晶片之背面固定 在第-晶片之背面上；複數條第—導線，用以電性連接第—晶片之主動面 及基板之背面；複數條第二導線，肋電性連接第二晶片之絲面及基板 之正面，帛封裝體帛以包覆第一晶片、第一黏著層、複數條第一導線 及基板之背面卜第二封裝體，用以包覆第二晶片、第二黏著層、複數條 第二導線、第-晶片之部份背面及基板之部份正面；及複數個導電元件， 係設置在基板之正面上。 本發明還揭露另-晶粒堆疊結構，包含:―基板，具有—正面及一背面 且分別配置有-線路佈局及具有—開σ貫穿基板；—第—晶片 動面及-背面’其中第-晶片之主動面朝下，且將第—晶片之背面藉由一 黏者層貼附在基板之部份背面上且黏著層覆蓋住開口之—表面第二曰 片，具有-主動面及-表面，其中第二晶片之主動面朝上，且第^ 背f由黏_定在第，之背面上；複數條第-導線，用以電性連 接第-晶片之主動面及基板之背面；複數條第二導線，㈣電性連接第二 晶片之主動面及基板之正面；第-雜體，用以包覆第—晶片黏著層、 複數條第-導線及基板之背面；第二封裝體，用以包覆第二晶片、部份黏 7 201005898 :複數個導電元件，係設置在基 著層、複數條第二導線及基板之部份正面 板之正面上。 ❹ 述之晶粒料結構，本發明揭露-種形成堆疊結構之方 匕.提供基板具有-正面及一背面且分別配置有一線路佈局及 =:開口貫穿基板之正面及背面；晶片在基板之部份背面上， 2將第-晶片之主動面朝下，第—晶片之背面藉由—第—黏著層貼附在基 =部Γ背面上且於開口曝露出第一晶片之未被第一黏著層所覆蓋之第一 之奇面，貼附第—晶片在第_晶片之背面上，係將第二晶片之主動面 上’且第二晶片之-背面藉由—第二黏著層貼附在未被第—黏著層所覆 蓋之第-晶片之背面慎；形成複數條第—導線，以電性連接第—晶片之主 動面及基板之背面；形成複數條第二導線，以電性連接第二晶片之主動面 及基板之正面；形成-第-封裝趙，用以包覆第—晶片、第—黏著層、複 數條第-導線及基板之背面；形成—第二封裝體，用以包覆第二晶片、第 二黏著層、第-晶片之部份背面、複數條第二導線及基板之部份正面；及 形成複數個導電元件’係形成在基板之正面上。 本發明再娜-種形成晶粒堆#之方法’包含:提供—基板其具有一 正面及-背面且分雜置有-線路佈局，及具有—開σ貫穿基板之正面及 背面；貼附-第-晶片在基板之部份背面上，係將第一晶片之主動面朝下， 將第-晶片之-背面藉由-黏著層貼附在基板之背面；貼附—第二晶片在 第-晶片之背面上’係將第二晶片之—主動面朝上且將第二晶片之一背面 $ _著& -⑼之背面上；形成複數條第—導線以電性連接第 日日片之主動面及基板之背面，形成複數條第二導線以電性連接第二晶片 之主動面及基板之正面；形成一第一封裝體用以包覆第一晶片、黏著層、 複數條第-導線及基板n形成第二封裝體肋包覆第二晶片、黏著 層、第-晶片之雜背©、複數條第二導線及基板之部份正面；及形成複 數個導電元件，係將複數個導電元件形成在基板之正面上。 8 201005898 有關本發明的特徵與實作，賊合圖示作最佳實施例詳細說明如下。 (為使對本發明的目的、構造、特徵、及其魏有進—步的瞭解，兹配合 實施例詳細說明如下。） 【實施方式】 本發明在麟撕的方㈣_種職結構及其織方法，係提供具有 開口之基板，使得獨尺寸之晶片可以覆晶方式朝關口貼附在基板上， 然後進行33粒疊之方法。為了能徹底地瞭解本發明，將在下顺描述中提 ❹㈣盡的步職额成。顯賊，本發_施行跡蚊“封裝的方式 之技藝者所熟⑽特殊細節。本發明的難實_，料詳細描述如 下’然而除了這些詳細描述之外’本發明還可以廣泛地施行在其他的實施 例中，且本發明的範料纽定，其以之後的專利範圍為準。 第2A圖至第2B圖表示具有開口之基板之晶粒堆昼封裝結構之各步驟 形成示意圖。首先，參考第2A圖，係先提供一基板1〇，其具有一正面及一 背面，且在正面及背面分別設置有一線路佈局⑽㈣(未在圖中表示），在 此，在基板10的正面與背面係可以配置相同或是不相同之線路佈局，而在 本實施例中’係用以堆叠不同尺寸及功能之晶粒為其主要之發明技術特 徵，因此，係以具有不同線路佈局之基板10做為實施例之說明。然而，要 說明的是’基板10之線路佈局之形成及其結構並非本發明之技術特徵，僅 以應用具有線路佈局之基板做為本發明之實施例說明，因此不再多加陳述。 接著，係利用半導體製程’在基板10的上方形成一圖案化之光阻層(未 在圖争表示）；接著進行顯影及侧，以移除部份基板，而形成一開口 12貫 穿基板10之正面及背面。在此’基板1〇之材料可以是單層或是多層之電 路板或是金屬薄板(metal foil)。 緊接著’第2B圖係表示將-第一晶片貼附在基板之背面之示意圖。在 201005898 第2B圖中’係先提供第一晶片30 ’其具有一主動面其一背面，且於主動面 上具有複數個焊塾32。接著’係將第一晶片30之主動面朝下，並且藉由第 一黏著層20將第一晶片30之背面對準基板1〇之開口 12，將第一晶片30 之部份背面固著在基板10之背面上，並且於基板10之開口 12曝露出第一 晶片30之部份背面。在此實施例中，第一黏著層2〇可以是二階段熱固膠 (B-stage) 〇 接下來，請參考第2C圖，係表示將第二晶片堆疊在第一晶片上之示意 圖。在第2C圖中，係提供一第一晶片50，其具有一主動面及一背面，且於 β 主動面上具有複數個焊墊52。接著，將第二晶片5〇之主動面朝上其第二 晶片50之背面藉由一第二黏著層40貼附在第一晶片3〇曝露於基板ι〇之 開口 12之背面上，以形成一晶粒堆疊結構。在此實施例中，第二黏著層可 以是晶粒黏著膠膜(die attach film)或是環氧樹脂(epoxy)。此外，在本實施例 中’第-晶片30與第二晶片50是為不同功能之晶片，藉此以增加晶粒堆 疊封裝結構之應用範圍。 、接著，請參考第2D圖，係表示將第一晶片、第二晶片分別祕板電性 連接之不意圖。在第2D圖中，係先將貼附在基板1〇上之第一晶片3〇與第 φ 二晶片50上下翻轉，使得第一晶片3〇之主動面朝上而第二晶片50之主動 面朝下。接著，利用打線接合(bonding wire)的方式，將複數條第一導線 之兩端，分成在第-以30之絲面之複油料32及^〇^; 面上，且在基板10的背面上配置有一線路佈局，因此，利用複數條第一導 線60可以電性連接第-晶片30及基板1〇。然後，再將第一晶片3〇與第二 ，片5〇下上翻轉’使得第—晶片3()之主動面朝下及第二晶片知之主動面 =。同樣地，利用打線接合的方式，將複數條第二導線％之兩端分別形 成在第二晶片5G之絲面之複數贿墊52及基板ig之正面上。由於 之正面上雜配置有-線路佈局，使得複數條第二導線％可以電 連接第-晶片50及基板1G。科’要制的是，在本發_實施例中， 201005898 在第二晶片5〇上形成複數條第二導線70然後再將第二晶片50與 第-曰曰片30上下倒轉，再在第一晶片3〇上形成複數條第一導線的。 ’參考第2Ε圖，絲示形成封裝體在基板上之示意目。料π Η)之ηΛ將一尚分子材料(未在圖中表示)注入第二晶片5〇之四周及基板 / 内。接者，對此高分子材料進行一烘程序(bakeprocess)，使 得南分子材料固化以形成一封裝趙以包覆住第二晶片％、第二黏 40、複數條第一導線6〇且覆蓋住基板1〇之開口 12及基板1〇之部份正面 上。然後’將第一晶片30與第二晶片5〇上下翻轉，使得第一晶片3〇之主 © 動面朝上。同樣地，再將另一高分子材料注入第-晶片30之四周。接下來， 對高分子材料進行-輯程序，使得高分子材料故化以形成另—封裝體卿 以包覆住第-晶片30、複數條第-導、線6〇以及基板1()之背面。在此實施 例中，高分子材料可以是雜、環氧樹脂、丙稀酸（acrylic)、及苯環丁嫌 (BCB)等材料。 緊接著’參考帛2F _表祕複數個導電元件職在基板之正面之示 意圖。在第2F圖中，在基板10之正面上係陣列排列方式，形成複數個導The adhesive layer attaches a part of the back surface of the second film to the back surface of the substrate, and exposes a part of the back surface of the first wafer not covered by the first adhesive layer; the second wafer has an active surface and a back surface. The active surface of the second wafer faces upward, and the back surface of the second wafer is fixed on the back surface of the first wafer via the second adhesive layer; the plurality of first wires are electrically connected to the active surface of the first wafer and a back surface of the substrate; a plurality of second wires, the ribs are electrically connected to the surface of the second wafer and the front surface of the substrate, and the package body is covered with the first wafer, the first adhesive layer, the plurality of first wires, and the back surface of the substrate a second package for covering the second wafer, the second adhesive layer, the plurality of second wires, a portion of the back surface of the first wafer, and a portion of the front surface of the substrate; and a plurality of conductive elements disposed on the substrate On the front. The present invention also discloses a further-die stack structure comprising: a substrate having a front surface and a back surface and respectively arranged with a line layout and having an open σ through substrate; a first wafer moving surface and a back surface The active side of the wafer faces downward, and the back side of the first wafer is attached to a part of the back surface of the substrate by an adhesive layer and the adhesive layer covers the second surface of the opening, having an active surface and a surface The active surface of the second wafer faces upward, and the first surface f is fixed on the back surface of the first wafer; the plurality of first conductors are electrically connected to the active surface of the first wafer and the back surface of the substrate; a second wire, (4) electrically connecting the active surface of the second wafer and the front surface of the substrate; the first-heavy body for covering the first wafer adhesive layer, the plurality of first-wires and the back surface of the substrate; the second package body, The second wafer, the partial adhesive 7 201005898: a plurality of conductive elements are disposed on the front surface of the base layer, the plurality of second wires and a part of the front panel of the substrate. The present invention discloses a method for forming a stacked structure. The substrate is provided with a front surface and a back surface and is respectively provided with a line layout and =: the opening penetrates the front and back surfaces of the substrate; the wafer is in the portion of the substrate On the back side, 2, the active side of the first wafer faces downward, and the back side of the first wafer is attached to the back surface of the base portion by the first adhesive layer and the first wafer is exposed to the first wafer. The first odd surface covered by the layer, attached to the first wafer on the back side of the first wafer, is attached to the active surface of the second wafer and the second wafer-back side is attached by the second adhesive layer The back surface of the first wafer not covered by the first adhesive layer is carefully formed; a plurality of first conductive wires are formed to electrically connect the active surface of the first wafer and the back surface of the substrate; and a plurality of second conductive wires are formed to electrically connect The active surface of the two wafers and the front surface of the substrate; forming a first-package Zhao for covering the first wafer, the first adhesive layer, the plurality of first conductors, and the back surface of the substrate; forming a second package for packaging Covering the second wafer, the second adhesive layer, the first wafer The back portion, the second portion of the plurality of wires and positive substrate; and forming a plurality of conductive elements' formed on the front line of the substrate. The method of the present invention further comprises: providing a substrate having a front side and a back side and having a miscellaneous arrangement - a line layout, and having an opening σ penetrating the front side and the back side of the substrate; attaching - The first wafer is on a part of the back surface of the substrate, and the active surface of the first wafer faces downward, and the back surface of the first wafer is attached to the back surface of the substrate by an adhesive layer; the second wafer is attached to the first wafer. On the back side of the wafer, the active side of the second wafer is facing up and the back side of one of the second wafers is on the back side of the _- & - (9); a plurality of first-wires are formed to electrically connect the first day of the film The active surface and the back surface of the substrate form a plurality of second wires electrically connected to the active surface of the second wafer and the front surface of the substrate; forming a first package for covering the first wafer, the adhesive layer, and the plurality of first wires And forming a second package rib to cover the second wafer, the adhesive layer, the first back of the first wafer, the plurality of second wires, and a portion of the front surface of the substrate; and forming a plurality of conductive elements, the plurality of conductive materials The component is formed on the front side of the substrate. 8 201005898 In relation to the features and implementations of the present invention, the preferred embodiment of the thief is illustrated in detail below. (In order to make the understanding of the object, the structure, the features, and the advantages of the present invention, the following detailed description will be given in conjunction with the embodiments.) [Embodiment] The present invention is in the form of a tearing (four) _ seed structure and its weaving method, A substrate having an opening is provided so that a single-sized wafer can be attached to the substrate in a flip-chip manner to the gate, and then a 33-stack method is performed. In order to fully understand the present invention, it will be mentioned in the following description (4). The thief, the present invention _ implementation of the mosquitoes "the way of encapsulation of the skilled person cooked (10) special details. The difficulty of the present invention _, the material is described in detail below 'however, in addition to these detailed descriptions, the invention can also be widely implemented In other embodiments, and the method of the present invention, which is based on the scope of the following patents, Figures 2A to 2B show the steps of forming the steps of the die-stacked package structure of the substrate having the opening. Referring to FIG. 2A, a substrate 1 is provided, which has a front side and a back side, and a line layout (10) (4) (not shown) is disposed on the front side and the back side, respectively, where the front side of the substrate 10 is The back side system may be configured with the same or different circuit layouts, and in the present embodiment, 'the die for stacking different sizes and functions is the main technical feature of the invention. Therefore, the substrate 10 having different line layouts is used. As an illustration of the embodiment, it is to be noted that the formation of the circuit layout of the substrate 10 and its structure are not the technical features of the present invention, and only the substrate having the line layout is applied as The embodiments of the invention are described so that they are not further stated. Next, a patterned photoresist layer is formed over the substrate 10 using a semiconductor process (not shown); then development and side are performed to remove portions. The substrate is formed to form an opening 12 extending through the front and back surfaces of the substrate 10. Here, the material of the substrate 1 can be a single layer or a multilayer circuit board or a metal foil. Illustrated is a schematic view of attaching a first wafer to the back side of the substrate. In FIG. 2B, the first wafer 30 is provided first with an active surface and a back surface, and has a plurality of solder pads 32 on the active surface. Then, the active surface of the first wafer 30 faces downward, and the back surface of the first wafer 30 is aligned with the opening 12 of the substrate 1 by the first adhesive layer 20, and the back surface of the first wafer 30 is fixed. On the back surface of the substrate 10, a portion of the back surface of the first wafer 30 is exposed at the opening 12 of the substrate 10. In this embodiment, the first adhesive layer 2〇 may be a two-stage thermosetting adhesive (B-stage). Next, please refer to the 2C chart, which means A schematic view of the second wafer stacked on the first wafer. In FIG. 2C, a first wafer 50 having an active surface and a back surface and having a plurality of pads 52 on the β active surface is provided. The active surface of the second wafer 5 is facing up, and the back surface of the second wafer 50 is attached to the back surface of the first wafer 3 and exposed on the opening 12 of the substrate by a second adhesive layer 40 to form a crystal. The particle stack structure. In this embodiment, the second adhesive layer may be a die attach film or an epoxy. Further, in the present embodiment, the first wafer 30 and the second wafer The wafer 50 is a wafer of different functions, thereby increasing the application range of the die-stacked package structure. Next, please refer to FIG. 2D, which shows the intention of electrically connecting the first wafer and the second wafer to each other. . In the 2D figure, the first wafer 3A and the φ2 wafer 50 attached to the substrate 1 are first turned upside down so that the active surface of the first wafer 3 is facing upward and the active surface of the second wafer 50 is Down. Then, the two ends of the plurality of first wires are divided into the surface of the first to 30th surface of the re-oil 32 and the surface of the substrate 10 by means of a bonding wire. A line layout is configured so that the first wafer 60 and the substrate 1 can be electrically connected by a plurality of first wires 60. Then, the first wafer 3〇 and the second wafer 5 are flipped upside down so that the active side of the first wafer 3() faces downward and the second wafer knows the active surface=. Similarly, both ends of the plurality of second wires % are formed on the front faces of the plurality of brims 52 and the substrate ig of the silk surface of the second wafer 5G by means of wire bonding. Since the front side is provided with a - line layout, the plurality of second wires % can electrically connect the first wafer 50 and the substrate 1G. In the present invention, 201005898 forms a plurality of second wires 70 on the second wafer 5, and then inverts the second wafer 50 and the first wafer 30 up and down, and then A plurality of first wires are formed on a wafer 3. Referring to Figure 2, the outline of the package on the substrate is shown. The η 之 之 Λ 注入 一 一 一 分子 分子 分子 分子 分子 分子 分子 分子 分子 分子 分子 分子 分子 分子 注入 注入 注入 注入 注入 注入 注入 注入 注入 注入Receiving, a bake process is performed on the polymer material, so that the south molecular material is solidified to form a package to cover the second wafer %, the second adhesive 40, and the plurality of first wires 6 and covered. The opening 12 of the substrate 1 and the front portion of the substrate 1 are on the front side. Then, the first wafer 30 and the second wafer 5 are turned upside down so that the main surface of the first wafer 3 faces upward. Similarly, another polymer material is injected into the periphery of the first wafer 30. Next, the polymer material is subjected to a procedure such that the polymer material is deformed to form another package body to cover the back surface of the first wafer 30, the plurality of first guides, the wires 6A, and the substrate 1 (). . In this embodiment, the polymer material may be a material such as a hetero, an epoxy resin, an acrylic, or a benzoquinone (BCB). Immediately after the reference 帛2F _ table, a plurality of conductive elements are intended to be on the front side of the substrate. In FIG. 2F, an array arrangement is formed on the front surface of the substrate 10 to form a plurality of guides.

電7G件90，例如金屬凸塊(metalbump)或是錫球(s〇lderbaji)，即可完成晶粒 ^ 堆疊之封裝結構。 W 另外，第3A圖至第3F圖係表示本發明之另一晶粒堆疊之封裝結構之 實施例。在第3A圖中，係先提供—基板1〇，其具有一正面及一背面，且在 正面及责面分別設置有一線路佈局(lay〇ut)(未在圖中表示），在此在基板 10的正面與背面係可以配置相同或是不相同之線路佈局而在本實施例 中，係用以堆疊不同尺寸及功能之晶粒為其主要之發明技術特徵，因此， 係以具有不同線路佈局之基板10做為實施例之說明。然而，要說明的是， 基板10之線路佈局之形成及其結構並非本發明之技術特徵，僅以應用具有 線路佈局之基板做為本發明之實施例說明，因此不再多加陳述。 接著’係利用半導體製程，在基板10的上方形成一圖案化之光阻層(未 201005898 在圖中表示）；接著進行顯影及侧，以移除部份基板，而形成—開口 12貫 穿基板ίο之正面及背面。在此，基板10之材料可以是單層或是多層之電 路板或是金屬薄板(metal foil” 緊接著，第3B圖係表示將-第—晶片貼附在基板之背面之示意圖。在 第3B圖中，係先提供第一晶片30，其具有一主動面其一背面，且於主動面 f具有複數辦墊…接著，碰第―晶片3Q之絲面朝下，並且藉由黏 著層2〇B將第一晶片3〇之背面對準基板1〇之開口⑵將第-晶片3〇之部 份背面E1著在基板1G之部份背面上，並且覆蓋住基板1Q之開口 12而曝露 Ο 出黏著層2〇B。在此實施例中，黏著層20B可以是晶粒黏著膠膜(DAF; die attach film)或是環氧樹脂(ep0Xy) 〇 接下來，請參考第3C圖’係表示將第二晶片堆昼在第一晶片上之示意 圖。在第3C圖中，係提供-第二晶片5G，其具有—主動面及_背面且^ 主動面上具有複數個焊整％。接著，將第二晶片5G之主動面朝上，其第二 晶片50之背面藉由黏著層20B固著在第一晶片3〇之背面上以形成一: 粒堆疊結構。在此實施例中，第―晶片3G與第二晶片5()是為不同功能之 晶片，藉此以增加晶粒堆疊封裝結構之應用範圍。 ❹ 接著，請參考第30圖，係表示將第一晶片、第二晶片分別與基板電性 連接之示意圖。在第3D®中’係先將貼附在基板1〇上之第—晶片3〇與第 一晶片50上下翻轉’使得第一晶片3〇之主動面朝上而第二晶片之主動 面朝下。接著’利用打線接合(bonding wire)的方式，將複數條第一導線6〇 之兩端’分別形成在第-晶片30之主動面之複數個·32及基板⑴之背 面上’且在基板1〇的背面上配置有一線路佈局，因此，利用複數條第一導 線60可以電性連接第一晶片3〇及基板1〇。然後，再將第一晶片3〇與第二 晶片50下上翻轉，使得第一晶片3〇之主動面朝下及第二晶片5〇之主動面 朝上。同樣地’利用打線接合的方式，將複數條第二導線7〇之兩端分別形 成在第二晶片50之主動面之複數個焊墊52及基板1〇之正面上。由於，在 12 201005898 性連接第佈局’使得複數條第二導線70可以電 也可θ% …糊•蝴萄實施例中， 第一曰G上形賴數條第二導線職後再將第二晶片50與 第一曰曰片30上下倒轉，再在第一晶片3〇上形成複數條第一導線⑼。 圖中緊ΪΓ參考第犯圖’係表示形成封裝體在基板上之示意圖。在第3E Π 分子材料(未在_示)注人第二晶片5g之四周及基板 Ο :口 12内。接|，對此兩分子材料進行—烘烤程序(_γ_)，使 得Μ子材·化以形成-封裝體以包覆住第二晶片％、曝露於開口 Π之崎層2GB、複數條第—導線⑼且覆蓋住基板1()之開口 η及基板ι〇 之部份正面上。織，將第—晶片3Q與第二晶片％上下翻轉使得第一 晶片30之主動面朝上。同樣地，再將另一高分子材料注入第一晶片3〇之 四周。接下來’對高分子材料進行—輯程序，使得高分子養故化以形 成另-封裝體80B以包覆住第-晶片30、部份黏著層2〇B、複數條第一導 線60以及基板10之背面。在此實施例中，高分子材料可以是石夕膠、環氧 樹脂、丙烯酸（acrylic)、及苯環丁烯（BCB)等材料。 緊接著，參考第3F圖係表示將複數個導電元件形成在基板之正面之示 % 意圖。在第3F圖中，在基板10之正面上係陣列排列方式，形成複數個導 電元件90，例如金屬凸塊(metai bump)或是錫球(s〇lder ball)，即可完成晶粒 堆疊之封裝結構。 雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發 明’任何熟習相像技藝者，在不脫離本發明之精神和範圍内，當可作些許 之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利 範圍所界定者為準。 【圖式簡單說明】 第1圖係根據習知之技術，表示具有開口之基板之封裝結構之示意圖； 13 201005898 表示具有開口之基板之晶粒 第2A圖至第2F圖係根據本發明之技術， 堆疊封裝結構之各步驟形成示意圖；及 第3A圖至帛3F圖係根據本發明之另一實施例，表示具有開口之基板 之晶粒堆疊封裝結構之各步驟形成示意圖。 【主要元件符號說明】 10 基板 12開口 20 第一黏著層 20B黏著層 30、5〇第一晶片 4〇第二黏著層 60 第一導線 70第二導線 祖、80B封裝體 90導電元件 100 基板 102 開口 120 晶片 122 焊墊 130 導線 140 封裝體The electric 7G piece 90, such as a metal bump or a solder ball, can complete the die-packed structure. Further, Figs. 3A to 3F show an embodiment of a package structure of another die stack of the present invention. In FIG. 3A, a substrate 1 is provided, which has a front side and a back side, and a layout layout (not shown) is disposed on the front side and the blame surface, respectively. The front and back sides of the 10 can be configured with the same or different circuit layouts. In this embodiment, the die for stacking different sizes and functions is the main technical feature of the invention, and therefore, has different line layouts. The substrate 10 is described as an embodiment. However, it is to be noted that the formation of the circuit layout of the substrate 10 and its structure are not technical features of the present invention, and the application of the substrate having the wiring layout is described as an embodiment of the present invention, and therefore will not be further described. Then, a semiconductor process is used to form a patterned photoresist layer on the substrate 10 (not shown in FIG. 201005898); then development and side are performed to remove part of the substrate, and the opening 12 is formed through the substrate. Front and back. Here, the material of the substrate 10 may be a single layer or a plurality of circuit boards or metal foils. Next, FIG. 3B is a schematic view showing the attachment of the first wafer to the back surface of the substrate. In the figure, a first wafer 30 is provided, which has an active surface and a back surface thereof, and has a plurality of pads on the active surface f. Then, the surface of the first wafer 3Q faces downward and is adhered by the adhesive layer 2 B aligns the back surface of the first wafer 3 with the opening (2) of the substrate 1 and places a portion of the back surface E1 of the first wafer 3 on the back surface of the substrate 1G, and covers the opening 12 of the substrate 1Q to expose the opening. Adhesive layer 2〇B. In this embodiment, the adhesive layer 20B may be a die attach film (DAF; die attach film) or an epoxy resin (ep0Xy). Next, please refer to the 3C figure A schematic diagram of the second wafer stacked on the first wafer. In FIG. 3C, a second wafer 5G is provided, which has an active surface and a back surface, and the active surface has a plurality of solder fill %. The active surface of the second wafer 5G faces upward, and the back surface of the second wafer 50 is fixed by the adhesive layer 20B. A wafer 3 is formed on the back surface to form a: grain stack structure. In this embodiment, the first wafer 3G and the second wafer 5 () are wafers of different functions, thereby increasing the application of the die stacked package structure. ❹ Next, please refer to Fig. 30, which is a schematic diagram showing the first wafer and the second wafer electrically connected to the substrate. In the 3D®, the first wafer is attached to the substrate 1 3〇 flipping up and down with the first wafer 50 such that the active side of the first wafer 3 is facing upward and the active side of the second wafer is facing downward. Then, a plurality of first conductors 6 are formed by means of bonding wires. Both ends of the crucible are formed on the plurality of surfaces 32 of the active surface of the first wafer 30 and the back surface of the substrate (1), and a line layout is disposed on the back surface of the substrate 1A. Therefore, the plurality of first wires 60 can be used. Electrically connecting the first wafer 3 and the substrate 1 . Then, the first wafer 3 and the second wafer 50 are flipped upside down, so that the active side of the first wafer 3 is facing downward and the second wafer 5 is active. Face up. Similarly, 'using the wire bonding method, The two ends of the plurality of second wires 7 are respectively formed on the front faces of the plurality of pads 52 and the substrate 1 of the active surface of the second wafer 50. Since the second layout of the 12 201005898 is connected to the first layout, the plurality of second wires are made. 70 can be electric or θ% ... paste, in the embodiment, the first 曰G is formed on the second wire after the second wafer 50 and the first cymbal 30 upside down, and then in the first A plurality of first wires (9) are formed on the wafer 3, and a schematic diagram of forming a package on the substrate is shown in the figure below. In the 3E 分子 molecular material (not shown), the second wafer 5g is injected. Around and substrate Ο: inside port 12. Connect|, the two-molecule material is subjected to a baking process (_γ_), so that the bismuth material is formed to form a package to cover the second wafer %, exposed to the open layer, 2 GB, and a plurality of sheets - The wire (9) covers the opening η of the substrate 1 () and a portion of the front surface of the substrate ι. The first wafer 3Q and the second wafer are flipped upside down so that the active side of the first wafer 30 faces upward. Similarly, another polymer material is injected into the periphery of the first wafer 3 . Next, the procedure of the polymer material is performed, so that the polymer is modified to form the other package 80B to cover the first wafer 30, the partial adhesion layer 2〇B, the plurality of first wires 60, and the substrate. The back of the 10th. In this embodiment, the polymer material may be a material such as Shiqi gum, epoxy resin, acrylic, or benzocyclobutene (BCB). Next, reference to the 3Fth diagram shows the intention of forming a plurality of conductive elements on the front side of the substrate. In FIG. 3F, an array arrangement is formed on the front surface of the substrate 10 to form a plurality of conductive elements 90, such as metal bumps or solder balls, to complete the die stacking. Package structure. While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The patent protection scope of the invention is subject to the definition of the scope of the patent application attached to the specification. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a package structure of an open substrate according to a conventional technique; 13 201005898 shows a crystal grain of a substrate having an opening, FIGS. 2A to 2F, according to the technology of the present invention, The steps of the stacked package structure are schematically illustrated; and FIGS. 3A to 3F are diagrams showing the steps of forming the die-stacked package structure of the substrate having the opening according to another embodiment of the present invention. [Major component symbol description] 10 substrate 12 opening 20 first adhesive layer 20B adhesive layer 30, 5 〇 first wafer 4 〇 second adhesive layer 60 first wire 70 second wire ancestor, 80B package 90 conductive element 100 substrate 102 Opening 120 wafer 122 pad 130 wire 140 package

1414

Claims (1)

201005898 / 十、申請專利範圍： 1· 一種晶粒堆疊結構，包含： 穿該 板’具有一正面及一背面且分別配置有一線路佈局及具有一開口貫 下一曰！’具有—絲面及，其中該第u之該主動面朝 面上第—黏著層將該第—晶片之部份該背面貼附在該基板之該背 一’並曝露出未被該第-黏著層覆蓋之該第—晶片之部份該背面； 一=晶片，具有-主動面及__背面，其中該第二晶片之該主動面朝 =上且㈣-第二黏著層將該第二晶片之該背面固定在該第―“之該背 ❹ 面複數條第-導線’用以電性連接該第一晶片之該主動面及該基板之該背 .複數條m連接該第二晶片之該絲面及該基板之該正 曲， 一第-封㈣’ _以包覆該第—晶片、該第—黏著層、 及該基板之該背面； 不 ^ ❿ 續第一第日Η封裝體係用以包覆該第U、該第二黏著層、該些第二導線、 該第-曰曰片之部份該背面及該基板之部份該正面；及 複數個導電元件’係設置在該基板之該正面上。 1 ^申^利範圍第1項所述之晶粒堆疊結構，射該基板選自於玻璃、石 m、電路板及金屬薄板所組成之族群中。 之尺月-ΓΓι範圍第1項所述之晶粒堆養結構’其中該第一晶片及該第二晶片 之尺寸大小不同。 固申膠第1 奴晶鄉#結構，其⑽—纖為二階段熱 其他麵為— 15 201005898 6. 如申凊專利範圍第！項所述之晶粒堆叠結構，其中該些導電元件為錫此 ball)。 7. 如申請專利範圍第！項所述之晶粒堆疊結構，其中該些導電元件為凸塊 rbumt)^ 〇 8. —種晶粒堆疊結構，包含： 某=板’具有-JL面及—背面且分觀置有—線路佈局及具有—開口貫穿該 -第-晶片’具有-主動面及—背面，其中該第—晶片之該主動面朝下，201005898 / X. Patent application scope: 1. A die stack structure comprising: the board s has a front side and a back side and is respectively provided with a line layout and has an opening; 'Having a silk surface and wherein the active surface of the second surface of the first surface of the first wafer adheres the back side of the first wafer to the back of the substrate and is exposed without the first The adhesive layer covers a portion of the back surface of the first wafer; a = wafer having an active surface and a back surface, wherein the active surface of the second wafer is facing up and (4) - the second adhesive layer is the second The back surface of the wafer is fixed on the "the back surface of the plurality of first-wires" for electrically connecting the active surface of the first wafer and the back of the substrate. The plurality of strips m are connected to the second wafer. The silk surface and the positive curvature of the substrate, a first seal (four)' _ to cover the first wafer, the first adhesive layer, and the back surface of the substrate; not the first first day Η packaging system The front surface of the U, the second adhesive layer, the second conductive layer, the second conductive layer, and the front surface of the substrate; and a plurality of conductive elements are disposed on the second conductive layer On the front side of the substrate, the die stack structure described in claim 1 is applied to the substrate and is selected from the group consisting of glass and stone. In the group consisting of a circuit board and a metal sheet, the size of the first wafer and the second wafer are different in the size of the first wafer and the second wafer. 1 奴晶乡# structure, its (10)-fiber is a two-stage heat, the other side is - 15 201005898 6. The grain stacking structure described in the scope of the invention, wherein the conductive elements are tin balls. 7. The die stack structure of claim 2, wherein the conductive elements are bumps rbumt ^ . . . . . . . . . . . . . . . . . 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒 晶粒The back side and the top view are provided with a line layout and having an opening through the -first wafer having an active surface and a back surface, wherein the active side of the first wafer faces downward 且將該第-晶片之該背面藉由—黏著層貼附在該基板之部份該背面上且該黏 著層覆蓋住該開口之一表面； -第二晶片’具有-主動面及—背面，其中該第二晶片之該主動面朝上， 且該第二晶片之該背面藉由該黏著層@定在該第—晶片之該背面上； 複數條第-導線’用以電性連接該第一晶片之該主動面及該基板之該背 面， 複數條第二導線’用以電性連接該第二晶片之該主動面及該基板之該正 面； 一第-封裝艎’個以包覆該第—晶片、該黏著層、該些第—導線及該 ❹ 基板之該背面； 第-封裝H ’剌以包覆該第二晶片、部份該黏著層、該些第二導線 及該基板之部份該正面；及 複數個導電元件，係設置在該基板之該正面上。 9.如申請專利範圍第8項所述之晶粒堆叠結構，其中該基板選自於單層電路 板、多層電路板及金屬薄板所組成之族群中。 瓜如申請專利範圍第8項所述之晶粒堆疊結構，其中該第一晶片及該第二晶片 之尺寸大小不同。 U.如申請專利範圍第8項所述之晶粒堆叠結構，其中該黏著層為_或晶粒 16 201005898 * 黏著層(die attach film)。 12. 如申請專利範圍第8項所述之晶粒堆疊結構，其㈣些導電元件為錫球 (solder ball) ° 13. 如申請專利範圍第8項所述之晶粒堆疊結構，其中該些導電元件為凸塊 (bump) ° 14. 一種形成晶粒堆疊結構之方法，包含： 提供-基板具有-正面及-背面且分別配置有—線路佈局及具有一開 口貫穿該基板之該正面及該背面； 貝占附一第一晶片在該基板之部份該背面上，係將該第-晶片之一主動面 朝下’該第-晶片之-背面藉由—第—黏著層貼附在該基板之部份該背面 上且於該開口曝露出未被該第一黏著層所覆蓋之該第一晶片之該背面； 貼附-第二晶片在該第-晶片之該背面上，係將該第二晶片之一主動面 朝上’該第二晶片之-背面藉由一第二黏著層貼附在未被該第一黏著層所 覆蓋之該第一晶片之該背面上； 形成複數條第-導線以電性連接該第—晶片之該主動面及該基板之該 背面； 形成複數條第二導線以電性連接該第二晶片之該主動面及該基板之該 正面； 形成第-封裝體，用以包覆該第一晶片、該第一黏著層、該些第一導 線及該基板之該背面； 形成一第二封裝鱧，用以包覆該第二晶片該第二黏著層該第一晶片 之部份該背面、該些第二導線及該基板之部份該正面；及 形成複數辦f讀’雜該些導電元件形絲絲板之該正面上。 1S-如申明專利範圍第14項所述之方法，其中該基板選自於單層電路板、多層 電路板及金屬薄板所組成之族群中。 16.如申請專纖圍第14項所述之方法，其中該第一晶片及該第二晶片之尺寸 17 201005898 大小不同。 17. 如申5胃專利範圍第14項所述之方法，其巾該第—黏著層為二階段熱固膠 (B-stage) ° 18. 如申請專利範圍第14項所述之方法，其中第二黏著層為環氧樹脂(ep〇xy)或 晶粒黏著膜(die attach film) 〇 2如申雜删第丨4顧叙方法，其巾輕導電元件祕球㈣Wan)。 .如申賴翻第14項所述之方法，其中導電元件為凸帅腎）。 21· 一種形成晶粒堆疊結構之方法，包括： e 提供基板，其具有-正面及—背面且分_置有-線路佈局，及具有 一開口貫穿該基板之該正面及該背面； 貼附-第-晶片在該基板之部份該背面上，係將該第一晶片之一主動面 下’將該第-晶片之-背面藉由一黏著層貼附在該基板之該背面； 貼附-第二晶片在該第一晶片之該背面上，係將該第二晶片之一主動面 上且將該第—晶片之—背面經由該黏著層固接在該第—晶片之該 上； 形成複數條第-導線以電性連接該第一晶片之該主動面及該基板 背面； _ 形成複數條第二導線以連接該第二晶片之該絲面及該基板之該 正面； 、該黏著層、該些第一導線及該 形成一第一封裝體用以包覆該第一晶片 基板之該背面； 形成-第二封裝體用以包覆該第二晶片、該黏著層、該第一晶片之部份 。背面、該些第二導線及該基板之部份該正面；及 22 l ^成複軸導電元件’係將該些導電元件形成在該基板之該正面上。 申明專利麵第2丨項所述之方法，其t該基板選自於單層電路板、多層 電路板及金屬薄板所組成之族群中。 18 201005898 23. 如申請專利範圍第21項所述之 大小不同。 ，、尹該第一晶片及該第二晶片之尺寸 24. 如申請專利範圍第21項所述之方 黏著臈(die attach film)。 、點者層為環氧樹脂(印oxy)或晶粒 25. 如申請專利範圍第21項所述之方法，苴 26 ”中該些導電元件為锡球(solderball)。 26. 如申凊專利範圍第μ項所述 法其中該些導電元件為凸塊(bump)。And the back surface of the first wafer is attached to a portion of the back surface of the substrate by an adhesive layer and the adhesive layer covers a surface of the opening; the second wafer has an active surface and a back surface. Wherein the active surface of the second wafer faces upward, and the back surface of the second wafer is disposed on the back surface of the first wafer by the adhesive layer; the plurality of first conductors are electrically connected to the first a plurality of second wires ' electrically connected to the active surface of the second wafer and the front surface of the substrate; and a first package to cover the active surface of the substrate and the back surface of the substrate a first wafer, the adhesive layer, the first conductive wires and the back surface of the germanium substrate; a first package H'剌 to cover the second wafer, a portion of the adhesive layer, the second conductive wires and the substrate a portion of the front surface; and a plurality of conductive elements disposed on the front surface of the substrate. 9. The die stack structure of claim 8, wherein the substrate is selected from the group consisting of a single layer circuit board, a multilayer circuit board, and a metal sheet. The die stack structure of claim 8, wherein the first wafer and the second wafer are different in size. U. The die stack structure of claim 8, wherein the adhesive layer is _ or a die 16 201005898 * die attach film. 12. The die stack structure of claim 8, wherein (4) the conductive elements are solder balls, and the die stack structure according to claim 8 wherein the The conductive element is a bump. 14. A method of forming a die stack structure, comprising: providing a substrate having a front side and a back side and respectively configured with a line layout and having the opening and the front surface of the substrate a first wafer on a portion of the back surface of the substrate, the active side of the first wafer is facing downward; the first wafer-back side is attached to the first adhesive layer a portion of the substrate on the back surface and exposing the back surface of the first wafer not covered by the first adhesive layer; attaching a second wafer on the back surface of the first wafer One of the second wafers is actively facing up; the back side of the second wafer is attached to the back surface of the first wafer not covered by the first adhesive layer by a second adhesive layer; - a wire electrically connecting the active surface of the first wafer and the Forming a plurality of second wires to electrically connect the active surface of the second wafer and the front surface of the substrate; forming a first package for covering the first wafer and the first adhesive layer The first wire and the back surface of the substrate; forming a second package 包覆 for covering the second wafer, the second adhesive layer, the back surface of the first wafer, the second wires, and the a portion of the substrate is the front side; and a plurality of sheets are formed to read the front surface of the conductive element shaped wire board. 1S - The method of claim 14, wherein the substrate is selected from the group consisting of a single layer circuit board, a multilayer circuit board, and a metal sheet. 16. The method of claim 14, wherein the first wafer and the second wafer have different sizes 17 201005898. 17. The method of claim 14, wherein the first adhesive layer is a two-stage thermosetting adhesive (B-stage), and the method of claim 14, wherein The second adhesive layer is an epoxy resin (ep〇xy) or a die attach film (〇), such as a method of applying a light conductive element (4) Wan. The method of claim 14, wherein the conductive element is a convex and handsome kidney. 21) A method of forming a die stack structure, comprising: e providing a substrate having a front side and a back side and having a line layout, and having an opening extending through the front side and the back side of the substrate; The first wafer is on the back surface of the substrate, and the first wafer is actively surfaced. The first wafer-back surface is attached to the back surface of the substrate by an adhesive layer; a second wafer on the back surface of the first wafer, the active surface of the second wafer and the back surface of the first wafer are fixed on the first wafer via the adhesive layer; The strip-wire is electrically connected to the active surface of the first wafer and the back surface of the substrate; _ forming a plurality of second wires to connect the surface of the second wafer and the front surface of the substrate; the adhesive layer, The first wires and the first package are formed to cover the back surface of the first wafer substrate; the second package is formed to cover the second wafer, the adhesive layer, and the first wafer Part. The back surface, the second wires and a portion of the substrate are front faces; and 22 l ^ is a multi-axis conductive member' which is formed on the front surface of the substrate. The method of claim 2, wherein the substrate is selected from the group consisting of a single-layer circuit board, a multi-layer circuit board, and a metal thin plate. 18 201005898 23. The sizes described in item 21 of the patent application range are different. , Yin, the size of the first wafer and the second wafer 24. The die attach film as described in claim 21 of the patent application. The point layer is an epoxy resin (printed oxy) or a crystal grain. 25. The method according to claim 21, wherein the conductive elements are solder balls. The method of item [51] wherein the conductive elements are bumps. ❹❹
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