TW201003867A - Wire bonding structure and method for bonding a wire - Google Patents

Wire bonding structure and method for bonding a wire Download PDF

Info

Publication number
TW201003867A
TW201003867A TW097144458A TW97144458A TW201003867A TW 201003867 A TW201003867 A TW 201003867A TW 097144458 A TW097144458 A TW 097144458A TW 97144458 A TW97144458 A TW 97144458A TW 201003867 A TW201003867 A TW 201003867A
Authority
TW
Taiwan
Prior art keywords
metal
wire bonding
metal pad
wire
pad
Prior art date
Application number
TW097144458A
Other languages
Chinese (zh)
Other versions
TWI372452B (en
Inventor
Chang-Ying Hung
Hsiao-Chuan Chang
Tsung-Yueh Tsai
Yi-Shao Lai
Jian-Cheng Chen
Wei-Chi Yih
Ho-Ming Tong
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to US12/501,693 priority Critical patent/US8076786B2/en
Publication of TW201003867A publication Critical patent/TW201003867A/en
Application granted granted Critical
Publication of TWI372452B publication Critical patent/TWI372452B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

Description

201003867 τ、發明說明： 【發明所屬之技術領域】 本發明係有關於一種銲線接合結構及方法，更 特別有關於-種銲線接合結構，藉由重新分配層之 設計，選用合適的新金屬接墊之特性取代原金屬 接墊之特性。 【先前技術】 參考第1 ® ’在半導體封裝構造製程中，録線 接合方法的技術廣泛地將銲線14應用於晶片10之 接塾11與基板12之接墊13間的電性連接。打線接 合製程是以金“主，但銅線具有低成本的優勢。 相較於金，銅具有較佳的導電性及導熱性，可使銅 製銲線之線徑較細及散熱效率較佳。然而，銅具有 延性不足及易氧化的缺點，使銅製銲線在應用上仍 有所限制。 目前，銅製銲線只能應用在大尺寸之晶片接墊 或低介電值材料（l〇w_K)晶圓之晶片接塾，其原因在 於銅製料接合製程之成功將取決於晶片接塾之結 構強度。為了避免銅製銲線接合製程之失敗，小尺 寸晶片接墊將被限制。 參考第2至4圖’其顯示習知銅製銲線接合方 參考第2圖，藉由-打線機，提供一銅製銲線 ，其包含一銅線22及一銅球24。該銅球以是利 201003867 用放電的方法或氫焰燒結成球而連接於該銅線22 之端。參考第3圖，將該銅球24施壓而變形。參 考第4圖’藉由一振動製程，將該銅球以接合於一 銘製接塾32'然而，在施壓製程時，由於銅之硬度 較大’因此施壓時該銅製銲線2G所造成之力將可能 損壞該IS製接墊3 2之結構。 ( 重新刀配層（Redistribution Layer ; RDL)主要 是應用於晶圓級晶片尺寸封裳構造（Wafer Level cmP scale Package; WLCSp)之錫球接合製程或覆晶 之凸塊接合製程。缺而，舌如_八π β .^ …、而重新刀配層並未應用於銲 線接合製程。 ^ 更百萬要提供一種銲線接合結構 'J, 、1、 一 法，能夠解決前述的問題 【發明内容】 本發明提供一種銲線接合 及-銲線。該晶片包含：：、、，“冓其包含-晶> 墊、-重新八㈣ 基材、至少-第-金屬為 金屬接墊配置於哕“屬接墊。該第一 -端及該重❹配層具有一第 接塾。”：：屬Γ第一端電性連接於該第-金屬 弟-知。該銲線接合於該第二金屬接塾。^ =本：明之銲線接合結構，藉 曰之…選用合適的新金屬接塾之特性取 201003867 金屬接墊之特性。由於藉由重新分配層之設計， 该第二金屬接墊可選用硬度大於該第一金屬接墊 (諸如鋁製接墊）之硬度的材質（諸如銅），因此在銲 線接合方法之施壓製程時，該銲線（諸如銅製銲線） 所造成之力將不會損壞該第一金屬接墊（諸如鋁 製接墊）之結構。再者，該第二金屬接墊可選用較 容易與該銲線（諸如銅製銲線）接合之材質（諸如201003867 τ, invention description: [Technical field of the invention] The present invention relates to a wire bonding structure and method, and more particularly to a wire bonding structure, by selecting a suitable new metal by designing a redistribution layer The characteristics of the pads replace the characteristics of the original metal pads. [Prior Art] Referring to the 1st '' in the semiconductor package structure process, the technique of the line bonding method widely applies the bonding wire 14 to the electrical connection between the interface 11 of the wafer 10 and the pad 13 of the substrate 12. The wire bonding process is based on gold, but the copper wire has the advantage of low cost. Compared with gold, copper has better conductivity and thermal conductivity, which makes the wire diameter of copper wire and the heat dissipation efficiency better. However, copper has the disadvantages of insufficient ductility and easy oxidation, which makes the copper bonding wire still limited in application. At present, copper bonding wire can only be applied to large-sized wafer pads or low dielectric materials (l〇w_K). Wafer wafer bonding is due to the fact that the success of the copper bonding process will depend on the structural strength of the wafer contacts. To avoid the failure of the copper bonding process, small die pads will be limited. References 2 to 4 Figure 2 shows a conventional copper wire bonding party. Referring to Figure 2, a copper wire is provided by a wire bonding machine, which comprises a copper wire 22 and a copper ball 24. The copper ball is discharged by 201003867. The method or hydrogen flame is sintered into a ball and connected to the end of the copper wire 22. Referring to Fig. 3, the copper ball 24 is pressed and deformed. Referring to Figure 4, the copper ball is bonded by a vibration process. A Ming dynasty 32', however, during the pressing process, Since the hardness of copper is large, the force caused by the copper bonding wire 2G at the time of pressing may damage the structure of the IS pad 32. (Redistribution layer (RDL) is mainly applied to the wafer. The wafer bonding process of Wafer Level cmP scale Package (WLCSp) or the bump bonding process of flip chip. In the absence of the tongue, the tongue is like _8πβ.^, and the re-mating layer is not applied. In the wire bonding process. ^ Millions to provide a wire bonding structure 'J, 1, 1, a method that can solve the aforementioned problems. [Invention] The present invention provides a wire bonding and bonding wire. ::,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Having a first connection.":: The first end of the Γ is electrically connected to the first metal - -. The wire is bonded to the second metal 塾. ^ = Ben: Ming wire bonding structure, by The characteristics of the new metal joints are selected to take the characteristics of the 201003867 metal pads. By the design of the redistribution layer, the second metal pad can be made of a material having a hardness greater than the hardness of the first metal pad (such as an aluminum pad), such as copper, so that during the bonding process of the wire bonding method The force caused by the bonding wire (such as a copper bonding wire) will not damage the structure of the first metal pad (such as an aluminum pad). Furthermore, the second metal pad can be easily used with the soldering. a material that is joined by a wire (such as a copper wire) (such as

銅）’用以增加兩者之間的接合力。另外，藉由重 新分配層之設計，該第二金屬接墊可設計成其尺 寸大於忒第一金屬接墊之尺寸，如此可提供較大 的結合面積’用以增加兩者之間的接合力。另外， 藉由重新分配層之設計，該複數個第二金屬接塾 可沿該第二排列方向（諸如非直線方向）排列，如此 可使該些第二金屬接塾之間具有微間距，用以增 加輸入/輸出接點。 讓本么月之上述和其他目的、特徵、和優 點能更明顯，下文將阶人& 又將配合所附圖示，作詳細說明如 下。 【實施方式】 、貝不本發明之一實施例之銲線 接合結構100。該銲绫技 接合結構10〇包含一晶片110 及 知線1 2 0。該日μ Ί 览〇亥曰日片包含一基材U4、至少 一第一金屬接墊137 , 32、一保護層112、一第一介質 5 201003867 層 116、一重新分配層 134(RedistributionLayer; RDL·)、至少一第二金屬接整I%及一第二介質層 H8。該基材114可為矽基材。該第一金屬接墊132 配置於該基材114上。該保護層112(諸如氮化物） 覆蓋該第一金屬接墊132及該基材114,並裸露出 一部分之該第一金屬接墊132,藉此使該第一金屬 接塾132具有一裸露面積A1。該第一介質層116, 諸如苯環丁烯（Benzocyclobutene ; BCB)覆蓋該保 a蒦層112,並裸露出該第一金屬接整132之裸露面 積A1。該重新分配層134配置於該第一介質層116 上’且該重新分配層134之第一端133電性連接 於該第一金屬接墊132之裸露面積A1。該重新分 配層134可為一金屬線路層，諸如凸塊下金屬層 (UBM)。該第二金屬接墊ι36電性連接於該重新 分配層134之第二端135。該第二介質層ι18，諸 如苯環丁烯（Benzocyclobutene ; BCB)覆蓋該第一 介質層116、重新分配層134及第二金屬接墊 136 ’並裸露出一部分之該第二金屬接墊136，藉 此使戎第一金屬接墊13 6具有一裸露面積A2。該 銲線120接合於該第二金屬接墊136之裸露面積 A2 ’如此以形成本發明之銲線接合結構。 在本實施例中，該銲線12〇可為非金所製， 諸如銅製銲線，且該銅製銲線之硬度大於金之硬 度。藉由重新分配層之設計，該第二金屬接墊i36 201003867 可選用硬度大於該第一金屬接墊132之硬度的材 貝或疋較谷易與該銲線12 0接合之材質。舉例而 言，若該第一金屬接墊132為鋁所製，且該銲線 120為銅製銲線，則該第二金屬接墊136可選用銅 所製，如此可得到硬度大於鋁製接墊或是較容易 與銅製銲線接合之銅製接墊。 參考第ό圖’在本實施例中，藉由重新分配層 之設計，該第二金屬接墊13 6可設計成其尺寸大 於該第一金屬接墊132之尺寸，亦即該第二金屬 接墊136之裸露面積大於該第一金屬接墊132之 裸露面積，如此可提供較大的結合面積。該第二 金屬接墊136可視需求而設計成矩形、圓形或八 角形等。 / 參考第7圖，在另一實施例中，該第_金屬接 墊132為複數個，其沿一第一排列方向（諸如直線 方向）排列。藉由重新分配層之設計，該第二金屬 接墊136亦為複數個，可沿一第二排列方向（諸如 非直線方向）排列，如此可使該些第二金屬接塾 136之間具有微間距（fine pitch)。 根據本發明之銲線接合結構，藉由重新分配 層之設計’選用合適的新金屬接墊之特性取代原 孟屬接墊之特性。諸如，由於藉由重新分配層之 設計’該第二金屬接墊可選用硬度大於該第一金 7 201003867 屬接墊（諸如鋁製接墊）之硬度的材質（諸如銅），因 此在婷線接合方法之施壓製程時，該焊線（諸如銅 製銲線）所造成之力將不會損壞該第一金屬接墊 (諸如鋁製接墊）之結構。再者，該第二金屬接墊可 選用較容易與該銲線（諸如銅製銲線）接合之材質 (諸如銅）’用以增加兩者之間的接合力。另外，藉 由重新分配層之設計’該第二金屬接墊可設計成 其尺寸大於a亥苐一金屬接塾之尺寸，如此可提供 較大的結合面積’用以增加兩者之間的接合力。 另外’藉由重新分配層之設計，該複數個第二金 屬接墊可沿该第二排列方向（諸如非直線方向）排 列，如此可使該些第二金屬接墊之間具有微間 距，用以增加輸入/輸出接點。 再參考第5圖，該基材114具有一表面ιι3， 其定義有一元件區142及一非元件區146。該第一 金屬接墊132位於該元件區142，並電性連接於該 元件區142之線路。藉由重新分配層丨之設計， 該第二金屬接墊136可設計成位於非元件區 146。由於該第二金屬料136位於該非元件區 146,因此在銲線接合方法之施壓製程時， 12〇(諸如銅製銲線)所造成之力將集中在該;;元件 區146，而不會損壞該元件區142之線路。 參考第8至㈣，其顯示本發明之—實施例之 201003867 于線接口方法。參考第8圖，提供一晶片110，其 3 ^ V第一金屬接墊132、一重新分配層134 及j少一第二金屬接墊136，該重新分配層134且 U3及—第二端135 ’該第一端133電 ’、接於該第一金屬接墊132 ’且該第二金屬接墊 36電性連接於該重新分配層134之第二端m。 =考第9圖’藉由一打線機1〇2，提供一鮮線 12〇 (啫如銅製銲線），其包含一線狀部122及一 ”24’其中該塊狀部124連接於該線狀部122之 一端’且該塊狀部124之剖面面積大於該線狀部122 面面積。該塊狀部124可為球形。舉例而言，Copper) is used to increase the bonding force between the two. In addition, by designing the redistribution layer, the second metal pad can be designed to have a size larger than the size of the first metal pad, so that a larger bonding area can be provided to increase the bonding force between the two. . In addition, by designing the redistribution layer, the plurality of second metal interfaces may be arranged along the second alignment direction (such as a non-linear direction), so that the second metal interfaces may have a fine pitch between the second metal interfaces. To increase the input / output contacts. The above and other purposes, features, and advantages of this month will be more apparent. The following will be explained in detail below with the accompanying drawings. [Embodiment] A wire bonding structure 100 according to an embodiment of the present invention. The solder joint structure 10A includes a wafer 110 and a line 120. The μ 曰 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材 基材·), at least one second metal is aligned with 1% and a second dielectric layer H8. The substrate 114 can be a tantalum substrate. The first metal pad 132 is disposed on the substrate 114. The protective layer 112 (such as nitride) covers the first metal pad 132 and the substrate 114, and exposes a portion of the first metal pad 132, thereby providing the first metal interface 132 with a bare area. A1. The first dielectric layer 116, such as Benzocyclobutene (BCB), covers the barrier layer 112 and exposes the exposed area A1 of the first metal junction 132. The redistribution layer 134 is disposed on the first dielectric layer 116 and the first end 133 of the redistribution layer 134 is electrically connected to the exposed area A1 of the first metal pad 132. The redistribution layer 134 can be a metal wiring layer such as a sub-bump metal layer (UBM). The second metal pad ι36 is electrically connected to the second end 135 of the redistribution layer 134. The second dielectric layer ι18, such as Benzocyclobutene (BCB), covers the first dielectric layer 116, the redistribution layer 134, and the second metal pad 136' and exposes a portion of the second metal pad 136. Thereby, the first metal pad 13 6 has a bare area A2. The bonding wire 120 is bonded to the exposed area A2' of the second metal pad 136 to form the wire bonding structure of the present invention. In the present embodiment, the bonding wire 12A may be made of non-gold, such as a copper bonding wire, and the hardness of the copper bonding wire is greater than the hardness of the gold. By the design of the redistribution layer, the second metal pad i36 201003867 may be made of a material having a hardness greater than the hardness of the first metal pad 132 or a material which is bonded to the bonding wire 120. For example, if the first metal pad 132 is made of aluminum, and the bonding wire 120 is a copper bonding wire, the second metal pad 136 can be made of copper, so that the hardness is greater than that of the aluminum pad. Or a copper pad that is easier to bond to a copper wire bond. Referring to FIG. 2, in the embodiment, the second metal pad 13 6 can be designed to have a size larger than the size of the first metal pad 132, that is, the second metal connection. The exposed area of the pad 136 is greater than the exposed area of the first metal pad 132, which provides a larger bonding area. The second metal pad 136 can be designed to be rectangular, circular or octagonal, etc., as desired. Referring to Fig. 7, in another embodiment, the first metal pad 132 is plural and arranged in a first alignment direction (such as a linear direction). By the design of the redistribution layer, the second metal pads 136 are also plural, and can be arranged along a second alignment direction (such as a non-linear direction), so that the second metal interfaces 136 can have a micro between Fine pitch. According to the wire bonding structure of the present invention, the characteristics of the original Meng mat are replaced by the design of the redistribution layer by selecting the characteristics of a suitable new metal pad. For example, due to the design of the redistribution layer, the second metal pad can be made of a material having a hardness greater than that of the first gold 7 201003867 pedestal (such as an aluminum pad), such as copper. When the bonding method is applied, the force caused by the bonding wire (such as a copper bonding wire) will not damage the structure of the first metal pad (such as an aluminum pad). Furthermore, the second metal pad can be made of a material (such as copper) that is easier to bond with the wire (such as a copper wire) to increase the bonding force between the two. In addition, by designing the redistribution layer, the second metal pad can be designed to have a size larger than the size of a metal joint, so that a larger bonding area can be provided to increase the joint between the two. force. In addition, by the design of the redistribution layer, the plurality of second metal pads can be arranged along the second alignment direction (such as a non-linear direction), so that the second metal pads can have a fine pitch between them. To increase the input / output contacts. Referring again to FIG. 5, the substrate 114 has a surface ι3 defining an element region 142 and a non-element region 146. The first metal pad 132 is located in the component region 142 and electrically connected to the circuit region 142. The second metal pad 136 can be designed to be located in the non-element region 146 by redistributing the design of the layer. Since the second metal material 136 is located in the non-element region 146, the force caused by 12 〇 (such as a copper bonding wire) will be concentrated in the pressing process of the wire bonding method; the component region 146 will not The line of the component area 142 is damaged. Referring to Figures 8 through (4), there is shown a line interface method of the 201003867 of the present invention. Referring to FIG. 8, a wafer 110 is provided having a 3^V first metal pad 132, a redistribution layer 134 and a second second metal pad 136, the redistribution layer 134 and the U3 and the second end 135. The first end 133 is electrically connected to the first metal pad 132 ′ and the second metal pad 36 is electrically connected to the second end m of the redistribution layer 134 . = test Fig. 9 'by a wire machine 1〇2, providing a fresh wire 12〇 (such as a copper wire) comprising a linear portion 122 and a "24", wherein the block portion 124 is connected to the wire One end of the portion 122' and the cross-sectional area of the block portion 124 is larger than the surface area of the linear portion 122. The block portion 124 may be spherical. For example,

Si部124是利用放電的方法或氫焰燒結成球而 連接於該線狀部122之一端。參考第lQw __ =製程’將該塊狀部124接觸於該接墊i32，並 1而變形。參考第11圖，藉由-振動製程，將今 ::12〇之塊狀部124接合於該第二金屬接塾‘ 如此以形成本發明之銲線接合方法。 雖然本發明已以前述實施例揭示，缺 :定本發明，任何本發明所屬技術領； 2識者，在不脫離本㈣之精神和範_ :當可 乍各種之更動與修改。因此本發明之保 後附之申請專㈣®所敎者為準。、 田？ 【圖式簡單說明】 201003867 第1圖為先前技術之銲線接合方法之剖面示意 圖。 第2至4圖為先前技術之銅製銲線接合方法之 剖面示意圖。 第5圖為本發明之一實施例之銲線接合結構之 剖面示意圖。 第6圖為本發明之該實施例之銲線接合結構之 第一及第二金屬接墊之平面示意圖。 第7圖為本發明之另一實施例之銲線接合結構 之第一及第二金屬接墊之平面示意圖。 第8至11圖為本發明之一實施例之銲線接合方 法之剖面示意圖。 11 接墊 13 接塾 22 銅線 32 接墊 102 打線機 112 保護層 114 基材 118 介質層 122 線狀部 132 金屬接墊 134 重新分配層 136 金屬接墊 146 非元件區 【主要元件符號說明 1〇 晶片 12 基板 14 銲線 2〇 銲線 24 銅球 10〇銲線接合結構 u〇晶片 113表面 116介質層 120銲線 124塊狀部 133端 135端 142元件區 201003867 A1 面積 A2 面積 11The Si portion 124 is connected to one end of the linear portion 122 by a method of discharging or a hydrogen flame sintering into a ball. The block portion 124 is brought into contact with the pad i32 with reference to the lQw __ = process, and is deformed by 1. Referring to Fig. 11, the block portion 124 of the present invention is bonded to the second metal joint by the -vibration process to form the wire bonding method of the present invention. The present invention has been disclosed in the foregoing embodiments, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the application of the invention (4) is subject to the provisions of the application. , Tian? [Simple description of the drawings] 201003867 Fig. 1 is a schematic cross-sectional view showing a prior art wire bonding method. Figures 2 through 4 are schematic cross-sectional views of prior art copper wire bonding methods. Fig. 5 is a schematic cross-sectional view showing a wire bonding structure according to an embodiment of the present invention. Fig. 6 is a plan view showing the first and second metal pads of the wire bonding structure of the embodiment of the present invention. Figure 7 is a plan view showing the first and second metal pads of the wire bonding structure according to another embodiment of the present invention. 8 to 11 are schematic cross-sectional views showing a bonding method of a bonding wire according to an embodiment of the present invention. 11 Pad 13 Connector 22 Copper wire 32 Pad 102 Wire machine 112 Protective layer 114 Substrate 118 Dielectric layer 122 Linear portion 132 Metal pad 134 Redistribution layer 136 Metal pad 146 Non-component area [Main component symbol description 1 〇 wafer 12 substrate 14 bonding wire 2 〇 bonding wire 24 copper ball 10 〇 wire bonding structure u 〇 wafer 113 surface 116 dielectric layer 120 bonding wire 124 block 133 end 135 end 142 component area 201003867 A1 area A2 area 11

Claims (1)

201003867 七、申請專利範圍： 1. 銲線接合結構，包含： 一晶片，包含： 一基材； 至少一第一金屬接塾，配置於該基材上； 一重新分配層（Redistribution Layer ; RDL)， 具有一第一端及一第二端，該第一端電性連接 於該第一金屬接墊；以及 至少一第二金屬接墊，電性連接於該重新分配 層之第二端；以及 一銲·線，接合於該第二金屬接塾。 2. 依申請專利範圍第1項之銲線接合結構，其中該 晶片，另包含： 一保護層，覆蓋該第一金屬接墊及該基材，並 裸露出一部分之該第一金屬接整，藉此使該第一 金屬接墊具有一裸露面積； 一第一介質層，覆蓋該保護層，並裸露出該第 一金屬接墊之裸露面積，其中該重新分配層配置 於該第一介質層上，且該重新分配層之第一端電 性連接於該第一金屬接墊之裸露面積；以及 一第二介質層，覆蓋該第一介質層、重新分配 層及第二金屬接墊，並裸露出一部分之該第二金 12 201003867 屬接墊，藉此使該第二金屬接墊具有一裸露面 積，其中該銲線接合於該第二金屬接墊之裸露面 積。 3. 依申請專利範圍第2項之銲線接合結構，其中該 第二金屬接墊之裸露面積大於該第一金屬接墊之 裸露面積。 4. 依申請專利範圍第1項之銲線接合結構，其中該 苐一金屬接塾之尺寸不同於該第一金屬接塾之尺 寸。 5. 依申請專利範圍第4項之銲線接合結構，其中該 第二金屬接墊之尺寸大於該第一金屬接塾之尺 寸。 6. 依申請專利範圍第1項之銲線接合結構，其中該 基材具有一表面’其定義有一元件區及一非元件 區，且該第一及第二金屬接墊分別位於該元件區 及非元件區。 °° 7. 依申請專利範圍第丨項之銲線接合結構，其中該 第二金屬接墊之硬度大於該第—金屬接墊之^ 度。 文 8. 依申請專利範圍》7項之銲線接合結構，其 第一金屬接墊為鋁所製。 μ 9·依申請專利範圍帛1項之銲線接合結構，其中該 13 201003867 第二金屬接墊為銅所製。 10·▲依申請專利範圍帛丨項之銲線接合結構，其中 該銲線為非金所製。 n.依申請專利範圍第10項之銲線接合結構，其中 該銲線之硬度大於金之硬度。 12\依申請專利範圍第u項之銲線接合結構，其 該銲線為銅所製。 13. 依申請專利範圍帛i項之鲜線接合結構，其中 該晶片包含複數個第一及第二金屬接墊，該些第 一金屬接墊沿一第一排列方向排列，該些第二仑 屬接塾沿一第二排列方向排列，且該第二排 向不同於該第一排列方向。 14. 依申請專利範圍第13項之銲線接 I 該第一排列方向Α α H 丹^中 併幻万向為一直線方向，且該第二 向為非直線方向。 J方 15二依申請專利範圍第i項之銲線接合結構 5亥重新分配層為一金屬線路層。 、 16二依申請專利範圍帛15J員之銲線接合結構 4重新分配層為—凸塊下金屬層（UBM)。 1 7.種銲線接合方法，包含下列步驟： 提供一晶片，其包含至少一第一金屬接墊、一 重新分配層及至少一第二金屬接墊，該重靳： 14 201003867 配層具有一第一端及一第二端，該第一端電性 連接於該第一金屬接墊，且該第二金屬接墊， 電性連接於該重新分配層之第二端；以及 一銲線接合於該第二金屬接墊。 18. ^申請專利範圍第17項之銲線接合方法，其中 該第二金屬#墊之尺寸不同於該第一金屬接塾之 尺寸。 19.1依申請專利範圍第18項之銲線接合方法，其令 該第二金屬接墊之尺寸大於該第一金屬接墊^尺 寸。 2〇.依申請專利範圍第17項之銲線接合方法，其中 該基材具有一表面，其定義有一元件區及一#元 件區且4第-及第二金屬接塾分別位於該元件 區及非元件區。 21.依申請專利範圍第17項之銲線接合方法，其中 f第二金屬接墊之硬度大於該第—金屬接墊之硬 22. 該 第依二項…接合方法，其中 23. 依申請專利範圍第 該第二金屬接墊為鋼 24. 依申請專利範圍第 22項之銲線接合方法，其中 所製。 17項之銲線接合方法，其中 15 201003867 丨玄銲線為非金所製。 25. 依申請專利範圍第24項之銲線接合方法，其中 該銲線之硬度大於金之硬度。 26·依申請專利範圍第25項之銲線接合方法，其中 該銲線為銅所製。 27>依申請專利範圍第Π項之銲線接合方法，其中 =晶片包含複數個第一及第二金屬接墊，該些第 五屬接墊沿—第一排列方向排列，該些第二八 屬接塾/口 -第二排列方向排列，且該第 向不同於該第—排列方向。 方 28·該項之銲線接合方法，其中 向為非直線方向為一直線方向，且該第二排列方 K 16201003867 VII. Patent application scope: 1. Wire bonding structure, comprising: a wafer comprising: a substrate; at least one first metal joint disposed on the substrate; a redistribution layer (RDL) a first end and a second end, the first end is electrically connected to the first metal pad; and the at least one second metal pad is electrically connected to the second end of the redistribution layer; A solder wire is bonded to the second metal joint. 2. The wire bonding structure according to claim 1, wherein the wafer further comprises: a protective layer covering the first metal pad and the substrate, and exposing a portion of the first metal to be aligned, Thereby, the first metal pad has a bare area; a first dielectric layer covering the protective layer and exposing the exposed area of the first metal pad, wherein the redistribution layer is disposed on the first dielectric layer And the first end of the redistribution layer is electrically connected to the exposed area of the first metal pad; and a second dielectric layer covering the first dielectric layer, the redistribution layer and the second metal pad, and A portion of the second gold 12 201003867 is exposed to the pad, whereby the second metal pad has a bare area, wherein the bonding wire is bonded to the exposed area of the second metal pad. 3. The wire bonding structure according to claim 2, wherein the exposed area of the second metal pad is larger than the exposed area of the first metal pad. 4. The wire bonding structure according to item 1 of the patent application, wherein the size of the first metal joint is different from the size of the first metal joint. 5. The wire bonding structure of claim 4, wherein the second metal pad has a size greater than a dimension of the first metal interface. 6. The wire bonding structure according to claim 1, wherein the substrate has a surface defining an element region and a non-element region, and the first and second metal pads are respectively located in the component region and Non-component area. The bonding wire bonding structure according to the scope of the patent application, wherein the hardness of the second metal pad is greater than the hardness of the first metal pad. Article 8. According to the wire bonding structure of the 7th patent application scope, the first metal pad is made of aluminum. μ 9· The wire bonding structure according to the patent application scope ,1, wherein the 13 201003867 second metal pad is made of copper. 10·▲The wire bonding structure according to the scope of application for patents, wherein the wire is made of non-gold. n. The wire bonding structure according to item 10 of the patent application scope, wherein the hardness of the bonding wire is greater than the hardness of the gold. 12\ The wire bonding structure according to item u of the patent application scope, the wire is made of copper. 13. The fresh wire bonding structure according to the patent application scope, wherein the wafer comprises a plurality of first and second metal pads, the first metal pads are arranged along a first alignment direction, and the second The genus is arranged along a second alignment direction, and the second directional direction is different from the first alignment direction. 14. According to the welding wire of item 13 of the patent application scope, the first alignment direction Α α H 丹 ^ is in the direction of the straight line, and the second direction is a non-linear direction. J-Fellow 15 2 According to the wire bonding structure of the i-th patent application scope 5 The redistribution layer is a metal circuit layer. 16 2 According to the scope of application for patents 焊 15J members of the wire bonding structure 4 redistribution layer is - under the bump metal layer (UBM). 1 7. A wire bonding method comprising the steps of: providing a wafer comprising at least a first metal pad, a redistribution layer and at least one second metal pad, the overlay: 14 201003867 layer having a a first end and a second end, the first end is electrically connected to the first metal pad, and the second metal pad is electrically connected to the second end of the redistribution layer; and a wire bonding And the second metal pad. 18. The wire bonding method of claim 17, wherein the size of the second metal #pad is different from the size of the first metal joint. 19.1 The wire bonding method according to claim 18, wherein the second metal pad is larger in size than the first metal pad. 2. The wire bonding method according to claim 17, wherein the substrate has a surface defining an element region and an # component region, and wherein the fourth and second metal interfaces are respectively located in the component region and Non-component area. 21. The wire bonding method according to claim 17, wherein the hardness of the second metal pad is greater than the hardness of the first metal pad. The second method is a bonding method, wherein the patent is applied for. The second metal pad of the range is steel 24. The wire bonding method according to claim 22 of the patent application, which is made. 17 wire bonding methods, of which 15 201003867 丨 焊 wire is made of non-gold. 25. The wire bonding method according to claim 24, wherein the wire has a hardness greater than a hardness of the gold. 26. The wire bonding method according to item 25 of the patent application scope, wherein the bonding wire is made of copper. The wire bonding method of the invention of claim 2, wherein the = chip comprises a plurality of first and second metal pads, and the fifth sub-pads are arranged along the first array direction, the second eight The genus/port-the second array direction is arranged, and the first direction is different from the first-arrangement direction. [28] The wire bonding method of the item, wherein the direction of the non-linear direction is a straight line direction, and the second array side K 16
TW097144458A 2008-07-11 2008-11-18 Wire bonding structure and method for bonding a wire TWI372452B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/501,693 US8076786B2 (en) 2008-07-11 2009-07-13 Semiconductor package and method for packaging a semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US7981108P 2008-07-11 2008-07-11

Publications (2)

Publication Number Publication Date
TW201003867A true TW201003867A (en) 2010-01-16
TWI372452B TWI372452B (en) 2012-09-11

Family

ID=41521774

Family Applications (3)

Application Number Title Priority Date Filing Date
TW097142458A TWI436465B (en) 2008-07-11 2008-11-04 Wire bonding structure, method for bonding a wire and method for manufacturing a semiconductor package
TW097142797A TWI385740B (en) 2008-07-11 2008-11-06 Wire bonding structure, method for enhancing the bond of a wire, and method for manufacturing a semiconductor package
TW097144458A TWI372452B (en) 2008-07-11 2008-11-18 Wire bonding structure and method for bonding a wire

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW097142458A TWI436465B (en) 2008-07-11 2008-11-04 Wire bonding structure, method for bonding a wire and method for manufacturing a semiconductor package
TW097142797A TWI385740B (en) 2008-07-11 2008-11-06 Wire bonding structure, method for enhancing the bond of a wire, and method for manufacturing a semiconductor package

Country Status (2)

Country Link
CN (1) CN101626003B (en)
TW (3) TWI436465B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112276281B (en) * 2020-10-19 2022-04-26 重庆久坤电子有限公司 Automatic wire bonding machine

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
US6091140A (en) * 1998-10-23 2000-07-18 Texas Instruments Incorporated Thin chip-size integrated circuit package
US20050224959A1 (en) * 2004-04-01 2005-10-13 Chippac, Inc Die with discrete spacers and die spacing method

Also Published As

Publication number Publication date
CN101626003A (en) 2010-01-13
TW201003808A (en) 2010-01-16
TWI385740B (en) 2013-02-11
CN101626003B (en) 2013-11-27
TWI372452B (en) 2012-09-11
TWI436465B (en) 2014-05-01
TW201003869A (en) 2010-01-16

Similar Documents

Publication Publication Date Title
TWI352414B (en) Semiconductor package structure
JP5624649B2 (en) Fusible input / output interconnect system and method for flip chip packaging with stud bumps attached to a substrate
TWI328867B (en) Integrated structure and method for fabricating the same
US9087754B2 (en) Structures and methods for improving solder bump connections in semiconductor devices
US8298947B2 (en) Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
US9129818B2 (en) Semiconductor device having conductive pads and a method of manufacturing the same
TWI286829B (en) Chip package
JP5528072B2 (en) Structure and method for improving solder bump connection in semiconductor devices
TWI343084B (en) Semiconductor device having conductive bumps and fabrication methodthereof
TW201115700A (en) Integrated circuit structure
TW200901345A (en) System and method for increased stand-off height in stud bumping process
TW201113996A (en) Semiconductor device
JP2015502038A (en) Structures and packaged semiconductor devices
US11810892B2 (en) Method of direct bonding semiconductor components
US6396156B1 (en) Flip-chip bonding structure with stress-buffering property and method for making the same
JP5705130B2 (en) Structure and method for improving solder bump connections in semiconductor devices
US8076786B2 (en) Semiconductor package and method for packaging a semiconductor package
KR20090018014A (en) Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates
TW201003867A (en) Wire bonding structure and method for bonding a wire
KR20030040644A (en) Wafer level chip scale package having stud bump and method for fabricating the same
US6827252B2 (en) Bump manufacturing method
TWI323502B (en) Semiconductor device and method for fabricating the same
US20110018135A1 (en) Method of electrically connecting a wire to a pad of an integrated circuit chip and electronic device
KR100311980B1 (en) infrared detector and method for manufacturing the same
US7176580B1 (en) Structures and methods for wire bonding over active, brittle and low K dielectric areas of an IC chip