JP5528072B2 - Structure and method for improving solder bump connection in semiconductor devices - Google Patents

Description

  The present invention relates to integrated circuits, and more particularly to structures using improved solder bump connections and methods of manufacturing such structures.

  Conventionally, high temperature C4 (Controlled Collapse Chip Connection) bumps are used to bond the chip to the substrate. The most common and widely used package is an organic laminate. Generally, C4 bumps (solder bumps) are formed from leaded solder in order to have excellent characteristics. For example, lead is known to reduce thermal coefficient (TCE) mismatch between the chip and the substrate (ie, organic stack). Thus, the C4 bumps reduce the stress applied during the cooling cycle, thereby preventing delamination or other damage to the chip or substrate.

  Currently, there is a requirement for lead-free in many countries, and manufacturers are required to implement new methods for producing chip-substrate junctions. For example, instead of leaded solder interconnects, solder interconnects of tin / copper, tin / silver (high concentration silver), and tin / gold combined with SAC alloys are used. However, the lead-free requirement raises concerns about the shortcomings of C4 interconnect. For example, cracks in chip metallurgy under C4 bumps (named “white bumps” for appearance in the CSAM inspection process) can lead to device damage. More specifically, the white bump is C4 that does not form a good electrical connection to the last metal pad of Cu, which results in failure of the chip in functional tests or in the field. This may be due, at least in part, to exacerbating the C4 / AlCu bump-Cu wire adhesion problem due to chip design using high stress Pb-free C4 (solder bumps).

  As one example, during chip bond reflow, the chip and its substrate are heated to a high temperature (approximately 250 ° C.) to form a solder interconnect bond. There is little increase in stress early in the cooldown. However, as the bond solidifies (about 180 ° C. for small lead-free bonds), an increase in stress is observed on the package. In particular, as the package (laminate, solder and chip) begins to cool, the solder begins to solidify (eg, at about 180 ° C.), the laminate begins to shrink, and the chip remains substantially the same size. Differences in thermal expansion between the chip and the substrate are absorbed by out-of-plane deformation of the device and substrate and by shear deformation of the solder joint. Maximum stress on the device occurs during the reflow cooldown period.

  When the solder is strong and exceeds the force of the chip, the structure on the chip begins to peel off due to the tensile stress. Mismatch between the TCE between the tip (3.5 ppm) and the laminate (16 ppm) causes high shear stress and causes interface failure (ie BEOL copper and dielectrics under C4 (eg FSG) Separation between)). This interface failure is embodied as a crack in the chip metal under the C4 bump. Furthermore, due to inadequate barrier integrity in the overlying films, Sn tends to diffuse from the Pb-free solder bumps through the BLM / capture pad structure into the final metal copper layer. When this happens, the last metal level of copper reacts with Sn to expand its volume and crack.

  Therefore, there is a need in the art to overcome the drawbacks and limitations described above.

  In a first aspect of the invention, a method of manufacturing a semiconductor structure includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of individual trenches in one or more dielectric layers that extend to the upper wiring layer. The method further includes depositing a ball limiting metal or a bump base metal in a plurality of individual trenches to form individual metal islands that contact the upper wiring level. Solder bumps are formed that are electrically connected to a plurality of individual metal islands.

  In a second aspect of the present invention, a method of manufacturing a package includes forming a plurality of individual trenches in one or more dielectric layers extending to an underlying wiring layer and contacting the underlying wiring layer. Depositing metal material in individual trenches to form an island of bump base metal or ball-restricted metal, depositing lead-free solder bumps that are electrically connected to the islands, and joining the laminated structure to the lead-free solder bumps And including.

  In a third aspect of the present invention, the solder bump structure includes a plurality of metal islands of bump base metal or ball limiting metal formed in one or more dielectric layers and in contact with the upper wiring layer in the lower dielectric layer. The solder bump is electrically connected to the metal island.

  By way of non-limiting example of exemplary embodiments of the invention, the invention will be described in the following detailed description with reference to the accompanying drawings.

Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention. Fig. 4 illustrates structure and processing steps according to aspects of the present invention.

  The present invention relates to integrated circuits, and more particularly to structures using improved solder bump connections and methods of manufacturing such structures. More particularly, the present invention provides structures that prevent cracks or delamination from the underlying BEOL vias and associated metal interconnects and / or pads and / or wires, as well as such structures. A method of manufacturing is provided. For example, in practice, the present invention prevents C4 stress from propagating throughout the wiring level. This propagation can lead to catastrophic wiring failures. Preventing this can be accomplished by providing individual metal islands or segments with under bump metallurgy or ball limiting metallurgy. This prevents the device from becoming inoperable due to the entire wiring layer being peeled off due to stress applied during the cooling period.

  The present invention is applicable to all C4 processes, including plating, screening, and physical placement methods such as C4NP (Controlled Collapse Chip Connection New Process). C4NP is a flip chip technology developed by International Business Machines that combines the advantages of 100 percent lead-free, high reliability, narrow pitch, and low material cost with the flexibility to use virtually all types of solder compositions. Is to provide. The processes and structures in the present invention can be used for known and next generations and are particularly applicable to 300 mm wafer technology using C4NP. Thus, the process of the present invention provides advantages for future copper interconnect generations.

Specifically, FIG. 1 shows a starting structure that includes a lower metal layer 12 formed in a dielectric material 10. The lower metal layer 12 can be, for example, a copper material lined with a tantalum nitride diffusion barrier layer. It will be appreciated by those skilled in the art that the metal layer 12 is not limited to copper lined with tantalum nitride, but can be, for example, titanium nitride lined with a conductive metal or other diffusion barrier layer. The dielectric material 10 may be, for example, SiO ₂ .

  A plurality of trenches 14 are formed in the dielectric material 10 and extend to the underlying metal layer 12, for example a wire. The trenches 14 form separate discrete segments that are designed to prevent cracking from affecting the entire metal layer (this would otherwise cause device failure). . The trench 14 can be formed using any conventional lithography and etching process. For example, the formation of trenches 14 can be accomplished by conventional photolithography in which openings are formed using an exposed masking layer, followed by trenches 14 formed in dielectric material 10 by etching (eg, reactive ion etching (RIE)) techniques. Can be processed. This can be a two-step etch process where the trench has two different cross-sectional shapes. Since these are conventional processes, those skilled in the art do not need further detailed description to practice the present invention.

  Trench 14 can range from 1 micron to 10 microns laterally and can be several different shapes and sizes (eg, smaller and larger openings). The trench 14 can include radial or arcuate offset segments that surround several size openings. In embodiments, the trench 14 may include one or more of a lattice pattern, checkerboard pattern, segmented lines, overlapping lines, offset lines, vertical lines, arc segments, or any combination discussed herein. Or a pattern of shapes.

  In an alternative embodiment (FIG. 4), a conventional wiring layer can be formed with multiple trenches 14 as a single trench. The trenches 14 discussed below can be lined with a diffusion barrier layer and filled with copper or other conductive material to form the upper wiring level. In this implementation, the process continues with that of FIG.

  FIG. 2 shows a metal liner 16, such as a diffusion barrier layer, deposited in the trench 14. The metal liner 16 may be a tantalum nitride material, for example. The metal liner 16 is deposited using conventional deposition methods such as physical vapor deposition (PVD), although other deposition techniques such as chemical vapor deposition (CVD) can be used with the present invention. . Chemical mechanical polishing (CMP) can be performed to flatten the surface of the structure of FIG.

  In FIG. 3, a metal material 18 is deposited in the trench 14. The upper wiring level can be formed using the metal material 18. More specifically, the metal material 18 may have a BEOL wiring structure formed in the trench of the dielectric layer 10. By segmenting the copper interconnect 18 (due to the trench configuration) and forming individual islands, the stress on this structure will only peel the outer island and not affect the entire metal layer . This prevents device failure when the structure is stressed. Also, chemical mechanical polishing (CMP) can be performed to flatten the surface of the structure of FIG.

  In the alternative embodiment shown in FIG. 4, a conventional wiring layer can be formed with multiple trenches 14 as a single trench. The trench 14 can be lined with a diffusion barrier layer and filled with copper or other conductive material to form the upper wiring level. In this implementation, the process continues with that of FIG.

In FIG. 5, dielectric layers 20, 22 are deposited on the planarized surface of the structure of FIG. 3 or FIG. In either situation, the dielectric layer 20 can be, for example, SiN. Alternatively, the dielectric layer 20 may have a multilayer structure of SiN, SiO ₂ , and SiN. The dielectric layer 22 can be a photosensitive polyimide or other type of insulating material deposited on the dielectric layer 20. The dielectric layers 20, 22 can be deposited using conventional deposition techniques such as, for example, CVD. In embodiments, the dielectric layers 20, 22 can range in thickness from about 5 to 10 microns in height, although other dimensions are contemplated by the present invention. In the case of photosensitive polyimide, the dielectric layer 22 can be about 5 microns thick.

  Referring to FIG. 6, a patterning step has been performed on the dielectric layers 20, 22 to form a plurality of individual vias 34. The plurality of individual vias 34 can be about 1 micron in width or diameter, depending on their shape, but this dimension is not considered a limiting feature of the present invention. In embodiments, the plurality of vias 34 can range from 1 micron to 10 microns laterally and can be several different shapes and sizes (eg, smaller and larger openings). The plurality of vias 34 may be, for example, radial or arcuate offset segments that surround several size openings. In embodiments, the plurality of vias 34 may be a grid pattern, checkerboard pattern, segmented lines, overlapping lines, offset lines, vertical lines, arc segments, or any combination discussed herein, It can be a pattern of more than one opening or shape.

  In an embodiment, the plurality of individual vias 34 prevents crack formation. This is further described below. The individual vias 34 can be formed by any conventional method, such as exposure and development, and no conventional etching process (eg, RIE) is required for the PSPI layer. Alternatively, vias 34 can be formed using conventional lithography and etching processes. Via 34 is aligned with metal material 18 and extends to metal material 18.

  As shown in FIG. 7, a metal material 36 is deposited on the via 34 in contact with the metal material 18. The metal material 36 may be TaN or TiW, for example. The individual islands created by the individual via metal form part of the ball limiting metal (BLM) or the bump base metal (ULM). In the via 34, the metallic material 36 can be, for example, about 0.55 microns thick (or slightly larger than half the diameter of the via 34). As a result, the metal material 36 extends above the layer 22. On top of the metal material 36, another metal layer 38 is deposited, for example a conductive pad made of Al or copper. In the embodiment, the metal layer 38 is an optional layer. A CrCu or Cu layer 40 can be deposited over the metal layer 38 to form a capture pad. The metal layers 36, 38, 40 can be deposited using conventional deposition techniques such as, for example, CVD.

  In FIG. 8, solder bumps are deposited on the metal layer 40. More specifically, lead-free solder bumps 28 such as tin / copper, tin / silver, and tin / gold combined with a SAC alloy are deposited on the metal layer 40.

  FIG. 9 shows a package chip indicated generally by the reference numeral 50. Package chip 50 shows solder bumps 28 connected to bonding pads 30 of laminate 32. The laminate 32 can be an organic or ceramic laminate. FIG. 9 also illustrates crack initiation and termination in the BLM segment (capture pad 30).

  It will now be appreciated by those skilled in the art that the present invention adds an additional segmentation pattern designed to prevent delamination of the entire wiring layer. This additional segmentation pattern blocks stress at the periphery of the wiring layer, which serves as a termination point for any crack propagation. That is, a peripheral segment or island outside the TaN / TiW layer 36a (in addition to the segment 18a when used in combination with the embodiment shown in FIGS. 1-3) blocks the stress, which is the propagation of cracks. Functions as the end point of In this way, any cracks that occur will stop at a single interconnect and therefore do not propagate along the entire interface between the metal tube (IMC) compound and the solder material in the BLM. This structure is applicable to any two parts that are joined using C4 solder bumps, including any chip stacking or “3D” applications, especially for lead-free C4.

  The method as described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chip is distributed by the manufacturer as a bare die or in package form, in raw wafer form (ie as a single wafer with multiple unpackaged chips). be able to. In the latter case, the chip is either a single chip package (using leads attached to a motherboard or other high level carrier, such as a plastic carrier), or a multichip package (either surface interconnect or embedded interconnect) Or a ceramic carrier using both. In any case, the chip is then integrated with other chips, discrete circuit elements, or other signal processing devices or all of them as either part of (a) an intermediate product such as a motherboard or (b) an end product. To do. The final product can be any product that includes an integrated circuit chip.

  The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, as used herein, the words “comprising”, “comprising”, or both refer to the specified feature, integer, step, action, element, component, or all of them. It will be understood that presence is indicated but does not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, or groups thereof or all of them.

  In the claims, if there is a corresponding structure, material, act, and equivalent of all means or step plus function elements, other specifically claimed It is intended to include any structure, material, or act for performing a function in combination with the claimed element. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments are intended to best explain the principles and practical applications of the invention, and further enable one of ordinary skill in the art to understand the invention in various embodiments along with various modifications suitable for the particular use envisioned. As such, it has been selected and described.

10 Dielectric material 12 Lower metal layer 14 Trench 16 Metal liner 18, 36 Metal material 20, 22 Dielectric layer 28 Solder bump 32 Laminate 34 Individual vias 36, 38, 40 Metal layer 50 Package chip

Claims (19)

A method of manufacturing a semiconductor structure, comprising:
Forming a plurality of individual trenches in the dielectric layer;
Depositing an upper wiring layer material in the plurality of individual trenches to form individual upper wiring layer islands of the upper wiring layer in the dielectric layer ;
Depositing one or more dielectric layers on the individual upper wiring layer islands of the upper wiring layer ;
Forming a plurality of individual vias extending to said upper wiring layer to the one or more dielectric layers,
Forming a discrete metal islands in contact with the upper wiring layer by depositing a ball limiting metallurgy or bump metallurgy on said plurality of individual vias,
Forming a solder bump for electrically connecting to said plurality of discrete metal islands,
Said method. Further comprising the method of claim 1 forming a metal layer between said plurality of discrete metal islands and the solder bumps.   The method of claim 2, wherein the metal layer comprises a capture pad and a conductive pad.   The method of claim 3, wherein the capture pad includes a nickel material deposited over the conductive pad and sandwiched between an upper gold layer and a lower barrier layer.   The method of claim 1, wherein the bump metal or ball limiting metal comprises a refractory metal base layer, a conductive metal intermediate layer, and a diffusion barrier top layer.   The method of claim 1, wherein the solder bump is a lead-free solder bump. Comprising the step of forming the plurality of discrete vias, etching an opening of various sizes and shapes to the one or more dielectric layers, the method according to claim 1.   The method of claim 1, wherein the one or more dielectric layers are two dielectric layers. The individual metal islands in contact with the respective upper wiring layer Island, The method of claim 1. A method of manufacturing a package, comprising:
Forming a plurality of individual trenches in the lower dielectric layer;
Filling the plurality of individual trenches with a conductive material in contact with an underlying metal line to form a metal layer;
Forming a plurality of individual vias in the one or more dielectric layers extending to the plurality of individual trenches filled with the conductive material of the underlying metal line ;
Depositing a metal material on the individual vias to form an island of bump base metal or ball restricted metal that contacts the underlying metal layer;
Depositing lead-free solder bumps that are electrically connected to the islands;
Bonding a laminated structure to the lead-free solder bump;
Said method. The method of claim 10 , further comprising forming a capture pad and a conductive pad between the solder bump and the island. The method of claim 10 , wherein the step of forming the plurality of individual vias includes forming openings of various sizes and shapes in the one or more dielectric layers. The method of claim 10, wherein the plurality of individual trenches filled with the conductive material contact the island. A plurality of individual trenches formed in the lower dielectric layer and filled with a conductive material;
It is formed in one or more dielectric layers, in the lower dielectric layer, a plurality of metal islands of UBM or ball limiting metallurgy in contact with the upper wiring layer including a plurality of discrete trenches filled with the conductive material ,
A solder bump electrically connected to the metal island;
Including solder bump structure. The structure of claim 14 , further comprising a laminate bonded to the solder bump, wherein the solder bump is a lead-free solder bump. 15. The structure of claim 14 , wherein the metal island is TaN or TiW. The conductive material formed on the lower dielectric layer is filled, further comprising a plurality of individual trench aligned electrical contact with the metal island structure of claim 14. The structure of claim 16 , wherein the conductive material is a diffusion barrier layer and copper. The structure of claim 14 , wherein the metal islands are of various sizes and shapes.

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