TW201003623A - System and method for driving a display panel - Google Patents

Abstract

A multi-branch pixel structure of display panel, such as LCoS, is disclosed. Each pixel cell of the display panel has at least two branches. The display panel has a pair of sub-data lines for each column of the pixel cells, and the sub-data lines are controllably coupled to the two branches respectively. According to one embodiment, the two branches enter an addressing mode and a displaying mode in turn, thereby substantially increasing operating speed and reducing coupling effect. According to another embodiment, a multiplexer is configured to multiplex the sub-data lines between the adjacent pixel cells, such that multiplexed output of the multiplexer is coupled to a shared data line that is shared between the adjacent pixel cells, thereby substantially decreasing the pixel pitch.

Description

201003623 VI. Description of the Invention: [Technical Field] The present invention relates to a display panel, and more particularly to a drive system and method for a lithographic liquid crystal (LCoS) panel having a multi-branch pixel structure. This application claims domestic priority based on the prior application (application No. 97125263, application 曰2008/7/4, title of invention "display panel and its multi-branch pixel structure"). [Prior Art] Liquid crystal on silicon (LCoS or LCOS) is a reflective technology that is commonly used as a pico projector because it can produce images with higher resolution than liquid crystal displays (LCDs) at a lower cost. (micro-projector) or micro-display system optical engine. The structure of the LCoS is similar to that of an LCD, and typically includes a plurality of pixels arranged in a matrix of rows and columns. The first figure shows a conventional LCoS pixel cell, which includes a transistor QA, which is addressed by a scan signal Scan on scan line (or gate line) i 2 . The pixel unit process also includes 5 201003623 a storage capacitor c, which receives and stores the data line via the image provided by the power source line 14 and the QA (or the gate of the QA is made up of the sweep line 12) Data. Located in the same column of the actuator or gate driver (not connected together, and controlled by the source of the scan driver by the data shown in the figure). Located in the same-line transistor driver or The source drivers (not connected to each other and controlled by the data crystal QA are first displayed by the sweeper in the drawing). During operation, the electrical QA is turned on (0n), and the mirror Scan is accessed. When the transistor is stored in the storage capacitor, it is stored in the capacitor C. The charge is transferred and displayed. It becomes LC S ^ f (4) to react time, so the operation speed is especially good. An important indicator: When the resolution of LCOS is increased, the requirements for operating speed will be stricter. Therefore, it is urgent to propose a new structure to increase the speed of L(10) = to achieve high capacity. The pixel unit is also important, and he is not important in the system. SUMMARY OF THE INVENTION The present invention is directed to a drive system and method for a display panel having a multi-branch structure (e.g., !XqS) for increasing operating speed and reducing coupling (c). 〇Upiing) effect 201003623 Another object of the present invention is to provide a novel multi-branched pixel structure 'to reduce pixel pitch and save wafer area β μ''13 according to an embodiment of the present invention, a display panel (eg, Lc〇s) The eight-pixel structure consists of a plurality of pixel knives arranged in a matrix form, and each pixel contains at least two branches in advance. The eight-eighth lean " access mode and display mode. The display panel includes sub-datalines', and the pixel unit lines corresponding to each row are controllably coupled to the two branches respectively. In operation, and the access is performed in a picture. A branch of the brother, so that the first data line provides \~1篆贤料P, transferred and stored in the first branch, and simultaneously displays the second score in the image data. Next, in one The image data provided by the second data line accessed in the adjacent frame is stored and stored in the branch, and the image data stored in the first branch is displayed at the same time; In another embodiment of the present invention, each element of the display panel includes at least two branches. For each row, a sub-data line is coupled to the data driver, and the multiplexer is positioned at the adjacent pixel. Two sub-data between units, 77. multiplex 'and multiplexer output of the multiplexer lightly multiplex the multiplexer line, thereby reducing the pixel pitch. In operation, ~ share capital, will be bit The two secondary data lines between the elements are multiplexed, and the adjacent multi-engine rounding coupling 201003623 is connected to a shared data line, which is shared between adjacent pixel units. During the access mode, the branch corresponding to the secondary data line of the multiplex output is accessed, so that the image data of the multiplexed output data line is stored in the access branch. The stored image data is displayed during the display mode. [Embodiment] The second A-picture shows a multi-branch pixel structure 200 of a non-fluorescent liquid crystal (LCoS) panel, and the second B-picture shows a pixel unit 20 of a multi-branch pixel structure of the second A-picture. Although LCoS is used herein as an illustration, those of ordinary skill in the art can apply the illustrated structure to other reflective/transmissive display panels, such as liquid crystal displays (LCDs). In Figure 2A, the multi-branch pixel structure 200 of the LCoS panel comprises a plurality of pixels or pixel cells 20 arranged in a matrix of rows and columns. The pixels 20 in the same column are controlled by scanning signals (ScanA η and ScanB η, η = 0, 1, 2, etc.) on the scanning lines (or gate lines) 22A and 22B; the pixels 20 in the same row are electrically Connect to the data line (or source line) 24. Scan lines 22A and 22B are controlled by a scan driver (or gate driver) 220, and data line 24 is controlled by a data driver (or source driver) 240. 8 201003623 Referring to the second B diagram, the pixel unit 20 includes at least two branches ', that is, an A branch and a B branch. Taking the A branch as an example, it includes an addressing transistor qAa (e.g., a metal semiconductor transistor), which is located on the scan line 22A ==

ScanA can access the access transistor QAA by accessing the gate of the transistor qAa. The channel-end (eg, source) of the access transistor QAa is electrically coupled to the data line 24. The knife holder also includes a storage capacitor Ca, which receives the image data located on the data line by accessing. The storage capacitor CA = is electrically connected to the other end of the access transistor QAa channel (for example, no pole). The other end of the remaining capacitor ^ is electrically connected to the reference voltage Vref or ground. Support package 3 a displaying transistor g〇A (example M〇S transistor) 'image data stored in the storage capacitor CA can be used to slow down the image by means of the body (4) Shown so far. The display transistor QDA = is controlled by the - control signal DA. The display transistor QDA channel is coupled to the second::) electrically coupled to the drain of the access transistor QAA, and the terminal (eg, one end of the sub-packet CA). Another p. P source that displays the transistor QDA channel ) Electrically coupled to the pixel electrode The capacitor CCl represents the equivalent capacitance of the liquid crystal between the pixel electrode P and the common electrode (common 9 201003623 rrrde). The common electrode of the display panel and the pixel electrode P are opposed to each other, and _ to a common voltage vc 〇 M. The stored image poor material applied to the corresponding pixel electrode p will change the transparency or reflectivity of the liquid crystal on the basin. The description of the above branch also applies to the access transistor QAb, the storage capacitor Cb, the display transistor QDB, the scan signal ScanB, and the control signal in the B branch. The third A picture and the third B picture show the operation of the pixel unit 2〇 of the second B picture. The fourth figure illustrates a timing chart of the related operations of the third map and the third b map. For frame N of the third A picture and the fourth picture, the A branch enters an addressing mode, at which time the scanning signal 3 is turned on ((10)) to access the transistor QAa, so that the image data provided by the data line 24 is as The crucible is stored in the storage capacitor Ca. At the same time, the display transistor DA is turned off (OFF) by the logic low level, which prevents the stored image data from affecting other branches (for example, the B branch). The scan driver 220 sequentially generates scan signals (ScanA, 3, etc.) for scanning (or accessing) the pixel units 20 of each column sequentially (e.g., from top to bottom).

When the A branch is in the access mode, the B branch is in the display (dlSplaying) mode, and the logic low level scan signal (ScanB 201003623 Ο, ScanB 1,

ScanB 2 λ, and the logic high level is widely spread) Turn off (〇FF) access transistor qab, QDb, so that the storage is turned on (ON) display transistor is shown in the figure) ^ g : The image of the previous frame of the capacitor Cb (not shown from the display. Next, for the third

Now enter the display mode, ~ picture and the picture frame of the fourth picture...1, A branch 〇, ScanA iH logic low level scan signal (ScanA and logic high level control transfer) off (〇FF) access transistor W , qda, so that the display is stored in the DA display (ON) display transistor. When the frame N image data of the tantalum capacitor Ca is in the display mode, the b branch is in the display mode, and the scan signal Sca R is taken from the mode so that the data line 24 is supplied with the 1~〇N) access transistor. QAb, CB. At the same time, the display of greed material can be stored in the storage capacitor nR. The Japanese QDb is turned off (OFF) by the logic low level. This control is like other branches (for example, the influence of the image data stored in the A-spot phantom storage) To the signal (scanBG, Se for the drive wire 22G to sequentially generate the sweep 1:5 1, ScanB 2, etc.), 1V / Liu Guang, such as from top to bottom) scan (using the read order (example)) the parent column of pixels Unit 20. 201003623 Because of the multi-branch pixel structure 200 of the LCoS panel described above, the read and display can be increased in different branches in the same period to increase the operating speed. The fifth figure shows the third A pixel unit 20 the same 捺 you, the value is an extra consideration to access the transistor QAB stray capacitance Cds. This hybrid a ~ thief capacitance

Cds will coupling the image data on data line 24 to trim capacitor CB, and the interference affects the stored charge in storage capacitor CB, which reduces display quality. Figure 6A shows a multi-branch pixel structure 600 of the LCoS panel of the embodiment of the present invention, and the sixth panel B shows a pixel unit 60 of the multi-branch pixel structure of Figure 6A. The multi-branch pixel structure 600 of the LCoS panel of the present embodiment is used to improve the Coophng effect of the aforementioned LCoS panel 200, but still retains its advantages', that is, high operating speed. The elements of the sixth and sixth panels, which are similar to the second and second panels, use the same component symbols. Although this embodiment is described with LCoS, those skilled in the art can apply the illustrated structure to other forms of display panels, such as liquid crystal displays (LCDs). In Figure 6A, the multi-branch pixel structure 6 of the LCoS panel comprises a plurality of pixels or pixel cells 60 arranged in a matrix of rows and columns. Pixels 6〇 in the same column are controlled by scan signals on scan lines 22A and 22B (ScanA n and 12 201003623

ScanB n, n = 0, 1, 2, etc.; pixels 60 in the same row are electrically connected to a set of sub-data lines 24A, 24B. Each set of secondary data lines 24A, 24B is merged into a single data line 24 by a set of switches (SWA, SWB). Scan lines 22A and 22B are controlled by a scan driver (or gate driver) 220, and data lines 24 are controlled by a data driver (or source driver) 240. Referring to Figure 6B, pixel unit 60 includes at least two branches, in this embodiment, an A branch and a B branch. Taking the A branch as an example, it includes an access transistor QAa, and the scan signal ScanA on the scan line 22A can access the access transistor qaa by accessing the gate of the transistor QAa. One end of the channel (e.g., source) of the transistor QAa is electrically discharged to the secondary line 24A. The A branch further includes a storage capacitor Ca and a display transistor qDa, which are identical in structure to the second B diagram and therefore will not be described again. The seventh and seventh panels show the operation of the pixel unit 6A of the sixth panel B. The eighth diagram illustrates a timing chart of the operations related to the seventh A diagram and the seventh B diagram. For frame N of Figure 7A and Figure 8, the A branch enters the addressing mode, at which time the scan signal & cut eight is turned on (〇n) 13 201003623 Access to the transistor QAa 'A branch switch黯For the closed circuit (cl〇se), and the closed SWB of the B branch is open (Qpen), the data D at a can be stored by the data edge and the image. in. At the same time, the second is stored in the health day, the body QDA is closed by the logic low signal DA (OPp), and this / quasi-control affects other branches (such as the B branch). Scanning scan signals (ScanA0, ScanA1, Sca and R (snap) scan (or access) per-two:: When the A branch is in access mode, the b-branch is logically high: system =-) Take the transistor (4), and the system 开启DB turns on (〇N) QDb, so that the previous image stored in the storage capacitor Cb is shown in the figure). Bessie (not showing the next 'for the seventh · p & map and the eighth picture frame'] V+1, a eight ancient: see = display mode, at this time the logic low level scan & ScanA 1, ο μ, anA2 special) 阙 〇 〇 〇 存取 存取 存取 存取 存取 存取 逻辑 Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α Α ) ) Open), and Β 14 201003623 The branch switch SWB is t γ d , U closed circuit (CW), which will enable the frame N image data stored in the storage valley CA to be displayed. When the bucket and the field A knife are in the display mode, the B branch is in the access mode. At this time, the scan signal ScanB is turned on ((10)) to access the transistor QAB; = the image data Data# is borrowed (four) the feed line, the secondary data The line is stored in the storage capacitor CBt. At the same time, the display transistor is turned off by the low level control signal DB (〇Fp), which prevents the stored image data from affecting other branches (for example, the A branch). Scan drive = 220 sequentially generates scan signals (q, s_b 丨, 2, etc.) for scanning (or accessing) each column of pixel cells 60 sequentially (e.g., from top to bottom). According to the multi-branch pixel structure 6 of the LC〇S panel described above, since the access and display can be performed in the same period in different branches, the speed can be increased (4). Furthermore, since the cut line is thinned and connected to the access transistor QAa and the access transistor QAb, respectively, the data line coupling effect shown in the fifth figure is thus avoided or substantially improved. 15 201003623 Crystal QAa, display transistor QDa and storage capacitor CA. The access transistor QAa can be accessed by the scan signal ScanA on the A-branch scan line by its gate. The one end (for example, the source) of the channel of the access transistor QAa is electrically coupled to the data line Data1 of the A branch. The storage capacitor CA can receive the image data on the data line Data1 via the access transistor QAa and the switch POL1. The first plate of the storage capacitor CA is electrically coupled to the other end of the access transistor QAa channel (for example, the drain). The second plate of the storage capacitor CA is electrically coupled to the ground or reference voltage. The image data stored in the storage capacitor CA is displayed via the display transistor QDA. The display transistor QDA is used to buffer the stored image data prior to display. Wherein, the gate of the display transistor QDA is controlled by the control signal DA. One end (e.g., source) of the display transistor QDa channel is electrically connected to the drain of the access transistor QAa and coupled to the first plate of the storage capacitor CA. The other end of the display transistor QDA channel (e.g., the drain) is electrically coupled to the pixel electrode P. The above description about the A branch also applies to the access transistor QAB, the storage capacitor CB, the display transistor QDB, the scan signal ScanB, the control signal DB, and the data line Data2 among the B branches. According to the multi-branch pixel structure shown in the ninth figure, each row requires the use of two data lines (i.e., Data 1 and Data 2 ) which occupy the wafer area and increase the lateral (adjacent) pixel pitch. 16 201003623 FIG. 10A shows a multi-branch pixel structure 1000 of an LCoS panel according to an embodiment of the present invention, and FIG. 10B shows a partial detail of a multi-branch pixel structure of FIG. The LCoS panel multi-branch pixel structure 1000 disclosed in this embodiment is used to improve pixel pitch and wafer area. Although LCoS is used here as an explanation, those skilled in the art can take the structure of the device into consideration of other flat (LCD) devices. Referring to Figure 10A, the LCoS panel] a person 攸 1000 contains arranged in rows and columns

A plurality of pixels or pixel cells 90 in the form of a matrix. Sweep signals (SCanA n and ScanB n, n = 0, 1, 2, etc.) on the same scan line 22A and 22B, which are controlled by the same (4) prime 9q, which are controlled by the thumb, the ΟΟΛ and the private driver (or the gate). Drive state) 220. Pixels 9〇οκ α , , ^ W located in the same row are electrically coupled to a set of data lines 25 ′ and adjacent 系 9 〇 share the same capital, Bessie line 25, such as the tenth map, tenth Figure B shows. Taking the line xch 1 (the +th β-picture) as an example, the data drive-under data line (sub-data is (or source driver) 240 by the line) Xch 1 a and the second data line X h ib Provide two materials. A similar situation 'For another row Xch2, the taste feeder driver 240 provides two pieces of information by the first data line Xch2a and the second data 飨v, T leaf line Xch2b. The second attack of a line (such as Xchl): the first one of the owing to the squatting line (such as Xchlb) and the adjacent line (such as Xch2): owing, 丨 one person feeding line (such as Xch2a) via a multiplex The Mux (1 b2a) is multiplexed. 201003623 Pixel Unit (e.g., unit) This shared data line 25 can be coupled to a shared data line 25 between the adjacent 1 and unit 2 of the output of the multiplexer Mux (lb2a). It is obtained by (overlap) the bonding unit 1 accessing the drain of the transistor QAb and the cell 2 accessing the source of the transistor QAa, as shown in the tenth c. This layout shows that the single το 1 and the idle pole of each transistor in the single it 2, as well as the shared source/drain (ie, the shared data line). Since adjacent pixel cells: enjoy their source/no-pole', the wafer area is greatly reduced, and the lateral pixel pitch is substantially reduced. The tenth to tenth to tenth-thth drawings show the operation of the multi-branch image of the LCoS panel (the tenth A/B diagram). As shown in the tenth-A diagram, the ^ branch enters an addressing mode during which the scan signal d^canA) turns on the access transistor QAa, but turns off the remaining transistors. Bit, the first (or A branch) sub-data, the line Xchna (η=ι, 2, etc.) can be stored in the multiplexer Mux and stored via the access transistor (10): sub: at the same time The data located in the second (or B branch) secondary data line c ratio = 1, 2, etc. is blocked. After the A branch access mode operation of all the pixel columns is entered, the A branch 曰 and the display π (displaying) mode are as shown in FIG. During this period, the # & ^ two system nickname DA turns on the display transistor QDa, but turns off the complex 18 201003623 transistor. In this way, the stored items are displayed. The image of the storage capacitor cA of the pixel column is invaded, as in the eleventh c. During this period, the sweep signal is not applied, the B branch enters the access mode, and the remaining transistors are turned off. Located in the first ... open access transistor QAb, but (n = 1, 2, etc.) data can pass, support) data line Xchnb QAB and store, and through the access transistor branch) sub-data line X two The data of the first (", 2, etc.) is blocked. Will advance; after the operation of the beta branch access mode, the b branch number is turned on and the display transistor is as shown in the figure D. During this period, the control letter is stored in all The pixel column is stored twice but the remaining transistors are turned off. Here, the present day is limited to the above-mentioned image data, that is, the displayed access and display modes are dropped, and the figure is shown in the eleventh D-th. Access, display mode: order; = pixel structure 10. It can be determined by two preferred embodiments, not using the two things that God has done::, within the range of interest. ..., should be G3 in the following Application No. 19 201003623 [Simplified Schematic] The first figure shows a pixel unit of a conventional LCoS. The second A shows the multi-branch pixel structure of the present invention. The second B shows one of the multi-branch pixel structures of the second A picture. Pixel unit. The third A picture and the third B picture show the operation of the pixel unit of the second B picture The fourth figure illustrates the timing diagram of the related operations of the third A and third B. The fifth figure shows the same LCoS operation as the third A picture, but additionally considers the stray capacitance Cds of the access transistor QAB. Figure A shows a multi-branch pixel structure of an embodiment of the present invention. Figure 6B shows one pixel unit of the multi-branch pixel structure of Figure A. The seventh and seventh B-pictures show the operation of the pixel unit of the sixth B-picture. The eighth figure illustrates a timing chart of the operations related to the seventh A and seventh B. The ninth figure shows the pixel unit of the multi-branch pixel structure. The tenth A shows the multi-branch pixel structure of the LCoS panel of the embodiment of the present invention. Figure 10B shows a partial detail of the multi-branch pixel structure of the tenth A. The layout diagram of the tenth C shows that adjacent pixel units share their source/drain. The eleventh to eleventh D-pictures show the LCoS panel. Operation of multi-branch pixel structure (10th A/B diagram) 20 201003623 [Description of main component symbols] 10 pixel unit 12 scan line 14 data line 20 pixel unit 22A (A branch) scan line 22B (B branch) scan line 24 data line 24A ( A branch) data line 24B (B branch) data line 200 multi-branch pixel structure 220 scan driver 240 tribute driver 60 pixel unit 600 multi-branch pixel structure 90 pixel unit 1000 multi-branch pixel structure 25 shared data line Data image data Scan scan signal Sc an A (A branch) scan signal 21 201003623

ScanB QA QAa QAb QDa QDb C Ca Cb Clc Cds Vref DA DB P VCOM SWA SWB Datal POL1, Mux Xchn (B branch) scan signal transistor (A branch) access transistor (B branch) access transistor (A branch Display transistor (B branch) display transistor storage capacitor (A branch) storage capacitor (B branch) storage capacitor LCD capacitor stray capacitance reference voltage (A branch) control signal (B branch) control signal pixel electrode common voltage ( A branch) switch (B branch) switch Data2 data line POL2 switch multiplexer (n) pixel row 22 201003623

Xchna Xchnb nth row) first (or A branch) secondary data line ηth row) second (or B branch) secondary data line 23

Claims (1)

201003623 VII. Patent application scope: 1. A driving system for a display panel, comprising: a plurality of pixel units arranged in a matrix form, each of the pixel units comprising at least two branches, the two branches sequentially entering an access mode and a display mode; and a set of sub-data lines corresponding to the pixel unit of each row, wherein the data lines are controllably coupled to the two branches, respectively. 2. The driving system of the display panel according to claim 1, wherein the display panel is a lithograph liquid crystal (LCoS) panel. 3. The driving system of the display panel according to claim 1, wherein the group of data lines are controllably combined into a single data line. 4. The driving system of the display panel according to claim 3, further comprising a set of switches for respectively controlling the connection between the two branches and the single data line. 5. The driving system of the display panel of claim 1, further comprising at least two scan lines corresponding to the pixel unit of each column, wherein the two branches of the pixel unit are respectively coupled to the two scan lines . The driving system of the display panel of claim 5, wherein each of the pixel units comprises: an access transistor, accessed by a corresponding scan line; a storage capacitor for Receiving and storing the image tribute on the corresponding data line, and a display transistor, so that the stored image data can be displayed. 7. The driving system of the display panel of claim 6, wherein: the gate of the access transistor is coupled to the corresponding scan line; the first end of the channel of the access transistor is coupled to the corresponding The second data line of the channel of the access transistor is coupled to one end of the storage capacitor. 8. The driving system of the display panel according to claim 7, wherein: the gate of the display transistor is coupled to a control signal, and the control signal activates the display mode; the first channel of the display transistor The end is coupled to the second end of the channel of the access transistor; and the second end of the channel of the display transistor is coupled to a pixel electrode. 25 201003623 9. The driving system of the display panel according to claim 6, further comprising: a device for providing a scanning signal to turn on an access transistor of one of the branches while simultaneously closing access of the other branch A transistor; and a device for providing a control signal to turn off the display transistor of one of the branches while simultaneously turning on the display mode of the other branch. 10. A driving method for a display panel, the display panel comprising a plurality of pixel units arranged in a matrix form, each of the pixel units comprising at least a first branch and a second branch, wherein the first data line (sub-data line) Controllly corresponding to the first branch, and the second data line controllably corresponding to the second branch, the driving method includes: accessing the first branch in a frame, so that the first data The image data provided by the line is transferred and stored in the first branch, and the image data stored in the second branch is simultaneously displayed; and the second branch is accessed in an adjacent frame, so that the second time The image data provided by the data line is transferred and stored in the second branch, and the image data stored in the first branch is simultaneously displayed. 11. The driving method of the display panel according to claim 10, wherein the display panel is an Occa-based liquid crystal (LCoS) panel. The method of driving a display panel according to claim 10, wherein the image data is stored in the storage capacitor of the first or second branch. 13. The driving method of the display panel according to claim 10, further comprising: buffering the image data stored in the first branch when the first branch is accessed; and when the second branch When accessed, the image data stored in the second branch is buffered. 14. The driving method of the display panel according to claim 13, wherein the stored image data is buffered to prevent the stored image data from being connected to the pixel electrode. 15. The driving method of a display panel according to claim 13, wherein: the first branch located in the same column is accessed by the first scan signal of the first scan line; and the second branch located in the same column is subjected to the first The second scan signal of the two scan lines is accessed. 27 201003623 16. The driving method of the display panel according to claim 15, wherein: the image data located in the first data line is transferred to the first branch of the same line by the first switch; and the second data is located The image data of the line is transferred to the second branch of the same row by the second switch. 17. A driving system for a display panel, comprising: a plurality of pixel units arranged in a matrix, each of the pixel units comprising at least two branches; a sub-data line coupled to one a data driver corresponding to one row of the pixel unit, the two secondary data lines respectively corresponding to the two branches; and a multiplexer for multiplexing the two secondary data lines located between adjacent pixel units ( Multiplex), and the multiplexer output of the multiplexer is coupled to a shared data line, which is shared by the adjacent pixel unit. 18. The driving system of the display panel of claim 17, wherein the two branches are respectively coupled to the shared data line. The driving system of the display panel according to claim 17, wherein the display panel is a lithograph liquid crystal (LCoS) panel. 20. The driving system of the display panel of claim 17, further comprising at least two scan lines corresponding to the pixel unit of each column, wherein the two branches of the pixel unit are respectively coupled to the two scan lines . 21. The driving system of the display panel of claim 20, wherein each of the branches comprises: an access transistor accessed by a corresponding scan line; a storage capacitor for receiving and storing Corresponding to the image data on the shared data line; and a display transistor for displaying the stored image data. 22. The driving system of the display panel according to claim 21, wherein: the gate of the access transistor is coupled to the corresponding scan line; and the first end of the channel of the access transistor is coupled to the corresponding The shared data line; and the second end of the access transistor is coupled to one end of the storage capacitor. 29 201003623 Application. The driving system of the shaft panel of the 22nd patent® is applicable to: ', the gate of the display transistor is connected to a control signal, and the control signal activates the display mode; s "the page of the channel of the non-transistor a second end of the channel connected to the access transistor; and a second end _ to a pixel electrode of the channel of the transistor. The display panel as described in claim 23 The drive system, the first end of the access transistor channel of the second branch of the second pixel is shared by the first end of the access transistor channel of the first branch of the first pixel unit, wherein the first pixel unit is adjacent to the first pixel unit The second pixel unit is a driving method for displaying a panel, the display panel includes a plurality of pixel units, and each image element includes at least two branches, and the driving method comprises: placing bits in adjacent pixels The sub-data line between the units is multiplexed, and the multiplexed output is connected to a shared data line, which is shared between adjacent pixel units, wherein one pixel row corresponds to There are two a data line, and the two secondary data lines are connected to the data driver; 30 201003623 accessing the branch corresponding to the secondary data line of the multiplex output, so that the image data of the multiplex output secondary data line is stored in the access 26. The method of driving a display panel according to claim 25, wherein the display panel is a lithograph liquid crystal (LCoS) panel. 27. claim 25 The driving method of the display panel further includes at least two scan lines corresponding to the pixel unit of each column, wherein the two branches of the pixel unit are respectively coupled to the two scan lines. The driving method of the display panel, wherein each of the branches includes: an access transistor, accessed by a corresponding scan line; a storage capacitor for receiving and storing image data of the corresponding shared data line And a display transistor for displaying the stored image data. 29. Driving of the display panel as described in claim 28 In the access mode, the access transistor is turned on, and the display transistor is turned off. 31 201003623 30. The driving method of the display panel according to claim 28, wherein the display mode is displayed during the display mode The transistor is turned on and the access transistor is turned off.