201001743 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體元件的製造方法，特別是有關於一 種可用以降低元仙部差排雜的半導體元件的製造方法。 【先前技術】 由於m族氮化物半導體材料之發光光譜涵蓋可見光至紫外光之 間的波長，再力n_L]n族氮化物半導體材料係為直接躍遷型半導體， 而被廣泛朗於發光二輔（LED)或f射二極體（ld 件上。 目⑽來製造isd之m族氮化物半導體元件的技術中，通 常將瓜族氮化物半導體層成長於適合卻非理想絲板上，目前此類 基板包3 (但不限制為）藍寶石、碎、GaAs或碳化轉異質蟲晶 基板然而所有A質$晶基板在高品質m族氮化物半導體層的沉積 中產生aat與熱不匹配的挑戰。晶格不匹配係由晶體中原子的間距 差異所造成’熱不匹配係由不同材料間熱膨脹係數的差異所造成。 通系碳化石夕材料與GaN系化合物的晶格係數差異約3〇/0左右， 藍寶石材料與GaN系化合物的晶格係數差異約13%左^，而於蟲 晶製程中，此晶格不匹配的情形往往會產生差制題，意即於元件 内部存在著縱向（與基板碰直的方向）貫穿的線差排缺陷。其中， 於肋氮化物轉體元件巾通常存在有雜為1Q9em 2左右的線差 排缺陷情形’如此大量的差排會通過組成相異之祕氮化物半導體 各層而轉移至元件最上層，最終導致元件的破裂。上述種種問題， 常使付雷射二極體關值電流、發光二極體與雷射三極體的元件壽 命以及元件的可靠度等特性的良率大大降低。 6 201001743 此外’熱不匹配亦應受到重視。通常在族氮化物半導體材料 生長於基板後，當樣品冷卻至室溫時，熱雜（收縮）速率的差里 在兩種材綱的介面處產生高度的應力，且應力量直接與所沉積的 膜層厚度有關，膜層越厚則應力越大。例如藍寶石較GaN且有更古 的熱膨脹係數，因此當藍寳石基板與GaN層冷卻時，介面處的不= 配問題使得GaN受職應力喊f石受聰應力，且當膜厚超過 1〇微米時’應料級超過GaN的斷縣度，可齡產生膜層之破 裂情形。 廣泛缺陷（線差排、錯位堆疊等）的存在導致元件效能大幅地 j亚導致操作壽命縮短。更具體而言，差排的行為類似非輕射複 a中心’因此降低了由該些材料所致成之發光二極體以及雷射二極 ^的發光鱗，且差排關題亦增加了暗電流。雖絲差排問題並 未妨糾缺發光二極_發展，但差齡在p_n接面元件，如高 電子遷移率電晶體、場效電晶體以及其他電元件巾引起過量的逆偏 [篇電机又差排可具有載子之強散射中心的作用，因此降低了電 子與電洞的遷料’關了衫半導體元件的效能。 如美國專利US6534332，揭露—種GaN薄層的製造方法。請 多考第1之結構示意圖10◦，其詳細的方法係為：首先在高溫（大 ' C的/JHL度）的遙晶環境下成長一第一 GaN層150於表面 有低。μ成長之緩衝層130的基板11〇上，再於溫度約為7〇〇。◦BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device which can be used to reduce the impurity. [Prior Art] Since the luminescence spectrum of the m-type nitride semiconductor material covers the wavelength between the visible light and the ultraviolet light, the n_L]n-nitride semiconductor material is a direct transition type semiconductor, and is widely used for the luminescent secondary ( In the technique of manufacturing an isd group of nitride semiconductor devices, LEDs or f-diodes (1) are generally used to grow a melon-based nitride semiconductor layer on a suitable but non-ideal silk plate. Substrate package 3 (but not limited to) sapphire, GaAs, or carbonized to heterogeneous crystal substrates. However, all A-type crystal substrates create aat-thermal mismatch challenges in the deposition of high quality m-type nitride semiconductor layers. The lattice mismatch is caused by the difference in the spacing of atoms in the crystal. The thermal mismatch is caused by the difference in thermal expansion coefficient between different materials. The difference in lattice coefficient between the carbonitride and GaN-based compounds is about 3〇/0. The lattice coefficient difference between the sapphire material and the GaN-based compound is about 13%, and in the process of the insect crystal, the lattice mismatch often causes a poor problem, that is, there is a vertical inside the component. The line difference (through the direction in which the substrate is struck) penetrates the line gap defect. Among them, the rib nitride transfer element sheet usually has a line defect of about 1Q9em 2, so that a large number of difference rows will be different in composition. The layers of the nitride semiconductor are transferred to the uppermost layer of the component, which eventually leads to the cracking of the component. These various problems often result in the lifetime of the laser diode, the lifetime of the LED and the component of the laser, and the components. The yield of features such as reliability is greatly reduced. 6 201001743 In addition, 'thermal mismatch should also be taken seriously. Usually after the family nitride semiconductor material is grown on the substrate, when the sample is cooled to room temperature, the rate of thermal (shrinkage) In the difference, high stress is generated at the interface of the two materials, and the amount of stress is directly related to the thickness of the deposited film. The thicker the film, the greater the stress. For example, sapphire has a higher coefficient of thermal expansion than GaN. When the sapphire substrate and the GaN layer are cooled, the non-alignment problem at the interface causes the GaN to be stressed by the stress, and when the film thickness exceeds 1 μm, the material level exceeds GaN. The degree of rupture of the age-producing film layer. The presence of extensive defects (line spacing, misalignment stacking, etc.) leads to a significant reduction in component performance resulting in a shortened operational life. More specifically, the difference in behavior is similar to non-light shots. The complex a center 'reduced the light-emitting diodes caused by the materials and the light-emitting diodes of the laser diodes, and the differential currents also increased the dark current. Although the problem of the silk row is not correct Luminous diodes _ development, but the age of the p_n junction components, such as high electron mobility transistors, field effect transistors and other electrical components caused excessive reverse bias [the motor and the row can have strong carrier The role of the scattering center, thus reducing the efficiency of the electron-and-hole relocation, is to turn off the performance of the semiconductor component of the shirt. As disclosed in US Pat. No. 6,534,332, a method of manufacturing a thin layer of GaN is disclosed. Please refer to the structure diagram 10 of the first one. The detailed method is as follows: First, a first GaN layer 150 is grown on the surface at a high temperature (large 'C/JHL degree) crystal environment. The growth of the buffer layer 130 on the substrate 11 is further increased to about 7 Torr. ◦
〜900 C的中溫蠢晶環境下成長一 GaN中間層（it-IL) 170，之 後再覆蓋一層高溫成長之第二GaN層19〇於GaN中間層17〇上， 二目的係藉由此中溫蠢晶條件下所形成的GaN中間層17〇來改善 磊晶品質。然而，由於緩衝層13〇、第一 GaN層15〇以及QaN 201001743 中間層170皆為氮化録糸材料’底層之差排缺陷容易貫穿該 中間層170而延伸至元件内部，而導致降低缺陷的效果不佳。 再者’美國專利US7135716提出一種發光二極體，其特徵係 在發光二極體内部形成一極性轉換層（p〇larity c〇nversi〇nA GaN interlayer (it-IL) 170 is grown in a medium-temperature stray crystal environment of ~900 C, and then a second high-growth GaN layer 19 is deposited on the GaN intermediate layer 17 ,. The GaN intermediate layer 17 formed under mild temperature conditions improves the epitaxial quality. However, since the buffer layer 13A, the first GaN layer 15A, and the QaN 201001743 intermediate layer 170 are all nitrided material, the underlying defect of the underlying layer easily extends through the intermediate layer 170 to the inside of the element, resulting in a defect reduction. not effectively. Further, U.S. Patent No. 7,317,716 discloses a light-emitting diode characterized in that a polarity conversion layer is formed inside the light-emitting diode (p〇larity c〇nversi〇n
Layer)。然而，此一發明所提出之極性轉換層係位於非結晶緩衝層 (am’h_ buffer layer)之上，會導致降低材料内部之缺陷密度 的效果反而因此減低。另外，上述發明使用之 (AlxInyGaz)Mg3切+Z)N2 與 SiaMg3属為 n_m 族氮化物或 π_ιν 族 氮㈣漏，有顺單純之m魏化合物㈣，其成絲件較為複 雜及嚴苛，更不利於製造生產。 有鑑於此’仍有必要·新的半賴元件結構或_半導體元 方法’以達到降低半導體元件内部缺陷之目標，並改善製程 ，良率’提升元件的可靠度與元件壽命，赠合市場需求。 【發明内容】Layer). However, the polarity conversion layer proposed by this invention is located on the amorphous buffer layer (am'h_buffer layer), which results in a reduction in the defect density inside the material, which is instead reduced. In addition, the above-mentioned invention uses (AlxInyGaz) Mg3 cut +Z)N2 and SiaMg3 belongs to n_m group nitride or π_ιν family nitrogen (four) drain, and there is a simple m Wei compound (4), and the filament forming part is more complicated and strict, and more Not conducive to manufacturing production. In view of this, it is still necessary to have a new semi-equivalent component structure or _semiconductor method to achieve the goal of reducing internal defects of semiconductor components and improve the process, yield 'improving the reliability of components and component life, giving market demand . [Summary of the Invention]
高濃體f f造方法’並利用於蟲晶製程中 杯明成之置人層，降低元件⑽的差排缺陷。 並形成二第;導體元件的製造方法，包含:提供-， 濃度衝編’接著，儀在_程中高 覆蓋-第成一置入層於第一半導體層表面，而後， 第二半導體Μ Ή上述置人層上’其中形成該置人層與覆蓋該 體發光元2 ‘組程序，最後，秘第二半導體層上成長-半導 本發明所提供之另一 緩衝層，並料— 件的製造方法’包含：提供- 成一弟—轉體層於緩衝層表面，接著，於蟲晶過程 8 201001743 中利用高濃度摻雜物f的方式形 面’而後覆蓋-第二半導體層、一置入層於第-半導體層表 程中高濃度摻雜物質的方式弟二置入層表面，再利用於磊晶製 面，並覆蓋-第三半導體層^成一第二置入層於第二半導體層表 層與覆蓋第三半導體声糸 入^上，其中，形成第二置入 長一料體發光元:為—組程序，最後，再於第三半導體層上成 本發明提供一種降低半導; 半導體層、一置入層、一 入 〜體7L件内部缺陷的結構，包含··一第 層位於該第-半導體層表t轉體層與—半導體發光元件，置 =件位於第二半導體層上’其中置 第一半導體層位於置入層上，半導 入層與第二半導體層為 一半導體層、一第體4内部缺陷的結構’包含:-第 第三半導體層與一半光:π導體層、-第二置入層、- ί層位於弟—置人層上，第二置人層位於第二半導 三半導體層位於第二置人層上，半導體發光元件位於 弟二+導體層上’其中第二置人層與第三半導體料—組次結構。 t發明所提供之降低元件畴缺陷的方法，全部製程皆於蟲晶 反應器内完成’不需額外的黃光微影餘，減少元件受到污染的機 會0 本發明所提供之置入層’可用以改善發光元件之發光特性以及 電氣特性。 【實施方式】 本發明在此所探討的方向為一種半導體元件的製造方法。為了 9 201001743 能徹底地瞭解本發明，將訂列的贿巾提崎㈣步 成。顯然地，本發明的施行並未限定於半導體元件之技藝 ^ 的特殊細節。另—方面’眾所周知的組成或步驟並未描述於‘、中白’ Z避免Μ本㈣不必狀_。本發_錄實施财詳= 述 如下，然而除了這些詳細描述之外，本發明還可以廣泛地 ^的實施射，且本發範圍衫岐，如讀料利範圍為 毕。 /賴補US686127G，揭露—_以提高發光效率之 體;Γ其主要方法係於基板上依序成長1型趣沾 ^體層、-未摻雜之A1GaN半導體層與_ p型趣沾半導體声， =η型搬aN半導體層表面，即於未摻雜之·心半導體芦曰 形成-不連續的空擾層（Ga、A1)其 ^ 來擾動發光層的_隙，以此提昇元件的發光微擾層 美國專利S6462357，揭露一種瓜族氮化 4 Ca s R其詳細的方法係细成長—Π魏化物〔收， 上的S ^aiZn’ ％ Hg) Ν]複合單晶島狀層於基板或基板 並物半導體層，藉此單晶島狀結構降低晶格錯位情形， 較為。°然而，單晶成長條件 曰: ’、不易製作’且由於此發明所使用的材料特性，使的石 曰曰過程中可調變條件變少，大大降低最佳化元件的取得。a 吴國專利US6627974，揭露-種具有7型 體元件，μ抑峡成μ聽铸體元件 201001743 二?法，係為在位於基板上之氮化物半導體層表面，利用 与制4成長—賴層，再彻黃光微 形狀，例如條紋、格紋或島狀結構。隨後， 體層自賴層之空隙向上錢向絲，並在完全覆蓋保 丁又:二τ =成τ型結構之氮化物半導體層。之後，在此一 缺㈣成其他的半導體層，喊少半導體間的差排 心二Γ:該保護層選擇使用較不易使氮化物半導體材料成長於 :、貝Sl〇x ’ SlxNy，丁1〇x或ZrOx)，且因上述特性而使得 =鄰:護層間得以形成τ型氮化物半導體結構。然、而，此專利所 ϊ :、:ΐ程ΪΓ且此專利所利用之cvd、賴或黃光微影等製 私存在汙染晶片成長面的可能性。 美國專利US6345063所使用之遮罩層（patterned mask aye〇為氧切（Si〇2)或氮切⑽），且上述遮罩層係由 以外的製程所形成，製程_，且存在有㈣晶片成長面 、可月b性。此外，此專利主張將城奶層直接成長於遮罩層上，此 則不易形成品質良好的遙晶層。The high-concentration f f method is used in the process of the insect crystal process to reduce the defect of the component (10). And forming a second method; the manufacturing method of the conductor element comprises: providing -, concentration punching 'then, the meter is high-covering in the process - the first layer is placed on the surface of the first semiconductor layer, and then the second semiconductor is placed On the human layer, a process of forming the set of layers and covering the body light-emitting elements 2', and finally, growing and semi-conductive on the second semiconductor layer, another buffer layer provided by the present invention, and a method for manufacturing the materials 'Including: providing - forming a brother-turning layer on the surface of the buffer layer, and then, in the process of insect crystals 8 201001743, using a high-concentration dopant f to form a surface' and then covering - the second semiconductor layer, a layer placed in the - a method of depositing a high concentration dopant in the surface of the semiconductor layer, the second layer is placed on the surface of the layer, and then applied to the epitaxial surface, and covering the third semiconductor layer to form a second implant layer on the surface of the second semiconductor layer and covering a semiconductor sound input device, wherein a second implanted long-body light-emitting element is formed: a set of procedures, and finally, a third semiconductor layer is provided on the third semiconductor layer to provide a reduced semiconductor; the semiconductor layer is placed Layer, one into ~ 7L member internal defect structure, comprising: a first layer located on the first semiconductor layer, the t-transfer layer and the semiconductor light-emitting element, and the device is located on the second semiconductor layer, wherein the first semiconductor layer is located on the implantation layer The semi-introducing layer and the second semiconductor layer are a semiconductor layer, and the structure of the internal defect of the first body 4 includes: - the third semiconductor layer and the half light: the π conductor layer, the - the second implant layer, the - ί layer On the younger layer, the second person layer is located on the second semiconductor semiconductor layer on the second person layer, and the semiconductor light emitting element is on the second + conductor layer, wherein the second person layer and the third semiconductor material - Group structure. The invention provides a method for reducing component domain defects, all processes are completed in the crystal cell reactor 'no need for additional yellow light micro shadows, reducing the chance of contamination of the component 0. The implant layer provided by the present invention can be improved Light-emitting characteristics and electrical characteristics of the light-emitting elements. [Embodiment] The direction of the present invention as discussed herein is a method of manufacturing a semiconductor device. In order to thoroughly understand the present invention for 9 201001743, the bribes to be ordered (IV) will be completed. Obviously, the practice of the present invention is not limited to the particular details of the art of semiconductor components. Another aspect is that the well-known composition or step is not described in the ‘, 中白’ Z to avoid Μ (4) not necessarily _. The present invention is also described below, but in addition to these detailed descriptions, the present invention can be widely implemented, and the scope of the present invention is as follows. / 赖补 US686127G, reveals - _ to improve the luminous efficiency of the body; Γ its main method is to grow on the substrate in order to form a type of interesting layer, - undoped A1GaN semiconductor layer and _ p type of semiconductor sound, = η type to move the surface of the aN semiconductor layer, that is, to form an undoped core semiconductor reed - a discontinuous interference layer (Ga, A1) which disturbs the _ gap of the luminescent layer, thereby improving the luminescence of the element The scrambling layer US Pat. No. S6462357 discloses a detailed method for the melon nitriding 4 Ca s R. The fine growth method is Π Π 化物 收 收 上 上 上 上 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合The substrate is combined with the semiconductor layer, whereby the single crystal island structure reduces the lattice misalignment. However, the single crystal growth condition 曰: ', is not easy to manufacture' and due to the material characteristics used in the invention, the variable conditions in the process of the stone slab are reduced, and the optimization of the element is greatly reduced. a Wu Guo patent US6627974, discloses a type 7 body element, μ suppression gorge into a sound-casting element 201001743, the method is to use the growth and deposition layer on the surface of the nitride semiconductor layer on the substrate. Then, the yellow light micro shape, such as stripes, plaids or island structures. Subsequently, the bulk layer is lifted from the gap of the layer to the wire, and is completely covered with a nitride semiconductor layer of two layers of τ = τ type. After that, there is a lack of (four) into other semiconductor layers, shouting less difference between the semiconductors. The choice of the protective layer is less likely to cause the nitride semiconductor material to grow:, S1〇x' SlxNy, Ding 1〇 x or ZrOx), and due to the above characteristics, = o: a layer-type nitride semiconductor structure is formed between the layers. However, this patent ϊ:,: ΐ程ΪΓ and the use of cvd, Lai or Huangguang lithography used in this patent has the possibility of contaminating the growth surface of the wafer. The mask layer (patterned mask aye〇 is oxygen cut (Si〇2) or nitrogen cut (10)) used in US Pat. No. 6,345,063, and the above mask layer is formed by a process other than the process, and there is (4) wafer growth. Face, can be b-type. In addition, this patent claims that the city milk layer is directly grown on the mask layer, which makes it difficult to form a good quality crystal layer.
美國專利US6794210，主張使用反介面活性材料 anU-surfactant)將基板魏化鎵_進行改質，喊成長於i 上的薄膜能減少差排缺_密度。其詳細的方法係為：於基板上形 成-氮化鎵（GaN)系複合半導體層，接著顧&等反介面活性材 料將上述GaN $複合半導體層部份表面進行改質，未改質的氣化嫁 2合半導體層表面處_成驗結構，有進行改質的部份形成空 八空間’其目的係湘該些空穴崎來自聽化鎵系複合半導體層 的差排缺陷’使其不至麵伸錢續触日日日層。然而，此專利中所 11 201001743 2的改質製程中需將Ga源（TMGa)與氨氣的供應暫時停止， 此舉反而易使磊晶薄膜受到損壞。 Γ IV /觀上^先4專W之缺失係為：缺陷阻礙層與其他i晶層皆為 ’龜_效咖心綱叫，= 枓特性減少製程可調變參數，降低最佳化元 ==的:，形，_層，存在有汙染晶=的 且有缺rdt日服供—全做蟲晶餘巾即可成長之 導: 以第—置入層作為缺陷阻擋層）之半 陷阻二之部因晶格不匹配所產生的差排問題，該缺 曰丨且松層之衣耘間易，並可避免上述問題。 、，本發明提供—辭導體元相製造方法，包含：雜— 亚形成一第—半導體層於緩衝層表面， 曰一 濃度摻雜物質的方式以形成—第 m在心4私中兩 後，覆蓋一第二置入層於第一半導體層表面，而 導體芦上#生體a於上相—置人層上，最後，再於第二半 導體層上成長-半導體發光元件牛 蓋第二半導體層為一袓 成广之形成弟-置入層與覆 偏層之w ’更包含執行複數次該組程序。以此製造方、 ^於第―半導體層財導料私件 2 覆蓋層的第二半導體層，可有_ =弟f人層以及作為 二半導體層，或可有二組以上的第 ^以及作為^蓋層的第 半導體層。 置入層以及作為覆盍層的第二 層、第二卜半導::明:：:二:層、第-半導體層、第-置入 其中〇㈣=上峨AWnyG〜N， 权弟—+導體層與第二轉體層皆可為 201001743 單層（single layer)或多層（multiplelayers)之半導體結構。。 為了更清楚地描述上述製程，本發明提供另一種包含二組第— 置入層以及作為覆蓋層的第二半導體層之半導體元件的製造方法， 包含：提供-緩衝層，並形成一第一半導體層於緩衝層表面，接著， 於從日日過中利用尚濃度摻雜物質的方式形成一第一置入層於第— 半«層表面，而後覆蓋一第二半導體層於第一置入層表面，再利 用於蠢晶製程中高濃度摻雜物質的方式形成一第二置入層於第二半 r Ϊ體層表面，並覆第三轉體層於第二置人層上，最後，再於 第：半‘體層上成長-半導體發光元件。其中，形成第二置入層與 覆蓋第三半導體層即為上述之一組程序。 ,請參考第二圖所示，係為根據本發明所提供之半導體元件 的製造方法所建構的一種製程流程圖。此製程流程大致可區分為五 ^大步驟’首先’步驟210係為於基板上形成―腿氮化物半導體緩 衝層’接著，步驟220於緩衝層上形成一第一瓜族氮化物半導體層， =驟230則於第—職氮化物半導體層表面，糊於i晶製程中高 ^摻雜物質的方式形成—職氮化物置人層，步驟湖則接著覆 V i層第二m族氮化物半導體層於上述Π族氮化物置入層上，最 ^步驟250則於第族氮化物半導體層上形成—腿氮化物半 ^體發，件結構。其中，第二圖中所示之由步驟24◦指向步驟 。3〇,前頭意味著步驟230與步驟240係為—組程序，該組程序 σ視衣耘品求而重複執行。於本發明中，該組程序係用以降低 内。卩的差排（dislocation)缺陷。 本發明所提供之置人層的形成，係為於懸氮化物半導體材料 i AlxInyGai-x_yN的磊晶過程中，以固定式摻雜濃度、調變式提高 201001743 摻雜濃度或調變式降低摻雜濃度等方式，摻雜高濃度之U.S. Patent No. 6,792,210, which claims the use of an anti-active material anU-surfactant to modify the substrate gallium gamma, and the film grown on i can reduce the poor deficiencies. The detailed method is: forming a gallium nitride (GaN)-based composite semiconductor layer on the substrate, and then modifying the surface of the GaN $ composite semiconductor layer by using an anti-surface active material such as & At the surface of the vaporized marl 2, the surface of the semiconductor layer is formed, and the modified portion is formed into an empty eight space. The purpose is to make the hole defects of the organic gallium-based composite semiconductor layer Do not extend the money to continue to touch the daily sun. However, in the modification process of 11 201001743 2 in this patent, it is necessary to temporarily stop the supply of Ga source (TMGa) and ammonia gas, which is liable to damage the epitaxial film. Γ IV / Guanshang ^ first 4 special W is missing: the defect barrier layer and other i crystal layers are 'turtle _ effect coffee heart, = 枓 characteristics reduce process adjustable parameters, reduce optimization elements = =:, shape, _ layer, there is pollution crystal = and there is a lack of rdt day service - all the worm crystal towel can grow the guide: the first layer is used as a defect barrier) The difference between the two parts due to the lattice mismatch, the lack of loose and easy to loose between the clothes, and can avoid the above problems. The present invention provides a method for manufacturing a conductor phase, comprising: forming a semiconductor layer on a surface of a buffer layer, and forming a concentration of a dopant substance to form a layer m after the core 4 is privately covered. a second implant layer is on the surface of the first semiconductor layer, and the conductor a is on the upper phase-on the human layer, and finally on the second semiconductor layer - the semiconductor light-emitting element has a second semiconductor layer For the formation of a group of Cheng Guang - the placement layer and the overlay layer w 'more include the execution of the group of procedures. The second semiconductor layer of the cover layer of the first semiconductor layer may have a _=di fa human layer and a second semiconductor layer, or may have two or more groups of ^ The first semiconductor layer of the cap layer. The placement layer and the second layer as the cover layer, the second semi-conducting:: Ming::: two: layer, the first-semiconductor layer, the first-in which the 〇 (four) = the upper AWnyG~N, the right brother - Both the conductor layer and the second rotor layer may be a 201001743 single layer or multiple layer semiconductor structure. . In order to more clearly describe the above process, the present invention provides another method of fabricating a semiconductor device including two sets of first implant layers and a second semiconductor layer as a cap layer, comprising: providing a buffer layer and forming a first semiconductor Laying on the surface of the buffer layer, and then forming a first implant layer on the surface of the first-half layer by using a concentration of dopants from the day, and then covering a second semiconductor layer on the first implant layer Surface, reusing a high concentration dopant in the stupid process to form a second implant layer on the surface of the second half of the body layer, and covering the third layer of the body on the second layer, and finally, : Half-body layer growth - semiconductor light-emitting elements. Wherein, forming the second placement layer and covering the third semiconductor layer is one of the above-described group procedures. Please refer to the second figure, which is a process flow chart constructed by the method for fabricating a semiconductor device according to the present invention. The process flow can be roughly divided into five steps: 'first' step 210 is to form a "leg nitride semiconductor buffer layer" on the substrate. Next, step 220 forms a first cassava nitride semiconductor layer on the buffer layer, Step 230 is formed on the surface of the first-stage nitride semiconductor layer, and the high-doping substance is formed in the i-crystal process to form a nitride layer, and the step lake is followed by the second m-nitride semiconductor layer of the V i layer. On the above-mentioned cerium nitride-implanted layer, the most step 250 forms a leg nitride half-body on the group nitride semiconductor layer. Wherein, the step shown in the second figure is directed to step by step 24◦. 3〇, the former means that step 230 and step 240 are a group program, and the group of programs is repeatedly executed. In the present invention, the set of programs is used to reduce the inside. Defects in dislocation. The formation of the donor layer provided by the present invention is to increase the doping concentration or the modulation type of the 201001743 doping concentration or the modulation type in the epitaxial process of the suspended nitride semiconductor material i AlxInyGai-x_yN. Doping concentration, etc., doping high concentration
Be 5 Mg »Be 5 Mg »
Ca ’ Sr ’ Ba ’ Zn，Cd ’ Hg，Si ’ Ge ’ Sn等材料，以形成如第五 A圖所示之第一置入層54〇a，或第五B圖所示之第二置入層 540b’亦可參考第三圖所示意之結構310。待第一置入層540a成 長完成，則停止摻雜高濃度物質的動作，並使冚族氮化物半導體材 料或AlxIriyGa^—y等材料的磊晶製程繼續進行，以形成一第二半導 體層550a於第一置入層540a上’請參考第三圖中之結構 320〜340所示’係為作為覆蓋層之第二半導體層的形成示意圖。在 覆盍第二半導體層550a時，會先形成不連續之島狀結構，如第三 圖之320所示。隨著成長時間增加，此不連續之島狀結構會開始互 相接合，如第三圖之330所示。最後即形成一平整之第二半導體層， 如第三圖之340所示。若於第二半導體層成長結束後，重新執行摻 雜高濃度物質的動作，則可獲得第二組置入層54〇b，請參考第五B 圖所描紛的結構示意圖。 其中’鎂於置入層中的摻雜濃度介於1〇xl〇2〇 cm_3〜 9.9xl〇22 cm-3’ 而較佳濃度範圍介於 5 〇χ1〇2〇 cm—3〜5 〇χΐ〇2ι u cm—3 ;石夕於置入層中的摻雜濃度介於l.〇xl〇i9 cm·3〜9.9χΐ〇22Ca ' Sr ' Ba ' Zn, Cd ' Hg, Si ' Ge ' Sn or the like to form a first implant layer 54 〇 a as shown in FIG. 5A or a second set as shown in FIG. The entry layer 540b' can also refer to the structure 310 illustrated in the third figure. After the growth of the first implantation layer 540a is completed, the action of doping the high concentration substance is stopped, and the epitaxial process of the material such as the bismuth nitride semiconductor material or the AlxIriyGa^y is continued to form a second semiconductor layer 550a. On the first placement layer 540a, 'refer to the structures 320 to 340 in the third figure' is a schematic diagram of the formation of the second semiconductor layer as a cover layer. When the second semiconductor layer 550a is covered, a discontinuous island-like structure is formed first, as shown by 320 of the third figure. As the growth time increases, the discontinuous island structures begin to join each other, as shown in 330 of the third figure. Finally, a flat second semiconductor layer is formed, as shown by 340 of the third figure. If the operation of doping the high-concentration substance is re-executed after the growth of the second semiconductor layer is completed, the second set of the implanted layer 54〇b can be obtained. Please refer to the schematic diagram of the structure shown in FIG. The doping concentration of 'magnesium in the implanted layer is between 1〇xl〇2〇cm_3~ 9.9xl〇22 cm-3' and the preferred concentration range is 5〇χ1〇2〇cm-3~5 〇χΐ 〇2ι u cm—3 ; the doping concentration of Shi Xi in the implanted layer is between l.〇xl〇i9 cm·3~9.9χΐ〇22
Cm—3 ’而較佳濃度範圍介於l.OxlO20 cm-3〜5·Ο102ΐ cm-3 ;鎮 與石夕的組合於置入層中的摻雜濃度介於l.〇xl〇19 cm-3〜9 9x1C)22 cm-3，而較佳濃度範圍介於丄〇χ1〇2〇 cm3〜5 〇χΐ〇2ΐ 3。另 外，上述之形成置入層的摻雜時間係為秒〜1()分鐘。 —请參考第四圖所示，係為置人層中不同摻雜濃度之輯原子與 覆盖於置人層上之第二半導體層表面型態之關係圖。第四a圖至第 四F圖等六個圖中，其摻雜濃度係分別為Μ〆，%如綱 14 201001743 cm 3 > ΐ_5χ ]^Q2i cm 3 » 8 8x i npn 〇 · l〇 cm-3,6.3xl〇2〇 cm-3,4 9χΐ〇2〇 cm—3。由上述六個圖中可比較出爽 一 一 於摻雜濃度較⑽第四F W ^南的弟四A圖，相較 凸起物的高度較高且ίΓ縣麵現之島狀 层w 门…度亦較向。意即於层晶製程中，加入置入 二4雜物濃度高於-數值後，則覆蓋於其上之第二（三）半導體 =始形成綠結構，且越高之摻雜濃度，可使得島狀結構且突起 =^顯。因此，在執行每—次形成置人層與覆蓋第二半導體層的 ，柄’母—次高濃度摻雜之摻雜濃度並不-定相同。例如，可逐 ^牛低摻雜浪度’或逐次提高摻雜濃度，亦可因應製程需求而調整 母一次程序的摻雜濃度。 另外，由第二圖巾的缺陷密度示意圖可發現，結構中的置 入層下，即第一半導體層中的差排缺陷（以細長直線示意）計有28 條，j而由於置人層形成於第—半導體層與第二半導體層之間，阻 ，了第半‘體層中部份差排缺陷的繼續延伸，而使得後續成長之 第-半導體層降低承接來自第__半導體層的差排缺陷數量，因此在 、’、σ構340中，可發現第二半導體層中的差排缺陷只剩下條。因 此本發明所提供之置人層，可用以使材料内部的差排缺陷被阻擔於 元件底。卩或使多個差排缺陷合併成—個，進而降低元件内部差排缺 陷總數。 本發明提供一種降低半導體元件内部缺陷的結構5〇〇，如第五 A圖所示，由下而上依序包含：一基板51〇、一半導體緩衝層52〇、 第一半導體層530、一第一置入層54〇a ' —第二半導體層550a 與一半導體發光元件560。其中，上述半導體發光元件56〇包含n 型皿族氮化物半導體導電層562、m族氮化物半導體發光層564、 15 201001743 化物半導體奸崎層566與P翻魏化物半導體導 上述之第-置入層54〇a位於第一半導體層53〇表面， 第二半導體層55Qa與第-半導體層53〇之間。其中第一置入声 540a與第二轉體層55Qa為—組次結構，則於半導體發光元件 56〇與第二半導體層55Qa間更可包含複數組·構。則此半導體 兀件結構_中，介於第-半導_ 530與半導體發光元件56〇 之間的次結構，可有-組或大於—組之第—置人層54〇&以及第二 半^層550a。然而’最接近難氮化物半導體發光層564的置 〇層上所覆蓋的第二半導體層亦可直接是N寵魏化物半導體導 ^。上述之半導體緩衝層52◦、第—半導體層53〇、置人層54〇a 二、弟二半導體層55Ga係為職氮化物或AlxI%Ga ， 本發明提供另一種降低半導體元件内部缺陷的結構500，如第 B圖=示，由下而上依序包含：—基板Μ◦、—半導體緩衝層 —第一半導體層53〇、一第-置入層540a、-第二半導體 5〇a、—第二置人層54〇b、—第三半導體層55〇b與-半導體 化鉍2件56〇。其中，上述半導體發光元件56〇包含N型羾族氮 、>導體導電層562、m族氮化物半導體發光層564、Ρ5ί!_ ^68物半$體電子阻檔層566與p型瓜族氮化物半導體導電層 一车ΐ逑第一置入層540a位於第一半導體層53〇表面，且介於第 位於^體層53Q與第二半導體層55Qa之間；上述第二置人層540b ;第一半^體層表面55〇a，並介於第二半導體層與第三半 201001743 導體層550b之間。其中上述之第二置入層54〇1?與第三半導體層 550b為一組次結構，則於半導體發光元件56〇與第二半導體^ 550a間更包含覆數組次結構。貝g此半導體元件、结構5〇〇中，介於 第-半導體層530與半導光元件56Q之間，可有複數組置入 層以及覆蓋於置人層上之半導體層。然而，最接近難氮化物半導 體發光層564的置人層上所覆蓋的第二半導體層亦可直接是n龍 族氮化物半導體導電層。上述之半導體緩衝層52Q、第—半導體層 530、第f人層540a、第二半導體層55〇a、第二置人層54〇b、 第三半導體層55〇b係為m族氮化物或AlxI%GaixyN，其中 〇Sx，y$ 1。 上述之各個置入層中的摻雜材料係為下列之一者或其組合：The preferred concentration range of Cm-3' is between 1.OxlO20 cm-3~5·Ο102ΐ cm-3; the doping concentration of the combination of town and Shixi in the implanted layer is between l.〇xl〇19 cm- 3~9 9x1C) 22 cm-3, and the preferred concentration range is 丄〇χ1〇2〇cm3~5 〇χΐ〇2ΐ 3. Further, the doping time for forming the implant layer described above is seconds to 1 (minutes). - Please refer to the fourth figure for the relationship between the atoms of different doping concentrations in the layer and the surface pattern of the second semiconductor layer overlying the layer. In the six graphs from the fourth to fourth F maps, the doping concentration is Μ〆, % 如 如 14 201001743 cm 3 > ΐ _5 χ ] ^ Q2i cm 3 » 8 8x i npn 〇 · l〇cm -3, 6.3xl 〇 2 〇 cm -3, 4 9 χΐ〇 2 〇 cm - 3. From the above six figures, we can compare the four-figure map with the doping concentration (10) and the fourth FW ^ south, which is higher than the height of the protrusions and the island-like layer w of the county. The degree is also relatively good. That is, in the layering process, after the concentration of the implanted 4 and 4 impurities is higher than the -value, the second (three) semiconductor overlying the green structure is formed, and the higher the doping concentration, the Island-like structure and protrusion = ^ display. Therefore, the doping concentration of the handle-female-sub-high-concentration doping is not the same in each of the formation of the encapsulating layer and the covering of the second semiconductor layer. For example, the doping concentration can be increased or the doping concentration can be increased one by one, and the doping concentration of the primary program can be adjusted according to the process requirements. In addition, it can be found from the defect density diagram of the second towel that there are 28 defects in the underlying layer in the structure, that is, in the first semiconductor layer (indicated by an elongated straight line), and j is formed by the layer. Between the first semiconductor layer and the second semiconductor layer, the continuation of the partial defect of the first half of the bulk layer is continued, so that the subsequent growth of the first semiconductor layer is reduced to receive the difference from the __ semiconductor layer The number of defects, therefore, in the ', σ structure 340, it can be found that only the strips are missing in the second semiconductor layer. Therefore, the deposit layer provided by the present invention can be used to prevent the defective defects inside the material from being blocked at the bottom of the element.卩 or combine multiple defective defects into one, which reduces the total number of internal faults in the component. The present invention provides a structure for reducing internal defects of a semiconductor device. As shown in FIG. 5A, the substrate includes a substrate 51A, a semiconductor buffer layer 52A, a first semiconductor layer 530, and a substrate. The first implant layer 54A'' is a second semiconductor layer 550a and a semiconductor light emitting element 560. The semiconductor light-emitting device 56A includes an n-type nitride semiconductor conductive layer 562, an m-type nitride semiconductor light-emitting layer 564, and a layer-by-nitride semiconductor layer 564. The layer 54A is located between the surface of the first semiconductor layer 53 and the second semiconductor layer 55Qa and the first semiconductor layer 53A. The first insertion sound 540a and the second rotating layer 55Qa have a group-order structure, and the complex structure can be further included between the semiconductor light-emitting element 56A and the second semiconductor layer 55Qa. Then, in the semiconductor device structure _, the sub-structure between the first-half-conductor 530 and the semiconductor light-emitting element 56, may have a group-- or a group---the first layer 54 〇 & Half layer 550a. However, the second semiconductor layer covered on the germanium layer closest to the hard nitride semiconductor light-emitting layer 564 may also be directly a N-paste semiconductor semiconductor. The above-mentioned semiconductor buffer layer 52, the first semiconductor layer 53, the donor layer 54A2, and the second semiconductor layer 55Ga are nitrides or AlxI%Ga, and the present invention provides another structure for reducing internal defects of the semiconductor device. 500, as shown in FIG. B, includes, from bottom to top, a substrate, a semiconductor buffer layer, a first semiconductor layer 53A, a first-in-layer layer 540a, a second semiconductor 5a, - a second set of layers 54 〇 b, a third semiconductor layer 55 〇 b and a semiconductor 铋 2 piece 56 〇. The semiconductor light-emitting device 56A includes an N-type lanthanum nitrogen, a conductive conductive layer 562, a m-type nitride semiconductor light-emitting layer 564, a 电子5ί!_^68 half-body electronic barrier layer 566, and a p-type cucurbit a nitride semiconductor conductive layer-vehicle first placement layer 540a is located on the surface of the first semiconductor layer 53 and interposed between the first body layer 53Q and the second semiconductor layer 55Qa; the second person layer 540b; The half body surface 55 〇 a is interposed between the second semiconductor layer and the third half 201001743 conductor layer 550b. The second placement layer 54〇1? and the third semiconductor layer 550b have a sub-structure, and further comprise a sub-array structure between the semiconductor light-emitting device 56A and the second semiconductor device 550a. In the semiconductor device and structure 5, between the first semiconductor layer 530 and the semi-light-guiding element 56Q, there may be a multilayer array and a semiconductor layer covering the donor layer. However, the second semiconductor layer covered on the donor layer closest to the hard nitride semiconductor light-emitting layer 564 may also be directly a n-type nitride semiconductor conductive layer. The semiconductor buffer layer 52Q, the first semiconductor layer 530, the f-th human layer 540a, the second semiconductor layer 55〇a, the second human layer 54〇b, and the third semiconductor layer 55〇b are made of a group m nitride or AlxI%GaixyN, where 〇Sx, y$ 1. The doping materials in each of the above-mentioned implanted layers are one or a combination of the following:
Be ’ Mg ’ Ca，Sr ’ Ba，Zn，Cd，Hg，Si，Ge，Sn。其中，鎂 於置入層中的摻雜濃度介於LOUWOcmj〜9 9xl〇22cm 3,而較 佳濃度範圍介於5_〇x 1〇2〇 cm-3〜5.0x⑴以cnr；3;矽於置入層中的 摻雜濃度介於Ι.ΟχΚμ9·3〜9.9xl〇22enr3,啸佳濃度範圍介 於j.Ox 1〇2〇 cnr3〜5.〇x 1〇21 cm.3 ;鎂與石夕的組合於置入層中的摻 雜濃度介於l.Ox’cm-3〜9.9xl〇22 cm_3，而較佳濃度範圍介於 l.〇Xl〇2〇 cm-3〜5·〇χ1〇21 cm-3。 s顯然地，依照上面實施例中的描述，本發明可能有許多的修正 與差異。因此需要在其附加的權利要求項之範圍内加以理解，除了 上述詳細的描述外，本發明還可以廣泛地在其他的實施例中施行。 上述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專 利fen，凡其它未麟本發明賴枕精神下所完成的等效改變或 修飾’均應包含在下述申請專利範圍内。 17 201001743 【圖式簡單說明] 第一圖 係為美國專利US6534332中所揭露的一種具有中 々 溫成長之GaN中間層（IT-IL)的結構示意圖； 第一圖 係為根據本發明所提供之半導體元件的製造方法所 建構的一種製程流程圖； 第圖 係為於本發明中，成長-島狀結構與覆蓋於置入層 上之半導體層的形成情形以及元件内部缺陷密度示 意圖； 第四A圖 第四B圖 第四C圖 第四D圖 第四E圖 $為根據本發明所建構之覆蓋於具有n族原子摻雜 濃度為8.8xl〇2i cm-3的第一置入層之第二半導體 層表面型態圖； 係為根據本發_建構之覆蓋於具有 濃度為2.9x1〇21cm-3的第—置入層 層表面型態圖； +¥體 據本發明所建構之覆蓋於具有 碾度為1·5χ1〇2ΐ cm-3的第一置芦 層表面型態圖； ㈣之弟二半導體 =為根據本發騎雜之覆蓋於具打 浪度為8.8xl〇2〇 cm-3的第一置 ’、多、 層表面型關； 置人層之第二半導體 係為根據本發明所建構之覆蓋 濃度為wwdt原子， 層表面型態圖； 置入層之弟二半導體 第四F圖 係為根據本發明所建構之覆蓋於具有U族原子私 雜 18 201001743 第五A圖 第五B圖 濃度為4.9><102〇 cm-3的第一置入層之第二半導體 層表面型態圖； 係為根據本發明所建構之一種降低半導體元件内部 缺陷的結構（具有一層置入層）； 係為根據本發明所建構之一種降低半導體元件内部 缺陷的結構（具有兩層置入層）。 19 201001743 【主要元件符號說明】 100 具有GaN (IT-IL)層的半導體元件結構 110 基板 130 緩衝層 150 第一 GaN層 170 GaN 中間層（IT-IL) 190 第二GaN層 210 於基板上形成一 ΠΙ族氮化物半導體緩衝層 220 於緩衝層上形成一第一皿族氮化物半導體層 230 於第-m族氮化物半導體層表面，利用於蟲晶製程中 同浪度摻雜物質的方式形成一皿族氮化物置入層 240 覆蓋-層第二111族氮化物半導體層於上述皿族氮化物 置入層上 250 於第二m族氮化物半導體層上形成-m族氮化物半導 體發光元件結構 310 具有島狀結構之半導體元件 320-340於置入層上進行後峙 排密度減少之示意圖^體層的成長情形，以及線差 510 基板 500 _低半導體元件内部缺陷的結構 520 半導體緩衝層 530 弟一半導體層 540a 第一置入層 540b 第二置入層 20 201001743 550a 550b 560 562 564 566 568 第二半導體層 第三半導體層 半導體發光元件 N型ΠΙ族氮化物半導體導電層 ΠΙ族氮化物半導體發光層 P型ΠΙ族氮化物半導體電子阻擋層 p型m族氮化物半導體導電層 21Be 'Mg' Ca, Sr ' Ba, Zn, Cd, Hg, Si, Ge, Sn. Wherein, the doping concentration of magnesium in the implanted layer is between LOUWOcmj~9 9xl〇22cm 3, and the preferred concentration range is from 5_〇x 1〇2〇cm-3~5.0x(1) to cnr; 3; The doping concentration in the implanted layer is between Ι.ΟχΚ9·3~9.9xl〇22enr3, and the concentration range of Xiaojia is between j.Ox 1〇2〇cnr3~5.〇x 1〇21 cm.3; magnesium and stone The doping concentration in the implanted layer is between 1.Ox'cm-3 and 9.9xl〇22 cm_3, and the preferred concentration range is between 1.〇Xl〇2〇cm-3~5·〇χ1 〇21 cm-3. s Apparently, the present invention may have many modifications and differences in accordance with the description in the above embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be The above are only the preferred embodiments of the present invention, and are not intended to limit the patent application of the present invention. Any equivalent changes or modifications made by the other inventions should be included in the following claims. Inside. 17 201001743 [Simplified Schematic] The first figure is a schematic diagram of a GaN intermediate layer (IT-IL) having a medium temperature growth as disclosed in US Pat. No. 6,534,332; the first figure is a semiconductor according to the present invention. A process flow chart constructed by the method for manufacturing a component; the first diagram is a schematic diagram of the formation of the growth-island structure and the semiconductor layer covering the implanted layer and the defect density inside the component in the present invention; 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 2 is a second embodiment of the first implant layer having a doping concentration of 8.8×1〇2i cm-3 with n-group atoms constructed according to the present invention. a surface pattern of the semiconductor layer; a surface pattern of the first layer placed at a concentration of 2.9 x 1 〇 21 cm -3 according to the present invention; The surface pattern of the first reed layer with a degree of rolling of 1. 5χ1〇2ΐ cm-3; (4) The second semiconductor = the coverage of the wave according to the present invention is 8.8xl〇2〇cm-3 The first set of ', multi, layer surface type off; the second half of the layer The system is constructed according to the present invention, and the coverage concentration is wwdt atom, and the surface surface pattern of the layer; the fourth F-picture of the second layer of the semiconductor layer is constructed according to the present invention and covered with a U-group atomic hybrid 18 201001743 5A, FIG. 5B is a second semiconductor layer surface pattern of the first implanted layer having a concentration of 4.9><102〇cm-3; and is a method for reducing internal defects of a semiconductor element according to the present invention. Structure (having a layer of implanted layer); is a structure (having two layers of implanted layers) for reducing internal defects of a semiconductor element constructed in accordance with the present invention. 19 201001743 [Description of main component symbols] 100 semiconductor element structure having GaN (IT-IL) layer 110 substrate 130 buffer layer 150 first GaN layer 170 GaN intermediate layer (IT-IL) 190 second GaN layer 210 is formed on a substrate A lanthanum nitride semiconductor buffer layer 220 is formed on the buffer layer to form a first group nitride semiconductor layer 230 on the surface of the first-m-type nitride semiconductor layer, and is formed by the same-wavelength doping substance in the worm process. a class of nitride-implanted layer 240 covering-layer of the second group 111 nitride semiconductor layer on the above-described dish nitride-implanted layer 250 to form a -m-group nitride semiconductor light-emitting element on the second group-m nitride semiconductor layer Structure 310 The semiconductor element 320-340 having an island structure is formed on the implanted layer to reduce the density of the rear drain layer, and the line difference 510 substrate 500_lower semiconductor element internal defect structure 520 semiconductor buffer layer 530 First semiconductor layer 540a first placement layer 540b second placement layer 20 201001743 550a 550b 560 562 564 566 568 second semiconductor layer third semiconductor layer semiconductor Optical element N-type bismuth nitride semiconductor conductive layer ΠΙ-nitride semiconductor light-emitting layer P-type bismuth nitride semiconductor electron blocking layer p-type m-nitride semiconductor conductive layer 21