TW201001653A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW201001653A
TW201001653A TW097148257A TW97148257A TW201001653A TW 201001653 A TW201001653 A TW 201001653A TW 097148257 A TW097148257 A TW 097148257A TW 97148257 A TW97148257 A TW 97148257A TW 201001653 A TW201001653 A TW 201001653A
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TW
Taiwan
Prior art keywords
substrate
metal
bump
semiconductor device
semiconductor
Prior art date
Application number
TW097148257A
Other languages
Chinese (zh)
Inventor
Tomokatsu Nakagawa
Masahiro Horio
Takaharu Miyazaki
Original Assignee
Sharp Kk
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Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW201001653A publication Critical patent/TW201001653A/en

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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Abstract

A semiconductor device is provided with an interposer substrate mounted on a film substrate, and a semiconductor element mounted on the interposer substrate. The interposer substrate is provided with a plurality of first substrate metal bumps, a plurality of first substrate pad metal pieces (23), and a plurality of substrate wirings (24). The semiconductor element is provided with a plurality of element metal bumps which are bonded to the first substrate metal bumps, respectively, by thermocompression, a plurality of element pad metal pieces (13), and a plurality of element wirings (14). The first substrate pad metal pieces (23) and the element pad metal pieces (13) have polygonal shapes wherein each corner protrudes outward. Each of the substrate wirings (24) is connected to a position at an interval from the apex of the corner of the corresponding first substrate pad metal piece (23), and each of the element wirings (14) is connected to a position at an interval from the apex of the corner of the corresponding element pad metal piece (13). Thus, in the semiconductor device, wiring disconnection is eliminated.

Description

201001653 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種使用有金屬凸塊之晶片複合型封裝之 半導體裝置。 ~ 【先前技術】 ./ w ITT 丁〒遐凡件之 晶片複合型封裝。於此類半導體裝置中，半導體元件係以 旎夠使汛號輸入輸出之方式而封裝於薄膜基板上。為了不 使半導體裝置之品質以及可靠性降低，必須防止因封裝而 引起之異常。 ~ 對例如TCP(Tapecarrierpackage，捲帶式封裝）或咖 (Chip on Fllm ’薄膜覆晶封裝）之半導體裝置中之構成進 說明。於半導體元件中，於封裝於薄膜基板上之面上，來 成有配置於與薄膜基板之接合部分之元件外部連接電極； 以及以連接元件外部連接電極與元件内部之方式而引繞之 元件配線’且於元件外部連 嫂…" 丨連接电極上形成含有金之金屬凸 鬼於缚膜基板上，於封裝半導體元件之面上， 置於與半導體元件之元件外部 _ 錫之入；^ M A 电★相對之位置且經鍍 =有鋼的内部引線、以及以能夠自 板外部之方式而弓i繞之基板配線。 接於基 於該等構成中，一面施加 P-, ^ A … 刀面將金屬凸姑 Γ内㈣線，並以金-錫共晶加以接合，，此可將丰: 體元件封裝於薄膜基板上。 了將丰¥BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a wafer composite package having metal bumps. ~ [Prior Art] ./ w ITT Ding Yufan's wafer composite package. In such a semiconductor device, the semiconductor element is packaged on the film substrate in such a manner that the nickname is input and output. In order not to degrade the quality and reliability of the semiconductor device, it is necessary to prevent an abnormality caused by the package. ~ The configuration in a semiconductor device such as a TCP (Tape carrier package) or a Chip on Fllm (film on-chip package) will be described. In the semiconductor device, the electrode is externally connected to the surface of the film substrate, and the component is externally connected to the electrode and the device. 'And external to the component..." The gold-containing metal bump is formed on the bonded substrate on the connection electrode, and is placed on the surface of the packaged semiconductor device and placed outside the component of the semiconductor component. Electric ★ relative position and plated = steel inner leads, and substrate wiring that can be wound from the outside of the board. Based on the configuration, a P-, ^ A ... blade surface is applied to the inner metal (4) wire and bonded by a gold-tin eutectic, which can be packaged on the film substrate. . Will be Feng ¥

(Inner Lead BonH· 再者，该接合方法被稱為ILB d Bondmg，内部引線接合）。 136777.doc 201001653 此處’元件外部連接電極與元件配線 形成圖案，但另一方而达 j金屬而 、— ，為了提高性能，有時會將層疊有 =數層金屬配線層者用作^件配線。此時，由於元件外部 接電極與71件配線係不同材料，因此必須使其等單獨分 開形成而連接。 例如’於專利文獻i中揭示有如下構成：如圖9所示，於 .夕卜部連接金屬配線部2〇1上設置用以與内部金屬配線205連 f接之突出部2〇2，且使内部金屬配線205層疊於突出部2〇2 上而進行連接。外部連接金屬配線部201中，成為導電連 :部分之㈣203以及開口窗2〇4以外之部分均被絕緣保 ^ 斤覆蓋但是，特別是當内部金屬配線2〇5層疊於突 $部2〇2之基端部X(相對於外部而突出之角度為90度之部 分）上時，因兩者材料之熱膨服率等之差異，將導致應力 k而於絕緣保護膜中容易產生應變以及破裂。因 此’於專利文獻1中，藉由將内部金屬配線205布設於與基 (.4部X空開間隔之部位，以防止絕緣保護膜之應變以及破 裂。 [專利文獻1]曰本專利特開昭62_23294〇號公報（^以年i 〇 月13日公開） 【發明内容】 上述封裝之半導體裝置係使金屬凸塊與内部引線接合之 構成，亦存在具有如下構成之半導體裝置，即，於薄膜基 板與半導體7L件之間介隔包含石夕基板等之插入式基板。於 α亥半導體裝置中’於插入式基板上，在封裝半導體元件之 136777.doc 201001653 ==有配置於與半導體元件之元件外部連接電極相 ，置上的基板外料接電極m夠以自基板外部 =妾：極連接於基板外部之方式而?ι繞之基板配線，且二 基板外部連接電極上形成有含有金之金屬凸塊。圖10表干 形成金屬凸塊之前之、忐a 不(Inner Lead BonH· Again, this bonding method is called ILB d Bondmg, internal wire bonding). 136777.doc 201001653 Here, 'the external connection electrode of the component is patterned with the component wiring, but the other one is made of metal, and - in order to improve the performance, the laminated metal layer is sometimes used as the wiring. . At this time, since the external electrode of the element and the wiring of the 71 pieces are different materials, it is necessary to separate and connect them. For example, as disclosed in Patent Document 1, there is a configuration in which a protruding portion 2〇2 for connecting to the internal metal wiring 205 is provided on the outer metal connecting portion 2〇1 as shown in FIG. The internal metal wiring 205 is laminated on the protruding portion 2〇2 to be connected. In the external connection metal wiring portion 201, the portion other than the (4) 203 and the opening window 2〇4 is covered by the insulation, but in particular, the internal metal wiring 2〇5 is laminated on the portion 2〇2 When the base end portion X (the portion protruding at an angle of 90 degrees with respect to the outside) is caused by the difference in thermal expansion ratio between the two materials, stress k is caused, and strain and crack are easily generated in the insulating protective film. . Therefore, in the patent document 1, the internal metal wiring 205 is disposed in a portion spaced apart from the base (the portion X is spaced apart to prevent strain and cracking of the insulating protective film. [Patent Document 1] SUMMARY OF THE INVENTION The above-described packaged semiconductor device has a structure in which metal bumps are bonded to internal leads, and a semiconductor device having the following configuration, that is, a thin film The interposer substrate including the Shishi substrate or the like is interposed between the substrate and the semiconductor 7L. In the αH semiconductor device, the semiconductor device is mounted on the interposer substrate, and the semiconductor device is disposed at 136777.doc 201001653 == The external electrode of the component is connected to the external phase of the substrate, and the external electrode of the substrate is connected to the substrate, and the substrate is connected to the outside of the substrate, and the external electrode of the two substrates is formed with gold. Metal bumps. Figure 10 before the surface of the metal bumps, 忐a not

件外部連接電極、基板外部連接雨s 1(7C 卜p運接电極）以及配線1〇2(元件配 、，皋、基板配線）之圖案例。 半導體元件係藉由金屬凸塊彼此之接合而封裝於插入式 土反上。於使金屬凸塊與内部引線接合之情形時 錫共晶而接合，因此赦壓 .p ”、、"•接之接合壓力較小，從而接合壓 力不易成為引起故障之眉 入“主 草原因然而’於使金屬凸塊彼此接 曰之f月形吟’若使用例如全 使未共晶…全接人= 料，則為了 :;存在如下:題：因較大之接合壓力，而導致各金屬： 列之几件外錢接電極以及基板外部連接電極產生破損 (衣紋或破裂箄之指應、 、 此姑人 於使半導體元件與插入式基 5之後’有時亦會由於兩者材料之熱膨服率等之差 =而使元件外部連接電極以及基板外部連接電極分別受 到應力而產生破損。 作為破損產生時之—-,, 不例，圖11表示在外部連接電極A pattern example of the external connection electrode and the external connection of the substrate, such as rain s 1 (7C pu transfer electrode) and wiring 1 〇 2 (element, 皋, substrate wiring). The semiconductor element is packaged on the plug-in soil by bonding the metal bumps to each other. When the metal bumps are bonded to the inner leads, the tin eutectic is joined, so that the bonding pressure of the p., "," is small, and the bonding pressure is not easily caused by the failure of the eyebrows. However, 'if the shape of the metal bumps are connected to each other', if the use of, for example, all of the uneutectic...all connected to the material =, for:: exists as follows: Title: due to the larger joint pressure, resulting in Metal: A few pieces of the external money electrode and the external connection electrode of the substrate are damaged (the indication of the clothing or rupture 、, after the semiconductor element and the plug-in base 5) sometimes also due to the two materials The difference between the thermal expansion rate and the like is such that the external connection electrode of the element and the external connection electrode of the substrate are damaged by stress, and are damaged. When the damage occurs, for example, FIG. 11 shows that the electrode is externally connected.

中產生有裂紋時之狀能 Α ^ g A 拍加 才（狀態。應力容易集中於金屬凸塊之 “，因此應力亦會施加至外部連接電極1G卜裂紋將自 起點起，一邊描繪圓弧，— 、 遭朝外側穿仃。因此，若外部 @極101中所產生之裂紋朝設有配線1G2之方向傳遞， J36777.doc 201001653 則會產生配線1〇2斷線之重大問題。因此，無法維持半導 體裝置之品質及可靠性較高。 ’ 又，不僅限於接合壓力較大之情形時，雖產生概率較 低，但於使接合壓力較小之金屬凸塊與内部引線接合之情 形時，有時元件外部連接電極上亦會產生破損。例如，= 在如下情形：為了使所有金屬凸塊確實地與内部引線接 觸’而以較強之力加以按壓，因此導致因金屬凸塊之高度 之不均-等，而於最高之金屬凸塊内產生應力集中。又 本發明係鑒於上述先前之問題開發而成者，其目的在於 提供一種能夠防止配線之斷線之半導體裝置。 為了解決上述問題，本發明之半導體裝置之特徵在於： 其係包含封裝S基板上之插人式基板、以及封裝於上述插 入式基板上之半導體元件者，上述插入式基板包含形成於 封裝上述半導體元件之位置上之複數個基板金屬部、分別 形成於上述各基板金屬部上之複數個基板突起電極、及分 別連接於上述各基板金屬部之複數條基板轉，上述半導 體元件包含分別藉由熱壓接而與上述各基板突起電極接人 之複數個元件突起電極、分別形成於上述各元件突起電極 之下之複數個元件金屬部、及分別連接於上述各元件:屬 部之複數條元件配線’且上述各基板金屬部以及上述各元 部壬各角朝外側突出之多角形狀’上述各基板配線 係連接於各自所對應之純金屬部之與肖之頂點空開間隔 之位置’上述各元件配線係連接於各自所對應之元件金屬 部之與角之頂點空開間隔之位置。 136777.doc 201001653 於先前，熱壓接時之接合壓力越大，則位於基板突起電 極之下之基板金屬部、以及位於元件突起電極之下之元件 金屬部越容易產生破損（裂紋或破裂等之損傷）。該破損將 導致基板配線以及元件配線斷線之事態。又，破損容易進 入至應力容易集中之角為止。 與此相對，根據上述構成，各基板配線係連接於各自所 對應之基板金屬部之與角之頂點空開間隔之位置，各元件 配線係連接於各自所對應之元件金屬部之與角之頂點空開 間隔之位置。藉此，即使於基板金屬部元件以及元件金屬 部上產生例如裂紋，亦可防止因該裂紋而使裂紋傳遞至基 板配線以及元件配線為止而產生斷線。 又，當將上述半導體元件封裝於插入式基板上時，為了 使各基板突起電極與各元件突起電極適當藉由熱壓接而接 合，本發明之半導體裝置較理想的是，上述各基板突起電 極以及上述各元件突起電極包含電阻為3χ10'8(Ω·ιη)以下之 金屬凸塊。或者，本發明之半導體裝置較理想的是應用於 上述各基板突起電極以及上述各元件突起電極包含拉伸強 度為1.0xl08(Pa)以上之金屬凸塊者。 又，本發明之半導體裝置較好的是，上述各基板突起電 極以及上述各元件突起電極具有長方體之形狀，上述各元 件配線配置於各自所對應之元件突起電極之與元件金屬部 相接之面的短邊側。 當各基板突起電極以及各元件突起電極具有長方體之形 狀時，藉由熱壓接，於元件突起電極之與元件金屬部相接 136777.doc -10- 201001653 之面上’朝長邊方向之展開較小，朝短邊方向之展開較 大。因此，元件金屬部中，由於為了朝上述長邊方向展門 而施加之力較小，因此不易產生斷裂，而由於為了朝上^ 短邊方向展開而施加之力較大，因此容易於上述長= 上產生斷裂。 同 因此’根據上述構成，夸元件配線配置於各自所對應之 元件突起電極之與元件金屬部相接之面的短邊側，藉:可 防止與基板突起電極、元件突起電極、元件金屬部：以及 兀件配線相連之路徑產生斷開（open)。 又’本發明之半導體裝置較好的是，上述各基板突起電 極以及上述各兀件突起電極具有長方體之形狀，上 板配線配置於各自所對岸之美杯办如+ & 相接之面的短邊側基板犬起電極之與基板金屬部 狀：各Si突起電極以及各元件突起電極具有長方體之形 :夺’於藉由熱壓接而於基板突起電極之與基板金屬部相 大之純邊方向之展開較小，朝短邊方向之展開較 ^因此，基板金屬部中，由於為了朝上述長邊方向展開 而施加之力較小’因此不易產生斷裂，而由於為了朝上述 短邊方向展開而施加之力較大，因此容易 上產生斷裂。 4贡違万向 據上述構成，各基板配線配置於各自所對應之 基板犬起電極之與基板金屬部相接之面的短邊側，因此可 件突起電極、基板突起電極、基板金屬部、以及 基板配線相連之路徑產生斷開。 136777.doc 201001653 又由於半導體凡件與插入式基板之熱膨服率之差，故 半導體元件與插入式基板之變形量將產生差。因此，越遠 離半導體元件之形成有各元件突起電極之面的中心附近， 半導體元件與插入式基板之變形量之差越大。若因該熱膨 脹所產生之力而導致朝卜；士、， 朝上速知邊方向產生有斷裂，則有於 上述路徑上產生斷開之虞。 因此’為了防止因熱膨脹而產生上述短邊方向之斷裂， 本發明之半導體裝置較理想的是’上述各元件突起電極以 如下方式而配置，即，盥夂Aw — ρ與各自所對應之元件金屬部相接之 面的長邊與上述半導體元件之形成有上述各元件突起電極 之面的長邊垂直。又，士名义 發月之半導體裝置較理想的是， =基板突起電極以如下方式而配置，即，與各自所對 有上述各基板突起電極之面插入式基板之形成 於又皇二了：？上述問題，本發明之半導體裝置之特徵在 :=，=薄膜基板包含形成於封裝上述半導= 件之位置上之讀個基板金屬部、及分料接於 板金屬部之複數條基板配線，上 4基 由熱厂《而與上述各基板金屬部接合之複=包含^藉 極、分別形成於上述各元件突起電極 2件大起電 屬部、及分別連接於上述各元件全個元件金 線’且上述各元件金屬部呈各二==配 上述各元件配線係連接於各自所對應之元件金::::角 136777.doc -12- 201001653 之頂點空開間隔之位置。 於先4，當因元件突起電極之高度之不均一而於熱壓接 日守產生應力集中時，該應力越大，位於元件突起電極之下 之兀件金屬部越容易產生破損（裂紋或破裂等之損傷）。該 破損將導致元件配線斷線之事態n損容易進入至應 力容易集中之角為止。 與此相對，根據上述構成，將各元件配線連接於各自所 對應之基板金屬部之與角之頂點空開間隔之位置。藉此， 即使於元件金屬部中產纟有例如裂、紋，亦可防止因該裂紋 而使裂紋傳遞至元件配線為止而產生斷線。 又，當將上述半導體元件封裝於薄膜基板上時，為了使 各基板金屬部與各元件突起電極適當藉由熱壓接而接合， 本發明之半導體裝置較理想的是，上述各元件突起電極包 含電阻為3χ10·8(Ω·ιη)以下之金屬凸塊。 如以上所述，於本發明之半導體裝置中，各基板金屬部 以及各元件金屬部呈各角朝外側突出之多角形狀，各基板 配線係連接於各自所對應之基板金屬部之與角之頂點空開 間隔之位置，各元件配線係連接於各自所對應之元件金屬 邰之與角之頂點空開間隔之位置，因此將獲得如下效果， I7即使基板金屬部元件以及元件金屬部中產生裂紋等， 亦可防止因該裂紋而使裂紋傳遞至基板配線以及元件配線 為止而產生斷線。 又，本發明之半導體裴置中，各元件金屬部呈各角朝外 側犬出之多角形狀，各元件配線係連接於各自所對應之元 136777.doc -13- 201001653 件金屬部之與角之頂點空開間隔之位置，因此將獲得如下 效果，即，即使元件金屬部中產生裂紋等’亦可防止因該 裂紋而使裂紋傳遞至元件配線為止而產生斷線。 【實施方式】 [實施形態1] 則為如下 若根據圖式對本發明之一實施形態進行說明 所述。 .圖1係表示本實施形態之半導體裝置1之-構成示例之側 視剖面圖。 如圖1所不，半導體裝置1包含以具有各種功能之方式而 構成之半導體元件n、封裝有半導體元件u之插入式基板 21/以及封裝有插入式基板21之薄膜基板31。半導體裝置 1係於TCP中具有被稱為晶片堆疊（Chip on Chip)之封裝 造的半導體裝置β 一半導體元件U以矽等之半導體材料作為主材料，具有較 薄之曰3片形狀。半導體元件11之厚度為725〜500 μηι。半導 胆元件丨1中之封裝於插入式基板2 1上之側之表面（封裝面） 呈長方形。於半導體元件11之封裝面上，形成有成為與插 入式基板21之接合要素之元件金屬凸塊12(元件突起電 極）、作為元件金屬凸塊12之基台之元件焊墊金屬13(元件 金屬部）、以及以連接元件焊墊金屬13與元件内部之方式 而引繞之元件配線1 4。 圖2U)表示半導體元件丨丨之封裝面之一構成示例。再 者’於圖2⑷中’省略元件金屬凸塊12以及元件配線以而 136777.doc 14 201001653 進行圖示。 如圖2(a)所示，元件焊墊金屬13係對應於與插入式基板 21之接合部位，沿著半導體之封裝面之四個邊㈣ 配置有複數個。詳細而t，元件焊塾金屬13於圖2⑷中， 於上邊側、即沿著長邊方向之左端至右端以相等間隔而配 置有三行，自中央朝下邊側即左邊側以及右邊側以相等間 隔而各配置有三行、以及於最τ邊之中央附近以相等間隔 而配置有一行。再者，圖2(a)僅表示一示例，元件焊墊金 屬13只要對應於與插入式基板21之接合部位而適當 可。 圖3(a)表示元件料金屬13之詳細構成。元件桿塾金屬 13自與半導體兀之封裝面垂直之方向觀察時，具有長 方形之形狀。又，元件配線14係以自元件焊墊金屬"之短 邊之直線部分、且與角之頂點空開間隔之位置起細窄延伸 之方式而配設。元件焊墊金屬13以及元件配線㈣藉由例 I 如銅而-體化亚形成圖案，其表面以形成開口部之方式而 被絕緣保護膜15所覆蓋。藉由開口部而露出銅之部分成為 進行導电連接之導電部16。於圖3(a)中，導電部16具有長 方形之形狀，但並不限於此。 兀件金屬凸塊12形成於元件焊墊金屬13上，詳細而言， ^成於絕緣保護膜15以及導電部16之上。元件金屬凸塊η —有金且具有長方體之形狀。元件金屬凸塊丨2之厚度為 8 μηι。但是，元件金屬凸塊12並不限於該形狀，只要係覆 盍至少導電部16且充分確保與插入式基板21之封裝強度之 136777.doc -15- 201001653 形狀即可，例如，亦可為立方體或球狀。又，元件金屬凸 塊12並不限於含有金，只要含有電阻為3χΐ〇、Ω·^以下之 金屬或者拉伸強度為以上之金屬即可。 插入式基板21係包含矽、化合物半導體或玻璃等之較薄 之晶片狀的基板。插入式基板21之厚度為725〜5〇〇。插 入式基板2丨中之封裝半導體元件„之側之表面（封裝面）呈 長方形。於插入式基板21之封裝面上，形成有成為與半導 體元件11之接合要素之第丨基板金屬凸塊22(基板突起電 極）、作為第1基板金屬凸塊22之基台之第i基板焊墊金屬 23(基板金屬部）、成為與薄膜基板31之接合要素之第]基板 金屬凸塊27、作為第2基板金屬凸塊27之基台之第2基板焊 墊金屬28、以及以連接第i基板焊墊金屬23與第2基板焊墊 金屬28之方式而引繞之基板配線24。 圖2(b)表示插入式基板21之封裝面之一構成示例。再 者，於圖2(b)中，省略第}基板金屬凸塊22、第2基板金屬 凸塊27以及基板配線24而進行圖示。於插入式基板2丨之封 裝面上以一點鏈線表示之區域係封裝半導體元件11之區 域第1基板知塾金屬2 3係設於上述區域内者，第2基板焊 塾金屬2 8係設於上述區域外者。 如圖2(b)所示，當於插入式基板21之封裝面上使半導體 兀件11之封裝面相向而封裝時，第1基板焊墊金屬23於與 半導體元件11之形成有元件焊墊金屬13之位置相對之位置 上配置有複數個。 圖3(b)表示第1基板焊塾金屬23之詳細構成。當自與插 136777.doc -16- 201001653 入式基板21之封裝面垂直之方向觀察時，第丨基板焊墊金 屬Μ具有較元件焊墊金屬13之尺寸更小之長方形之形狀。 又，基板配線24係以自第}基板焊墊金屬2;3之短邊之直線 部分、且與角之頂點空開間隔之位置起細窄延伸之方式而 配。又。第1基板焊塾金屬23以及基板配線24係藉由例如銘 或銅而-體化並形成圖t，其表面以形成開口部之方式而 被絕緣保護膜25所覆蓋。藉由開口部而露出銘或銅之部分 成為進行導電連接之導電部26。於圖3(b)中，導電部^具 有長方形之形狀，但並不限於此。 第1基板金屬凸塊22形成於第丨基板焊墊金屬23上，詳細 而言形成於絕緣保護膜25以及導電部26之上。第i基板金 屬凸塊22含有金’且具有長方體之形狀。第ι基板金屬凸 塊22之厚度為15师。但是，第1基板金屬凸塊22並不限於 該形狀，只要是覆蓋至少導電部26且充分確保與半導體元 件11之封裝強度之形狀即可，例如，亦可為方柱或球狀。 又，第1基板金屬凸塊22並不限於含有金，只要含有電阻 為3x10 (Ω·ιη)以下之金屬或者拉伸強度為丨〇xi〇8(pa)以上 之金屬即可。第1基板金屬凸塊22與元件金屬凸塊12分別 藉由熱壓接而接合。 如圖2(b)所示，第2基板焊墊金屬28對應於與薄膜基板 31之接合部位，沿著插入式基板21之封聚面之四個邊緣而 配置有複數個。詳細而言，第2基板焊墊金屬28於四個邊 緣刀別以相m隔而各g己設有一行。再者’圖2⑻僅表示 一示例，第2基板焊墊金屬28只要係對應於與薄膜基板31 136777.doc 201001653 之接合部位而適當配置即可。 當自與插入式基板21之封裝面垂直之方向觀察時，第2 基板焊墊金屬28具有與第1基板焊墊金屬23相同之長方形 之形狀。又，基板配線24係以自第2基板焊墊金屬28之短 邊之直線部分、且與角之頂點空開間隔之位置起細窄延伸 之方式而配設。第2基板焊墊金屬28亦係與第！基板焊墊金 屬23以及基板配線24同時，藉由例如鋁或銅而一體化並形 成圖案。第2基板焊墊金屬28之表面以形成開口部之方式 被絕緣保護膜所覆蓋。藉由開口部而露出鋁或銅之部分成 為進行導電連接之導電部。 第2基板金屬凸塊27形成於第2基板焊墊金屬“上，詳細 而言，形成於絕緣保護膜以及導電部之上。第2基板金屬 凸塊27含有金’且具有長方體之形狀。第2基板金屬凸塊 27之厚度為15 _。但是，第2基板金屬凸塊27並不限於該 形狀’只要係覆蓋至少導電部且充分確保與薄膜基板以 封裝強度之形狀即可。 溽胰丞板31係於含有 …-，「” WΡ匕峰签何上形 成含有銅之配線32而製作 Α 衣讣炙I扳。配線32中，除作為内部 引線而與插入式某# ?#人 飞土板21接合之部分、以及作為外部引線而 ”夕4接D之部分料，均被絕緣保額Μ所覆蓋。When there is a crack, the shape energy Α ^ g A is applied (the state. The stress is easily concentrated on the metal bump), so the stress is also applied to the external connection electrode 1G. The crack will start from the starting point and draw an arc. — 、 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The quality and reliability of the semiconductor device are high. In addition, when the bonding pressure is large, the probability of occurrence is low, but when the metal bump having a small bonding pressure is bonded to the internal lead, sometimes Damage may also occur on the external connection electrode of the component. For example, = in the following case: in order to make all the metal bumps are in positive contact with the inner leads, and pressed with a strong force, the height of the metal bumps is uneven. - etc., and stress concentration occurs in the highest metal bump. The present invention has been developed in view of the above problems, and an object thereof is to provide a wiring prevention In order to solve the above problems, the semiconductor device of the present invention is characterized in that it comprises a plug-in substrate on a package S substrate, and a semiconductor component packaged on the interposer substrate, the interposer substrate a plurality of substrate metal portions formed at a position where the semiconductor element is packaged, a plurality of substrate protrusion electrodes respectively formed on the substrate metal portions, and a plurality of substrate electrodes respectively connected to the substrate metal portions, wherein the semiconductor The device includes a plurality of component bump electrodes respectively connected to the substrate bump electrodes by thermocompression bonding, a plurality of component metal portions respectively formed under the respective component bump electrodes, and respectively connected to the respective components: a plurality of component wires "and a polygonal shape in which each of the substrate metal portions and the respective element portions are outwardly protruded". The respective substrate wires are connected to the respective apex portions of the corresponding pure metal portions. Position 'The above-mentioned component wirings are connected to the corresponding component metal parts The position at which the apex of the corner is spaced apart. 136777.doc 201001653 Previously, the greater the bonding pressure during thermocompression bonding, the metal portion of the substrate below the protruding electrode of the substrate, and the metal portion of the component under the protruding electrode of the element The damage is more likely to occur (damage such as cracks or cracks). This damage causes a situation in which the substrate wiring and the component wiring are broken. Further, the damage easily enters the corner where the stress tends to concentrate. In contrast, according to the above configuration, each substrate The wiring system is connected to the position of the corresponding metal portion of the substrate at a position spaced apart from the apex of the corner, and each component wiring is connected to a position at which the corresponding metal portion of the element is spaced apart from the apex of the corner. For example, cracks are generated in the substrate metal portion and the element metal portion, and it is possible to prevent the crack from being transmitted to the substrate wiring and the element wiring due to the crack. Further, when the semiconductor element is packaged on the interposer substrate, the semiconductor device of the present invention preferably has the above-mentioned substrate bump electrodes in order to bond the substrate bump electrodes and the device bump electrodes as appropriate by thermocompression bonding. And each of the element bump electrodes includes a metal bump having a resistance of 3 χ 10'8 (Ω·ιη) or less. Alternatively, the semiconductor device of the present invention is preferably applied to each of the substrate bump electrodes and the respective element bump electrodes including metal bumps having a tensile strength of 1.0 x 10 (Pa) or more. Further, in the semiconductor device of the present invention, each of the substrate bump electrodes and each of the element bump electrodes has a rectangular parallelepiped shape, and each of the element wirings is disposed on a surface of the corresponding element bump electrode that is in contact with the element metal portion. Short side. When each of the substrate bump electrodes and each of the element bump electrodes has a rectangular parallelepiped shape, the surface of the element bump electrode is connected to the element metal portion by 136777.doc -10- 201001653 by thermocompression bonding. Smaller, larger in the direction of the short side. Therefore, in the element metal portion, since the force applied to the door in the longitudinal direction is small, the breakage is less likely to occur, and since the force applied to expand in the direction of the short side is large, it is easy to be long. = A break occurred on the top. Therefore, according to the above configuration, the element wiring is disposed on the short side of the surface of the element bump electrode corresponding to the element metal portion, and the substrate bump electrode, the element bump electrode, and the element metal portion can be prevented: And the path connecting the components of the wiring is opened. Further, in the semiconductor device of the present invention, it is preferable that each of the substrate bump electrodes and the respective bump projecting electrodes have a rectangular parallelepiped shape, and the upper panel wiring is disposed on the surface of each of the opposite shores such as the + & The side substrate of the dog substrate and the metal portion of the substrate: each of the Si bump electrodes and each of the element bump electrodes has a rectangular parallelepiped shape: a pure side that is larger than the metal portion of the substrate by the thermocompression bonding on the substrate bump electrode Since the development of the direction is small and the development in the short-side direction is relatively small, the force applied to the metal portion of the substrate for the development in the longitudinal direction is small, so that the fracture is less likely to occur, and the surface is expanded in the short-side direction. The force applied is large, so it is easy to cause breakage. According to the above configuration, each of the substrate wirings is disposed on the short side of the surface of the substrate-inducing electrode corresponding to the substrate and the substrate metal portion, so that the protruding electrode, the substrate protruding electrode, and the substrate metal portion can be formed. And the path connecting the substrate wiring is broken. 136777.doc 201001653 In addition, due to the difference in thermal expansion ratio between the semiconductor device and the interposer substrate, the amount of deformation of the semiconductor device and the interposer substrate is poor. Therefore, the farther away from the center of the surface of the semiconductor element on which the element bump electrode is formed, the difference in the amount of deformation between the semiconductor element and the interposer substrate is larger. If the force generated by the thermal expansion causes a sag; if there is a break in the direction of the upward direction, there is a rupture in the above path. Therefore, in order to prevent the above-described short-side direction fracture due to thermal expansion, it is preferable that the semiconductor device of the present invention is configured such that the above-mentioned respective element bump electrodes are arranged in such a manner that 盥夂Aw — ρ and the corresponding element metal The long sides of the surfaces in contact with each other are perpendicular to the long sides of the surface of the semiconductor element on which the respective element bump electrodes are formed. Further, it is preferable that the semiconductor device of the month of the month is such that the substrate protruding electrodes are arranged in such a manner that the surface-inserted substrate which is opposed to each of the substrate protruding electrodes is formed by the second: In the above problem, the semiconductor device of the present invention is characterized in that: =, = the film substrate comprises a read substrate metal portion formed at a position where the semiconductor device is packaged, and a plurality of substrate wirings which are connected to the metal portion of the board, The upper 4 bases are joined to the metal portions of the respective substrates by the thermal plant, and the plurality of electrodes are respectively formed on the protruding portions of the respective elements, and the respective components are respectively connected to the respective components. The line 'and the metal parts of the above-mentioned respective elements are two == each of the above-mentioned element wiring lines is connected to the position of the corresponding element gold:::: corner 136777.doc -12- 201001653. In the first 4, when the stress concentration due to the unevenness of the height of the protruding electrodes of the element is generated, the larger the stress, the more easily the metal part of the element under the protruding electrode of the element is broken (crack or crack). Such as damage). This damage will cause the component n-loss to be easily broken into the corner where the stress is easily concentrated. On the other hand, according to the above configuration, each element wiring is connected to a position at which the corresponding metal portion of the substrate is spaced apart from the apex of the corner. Thereby, even if cracks and streaks are generated in the element metal portion, it is possible to prevent the crack from being transmitted to the element wiring due to the crack. Further, when the semiconductor element is packaged on a film substrate, in order to bond each of the substrate metal portions and the respective device bump electrodes by thermocompression bonding, the semiconductor device of the present invention preferably includes the respective device bump electrodes. The metal bump having a resistance of 3 χ 10·8 (Ω·ιη) or less. As described above, in the semiconductor device of the present invention, each of the substrate metal portion and each of the element metal portions has a polygonal shape in which each corner protrudes outward, and each of the substrate wirings is connected to the corner of the corresponding substrate metal portion. At the position of the gap interval, the wiring of each element is connected to the position of the corresponding element metal 空 at the apex of the corner, so that the following effects are obtained, and even if cracks occur in the metal part of the substrate and the metal part of the element, It is also possible to prevent the crack from being transmitted to the substrate wiring and the component wiring due to the crack. Further, in the semiconductor device of the present invention, the metal portions of the respective elements have a polygonal shape in which the corners are outwardly outward, and the component wirings are connected to the respective corners of the metal parts of the corresponding element 136777.doc -13 - 201001653 Since the apex is spaced apart from the space, it is possible to prevent the occurrence of cracks or the like in the element metal portion, thereby preventing the crack from being transmitted to the element wiring due to the crack. [Embodiment] [Embodiment 1] Hereinafter, an embodiment of the present invention will be described based on the drawings. Fig. 1 is a side sectional view showing an example of the configuration of the semiconductor device 1 of the present embodiment. As shown in Fig. 1, the semiconductor device 1 includes a semiconductor element n configured to have various functions, a plug-in substrate 21 on which a semiconductor element u is packaged, and a film substrate 31 on which a plug-in substrate 21 is packaged. The semiconductor device 1 is a semiconductor device having a package called a chip on chip, and a semiconductor element U is made of a semiconductor material such as tantalum as a main material, and has a thin three-chip shape. The thickness of the semiconductor element 11 is 725 to 500 μm. The surface (packaging surface) of the side of the semi-conductive element 丨1 packaged on the interposer substrate 21 has a rectangular shape. On the package surface of the semiconductor element 11, an element metal bump 12 (element bump electrode) which is a bonding element with the interposer substrate 21, and a component pad metal 13 which is a base of the element metal bump 12 are formed (element metal) And a component wiring 14 that is connected by connecting the component pad metal 13 to the inside of the component. Fig. 2U) shows an example of the configuration of a package surface of a semiconductor device. Further, in the Fig. 2 (4), the element metal bump 12 and the element wiring are omitted and 136777.doc 14 201001653 is illustrated. As shown in Fig. 2(a), the element pad metal 13 corresponds to the joint portion with the interposer substrate 21, and is disposed along the four sides (four) of the package surface of the semiconductor. In detail, in the element welding metal 13 in Fig. 2 (4), three rows are arranged at equal intervals on the upper side, that is, from the left end to the right end in the longitudinal direction, and are equally spaced from the center toward the lower side, that is, the left side and the right side. Each of the three rows is arranged, and one row is arranged at equal intervals near the center of the most τ side. Further, Fig. 2(a) shows only an example, and the element pad metal 13 may be appropriately provided in correspondence with the joint portion with the interposer substrate 21. Fig. 3(a) shows the detailed configuration of the component material metal 13. The element rod base metal 13 has a rectangular shape when viewed in a direction perpendicular to the package surface of the semiconductor crucible. Further, the element wiring 14 is disposed so as to extend narrowly from the straight portion of the short side of the element pad metal and at a position spaced apart from the apex of the corner. The element pad metal 13 and the element wiring (4) are sub-patterned by, for example, copper, and the surface thereof is covered with the insulating protective film 15 so as to form an opening. The portion of the copper exposed through the opening serves as the conductive portion 16 for electrically connecting. In Fig. 3(a), the conductive portion 16 has a rectangular shape, but is not limited thereto. The element metal bumps 12 are formed on the element pad metal 13, in particular, over the insulating protection film 15 and the conductive portion 16. The element metal bump η has gold and has a rectangular parallelepiped shape. The thickness of the component metal bump 丨 2 is 8 μηι. However, the element metal bumps 12 are not limited to this shape, as long as they are at least the conductive portion 16 and sufficiently ensure the shape of the package strength of the interposer substrate 21, for example, a cube. Or spherical. Further, the element metal bumps 12 are not limited to containing gold, and may be any metal having a resistance of 3 Å or less, or a metal having a tensile strength of at least 3.0. The interposer substrate 21 is a thin wafer-shaped substrate such as germanium, a compound semiconductor or glass. The thickness of the interposer substrate 21 is 725 to 5 Å. The surface (package surface) on the side of the packaged semiconductor element „ in the interposer substrate 2 has a rectangular shape. On the package surface of the interposer substrate 21, a second substrate metal bump 22 which is a bonding element with the semiconductor element 11 is formed. (substrate bump electrode), i-th substrate pad metal 23 (substrate metal portion) which is a base of first substrate metal bump 22, and substrate metal bump 27 which is a bonding element with film substrate 31, as The second substrate pad metal 28 of the base of the substrate metal bumps 27 and the substrate wiring 24 wound so as to connect the i-th substrate pad metal 23 and the second substrate pad metal 28. FIG. 2(b) The configuration of one of the package faces of the interposer substrate 21 is shown in Fig. 2(b), and the second substrate metal bumps 22, the second substrate metal bumps 27, and the substrate wires 24 are omitted. The region indicated by the one-dot chain line on the package surface of the interposer substrate 2 is a region in which the semiconductor element 11 is packaged. The first substrate is made of the metal 2 3 in the region, and the second substrate solder metal is provided in the region. Outside the above areas. As shown in Figure 2(b), when When the package surface of the interposer substrate 21 faces the package surface of the semiconductor element 11 and is packaged, the first substrate pad metal 23 is disposed at a position opposing the position where the element pad metal 13 of the semiconductor element 11 is formed. Fig. 3(b) shows the detailed structure of the first substrate pad metal 23. When viewed from the direction perpendicular to the package surface of the 136777.doc -16-201001653 input substrate 21, the second substrate pad metal Μ It has a rectangular shape smaller than the size of the component pad metal 13. Further, the substrate wiring 24 is spaced apart from the apex of the corner from the straight portion of the short side of the substrate pad metal 2; Further, the first substrate pad metal 23 and the substrate wiring 24 are formed by, for example, inscription or copper, and the surface is formed to be insulated by forming an opening. The film 25 is covered by the opening portion to expose the portion of the inscription or the copper to the conductive portion 26 for electrically connecting. In Fig. 3(b), the conductive portion has a rectangular shape, but is not limited thereto. Metal bumps 22 are formed on the second substrate pad The genus 23 is formed in detail on the insulating protective film 25 and the conductive portion 26. The i-th substrate metal bump 22 contains gold 'and has a rectangular parallelepiped shape. The thickness of the ι substrate metal bump 22 is 15 divisions. The first substrate metal bump 22 is not limited to this shape, and may be a shape that covers at least the conductive portion 26 and sufficiently secures the package strength with the semiconductor element 11, and may be, for example, a square pillar or a spherical shape. The substrate metal bump 22 is not limited to containing gold, and may have a metal having a resistance of 3×10 (Ω·ιη) or less or a metal having a tensile strength of 丨〇xi 8 (pa) or more. The first substrate metal bump 22 and the element metal bumps 12 are joined by thermocompression bonding, respectively. As shown in Fig. 2(b), the second substrate pad metal 28 is disposed at a plurality of edges along the four edges of the sealing surface of the interposer substrate 21 corresponding to the bonding portion with the film substrate 31. Specifically, the second substrate pad metal 28 is provided with a row in each of the four edge knives. Further, Fig. 2 (8) shows only an example, and the second substrate pad metal 28 may be disposed as appropriate in accordance with the joint portion with the film substrate 31 136777.doc 201001653. The second substrate pad metal 28 has the same rectangular shape as the first substrate pad metal 23 when viewed from a direction perpendicular to the package surface of the interposer substrate 21. Further, the substrate wiring 24 is disposed so as to extend narrowly from a straight portion of the short side of the second substrate pad metal 28 so as to be spaced apart from the apex of the corner. The second substrate pad metal 28 is also the same! The substrate pad metal 23 and the substrate wiring 24 are simultaneously integrated and patterned by, for example, aluminum or copper. The surface of the second substrate pad metal 28 is covered with an insulating protective film so as to form an opening. The portion of the aluminum or copper is exposed by the opening to form a conductive portion for electrically connecting. The second substrate metal bump 27 is formed on the second substrate pad metal "in detail, and is formed on the insulating protective film and the conductive portion. The second substrate metal bump 27 contains gold" and has a rectangular parallelepiped shape. 2 The thickness of the substrate metal bump 27 is 15 _. However, the second substrate metal bump 27 is not limited to the shape 'as long as it covers at least the conductive portion and sufficiently ensures the shape of the package with the film substrate. The board 31 is formed by including a ...-, "W" peak to form a copper-containing wiring 32 to make a jacket. In the wiring 32, the portion joined to the plug-in type ### human soil plate 21 as the inner lead and the portion which is the outer lead and the "fourth-side D" are covered by the insulation guarantee.

當於薄膜基板3+ A 土板之形成有内部引線之面上使插入式基板 2 1之封裝面相向而抖祐主 封虞時，配線32中之内部引線於與插入 式基板21之形成有第2 屬8之位置相對之位置 上配置有複數個，第9其 弟2基板知墊金屬28與内部引線分別藉 136777.doc ，18- 201001653 由ILB而接合。 又，薄膜基板31具有長方形之孔34。當使插入式基板幻 封裝於薄膜基板31上時，孔34係以封裝於插入式基板21上 之半導體元件11不會與薄膜基板31發生干涉之尺寸及位置 而設置。插入式基板21與薄膜基板31之間之間隙，半導體 元件11與插入式基板2 1之間之間隙、以及半導體元件丨丨與 薄膜基板3 1之間之間隙係藉由底層填充材料3 5而填充。 繼而，對具有上述構成之半導體裝置丨之製造方法進行 說明。 首先，藉由先前所存在之各種製作方法，於半導體元件 11插入式基板2 1以及薄膜基板3 i上分別形成下述構成要 素亦即，於半導體兀件丄丄上形成元件金屬凸塊元件 焊墊金屬13以及元件配線14β於插入式基板21上形成糾 基板金屬凸塊22、第i基板焊塾金屬23、第2基板金屬凸塊 ，第2基板浑塾金屬28以及基板配線24。於薄膜基板3丄 上形成配線32、絕緣保護膜33以及孔34。 ，而，-面參照圖4⑷〜⑷，—面對半導體元件u、插 入式基板21以及薄膜基板31之封裝方法進行詳細說明。 圖4⑷〜(d)係表示半導體裝置1之封裝流程之圖。 =a)所不，將薄膜基板似置於封裝裝置（未圖示） 之位1時，薄膜基板31係被按壓並固定於未形成有配㈣ 使插入式基板21之封裝面 之面相向’並施加熱及壓 繼而，如圖4(b)所示，—方面When the package surface of the interposer substrate 21 is opposed to the main package on the surface of the film substrate 3+A soil plate on which the inner leads are formed, the inner leads of the wiring 32 are formed with the interposer substrate 21. The second genus 8 is disposed at a plurality of positions relative to each other, and the ninth dynasty 2 substrate is known to be bonded to the inner lead by 136777.doc, 18-201001653 by the ILB. Further, the film substrate 31 has a rectangular hole 34. When the interposer substrate is magically packaged on the film substrate 31, the holes 34 are provided in such a size and position that the semiconductor element 11 packaged on the interposer substrate 21 does not interfere with the film substrate 31. The gap between the interposer substrate 21 and the film substrate 31, the gap between the semiconductor element 11 and the interposer substrate 21, and the gap between the semiconductor element 丨丨 and the film substrate 31 are by the underfill material 35. filling. Next, a method of manufacturing the semiconductor device having the above configuration will be described. First, by the various fabrication methods previously formed, the following components are formed on the interposer substrate 21 and the thin film substrate 3 i of the semiconductor device 11, that is, the device metal bump device is formed on the semiconductor device The pad metal 13 and the element wiring 14β form the correction substrate metal bump 22, the i-th substrate pad metal 23, the second substrate metal bump, the second substrate base metal 28, and the substrate wiring 24 on the interposer substrate 21. A wiring 32, an insulating protective film 33, and a hole 34 are formed on the film substrate 3A. Further, the method of encapsulating the semiconductor element u, the interposer substrate 21, and the film substrate 31 will be described in detail with reference to Figs. 4(4) to 4(4). 4(4) to (d) are diagrams showing the packaging flow of the semiconductor device 1. = a) If the film substrate is placed in the position of the package device (not shown), the film substrate 31 is pressed and fixed to the surface where the package surface of the interposer substrate 21 is not formed. And applying heat and pressure, as shown in Figure 4(b),

與薄膜基板3 1 # 士、女& A 似' 1 <形成有内部引線 136777.doc ，19· 201001653 力，-方面將插入式基板2】之第2基板金屬凸塊mThe film substrate 3 1 #士,女 & A is like '1 < formed with internal leads 136777.doc, 19·201001653 force, - the second substrate metal bump of the insert substrate 2]

壓）至薄膜基板31之内邱与丨始、，人B ^ 門邓引線，亚以金-錫共晶而接合。亦 即，猎由ILB而將插λ _4*，#』a 予播入式基板21封裝於薄膜基板31上。此 時’係使金-錫Jt S _^人 ，、曰曰而接合，因此於熱壓接時無需較大之 接合壓力。 .塵而如圖4之（c)所示，使半導體元件11穿過薄膜基板 31之孔34_。接著，—方面使半導體元件U之封裝面舆插 入式基板21之封裝面相向，並施加熱及廢力，—方面將半 導體元件11之元件金屬凸塊12®接至插入式基板21之第i 基板金屬凸塊22而接合。㈣，係使金彼此接合，因此於 熱壓接時會施加較大之接合壓力。再者，按壓插入式基板 2 1之與封裝面相反之側的面。 繼而’如圖4之⑷所示，於插入式基板21與薄膜基板31 之間之間隙、半導體元件11與插入式基板21之間之間隙、 以及半導體元件11與薄膜基板31之間之間隙注入並填充底 層填充材料35。藉此，半導體裝置1製作完成。 如以上所述’於半導體裝置1中’於將半導體元件u封 衣於插入式基板21上時，為了使含有金之元件金屬凸塊u 與含有金之第1基板金屬凸塊22接合，而施加有較大之接 口I力。其原因在於，含有金且拉伸強度較強之金屬 (1.108(Pa)以上之金屬）係即使施加較弱之壓力亦不會引 起塑性變形’從*難以利則交弱之壓力來接合之材料。 因此，上述材料必需施加較強之壓力來進行接合，故而 更容易弓丨起元件焊墊金屬13以及第丨基板焊墊金屬U產生 136777.doc •20· 201001653 破損（裂紋或破裂等之損傷）。因此，在先前，如圖u所 示，存在S較大之接合壓力，而使得位於各金屬凸塊之下 之外部連接電極⑻產生I紋之問題m成為導致配 線102斷線之事態的重大問題。 因此，本發明之發明者對上述問題進行了驗證。其結果 發現’當位於金屬凸塊之下之外部連接電極ι〇ι產生裂紋 夺°亥表紋令易進入至應力容易集中之角為止。亦即已得 知，裂紋係以傳遞能量朝向外部連接電極ι〇ι之存在角之 位置穿行之方式而產生。Pressed to the inside of the film substrate 31, Qiu and Qi, the human B ^ Men Deng lead, sub-jointed with gold-tin eutectic. That is, the blasting λ_4*, #』a is inserted into the film substrate 31 by the ILB. At this time, the gold-tin Jt S _^ is joined and joined, so that no large bonding pressure is required at the time of thermocompression bonding. Dust is as shown in Fig. 4(c), and the semiconductor element 11 is passed through the hole 34_ of the film substrate 31. Then, the package surface of the semiconductor device U is opposed to the package surface of the interposer substrate 21, and heat and waste force are applied, and the element metal bump 12® of the semiconductor element 11 is connected to the i-th of the interposer substrate 21. The substrate metal bumps 22 are joined. (4) The gold is joined to each other, so that a large joint pressure is applied during the thermocompression bonding. Further, the surface of the interposer substrate 21 opposite to the package surface is pressed. Then, as shown in (4) of FIG. 4, a gap between the interposer substrate 21 and the film substrate 31, a gap between the semiconductor element 11 and the interposer substrate 21, and a gap between the semiconductor element 11 and the film substrate 31 are injected. The underfill material 35 is filled. Thereby, the semiconductor device 1 is completed. When the semiconductor element u is sealed on the interposer substrate 21 as described above, in order to bond the gold-containing element metal bump u to the gold-containing first substrate metal bump 22, Apply a large interface I force. The reason for this is that a metal containing a strong tensile strength (a metal having a tensile strength of 1.108 (Pa) or more) is a material which is not plastically deformed even if a weak pressure is applied, and is bonded by a pressure which is difficult to cope with. Therefore, the above materials must be applied with a strong pressure to bond, so that it is easier to bow the component pad metal 13 and the second substrate pad metal U to generate 136777.doc • 20· 201001653 damage (crack or crack damage) . Therefore, in the prior art, as shown in Fig. u, there is a large joint pressure of S, and the problem that the external connection electrode (8) located under each metal bump produces an I pattern becomes a major problem that causes the wiring 102 to be broken. . Therefore, the inventors of the present invention verified the above problems. As a result, it was found that when the external connection electrode ι〇ι located under the metal bumps is cracked, it is easy to enter the corner where the stress is easily concentrated. That is, it has been known that the crack is generated in such a manner that the transfer energy passes toward the position where the external connection electrode ι is located.

基於上述況，半導體裝置丨具有如下構成··於半導體 元件11中，將除了無助於動作之虛設配線等以外的、嚴禁 產生斷線之7L件配線14配設於位於元件金屬凸塊12之下的 兀件焊墊金屬13之與角之頂點空開間隔之位置，且於插入 式基板21上，將除了無助於動作之虛設部配線等以外的、 嚴禁產生斷線之基板配線24配設於位於第丨基板金屬凸塊 22之下的第1基板焊墊金屬23之與角之頂點空開間隔之位 置。藉此，即使元件焊墊金屬13以及第1基板焊墊金屬23 產生裂紋，亦可防止因該裂紋而使裂紋傳遞至元件配線14 或基板配線24為止而產生斷線。 再者’於上述半導體裝置1中’在薄膜基板Η上，亦可 於封I插入式基板2 1之部分以外之區域適當封裝其他晶片 電容器等。又’亦可於元件金屬凸塊12與元件焊塾金屬13 之間、第1基板金屬凸塊22與第1基板焊墊金屬23之間、以 及第2基板金屬凸塊27與第2基板焊墊金屬28之間，設置益 136777.doc -21 - 201001653 不進行訊號之輸入輸出之虛設配線。 又’於半導體裝置1中，半導體元件丨丨中之元件焊墊金 屬13、以及插入式基板21中之第1基板焊墊金屬23及第2基 板焊墊金屬2 8並不限於上述形狀’而亦可為各角朝外側突 出之多角形狀。但是較理想的是，外形形狀之直線部分大 於元件配線14或基板配線24之寬度。圖5(a)及表示一示 例。 圖5(a)表示正六角形之焊墊金屬51a之一構成示例。配線 52a係以自焊墊金屬5 1 a之直線部分、且與角之頂點空開間 隔之位置起細窄延伸之方式而配設。圖5(b)表示八角形之 焊墊金屬51b之一構成示例。配線52b係以自焊墊金屬 之直線部分、且與角之頂點空開間隔之位置起細窄延伸之 方式而配設。於圖5⑷(b)之任一構成中，其表面均係以形 成適當形狀之開口部之方式而被絕緣保護膜所覆蓋。 此處，就防止斷開之產生的方面而言更好的是，當半導 體7G件11之元件金屬凸塊12、以及插入式基板21之第1基 板金屬凸塊22具有長方體之形狀時，於元件金屬凸塊^之 與元件焊墊金屬13相接之面（以下，簡寫為元件凸塊底面） 之短邊側配置元件配線〗4，且於第〗基板金屬凸塊U之與 第1基板焊塾金屬23相接之面（以下，簡寫為基板凸塊底面） 之短邊側配置基板配線24。 圖6係表示元件金屬凸塊12與第】基板金屬凸塊^進行献 產接時之各封裝面之展開的圖。於圖6中，將元件金屬凸 塊12以及第i基板金屬凸塊22一併記作凸塊。又，幻方向 136777.doc •22- 201001653 以及Y1方向分別表示元件凸塊底面及基板凸塊底面之短邊 方向及長邊方向。 子元件五屬凸塊12與第1基板金屬凸塊22進行熱壓接 寺如圖6所不，各金屬凸塊會因該壓力而朝與封裝面平 仃之方向（橫向：X1方向以及幻方向）展開。因此，伴隨著 元:金屬凸塊12之橫向展開，對固定元件金屬凸㈣之元 件焊墊金屬13亦施加朝相同之橫向展開之力。此時，當施 1至7C件焊塾金屬13之力較大時，元件焊塾金屬η將產生 斷裂而引起斷開。又，伴隨著第丨基板金屬凸塊22之橫向 展開，第1基板焊墊金屬23中亦會產生同樣之現象。 此田元件金屬凸塊12以及第1基板金屬凸塊22具有 長方體之形狀時，將考慮到於元件凸塊底面以及基板凸塊 底面，對長邊之中點與短邊之中點之間之微小區域所施加 之朝橫向展開之力。 此％ ’於長邊之中點’朝Y1方向之展開會因由鄰接之微 小區域之金屬凸塊所支持而縮小。再者，若長邊之長度無 限大，則朝Y1方向之展開為零，藉由熱壓接而產生之與金 屬凸塊厚度之減少部分等量之體積之金屬將朝X1方向展 開。 另方面’於紐邊之中點，朝X1方向之展開會因由鄰接 之微小區域所支持之力較弱而增大。並且’由於在幻方向 上亦會展開，因此力會分散’使得Y1方向之展開比較小。 再者’若短邊之長度接近於零’則於短邊之中點之展開為 「Y1方向-XI方向」。 136777.doc -23- 201001653 因此’ Y1方向之焊墊金屬難以產生斷裂，而X1方向之 焊塾金屬容易產生斷裂。亦即’元件焊墊金屬13以及第j 基板焊塾金屬23中’由於為了朝元件凸塊底面以及基板凸 塊底面之長邊方向展開而施加之力較小，因此難以產生斷 裂，而由於為了朝元件凸塊底面以及基板凸塊底面之短邊 方向展開而施加之力較大，故而容易朝元件凸塊底面以及 基板凸塊底面之長邊方向產生斷裂。 由於所產生之裂紋朝向焊墊金屬之存在角之位置傳遞， 因此當以連接焊墊金屬之角與角之方式而產生裂紋並導致 太干墊金屬產生斷裂時，被分離之部分呈孤立狀態。因此， 當被分離之部分連接有配線時’會產生斷開。上述被分離 之邛刀位於元件凸塊底面以及基板凸塊底面之長邊側的情 況將增多。 因此，較理想的是，使元件配線14以及基板配線24自 件凸塊底面以及基板凸塊底面之短邊側伸出。藉此，即 於兀件焊塾金屬13以及第丨基板焊墊金屬23朝元件凸塊 面以及基板凸塊底面之長邊方向產生斷裂之情形時，亦 防止與元件配線14、元件焊塾金屬13、元件金屬凸塊Η 第1基板金屬凸塊22、第1基板焊塾金屬23、以及基板配 24連接之路徑產生斷開。 ，又，由於半導體元件u與插入式基板2ι之熱膨脹率 差，故+導體元件η與插入式基板21 例如，假設半導體元件u之敎膨 .、、、％脹率較大，而插入式基 2 1之熱膨嚴率較小。圖7矣- 千罕乂』® 7表不此時之各構件之變形量。 136777.doc -24- 201001653 半導體元件11之封裝面以及插入式基板21之封裝面為長方 形時，半導體元件1 1以及插入式基板2 i以封裝面之中央附 近為中心而朝長邊方向以及短邊方向變形。 因此，如以圖7所標之箭頭長度所示，越是遠離封裝面 之中心，半導體元件丨丨與插入式基板2丨之變形量之差越將 立曰大。變开々直之差越大，施加至元件凸塊金屬丨3以及第丄 基板焊墊金屬23之力越成比例地增大。又，施加至元件焊 墊金屬13以及第1基板焊墊金屬23之力大於施加至配置於 封裝面之長邊方向之端側者之力。 因此，虽上述力增大時，如圖丨丨所示，元件焊墊金屬13 以及第1基板焊墊金屬23將產生斷裂。若裂紋以連接元件 凸塊底面以及基板凸塊底面之短邊方向上之角與角之方式 而進入，則上述路徑有可能產生斷開。 因此，當元件金屬凸塊12以及第i基板金屬凸塊22具有 長方體之形狀，且具有自元件凸塊底面以及基板凸塊底面 之短邊側#，配設有&件配線14以及基板配線24之構成 時’較理想的是’以半導體元件Μ封裝面之長邊與元件 金屬凸塊12之元件凸塊底面之長邊垂直之方式來配置元件 金屬凸塊12 ’且以插入式基板21之封裝面之長邊與第以 板金屬凸塊22之基板凸塊底面之長邊垂直之方式來配置第 1基板金屬凸塊22。圖2(a)及圖2(b)圖示該構成。 藉此’可防止藉由熱膨脹而於元件焊墊金_以及第i 基板焊塾金屬23中’以連接元件凸塊底面以及基板凸塊底 面之短邊方向上之角與角之方式而產生裂紋。因此，可防 136777.doc •25· 201001653 止上述路徑產生斷開。In the semiconductor device 11, the semiconductor device 11 has the following configuration: In the semiconductor device 11, the 7L wiring 14 that is not allowed to be broken except for the dummy wiring that does not contribute to the operation is disposed in the component metal bump 12 The lower electrode pad metal 13 is spaced apart from the corner of the corner, and the substrate wiring 24 is not allowed to be broken except for the dummy portion wiring which does not contribute to the operation on the interposer substrate 21. The first substrate pad metal 23 located under the second substrate metal bump 22 is spaced apart from the apex of the corner. As a result, even if the element pad metal 13 and the first substrate pad metal 23 are cracked, it is possible to prevent the crack from being transmitted to the element wiring 14 or the substrate wiring 24 due to the crack. Further, in the above-described semiconductor device 1, 'on the film substrate ,, another wafer capacitor or the like may be appropriately packaged in a region other than the portion of the package-inserted substrate 2 1 . Further, it is also possible to solder between the element metal bump 12 and the component pad metal 13, between the first substrate metal bump 22 and the first substrate pad metal 23, and between the second substrate metal bump 27 and the second substrate. Between the mat metal 28, the setting 136777.doc -21 - 201001653 does not carry out the dummy wiring of the input and output of the signal. Further, in the semiconductor device 1, the element pad metal 13 in the semiconductor device and the first substrate pad metal 23 and the second substrate pad metal 28 in the interposer substrate 21 are not limited to the above shape ' It can also be a polygonal shape in which the corners protrude outward. However, it is preferable that the straight portion of the outer shape is larger than the width of the component wiring 14 or the substrate wiring 24. Fig. 5(a) shows an example. Fig. 5(a) shows an example of the configuration of one of the positive hexagonal pad metal 51a. The wiring 52a is disposed so as to extend narrowly from the straight portion of the pad metal 5 1 a and at a position spaced apart from the apex of the corner. Fig. 5(b) shows an example of the configuration of one of the octagonal pad metal 51b. The wiring 52b is disposed so as to extend narrowly from the straight portion of the pad metal and at a position spaced apart from the apex of the corner. In any of the configurations of Fig. 5 (4) and (b), the surface thereof is covered with an insulating protective film so as to form an opening of an appropriate shape. Here, in terms of preventing the occurrence of the disconnection, when the element metal bump 12 of the semiconductor 7G member 11 and the first substrate metal bump 22 of the interposer substrate 21 have a rectangular parallelepiped shape, The short side of the element metal bumps on the surface of the element pad metal 13 (hereinafter, abbreviated as the bottom surface of the element bump) is disposed on the short side, and the first substrate is formed on the first substrate metal bump U and the first substrate. The substrate wiring 24 is disposed on the short side of the surface where the solder metal 23 is in contact (hereinafter, abbreviated as the bottom surface of the substrate bump). Fig. 6 is a view showing the development of the respective package faces when the element metal bumps 12 and the substrate metal bumps are assembled. In Fig. 6, the element metal bumps 12 and the i-th substrate metal bumps 22 are collectively referred to as bumps. Further, the magic direction 136777.doc •22-201001653 and the Y1 direction indicate the short side direction and the long side direction of the bottom surface of the element bump and the bottom surface of the substrate bump, respectively. The sub-element five-bump 12 and the first substrate metal bump 22 are thermo-compressed. As shown in FIG. 6, each metal bump may be in a direction perpendicular to the package surface due to the pressure (lateral direction: X1 direction and illusion). Direction) Expand. Therefore, with the lateral expansion of the metal bumps 12, the component pad metal 13 of the fixing member metal bump (4) is also biased toward the same lateral direction. At this time, when the force of applying the 1 to 7C pieces of the yttrium metal 13 is large, the element yttrium metal η will be broken to cause disconnection. Further, the same phenomenon occurs in the first substrate pad metal 23 along with the lateral development of the second substrate metal bumps 22. When the field element metal bump 12 and the first substrate metal bump 22 have a rectangular parallelepiped shape, the bottom surface of the element bump and the bottom surface of the substrate bump are considered, and between the midpoint of the long side and the midpoint of the short side. The force exerted by the tiny areas in the lateral direction. The expansion of this % 'in the middle of the long side" toward the Y1 direction is reduced by the support of the metal bumps of the adjacent small areas. Further, if the length of the long side is not large, the expansion in the Y1 direction is zero, and the metal of the volume equivalent to the reduction of the thickness of the metal bump by the thermocompression bonding is spread toward the X1 direction. On the other hand, in the middle of the New Zealand side, the expansion in the X1 direction will increase due to the weaker force supported by the adjacent small areas. And because the force is also unfolded in the magical direction, the force will be dispersed so that the development of the Y1 direction is relatively small. Furthermore, if the length of the short side is close to zero, the point in the short side is expanded to "Y1 direction - XI direction". 136777.doc -23- 201001653 Therefore, the pad metal in the Y1 direction is hard to break, and the solder metal in the X1 direction is prone to breakage. In other words, the 'component pad metal 13 and the j-th substrate pad metal 23' are less likely to be applied in order to spread toward the longitudinal direction of the bottom surface of the element bump and the bottom surface of the substrate bump, and thus it is difficult to cause breakage. Since the force applied to the bottom surface of the element bump and the bottom surface of the substrate bump is large, the force is easily generated in the longitudinal direction of the bottom surface of the element bump and the bottom surface of the substrate bump. Since the generated crack is transmitted toward the position of the presence angle of the pad metal, when the crack is generated in such a manner as to connect the corner metal and the corner of the pad metal and the dry pad metal is broken, the separated portion is in an isolated state. Therefore, when the separated portion is connected with wiring, a disconnection occurs. The above-mentioned separated boring tool is placed on the long side of the bottom surface of the element bump and the bottom surface of the substrate bump. Therefore, it is preferable that the element wiring 14 and the substrate wiring 24 protrude from the short side of the bottom surface of the bump and the bottom surface of the substrate bump. Thereby, when the element welding metal 13 and the second substrate pad metal 23 are broken toward the longitudinal direction of the element bump surface and the substrate bump bottom surface, the component wiring 14 and the component solder metal are also prevented. 13. Element Metal Bump 路径 The path of the first substrate metal bump 22, the first substrate pad metal 23, and the substrate 24 is disconnected. Further, since the thermal expansion coefficient of the semiconductor element u and the interposer substrate 2 is inferior, the +conductor element η and the interposer substrate 21 are assumed to have a large expansion ratio, for example, a large expansion ratio of the semiconductor element u, and a plug-in type. The thermal expansion rate of 2 1 is small. Figure 7矣- 千罕乂』7 shows the amount of deformation of each component at this time. 136777.doc -24- 201001653 When the package surface of the semiconductor element 11 and the package surface of the interposer substrate 21 are rectangular, the semiconductor element 1 1 and the interposer substrate 2 i are oriented toward the long side and the center around the center of the package surface. Deformed in the side direction. Therefore, as indicated by the length of the arrow indicated in Fig. 7, the farther away from the center of the package surface, the difference in the amount of deformation between the semiconductor element 丨丨 and the interposer substrate 2丨 becomes larger. The larger the difference in the straightening, the more the force applied to the element bump metal 丨3 and the second substrate pad metal 23 increases proportionally. Further, the force applied to the element pad metal 13 and the first substrate pad metal 23 is greater than the force applied to the end side disposed in the longitudinal direction of the package surface. Therefore, when the above force is increased, the element pad metal 13 and the first substrate pad metal 23 are broken as shown in FIG. If the crack enters by the angle and the angle between the bottom surface of the bump of the connecting member and the bottom surface of the bottom surface of the substrate bump, the above-mentioned path may be broken. Therefore, when the element metal bumps 12 and the i-th substrate metal bumps 22 have a rectangular parallelepiped shape and have a short side side # from the bottom surface of the element bump and the bottom surface of the substrate bump, the & wiring 14 and the substrate wiring are disposed. In the case of the configuration of 24, it is preferable that the element metal bump 12' is disposed such that the long side of the semiconductor element package surface is perpendicular to the long side of the element bump bottom surface of the element metal bump 12 and the interposer substrate 21 is formed. The first substrate metal bump 22 is disposed such that the long side of the package surface is perpendicular to the long side of the bottom surface of the substrate bump of the plate metal bump 22. 2(a) and 2(b) illustrate this configuration. Therefore, it is possible to prevent cracks from occurring in the element pad gold _ and the i-th substrate pad metal 23 by thermal expansion to connect the bottom surface of the element bump and the short side direction of the bottom surface of the substrate bump. . Therefore, it is possible to prevent 136777.doc •25· 201001653 from being disconnected.

[實施形態2J 右根據圖式對本發明之其他實施形態進行說明，則為如 二述:再者，本實施形態中所說明者以外之構成與上述 相同。又’為了便於說明’對與上述實施形態1 之圖式中所不之構件具有相同功能之構件附以相同符號， 並省略其說明。 圖8係表示本實施形態之半導體裝置4〇之一構成示例之 側視剖面圖。 如圖8所示，半導體裝置40包含半導體元件U、以及封 裝有半導體元件U之薄膜基板41。半導體裝置4〇係具有被 稱為⑶F等之封裝構造者，例如，可用作液晶面板之源極 驅動器。 薄膜基板41係於含有聚醯亞胺等之薄膜之絕緣基材上形 成含有銅之配線42而製作之基板。於配線42中，除作為内 部引線而與半導體元件11接合之部分、以及作為外部引線 而與外部接合之部分以外，均被絕緣保護膜们所覆蓋。 當於薄膜基板41之形成有内部引線之面上使半導體元件 11之封裝面相向而封裝時，配線42中之内部引線於與半導 體几件11之形成有元件金屬凸塊12之位置相對之位置配置 2複數個。元件金屬凸塊12與内部引線分別藉由ILB而接 合。又，半導體元件11與薄膜基板41之間之間隙藉由底層 填充材料45而填充。 曰 具有上述構成之半導體裝置40中，將半導體元件丨丨封裝 136777.doc -26- 201001653 於薄胰基板41上時，係使含有金之元件金屬凸塊12與經鍍 錫之内部引線共晶而接合，因此熱壓接之接合壓力較小。 但是，為了使元件金屬凸塊12均確實地與内部引線接 觸έ以較強之力加以按壓，故而有時會因元件金屬凸塊 12之高度之不均一等，而使應力集中產生於最高之元件金 屬凸塊12中。當所產生之應力較大時，位於已產生應力集 中之元件金屬凸塊12之下的元件焊墊金屬13會產生破損。 裂紋容易以使傳遞之能量朝向元件焊墊金屬13之存在角之 位置穿行之方式而產生。 因此，半導體裝置4〇具有如下構成：使半導體元件U中 之元件配、泉1 4均配设於位於元件金屬凸塊〖2之下的元件焊 墊金屬13之與角之頂點空開間隔之位置。藉此，即使元件 焊塾金屬13產生裂紋，亦可防止因該裂紋而使裂紋傳遞至 元件配線14為止而產生斷線。 一本叙明亚不限定於上述各實施形態，而可於請求項所揭 不之把圍内進行各種變更’關於將不同實施形態中所分別 揭示之技術手段加以適當組合而獲得之實施形態，亦包含 於本發明之技術範圍内。 [產業上之可利用性] 本發明不僅可較佳用於期望防止因金屬凸塊之接合應力 而產生之破損所引起的配線之斷線的半導體裝置之相關領 域’而且可較佳用於製造半導體裝置之相關領域，例如， 形成配線圖案之相關領域’進而亦可廣泛用於包含半導體 裝置之設備之領域。 136777.doc -27· 201001653 【圖式簡單說明】 圖1係表示本發明之半導體裝置之一 視圖； 實施形態之剖 面側 圖2係表示設於上述半導體裝置上之各構件之封裝面之 構成之俯視圖，圖2⑷表示設於上述半導體裝置上之 體元件之封裝面之構成，圖2(b)表示設於上述半導體裝置 上之插入式基板之封裝面之構成； 圖3係表示設於上述半導體裝置上之各構件之封裝面之 構成之俯視圖，圖3(a)表示上述半導體元件之封裝面之元 件焊塾金屬以及元件配線之構成，圖3(b)表示上述插入式 基板之第1基板焊墊金屬以及基板配線之構成； 圖4⑷〜(d)係表示上述半導體|置之封裝步驟之剖面側 視圖； 圖5係表示焊墊金屬以及配線之其他構成之俯視圖，圖 5(a)表示正六角形之焊墊金屬之構成示例，圖5(b)表示八 角形之焊墊金屬之構成示例； 圖6係表示熱壓接時之金屬凸塊之展開之圖； 圖7係概念性地表示上述半導體裝置之半導體元件以及 插入式基板於熱膨脹時之變形之圖； 圖8係表示本發明之半導體裝置之其他實施形態之剖面 側視圖； 圖9係表示先前之半導體裝置之外部連接金屬配線部以 及内部金屬配線之構成之俯視圖； 圖10係表示先前之半導體裝置之外部連接電極以及配線 136777.doc •28- 201001653 之圖案例之俯視圖；及 圖π係表示上述外部連接電極中產 王有裂紋時 俯視圖。 【主要元件符號說明】 1 半導體裝置 11 半導體元件 12 元件金屬凸塊（元件突起電才 13 元件焊墊金屬（元件金屬部） 14 元件配線 15 絕緣保護膜 16 導電部 21 插入式基板 22 第1基板金屬凸塊（基板突起 23 第1基板焊墊金屬（基板金屬 24 基板配線 25 絕緣保護膜 26 導電部 27 第2基板金屬凸塊 28 第2基板焊墊金屬 31 薄膜基板（基板） 32 配線 33、43 絕緣保護膜 34 35、45 底層填充材料 136777.doc 之狀態 之 -29- 201001653 40 半導體裝置 41 薄膜基板 42 配線（基板金屬部、基板配線） 136777.doc -30-[Embodiment 2J] The other embodiments of the present invention will be described with reference to the drawings. The configuration of the present embodiment is the same as that described above. Further, members having the same functions as those of the members of the above-described first embodiment are denoted by the same reference numerals, and their description will be omitted. Fig. 8 is a side sectional view showing an example of the configuration of a semiconductor device 4 of the present embodiment. As shown in Fig. 8, the semiconductor device 40 includes a semiconductor element U and a film substrate 41 on which the semiconductor element U is mounted. The semiconductor device 4 has a package structure called a CDF or the like, and can be used, for example, as a source driver of a liquid crystal panel. The film substrate 41 is formed by forming a wiring 42 containing copper on an insulating substrate containing a film of polyimide or the like. The wiring 42 is covered with an insulating protective film except for a portion joined to the semiconductor element 11 as an internal lead and a portion joined to the outside as an external lead. When the package surface of the semiconductor element 11 is opposed to each other on the surface of the film substrate 41 on which the internal leads are formed, the inner leads in the wiring 42 are opposed to the positions of the semiconductor pieces 11 on which the element metal bumps 12 are formed. Configure 2 multiples. The element metal bumps 12 and the inner leads are respectively joined by the ILB. Further, the gap between the semiconductor element 11 and the film substrate 41 is filled by the underfill material 45. In the semiconductor device 40 having the above configuration, when the semiconductor device is packaged on the thin pancreatic substrate 41, the gold-containing component metal bump 12 and the tin-plated inner lead are eutectic. With the joining, the joining pressure of the thermocompression bonding is small. However, in order to make the element metal bumps 12 reliably contact with the inner leads and press them with a strong force, the stress concentration may be generated at the highest due to the unevenness of the height of the element metal bumps 12 and the like. The component is in the metal bump 12. When the generated stress is large, the component pad metal 13 located under the element metal bump 12 in which the stress is concentrated may be damaged. The crack is easily generated in such a manner that the transmitted energy is directed toward the existence angle of the component pad metal 13. Therefore, the semiconductor device 4A has a configuration in which the elements of the semiconductor element U and the springs 14 are disposed at an apex of the corners of the element pad metal 13 located under the element metal bumps 〖2. position. Thereby, even if cracks occur in the element bead metal 13, it is possible to prevent the crack from being transmitted to the element wiring 14 due to the crack. A description of the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are obtained. It is also included in the technical scope of the present invention. [Industrial Applicability] The present invention can be preferably used not only in the field of semiconductor devices in which it is desired to prevent wire breakage due to breakage of metal bumps, but also in manufacturing. Related fields of semiconductor devices, for example, related fields in which wiring patterns are formed, can be widely used in the field of devices including semiconductor devices. 136777.doc -27·201001653 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a semiconductor device according to the present invention; FIG. 2 is a cross-sectional side view showing the configuration of a package surface of each member provided on the semiconductor device. 2(4) shows the structure of the package surface of the body element provided on the semiconductor device, and FIG. 2(b) shows the structure of the package surface of the interposer substrate provided on the semiconductor device; FIG. 3 shows the structure of the semiconductor package provided in the semiconductor device; FIG. 3(a) shows the configuration of the component pad metal and the component wiring of the package surface of the semiconductor device, and FIG. 3(b) shows the first substrate of the interposer substrate. 4(4) to 4(d) are cross-sectional side views showing the steps of packaging the semiconductors; and FIG. 5 is a plan view showing other structures of the pad metal and the wiring, and FIG. 5(a) shows FIG. 5(b) shows an example of the configuration of the octagonal pad metal; FIG. 6 is a view showing the unfolding of the metal bump during thermocompression bonding; FIG. 8 is a cross-sectional side view showing another embodiment of the semiconductor device of the present invention; FIG. 9 is a view showing a semiconductor device of the semiconductor device and a deformation of the interposer substrate during thermal expansion; FIG. 10 is a plan view showing a configuration example of an external connection metal wiring portion and an internal metal wiring; FIG. 10 is a plan view showing an external connection electrode of the conventional semiconductor device and a wiring pattern of 136777.doc • 28-201001653; and FIG. The middle view of the middle king has a crack. [Description of main component symbols] 1 semiconductor device 11 semiconductor device 12 device metal bump (element bump electrode 13 device pad metal (element metal portion) 14 device wiring 15 insulating protective film 16 conductive portion 21 interposer substrate 22 first substrate Metal bumps (substrate projections 23 first substrate pad metal (substrate metal 24 substrate wiring 25 insulating protective film 26 conductive portion 27 second substrate metal bump 28 second substrate pad metal 31 thin film substrate (substrate) 32 wiring 33, 43 Insulating protective film 34 35, 45 Underfill material 136777.doc state -29- 201001653 40 Semiconductor device 41 Thin film substrate 42 Wiring (substrate metal portion, substrate wiring) 136777.doc -30-

Claims (1)

201001653 十、申請專利範圍： 1· 一種半導體裝置，其特徵在於：其係包含封裝於基板上 之插入式基板、及封裝於上述插入式基板上之半導體元 件，上述插入式基板包含形成於封裝上述半導體元件之 位置上之複數個基板金屬部、分別形成於上述各基板金 屬部之上的袓數個基板突起電極、及分別連接於上述各 基板金屬部之複數條基板配線，上述半導體元件包含分 別藉由熱壓接而與上述各基板突起電極接合之複數個元 件突起電極、分別形成於上述各元件突起電極之下之複 數個元件金屬部'及分別連接於上述各元件金屬部之複 數條元件配線， 上述各基板金屬部以及上述各元件金屬部呈各角朝外 側突出之多角形狀， 上述各基板配線係連接於各自所對應之基板金屬邹之 與角之頂點空開間隔之位置’上述各元件配線係連接於 各自所對應之元件金屬部之與角之頂點空開間隔之位 置。 2.如請求項1之半導體裝置，其中 上述各基才反突起電極以及上述各元#突起電極包含電 阻為3χ1〇·8(Ω·ηι)以下之金屬凸塊。 毛 3 ·如請求項1之半導體裝置，其中 上述各基板突起電極以及上述各元件突起電極包含拉 伸強度為l_〇xl〇8(Pa)以上之金屬凸塊。 4.如請求項1之半導體裝置，其中 136777.doc 201001653 上述各基板突起電極以及上述各元件突起電極具有長 方體之形狀， 上述各元件配線配置於各自所對應之元件突起電極之 與元件金屬部相接之面的短邊側。 5. 如請求項1之半導體裝置，其中 上述各基板突起電極以及上述各元件突起電極具有長 方體之形狀， 上述各基板配線配置於各自所對應之基板突起電極之 與基板金屬部相接之面的短邊側。 6. 如請求項4之半導體裝置，其中 上述各元件突起電極係以與各自所對應之元件金屬部 相接之面的長邊與上述半導體元件之形成有上述各元件 突起電極之面的長邊垂直之方式而配置。 7. 如請求項5之半導體裝置，其中 上述各基板突起電極係配置為：與各自所對應之基板 金屬部相接之面的長邊係與上述插入式基板之形成有上 述各基板突起電極之面的長邊成垂直。 8. 一種半導體裝置，其特徵在於：其係包含薄膜基板、及 封裝於上述薄膜基板上之半導體元件，上述薄膜基板包 含形成於封裝上述半導體元件之位置上之複數個基板金 屬部、及分別連接於上述各基板金屬部之複數條基板配 線，上述半導體元件包含分別藉由熱壓接而與上述各基 板金屬部接合之複數個元件突起電極、分別形成於上述 各元件突起電極之下之複數個元件金屬部、及分別連接 136777.doc 201001653 於上述各元件金屬部之複數條元件配線， 上述各元件金屬部呈各角朝外側突出之多角形狀， 上述各元件配線係連接於各自所對應之元件金屬部之 與角之頂點空開間隔之位置。 9.如請求項8之半導體裝置，其中 上述各元件突起電極包含電阻為3χ1(Γ8(Ω·ηι)以下之金 屬凸塊。 136777.doc201001653 X. Patent Application Range: 1. A semiconductor device, comprising: a plug-in substrate packaged on a substrate; and a semiconductor device packaged on the interposer substrate, wherein the interposer substrate is formed in the package a plurality of substrate metal portions at positions of the semiconductor elements, a plurality of substrate protruding electrodes respectively formed on the substrate metal portions, and a plurality of substrate wirings respectively connected to the substrate metal portions, wherein the semiconductor elements include a plurality of element protruding electrodes joined to the substrate protruding electrodes by thermocompression bonding, a plurality of element metal portions respectively formed under the respective element protruding electrodes, and a plurality of elements respectively connected to the respective element metal portions In the wiring, each of the metal portions of the substrate and the metal portion of each of the elements protrude in a polygonal shape in which each corner protrudes outward, and each of the substrate wirings is connected to a position at which the apex of the substrate metal and the corner of the corresponding substrate are spaced apart. Component wiring is connected to the corresponding component gold The position of the genus and the apex of the corner is spaced apart. 2. The semiconductor device according to claim 1, wherein each of said base reverse electrode and said each of said bump electrodes comprises a metal bump having a resistance of 3 χ 1 〇 8 (Ω·ηι) or less. The semiconductor device according to claim 1, wherein each of the substrate bump electrodes and each of the element bump electrodes includes a metal bump having a tensile strength of l_〇xl 8 (Pa) or more. 4. The semiconductor device according to claim 1, wherein each of the substrate bump electrodes and each of the element bump electrodes has a rectangular parallelepiped shape, and each of the element wirings is disposed on each of the corresponding element bump electrodes and the element metal portion. The short side of the face. 5. The semiconductor device according to claim 1, wherein each of the substrate bump electrodes and each of the element bump electrodes has a rectangular parallelepiped shape, and each of the substrate wirings is disposed on a surface of the substrate bump electrode corresponding to the substrate metal portion. Short side. 6. The semiconductor device according to claim 4, wherein each of the element bump electrodes has a long side of a surface in contact with the corresponding element metal portion and a long side of the semiconductor element on which a surface of each of the element bump electrodes is formed. Configured in a vertical manner. 7. The semiconductor device according to claim 5, wherein each of the substrate protruding electrode portions is disposed such that a long side of a surface in contact with the corresponding metal portion of the substrate and a protruding electrode of the substrate are formed on the interposer substrate The long side of the face is vertical. A semiconductor device comprising a thin film substrate and a semiconductor element packaged on the thin film substrate, wherein the thin film substrate includes a plurality of substrate metal portions formed at positions of the semiconductor element, and are respectively connected In the plurality of substrate wires of each of the substrate metal portions, the semiconductor device includes a plurality of device bump electrodes bonded to the substrate metal portions by thermocompression bonding, and a plurality of device bump electrodes respectively formed under the respective device bump electrodes The element metal portion and the plurality of element wires connected to the metal portions of the respective elements are respectively connected to each other, and the metal portions of the respective elements protrude in a polygonal shape in which the respective corners protrude outward, and the respective component wires are connected to the respective components. The position of the metal portion and the apex of the corner are spaced apart. 9. The semiconductor device according to claim 8, wherein each of the element bump electrodes comprises a metal bump having a resistance of 3 χ 1 (Γ8 (Ω·ηι) or less. 136777.doc
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