200948239 九、發明說明： 【發明所屬之技術領域】 本發明與電路板製造技術有關，尤其涉及在電路板内嵌 埋電子元件的技術。 【先前技術】200948239 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to circuit board manufacturing technology, and more particularly to a technique of embedding electronic components in a circuit board. [Prior Art]
Ο 隨著電子元件的積集化及微小化’對嵌埋電子元件於電 路板之要求與日倶增。 美國專利第6928726號揭露一種内埋電子元件之電路 板及製法。其中該電子元件之兩端電極係呈上下配置（直立 式），並利用盲孔及錫球而與上、下線路層做「縱向電性連 I」准直立式的電子元件本身高度高，加上縱向電性連 通結構，導致電路爐财敍幅提高，紐滿 板之要求。 电岭 一為解決上述厚度增加之問題，美國專利第7242591號提 出-種「橫向紐賴」㈣路板及肢 = 左右配置(平躺式)，並利用導電= 通之=相鄰的線路層做橫向導通。惟，為達成横向電性連 壁上形# a製法包括：1)於—貫穿孔進行電鑛，以於盆孔 客I成—鍍層；2)固定電子元件於該導電孔中 ς «於該電子元件之兩側；以及 擴I、導電 件的兩端雷L 步驟僅在於造成連接該電子元 牛的兩端電__形成·，以免短路而無法動作子^ 200948239 【發明内容】 本發賴供-私埋電子元錄電料 隨後述及的步驛。首先，提供一怒板及m 表面有一金屬層，且广 于疋件。該芯板 件之兩相對側各且有it方向界定有一貫穿孔。該電子元 該電子元件固定_^二 板之貫穿孔的孔壁。該端電極 © ❹ 穿孔的緣填辑^ 金屬，隹:ϊ 件之間的間隙中。接著，對該芯板的 • g订案化製程，以形成—線路層。最後，形成一導 該電子元件之間’用以電性連接該芯板之 線路層與該電子疋件之端電極之該端面。 本發月進步&供根據上述製法所製造的電路板，立结 構t括-芯板、一電子元件、一絕緣填充層及_導電結構: 該芯板的表面有一線路層，且其板厚方向界定有一貫穿孔。 該電子元件容置於該芯板之貫穿孔中。該電子元件之兩相對 側各具有一端電極。其中，各端電極係面對該芯板之貫穿孔 的孔壁，且有一端面係外露於該貫穿孔的一孔口。該絕緣填 充層係填充於該芯板之貫穿孔的孔壁與該電子元件之間的 間隙中。該導電結構係橋接該電子元件之端電極之該端面及 該芯板之線路層，以達成兩者之電性連接。 在本發明中，該電路板更包括一阻層。該阻層係形成於 該芯板上，且界定有一開口以接收該導電結構。如此，該兩 端電極上的導電結構不致因為壓合過程中造成坍塌而形成 200948239 短路，導致低良率。 成厚電料件於電路板内不會造 明：==:明内容與更詳細的技術及功效說 【實施方式】 ❹ Ο =:月方二係為—種製造嵌埋電子元件之電路板的方 、’ ”崎佳實施方式係顯示於第丨〜， 法包括隨後述及的步驟。 八宁知出以方 首先如第1圖所示，提供一芯板（c〇re)卜其包括 -介電層20及兩金屬層1〇分別被覆於該介電層⑼之上、 下表面。該芯板1在其板厚方向界定有— 貫穿/l議，該貫 穿孔100係貫穿該介電層2〇及金屬層1〇。在本例中，該芯 板1係-銅箔基板(c〇Pper Clad Laminate)其表面覆有該些 金屬層10’但不限於此，例如可為一完成前處理之多層電 路板’其表面壓合具有金屬層的介電層。此外，該貫穿孔 1〇〇可藉由機械或雷射鑽孔以及沖模等方式加卫成形。 接著，如第2圖所示，先將該芯板i放置於黏貼有一可 剝離膠層31的-載板3上，續將欲紐的—電子元件*置 入該芯板1的貫穿孔100 +，並使該電子元件4黏置於位在 該貫穿孔100底面的可剝離膠層31上。藉由該可剝離膠層 31，該電子元件4得以暫時地定位於該额丨的貫穿孔1〇〇 中的適當位置。在本例中，該可剝離膠層31為—種雙面黏 200948239 性不同且可重複黏貼的雙面膠帶，但不限於此，舉凡雙面具 有黏性或單面有黏性但可提供承載，且容易撕除之物體都可 做為剝離層。其中’該雙面膠帶在黏賴載板3之—侧面的 黏性，尚於黏貼該電子元件4及該芯板丨之另一侧面，以方 便在後續步驟中將該可制離膠層31連同該載板3一併移除。 在本實施例中，該電子元件4為—晶片型元件，例如一 晶片型電容或電阻等，其多為扁平狀且兩相對側各具有一端Ο With the accumulation and miniaturization of electronic components, the demand for embedded electronic components in circuit boards has increased. U.S. Patent No. 6,928, 726 discloses a circuit board and a method of manufacturing an embedded electronic component. The electrodes at both ends of the electronic component are arranged vertically (upright), and the high-level electronic components of the vertical and vertical lines are connected with the upper and lower circuit layers by using blind holes and solder balls. The upper vertical electrical connection structure leads to an increase in the circuit fuel economy and the requirement of the full board. In order to solve the above problem of increasing the thickness of the electric ridge, U.S. Patent No. 7,242,591 proposes a kind of "horizontal ray" (four) road plate and limb = left and right configuration (flat type), and uses conductive = pass = adjacent circuit layer Do horizontal conduction. However, in order to achieve the lateral electrical wall-to-wall shape, the method includes: 1) conducting electric ore in the through-hole, so as to form a hole in the hole; 2) fixing the electronic component in the conductive hole 于Both sides of the electronic component; and the expansion of the I, the two ends of the conductive member, the step of the lightning L is only to cause the two ends of the electronic elementary cow to be electrically connected to form a short circuit to prevent the short circuit from being able to operate. ^200948239 [Summary of the Invention] The steps to be followed by the supply-embedded electronic components. First, an anger plate and a metal layer are provided on the surface of the m, and are wider than the enamel. The opposite sides of the core plate are each defined with a consistent perforation. The electronic component fixes the hole wall of the through hole of the _^ board. The terminal electrode © ❹ Perforated edge fill ^ Metal, 隹: 间隙 between the gaps between the pieces. Next, the core of the core board is programmed to form a circuit layer. Finally, a conductive layer between the electronic components is formed to electrically connect the circuit layer of the core board and the end electrode of the electronic component. The present invention is a circuit board manufactured by the above method, a vertical structure including a core plate, an electronic component, an insulating filling layer and a conductive structure: the surface of the core plate has a wiring layer and a thickness thereof The direction is defined by consistent perforation. The electronic component is received in the through hole of the core board. The opposite sides of the electronic component each have an end electrode. Wherein, each end electrode faces a hole wall of the through hole of the core plate, and an end surface is exposed to an opening of the through hole. The insulating filling layer is filled in a gap between the wall of the through hole of the core board and the electronic component. The conductive structure bridges the end face of the terminal electrode of the electronic component and the circuit layer of the core board to achieve electrical connection therebetween. In the present invention, the circuit board further includes a resist layer. The resist layer is formed on the core and defines an opening to receive the conductive structure. Thus, the conductive structure on the two terminals does not cause a 200948239 short circuit due to collapse during the pressing process, resulting in low yield. Thickened electrical components are not made in the circuit board: ==: Ming content and more detailed technology and efficacy [Implementation] ❹ Ο =: Yuefang II is a kind of circuit board for manufacturing embedded electronic components The party, ' 崎 崎 实施 实施 实施 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , - a dielectric layer 20 and two metal layers 1 被 are respectively coated on the upper surface and the lower surface of the dielectric layer (9). The core plate 1 defines a through-hole in the direction of the thickness of the core plate 1 The electric layer 2〇 and the metal layer 1〇. In this example, the core 1st-copper foil substrate (c〇Pper Clad Laminate) has a surface covered with the metal layers 10' but is not limited thereto, and may be, for example, The pre-processed multilayer circuit board 'the surface thereof is press-fitted with a dielectric layer having a metal layer. Further, the through hole 1 can be shaped by mechanical or laser drilling and die, etc. Next, as in the second As shown in the figure, the core board i is first placed on the carrier board 3 to which a peelable adhesive layer 31 is adhered, and the electronic component* of the button is continuously placed. The through hole 100 + of the core board 1 and the electronic component 4 are adhered to the peelable adhesive layer 31 located on the bottom surface of the through hole 100. By the peelable adhesive layer 31, the electronic component 4 is temporarily Positioned in the through hole 1〇〇 of the frontal ridge. In this example, the peelable adhesive layer 31 is a double-sided adhesive tape having different double-sided adhesive 200948239 and re-stickable, but is not limited thereto. Any object that has double-sided adhesiveness or is viscous on one side but can provide load and is easy to tear can be used as a peeling layer. Among them, the adhesiveness of the double-sided tape on the side of the carrier 3 is still The electronic component 4 and the other side of the core plate are adhered to facilitate removal of the removable adhesive layer 31 together with the carrier 3 in a subsequent step. In the embodiment, the electronic component 4 a wafer-type component, such as a chip-type capacitor or resistor, etc., which are mostly flat and have opposite ends on opposite sides
=極4卜如第2 _示’該電子元件4係水平地放置於該 貫穿孔100中’使得其端電極“面對該錄】之貫穿孔刚 的孔壁101。 續參閱第3 ®，係顯示利用—絕緣填充料，例如填充油 墨（Paging ink)等’將該電子元件4固定於該芯板ι的 貫穿JL 100中的步驟。首先，將該絕緣填充料填充於該芯板 1之貝穿孔100中，使得該芯板J之的孔壁1〇1與該電子元 件4之間的間隙佈滿該絕緣填充料。待該絕緣填充料固化 ㈣⑹後，即成為一絕緣填充層5，用以將該電子元件ι永 ==5之貫穿孔1〇°中。其中，該絕緣填充 ^顧4絲式、印财式、或其它方式填綠 100 中。 參閱第2A及2B圖，係顯示將該電子元件4固定於該 貫穿孔100中的另一種作法。名筮h 口疋瓦忍 穿孔⑽中預先填充填=A圖中，該芯板1的貫 該電子元件4係被暫時地=4=時’在第2B圖中’ .疋位於該可剝離膠層31及該载板 置。接者’將該载板3與該芯板1對位疊合㈣ 200948239 up)’並使得該電子元件4恰置於該芯板i的貫穿孔1〇〇中。 待該絕緣填充料5a固化(cure)後，即第3圖中所示的絕緣填 充層5，從而使得該電子元件丨能永久性地固定於該芯板i 之貫穿孔100中。藉由對位疊合的方式，可避免該電子元件 4邊緣產±空穴(voui)現象’ p方止當進行高溫製程或可靠度 測試時產生爆板狀況。 ❹ 接繽第二圖’第4圖係顯示一併移除該可剝離膠層31 連同該載板3，得到下娜露之基板。值得—提的是，由於 該電子元件1與該芯板1之底面原先同受該載板3及該可剝 離膠層31的支撐而相互#平。因此，在該可剝離膠層31 及該載板3移除後，該電子元件4的絲細與該芯板（ 的底面齊平的方式外露。 復將第4圖的整個基板上下顛倒（flip)放置，使得該 電子元件4與該芯板丨齊平的面朝上，如第$圖所示吼日^ 該電子疋件4的端電極41的一端面41〇係外露於貫 100 的一孔口 102。 參7 6圖’續將該第5圖的基板進行刷磨（咖 作業，以去除該絕緣填充料5溢出該貫穿孔ι〇〇的部份，以 及清潔電子元件4及該芯板丨表面。 程以再進行曝光、顯影，等圖案化製 ΐ的線路二3表㈣金4層1G綱形賴有線路圖 參閲第8圖，續在該芯板〗與該電子元件 數導電結構6’用以電性連接該芯板i之的線路層收與= 200948239 電子元件4之端電極Μ之該端面_。在本例中，該 結構6可制·或鋼板，以印刷的方式 塗印在對應的位置上㈣成。第九圖係第 /圖之4之俯。如第域所示，本發明相較於先前技 術無須進行切割之步驟，製程相對簡單。 ❹ ❹ 續參閱第U)圖’可再利用多層印刷電路製造技術，於 該芯板1之上下側，各疊加—線路增層結構7，a包括一介 電層73、疊加㈣介電層73上的—線路層71，以及形成於 該介電層73中的-導通結構72，且該導通結構72電性連 接至該芯板1表面的線路層10a。又，該線路增層結構7表 面更形成’焊層74,謂畴層74表面界定有複數個開 孔740，俾以形成複數電性連接墊乃於該些開孔74〇中。 該電性連接墊75係供電性連接其他導體元件（未顯示），藉 由該導體tl件以電性連接其他電子裝置。其中該線路增層結 構7可以如前述中地為多層結構，亦可為單層結構。 第Π〜14 _顯示本發财法之另-較佳實施方式的 後段製造餘，其前段製造流程與第i至7圖相同，容不贊 述。 一在元成上述第7圖所示的步驟之後，接著如第u圖所 不地於該芯板1表面塗佈的—絲像㈣9a (p—ge material) ’並進行圖案化製程以形成一阻層9，如第12圖 所示。該阻層9界定有複數開σ 90，以外露出該電子元件4 的端電極41 _面41〇,以及部份義芯板丨的線路層 10a、-貝利用刮刀91將一導電膏92 ( conductive paste )填 11 200948239 入該些開口 90中。 >參閱第圖並配合第⑽，待該開口 ％中 嘗92固化後’成為—導電結構6，用以電性^ 之的線路層10a與該電子元件4。 連接以心板1 〇 ❹ 續參閱第14圖，復於該第13圖的基被 ，層、賴7,其類似於第1〇圖之結構，容不費：。值 付-提=疋，在本實施例中，該兩導電結構6中間係以該阻 層9相隔，且料’稍於後續之疊加之製程相當有助益。 該阻層卜方面可作為多層電路板的介電層，另—方面可阻 隔該電子元件4上的兩導電結構6,簡免該兩導電結構6 在增層壓合的過程快塌，導致兩端電極短路。 從上述說明中，可以理解到本發明之電路板的線路層與 ”内埋之電子元件的^端電極之間係藉由橫向導通者，不增 加該電路板之厚度。尤其是該導電結構與該絕緣填充層的空 間配置是轉精心設計的，使其製程相對簡單。 ^無論如何，任何人都可以從上述例子的說明獲得足夠教 導，並據而了解本發明内容確實不同於先前技術，且具有產 業上之利用性，及足具進步性。是本發明確已符合專利要 件，爰依法提出申請。 12 200948239 【圖式簡單說明】 第1-8及10圖，係顯示本發明嵌埋電子元件之電路板製 造流程之一實施例的剖面示意圖。 第2A及2B圖，係顯示第二圖的另一種實施態樣。 第9圖，係第8圖之結構的一俯視圖。 第11-14圖，係承接第七圖，顯示本發明嵌埋電子元件之 電路板製造流程之另一實施例的剖面示意 圖。 【主要元件符號說明】 1芯板 10金屬層 10a線路層 100貫穿孔 101孔壁 102 孔口 20介電層 3載板 31可剝離膠層 4電子元件 41端電極 410端面 5絕緣填充層 5a絕緣填充料 6導電結構 7線路增層結構 71線路層 72導通結構 73介電層 74防焊層 740開孔 75電性連接墊 9阻層 9a光影像材料 90開口 91刮刀 92導電膏 13= 4, as shown in the second embodiment, the electronic component 4 is placed horizontally in the through hole 100 such that its end electrode "faces the recording hole" of the through hole 101 of the hole. Continued to refer to the 3®, The step of fixing the electronic component 4 to the core plate 1 through the JL 100 by using an insulating filler such as a Paging ink, etc. First, filling the insulating filler into the core 1 In the perforation 100, the gap between the hole wall 〇1 of the core board J and the electronic component 4 is filled with the insulating filler. After the insulating filler is cured (4) (6), it becomes an insulating filling layer 5, The through hole is used for the electronic component ι ===5, wherein the insulation is filled in a 4-wire type, a printed form, or other way to fill the green 100. Referring to Figures 2A and 2B, Another method of fixing the electronic component 4 in the through hole 100 is shown. The pre-filled filling in the hole punching hole (10) is filled in the figure A, and the electronic component 4 of the core board 1 is temporarily =4 = when 'in Figure 2B'. The crucible is located in the peelable adhesive layer 31 and the carrier plate. The carrier 'the carrier board 3 The core board 1 is overlapped (4) 200948239 up)' and the electronic component 4 is placed in the through hole 1〇〇 of the core board i. After the insulating filler 5a is cured, that is, in FIG. The insulating filling layer 5 is shown, so that the electronic component can be permanently fixed in the through hole 100 of the core board i. By means of the alignment of the alignment, the edge of the electronic component 4 can be avoided. (voui) Phenomenon' p-stop occurs when a high-temperature process or reliability test is performed. ❹ The second figure of Figure 4 shows that the peelable adhesive layer 31 is removed together with the carrier plate 3, Obtaining a substrate of the lower radiance. It is worth mentioning that since the electronic component 1 and the bottom surface of the core board 1 are originally supported by the carrier 3 and the peelable adhesive layer 31, they are mutually flat. After the peelable adhesive layer 31 and the carrier 3 are removed, the wire of the electronic component 4 is exposed in a manner flush with the bottom surface of the core plate. The entire substrate of FIG. 4 is placed upside down, so that The electronic component 4 is flush with the core plate face up, as shown in Fig. 吼, the end electrode 41 of the electronic component 4 An end face 41 is exposed to an opening 102 of the 100. VII. Figure 7 continues to brush the substrate of Fig. 5 (coffee operation to remove the insulating filler 5 overflowing the through hole ι Part, as well as cleaning the electronic component 4 and the surface of the core plate. The process is followed by exposure, development, and other patterns of the patterned circuit. Table 3 (4) Gold 4 layer 1G pattern depends on the circuit diagram. Continued in the core board and the electronic component number conductive structure 6' for electrically connecting the core layer i of the circuit layer to receive the end face of the terminal electrode 电子 of the electronic component 4 = 200948239. In this example, the The structure 6 can be made or plated and printed on the corresponding position (4). The ninth picture is the 4th / 4th. As shown in the first section, the present invention is relatively simple in that the process is not required to perform the cutting step as compared to the prior art. ❹ 续 continued to refer to the U) diagram of the reusable multilayer printed circuit fabrication technology. On the lower side of the core board 1, each superposed-line build-up structure 7, a includes a dielectric layer 73, and a (four) dielectric layer 73. The upper-circuit layer 71, and the conductive structure 72 formed in the dielectric layer 73, and the conductive structure 72 is electrically connected to the wiring layer 10a on the surface of the core board 1. Moreover, the surface of the circuit build-up structure 7 further forms a solder layer 74. The surface of the domain layer 74 defines a plurality of openings 740 for forming a plurality of electrical connection pads in the openings 74. The electrical connection pad 75 is electrically connected to other conductor elements (not shown), and the conductor tl is electrically connected to other electronic devices. The line build-up structure 7 may be a multi-layer structure as in the foregoing, or may be a single-layer structure. Π Π 14 14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ After the step shown in FIG. 7 above, the silk image (4) (p-ge material) coated on the surface of the core 1 is not subjected to a patterning process to form a pattern. The resist layer 9 is as shown in Fig. 12. The resist layer 9 defines a plurality of openings σ 90, and the terminal electrodes 41 _ face 41 露出 of the electronic component 4 are exposed, and the circuit layers 10 a and _ of the partial core board 利用 a conductive paste 92 by a blade 91 (conductive Paste ) Fill in 11 of these openings 90 200948239. > Referring to the figure and in conjunction with the above (10), after the curing of the opening % is cured, the conductive layer 6 is electrically connected to the wiring layer 10a and the electronic component 4. Connected to the heart plate 1 〇 续 Continue to refer to Figure 14, the base layer of the Figure 13, the layer, the Lai 7, which is similar to the structure of Figure 1, is not to be used: In the present embodiment, the two conductive structures 6 are separated by the barrier layer 9 and the process of the material is slightly more advantageous than the subsequent stacking process. The resist layer can be used as a dielectric layer of the multi-layer circuit board, and the two conductive structures 6 on the electronic component 4 can be blocked on the other hand, so that the two conductive structures 6 are quickly collapsed during the lamination process, resulting in two The terminal electrode is shorted. From the above description, it can be understood that the circuit layer of the circuit board of the present invention and the "electrode of the embedded electronic component are connected by the lateral conduction without increasing the thickness of the circuit board. Especially the conductive structure and The spatial configuration of the insulating fill layer is carefully designed to make the process relatively simple. ^ In any case, anyone can obtain sufficient teaching from the description of the above examples, and it is understood that the present invention is indeed different from the prior art, and It has industrial applicability and is progressive. It is the invention that has met the patent requirements and has applied for it according to law. 12 200948239 [Simplified illustration] Figures 1-8 and 10 show the embedded electrons of the present invention. FIG. 2A and FIG. 2B are diagrams showing another embodiment of the second diagram. FIG. 9 is a plan view of the structure of FIG. 8. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view showing another embodiment of a circuit board manufacturing process for embedding electronic components according to the present invention. [Main component symbol description] 1 core board 10 metal layer 10a circuit layer 100 through hole 101 hole wall 102 hole 20 dielectric layer 3 carrier 31 peelable adhesive layer 4 electronic component 41 end electrode 410 end face 5 insulating filling layer 5a insulating filler 6 conductive structure 7 line build-up structure 71 line Layer 72 conduction structure 73 dielectric layer 74 solder mask 740 opening 75 electrical connection pad 9 resistance layer 9a optical image material 90 opening 91 blade 92 conductive paste 13