200947672 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有儲能電容器之積體電路，且更特 定言之係關於一種記憶體裝置。 本發明主張分別於2〇08年3月2 i日及2〇〇8年1 i月26曰所 •申請之韓國專利申請案第10_20〇8_〇〇26342號及第1〇 2〇〇8_ 0U7999號之優先權，該等申請案全文以引用的方式併入 本文中。 φ 【先前技術】 經常藉由-低電壓在高速下操作諸如動態隨機存取記憶 體（dram)之記憶體。在該高速操作中，封裝/板之小的電 感干擾電流供應。當使用一低供電電壓以減小電力消耗 時，該供電電壓中之雜訊顯著地改變電路延遲，引起記憶 體裝置中之錯誤。 為了克服該問題，有必要減小供電電壓中之雜訊。亦 ’需要減小外部電源與晶片上電路之間的阻抗或藉由增 加在晶片中之電路周圍的儲能電容器之電容來減小阻抗。 在此，儲能電容器已用於電力供應裝置中以將由電力消耗 引起之電壓降最小化。 儘管使用具有針對高頻雜訊之小等效串聯電阻（ESR)的 儲能電容器可能獲得足夠小的阻抗，但該方案需要具有針 對低頻雜訊之相對大之電容的儲能電容器。 【發明内容】 本發明之-些實施例係針對於提供一種储能電容器，其 137510.doc 200947672 用於在不必增加晶片面積的情況下穩定化低頻雜訊。 本發明之一些實施例亦係針對於提供一種儲能電容器， 其用於在施加咼電壓時藉由使用大容量電容器來防止漏電 流的增加。 本發明之一些實施例亦係針對於提供一種儲能電容器， 其用於在不佔據額外面積的情況下實現大電容。 本發明之一些實施例亦係針對於提供一種積體電路，其 具有一具有以上特徵之儲能電容器。 本發明之一些實施例亦係針對於提供一種半導體記憶體 裝置，其用於在施加高電壓時藉由使用單元電容器作為周 邊電路之儲能電容器來防止漏電流的增加。 根據本發明之一態樣，提供一種儲能電容器，其包含一 第一電力供應單元及一第二電力供應單元及串聯連接於該 第一電力供應單元與該第二電力供應單元之間的至少兩個 大容量電容器。 根據本發明之另一態樣，提供一種儲能電容器，其包含 一第一電力供應單元及一第二電力供應單元、一具有並聯 連接之複數個大容量電容器的第一電容器群組，及一具有 並聯連接之複數個大電容器的第二電容器群組，其中該第 一電容器群組與該第二電容器群組串聯連接於該第一電力 供應單元與該第二電力供應單元之間。 該儲能電容器可進一步包含一 M〇s電容器，其與該至少 兩個大容量電容器並聯連接於第一電力供應單元與第二電 力供應單元之間。可將該大容量電容器安置於基板上之 137510.doc 200947672 MOS電容器之上。 該大容量電容器可為堆疊電容器’其包含依序堆疊之一 下部電極導電層、一介電層，及一上部電極導電層。該第 一電力供應單元可包含一接收第一電力供應之第一電力 線，且第一電極可連接至該第一電力線，且該第二電力供 應單兀可包含一接收第二電力供應之第二電力線，且第三 電極可連接至該第二電力線。 該介電層可為一高介電薄臈或一鐵電薄膜。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having a storage capacitor, and more particularly to a memory device. The present invention claims to be filed on March 2, 2008 and February 2, 2008, in the Korean Patent Application No. 10_20〇8_〇〇26342 and No. 1〇2〇〇8_ Priority is claimed in U.S. Patent Application Serial No. U.S. φ [Prior Art] A memory such as a dynamic random access memory (dram) is often operated at a high speed by a low voltage. In this high speed operation, the small inductance of the package/board interferes with the current supply. When a low supply voltage is used to reduce power consumption, the noise in the supply voltage significantly changes the circuit delay, causing errors in the memory device. In order to overcome this problem, it is necessary to reduce the noise in the supply voltage. It is also desirable to reduce the impedance between the external power supply and the circuitry on the wafer or to reduce the impedance by increasing the capacitance of the energy storage capacitor around the circuitry in the wafer. Here, the storage capacitor has been used in a power supply device to minimize the voltage drop caused by power consumption. Although it is possible to obtain a sufficiently small impedance using a storage capacitor having a small equivalent series resistance (ESR) for high frequency noise, this solution requires a storage capacitor having a relatively large capacitance for low frequency noise. SUMMARY OF THE INVENTION Some embodiments of the present invention are directed to providing a storage capacitor, 137510.doc 200947672 for stabilizing low frequency noise without having to increase the area of the wafer. Some embodiments of the present invention are also directed to providing a storage capacitor for preventing an increase in leakage current by using a large-capacity capacitor when a 咼 voltage is applied. Some embodiments of the present invention are also directed to providing a storage capacitor for achieving large capacitance without occupying additional area. Some embodiments of the present invention are also directed to providing an integrated circuit having a storage capacitor having the above features. Some embodiments of the present invention are also directed to providing a semiconductor memory device for preventing an increase in leakage current by using a cell capacitor as a storage capacitor of a peripheral circuit when a high voltage is applied. According to an aspect of the present invention, an energy storage capacitor includes a first power supply unit and a second power supply unit and is connected in series between the first power supply unit and the second power supply unit. Two large capacitors. According to another aspect of the present invention, a storage capacitor includes a first power supply unit and a second power supply unit, a first capacitor group having a plurality of large-capacity capacitors connected in parallel, and a first capacitor group a second capacitor group having a plurality of large capacitors connected in parallel, wherein the first capacitor group and the second capacitor group are connected in series between the first power supply unit and the second power supply unit. The energy storage capacitor may further include an M〇s capacitor connected in parallel with the at least two bulk capacitors between the first power supply unit and the second power supply unit. The bulk capacitor can be placed over the 137510.doc 200947672 MOS capacitor on the substrate. The bulk capacitor may be a stacked capacitor 'which includes one of a lower electrode conductive layer, a dielectric layer, and an upper electrode conductive layer. The first power supply unit may include a first power line receiving the first power supply, and the first electrode may be connected to the first power line, and the second power supply unit may include a second receiving second power supply A power line, and the third electrode is connectable to the second power line. The dielectric layer can be a high dielectric thin crucible or a ferroelectric thin film.
根據本發明之另外態樣，提供一種半導體記憶體裝置， 其包含一具有單元電容器之記憶體單元，及一具有儲能電 容器之周邊電路。該儲能電容器包含至少兩個大容量電容 器，其串聯連接於第-電力供應單元與第三電力供應單元 之間，且該等大容量電容器中之每一者具有 之電容大體上相同的電容。 根據本發明之又—態樣，提供—種半導體記憶體裝置， 其包含一具有單元電容器之記憶體單元，及一具有健能電 容器之周邊電路。該儲能電容器包含一具有並聯連接之複 數個大容量電容器的第一電容器群組，及一具有並聯連接 之複數個大電容器的第二電容器群組。該第一電容器群組 及該第二電容器群組串聯連接於第—電力供應單元與第二 電力：應單元之間，且第一電容器群組及第二電容器群組 之大各量電容器中之每一者具有與單元電容器之電容等同 因 為記憶體裝置包含在一 平面中之一單元陣列區域及一 137510.doc 200947672 周邊區域，所以當在單元區域中圖案化單元電容器時，等 同地在周邊電路區域中圖案化大容量電容器。特定言之， 根據本發明之實施例，該單元電容器為一堆疊電容器，其 具有形成於該記憶體裝置中之基板上之位元線上的位元線 上電容器（COB)結構。 在形成具有該堆疊結構之單元電容器過程中，大容量電 -容器可等同地形成於周邊電路區域中。亦即，大容量電容 器可形成於無金屬接觸點之周邊電路區域内，且可將大容 © 量電容器安置於MOS電容器之上。 第一電力供應單元可為選自由一供電電壓（Vdd)線、— 高電壓（Vpp)線、一核心電壓（Vc〇re)線，及一位元線預充 電電壓（Vblp)線組成之群組的一者。第二電力供應單元可 為一接地電壓（Vss)線或一反向偏壓電壓（Vbb)線。 【實施方式】 可藉由以下描述瞭解本發明之其他目標及優點，且參看 ❹ 本發明之實施例其可變得顯而易見。 圖1為說明根據本發明之第一實施例之儲能電容器的圖 式。 參看圖1 ’根據第一實施例之儲能電容器包含一第—電 力供應單元120、一第二電力供應單元14〇,及在第一電力 供應單元120與第二電力供應單元14〇之間的至少兩個大容 量電容器160及180。根據第一實施例之儲能電容器進—步 包含並聯連接至第一電力供應單元12〇與第二電力供應單 凡140之間的河〇8電容器17〇，^1〇8電容器17〇連接至大容 137510.doc 200947672 量電容器’該等大容量電容器。可省略該]y[〇S電容器 170 ° MOS電晶體17〇具有在ηρ範圍（例如，數十ηΙ?)内之電 容。大容量電容器160及180各自具有在μΡ範圍（例如，若 干μΐ7)内之電容。大容量電容器16〇及ι8〇各自具有第一電 極（儲存節點）、介電質及第二電極（板）之堆疊結構。可使 用多晶石夕或金屬薄膜形成大容量電容器80中之每_ 者的第一電極及第二電極。可使用高介電質或鐵電體形成 該介電質。 如以上所描述’根據第一實施例之儲能電容器使用大容 量電容器160及180以用於移除低頻雜訊。因為大容量電容 器160及180各自具有當施加高電壓時漏電流增加的問題， 所以可串聯連接至少兩個大容量電容器。 大容量電容器160及180具有大ESR。因為藉由僅使用大 谷量電容器160及180可能無法移除高頻雜訊，所以電 容器170與大容量電容器160及18〇結合使用以移除任何高 頻雜訊。 圖2為根據本發明之第二實施例之儲能電容器的電路 圖。 參看圖2，該儲能電容器包含一第一電力供應單元22〇、 一第二電力供應單元240、一具有並聯連接之複數個大容 量電容器的第一電容器群組260，及一具有並聯連接之複 數個大容量電容器的第二電容器群組28〇。 在此，第一電容器群組260與第二電容器群組28〇串聯連 接於第一電力供應群組220與第二電力供應群組24〇之間。 137510.doc 200947672 另外，圖2中之儲能電容器進一步包含並聯連接至第一電 力供應單元220及第二電力供應單元240之MOS電容器 270。該MOS電容器270可為可選的。 MOS電容器270具有在pF範圍（例如，數十nF)内之電 容。第一電容器群組260及第二電容器群組280中之大容量 電容器中之每一者具有在pF範圍（例如，若干pF)内的電 容。儘管該兩個電容器群組260及280在圖2中被展示為串 聯連接，但亦可串聯連接三個或三個以上電容器群組260 φ 及 280。 類似於圖1中之大電容器160及180，在每一電容器群組 260及280中之大容量電容器中之每一者包含第一電極（一 儲存節點）、介電質及第二電極（一板）之堆疊結構。可使用 多晶矽及金屬薄膜，以及高介電質及鐵電體形成電容器群 組260及2 80之大容量電容器的第一電極及第二電極。 圖3為圖2中之電容器群組260及280的布局圖。若如在第 二實施例中串聯連接電容器群組260及280，則易於圖案化 ® 電容器群組260及280之大容量電容器的第二電極（板）。 參看圖3，形成用於接收第一電力供應之第一電力線320 '及用於接收第二電力供應之第二電力線340。第一電力線 3 20連接至第一電容器群組260中之大容量電容器的第一電 極363A、363B、363C及363D。第二電力線340連接至第二 電容器群組280中之大容量電容器的第一電極383A、 383B、3 83C及3 83D。第一電容器群組260及第二電容器群 組280之大容量電容器的第二電極（板）365藉由單一導電層 137510.doc 200947672 圖案共同地形成。 根據圖it所展示之坌—參> 之第實施例的儲能電容器可具有與 圖3之布局相同之 局’除了可改變大容量電容器之數目 以外。 - W4為圖3中之儲能電容器沿線Α·Β所截之橫截面圖。 參看圖4帛電力線32()及第三電力線34()係於基板31〇 上製備第一電力線320及第二電力線340作為諸如金屬或 多μ夕之導電層而經圖案化。第一電極％从、如β、 〇 383Α及383Β穿透絕緣層且與第-電力線320及第二電力線 340接觸〃電質364形成於包含第一電極363Α、363Β、 383Α及383Β的基板31〇上。第二電極如形成於介電質州 上。對於本實施例中之所有大容量電容器，介電質364及 第一電極365可各自相同薄膜共同地形成。或者，對於每 一大谷量電容器’可個別地形成介電質364及第二電極 365 ° ©圖5為具有儲能電容器之M〇s電容器及大容量電容器之 基板的橫截面圖。大容量電容器51〇安置於基板（例如，矽 基板Si-sub)上之MOS電容器530的頂部。 MOS電容器530包含形成於矽基板Si_sub處之一閘極〇、 一源極S’及一汲極D。源極S及汲極D連接至第二電力線 VSS，且閘極G連接至第一電力線VDD。在圖5中，將大容 量電容器及連接線說明為一等效電路。 圖6為說明根據相關技術之DRAM之電路圖。參看圖6， 根據相關技術之記憶體單元包含一連接至字線及位元線之 137510.doc 200947672 存取電晶體Tr，及一用於儲存單元資料之單元電容器 Cap。根據本發明之實施例的儲能電容器可應用於具有" 中所展示之單元電容器的記憶體裝置。 圖7為根據本發明之第二實施例之記憶體裝置的橫截面 圖圖7說明在一半導體記憶體裝置中如何組態記憶體單 兀及儲能電容器，該半導體記憶體裝置包含一具有一單元 電容器之記憶體單元及一具有一儲能電容器之周邊電路。 參看圖7,具有一單元電容器72〇A之記憶體單元形成於 〇 -單兀區域内，且包含-儲能電容器之周邊電路形成於一 周邊區域内。 該儲能電容器包含串聯連接於第一電力線7108與第二電 力線710C之間的一第一大容量電容器72〇B及一第二大容 量電容器720C。儘管在圖7中展示兩個大容量電容器，但 可包含兩個以上之大容量電容器。儘管未在圖7中展示， 但可以如圖1、圖2及圖5中所展示之各種方法形成儲能電 ©容器。特定言之，如圖5中所展示，可進一步包含一連接 至該第一大容量電容器720B及該第二大容量電容器72〇c 之MOS電容器。 在本實施例中，儲能電容器之第一大容量電容器72犯及 第二大容量電容器720C可各自具有與單元電容器720A之 電容大體上相同之電容。 單元電容器720A為一堆疊電容器’其具有形成於用於位 元線71 0A或在位元線710A上之基板上的位元線上電容器 (COB)結構。單元電容器72〇A包含一儲存節點722、一形 1375I0.doc -10- 200947672 成於該儲存節點722A上的介電質724A，及一形成於該介 電質724A上的板狀電極726A。 第一大容量電容器720B包含：一第一電極722B，其具 有分別與儲存節點722 A之材料及表面積相同之材料及表面 積；一介電質724B，其形成於第一電極722A上且具有與 '單元電容器之介電質724A之材料相同的材料；及一第二電 極726B，其形成於介電質724B上且由與板狀電極726A之 材料相同的材料製成。因此，單元電容器720A及第一大容 〇 量電容器720B各自具有大體上相同之電容。第二大容量電 容器之第一電極722C、介電質724C及第二電極726C可大 體上等同於第一大容量電容器720B之第一電極、介電質及 第二電極。 第一大容量電容器720B之第一電極722B連接至第一電 力線710B且與第一電力線710B接觸，且第二大容量電容 器720C之第一電極722C連接至第二電力線710C且與第二 電力線710C接觸。第一大容量電容器720B之第一電極 ® 722B及第二大容量電容器720C之第一電極722C分別藉由 圖案化相同材料之導電層而形成。 •第一大容量電容器720B之第二電極726B及第二大容量 . 電容器720C之第二電極726C藉由單一導電圖案共同地形 成。 第一電力線710B及第二電力線710C係由與在單元區域 中之位元線的導電層之材料相同之材料的導電層形成。藉 由圖案化將第一電力線710B與第二電力線710C分離。除 137510.doc 200947672 使用用於位元線之導電層之外，亦可使用用於第—電力線 710B及第二電力線71〇c之其他導電層。 第一電力線710B接收對應於用於記憶體之内部電路令的 一或多個信號之邏輯"高"的電壓位準。舉例而言，第一電 力線710B可為供電電壓（vdd)線、高電壓（Vpp)線核心電 壓（Vcore)線及位元線預充電電壓（Vblp)線中之任一者。 •第二電力線710C接收對應於用於記憶體之内部電路中的 一或多個信號之邏輯"低"的電壓位準。舉例而言，第二電 ❿ 力線710(：可為一接地電壓（Vss)線或一反向偏壓電壓（Vbb) 線。 第一大容量電容器720B及第二大容量電容器72〇c之每 一介電層可為一高介電膜或一鐵電層。 在圖7中，參考數字7〇2表示一矽基板Si_sub，參考數字 703表示一單元電晶體之閘電極，且參考數字7〇4、7〇5及 706為接觸插塞。 φ 根據本發明之第四實施例之半導體記憶體裝置可在電容 器群組中之每一者中包含圖5之儲能電容器。在此，在每 一群組中之大容量電容器中的每一者具有與單元電容器之 結構相同的結構。 如以上所描述，根據本發明之實施例的儲能電容器及具 有其之半導體可應用於配合諸如動態隨機存取記憶體 (dram)之半導體積體電路及其他半導體裝置中之儲能電 容器使用電力供應方案的所有狀況。根據本發明之實施例 的儲能電容器在具有形成於位元線上之單元電容器的 137510.doc -12· 200947672 dram中係非常有用的。特定言之’根據本發明之實施例 的儲能電容器可有利地形成於不具有金屬接觸點之所有周 電路中，因為早元電容器不使用於周邊電路區内。因為 電力終端可安置於]^08電晶體上且不存在阻止形成本發明 之儲能電容器的限制’所以有可能在不增加面積的情況下 増加電容。另外，大容量電容器可形成於周邊電路中之任 一區域中。According to still another aspect of the present invention, a semiconductor memory device comprising a memory cell having a cell capacitor and a peripheral circuit having a storage capacitor is provided. The energy storage capacitor includes at least two bulk capacitors connected in series between the first power supply unit and the third power supply unit, and each of the large capacity capacitors has a capacitance of substantially the same capacitance. According to still another aspect of the invention, there is provided a semiconductor memory device comprising a memory cell having a cell capacitor and a peripheral circuit having a robust capacitor. The energy storage capacitor includes a first capacitor group having a plurality of bulk capacitors connected in parallel, and a second capacitor group having a plurality of large capacitors connected in parallel. The first capacitor group and the second capacitor group are connected in series between the first power supply unit and the second power: response unit, and the plurality of capacitors of the first capacitor group and the second capacitor group are Each has the same capacitance as the cell capacitor because the memory device includes one of the cell array regions in a plane and a peripheral region of 137510.doc 200947672, so when the cell capacitor is patterned in the cell region, it is equivalent to the peripheral circuit. Patterned bulk capacitors in the area. Specifically, in accordance with an embodiment of the present invention, the unit capacitor is a stacked capacitor having a bit line capacitor (COB) structure formed on a bit line on a substrate in the memory device. In forming a unit capacitor having the stacked structure, a large-capacity electric-container can be equally formed in a peripheral circuit region. That is, the bulk capacitor can be formed in the peripheral circuit area where there is no metal contact, and a large capacitance capacitor can be placed over the MOS capacitor. The first power supply unit may be selected from the group consisting of a supply voltage (Vdd) line, a high voltage (Vpp) line, a core voltage (Vc〇re) line, and a one-line pre-charge voltage (Vblp) line. One of the groups. The second power supply unit may be a ground voltage (Vss) line or a reverse bias voltage (Vbb) line. [Effects] Other objects and advantages of the present invention will become apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a storage capacitor according to a first embodiment of the present invention. Referring to FIG. 1 'The energy storage capacitor according to the first embodiment includes a first power supply unit 120, a second power supply unit 14A, and between the first power supply unit 120 and the second power supply unit 14A. At least two bulk capacitors 160 and 180. The energy storage capacitor according to the first embodiment further includes a port 8 capacitor 17A connected in parallel between the first power supply unit 12 and the second power supply unit 140, and the capacitor 17 is connected to大容137510.doc 200947672 Volume capacitors 'These large capacity capacitors. This y [〇S capacitor 170 ° MOS transistor 17 〇 has a capacitance in the range of η ρ (for example, tens of η Ι )). The bulk capacitors 160 and 180 each have a capacitance in the range of μΡ (e.g., several μΐ7). The bulk capacitors 16A and ι8〇 each have a stacked structure of a first electrode (storage node), a dielectric, and a second electrode (plate). The first electrode and the second electrode of each of the large-capacity capacitors 80 may be formed using a polycrystalline or a thin metal film. The dielectric can be formed using a high dielectric or ferroelectric. As described above, the energy storage capacitor according to the first embodiment uses the large capacity capacitors 160 and 180 for removing low frequency noise. Since the large-capacity capacitors 160 and 180 each have a problem that the leakage current increases when a high voltage is applied, at least two large-capacity capacitors can be connected in series. The bulk capacitors 160 and 180 have a large ESR. Since high frequency noise may not be removed by using only the large amount capacitors 160 and 180, the capacitor 170 is used in conjunction with the bulk capacitors 160 and 18 to remove any high frequency noise. Fig. 2 is a circuit diagram of a storage capacitor in accordance with a second embodiment of the present invention. Referring to FIG. 2, the energy storage capacitor includes a first power supply unit 22, a second power supply unit 240, a first capacitor group 260 having a plurality of large-capacity capacitors connected in parallel, and a parallel connection. A second capacitor group 28 of a plurality of bulk capacitors. Here, the first capacitor group 260 and the second capacitor group 28 are connected in series between the first power supply group 220 and the second power supply group 24A. 137510.doc 200947672 Additionally, the energy storage capacitor of FIG. 2 further includes a MOS capacitor 270 connected in parallel to the first power supply unit 220 and the second power supply unit 240. The MOS capacitor 270 can be optional. The MOS capacitor 270 has a capacitance in a pF range (e.g., several tens of nF). Each of the bulk capacitors in the first capacitor bank 260 and the second capacitor bank 280 has a capacitance in the pF range (e.g., several pF). Although the two capacitor banks 260 and 280 are shown in series as shown in Figure 2, three or more capacitor banks 260 φ and 280 may be connected in series. Similar to the large capacitors 160 and 180 of FIG. 1, each of the bulk capacitors in each of the capacitor groups 260 and 280 includes a first electrode (a storage node), a dielectric, and a second electrode (a Stacked structure of the board). The first electrode and the second electrode of the large-capacity capacitors of the capacitor banks 260 and 280 can be formed using a polysilicon and a metal thin film, and a high dielectric and ferroelectric. 3 is a layout view of the capacitor groups 260 and 280 of FIG. If the capacitor groups 260 and 280 are connected in series as in the second embodiment, it is easy to pattern the second electrodes (plates) of the bulk capacitors of the ® capacitor groups 260 and 280. Referring to FIG. 3, a first power line 320' for receiving a first power supply and a second power line 340 for receiving a second power supply are formed. The first power line 3 20 is connected to the first electrodes 363A, 363B, 363C, and 363D of the bulk capacitor in the first capacitor group 260. The second power line 340 is coupled to the first electrodes 383A, 383B, 3 83C, and 83D of the bulk capacitors of the second capacitor group 280. The second electrode (plate) 365 of the bulk capacitor of the first capacitor group 260 and the second capacitor bank 280 is collectively formed by a single conductive layer 137510.doc 200947672 pattern. The energy storage capacitor of the first embodiment of the present embodiment shown in Fig. 1 can have the same layout as the layout of Fig. 3 except that the number of large capacity capacitors can be changed. - W4 is a cross-sectional view of the energy storage capacitor of Figure 3 taken along line Α·Β. Referring to Fig. 4, the power line 32() and the third power line 34() are formed on the substrate 31A to form a first power line 320 and a second power line 340 which are patterned as a conductive layer such as metal or a plurality of layers. The first electrode % penetrates the insulating layer from, for example, β, 〇383Α, and 383Β, and is in contact with the first power line 320 and the second power line 340. The electric potential 364 is formed on the substrate 31 including the first electrodes 363, 363, 383, and 383. on. The second electrode is formed, for example, on a dielectric state. For all of the bulk capacitors in this embodiment, the dielectric 364 and the first electrode 365 can be formed collectively of the same film. Alternatively, the dielectric 364 and the second electrode 365 may be individually formed for each large-capacitor capacitor. © Fig. 5 is a cross-sectional view of a substrate having an M s capacitor and a large-capacity capacitor of a storage capacitor. The bulk capacitor 51 is disposed on top of the MOS capacitor 530 on the substrate (e.g., 矽 substrate Si-sub). The MOS capacitor 530 includes a gate electrode, a source S', and a drain D formed at the germanium substrate Si_sub. The source S and the drain D are connected to the second power line VSS, and the gate G is connected to the first power line VDD. In Fig. 5, a large capacity capacitor and a connecting line are described as an equivalent circuit. Fig. 6 is a circuit diagram showing a DRAM according to the related art. Referring to Fig. 6, a memory cell according to the related art includes a 137510.doc 200947672 access transistor Tr connected to a word line and a bit line, and a cell capacitor Cap for storing cell data. The energy storage capacitor according to an embodiment of the present invention can be applied to a memory device having a unit capacitor as shown in ". 7 is a cross-sectional view of a memory device in accordance with a second embodiment of the present invention. FIG. 7 illustrates how a memory cell and a storage capacitor are configured in a semiconductor memory device, the semiconductor memory device including a A memory unit of a unit capacitor and a peripheral circuit having a storage capacitor. Referring to Fig. 7, a memory cell having a unit capacitor 72A is formed in a 〇-monotron region, and a peripheral circuit including a storage capacitor is formed in a peripheral region. The storage capacitor includes a first bulk capacitor 72A and a second capacitor 720C connected in series between the first power line 7108 and the second power line 710C. Although two bulk capacitors are shown in Figure 7, more than two bulk capacitors may be included. Although not shown in Figure 7, the energy storage device can be formed by various methods as shown in Figures 1, 2 and 5. Specifically, as shown in FIG. 5, a MOS capacitor connected to the first bulk capacitor 720B and the second bulk capacitor 72〇c may be further included. In the present embodiment, the first bulk capacitor 72 of the energy storage capacitor and the second bulk capacitor 720C may each have substantially the same capacitance as the capacitance of the unit capacitor 720A. The unit capacitor 720A is a stacked capacitor 'which has a capacitor (COB) structure formed on a bit line for the bit line 71 0A or on the substrate on the bit line 710A. The unit capacitor 72A includes a storage node 722, a dielectric 1724I0.doc -10-200947672 dielectric 724A formed on the storage node 722A, and a plate electrode 726A formed on the dielectric 724A. The first bulk capacitor 720B includes: a first electrode 722B having the same material and surface area as the material and surface area of the storage node 722 A; a dielectric 724B formed on the first electrode 722A and having a ' The material of the dielectric 724A of the unit capacitor is the same material; and a second electrode 726B is formed on the dielectric 724B and made of the same material as the material of the plate electrode 726A. Therefore, the unit capacitor 720A and the first large capacitance capacitor 720B each have substantially the same capacitance. The first electrode 722C, the dielectric 724C, and the second electrode 726C of the second bulk capacitor may be substantially identical to the first electrode, the dielectric, and the second electrode of the first bulk capacitor 720B. The first electrode 722B of the first bulk capacitor 720B is connected to the first power line 710B and is in contact with the first power line 710B, and the first electrode 722C of the second bulk capacitor 720C is connected to the second power line 710C and is in contact with the second power line 710C. . The first electrode ® 722B of the first bulk capacitor 720B and the first electrode 722C of the second bulk capacitor 720C are each formed by patterning a conductive layer of the same material. • The second electrode 726B of the first bulk capacitor 720B and the second bulk. The second electrode 726C of the capacitor 720C is formed in common by a single conductive pattern. The first power line 710B and the second power line 710C are formed of a conductive layer of the same material as that of the conductive layer of the bit line in the cell region. The first power line 710B is separated from the second power line 710C by patterning. In addition to 137510.doc 200947672, other conductive layers for the first power line 710B and the second power line 71〇c may be used in addition to the conductive layer for the bit line. The first power line 710B receives a logic "high" voltage level corresponding to one or more signals for internal circuit commands of the memory. For example, the first power line 710B can be any of a supply voltage (vdd) line, a high voltage (Vpp) line core voltage (Vcore) line, and a bit line pre-charge voltage (Vblp) line. • The second power line 710C receives a voltage level corresponding to the logic "low" of one or more signals in the internal circuitry of the memory. For example, the second electric power line 710 (may be a ground voltage (Vss) line or a reverse bias voltage (Vbb) line. The first large capacity capacitor 720B and the second large capacity capacitor 72 〇 c Each of the dielectric layers may be a high dielectric film or a ferroelectric layer. In FIG. 7, reference numeral 7〇2 denotes a germanium substrate Si_sub, reference numeral 703 denotes a gate electrode of a unit cell, and reference numeral 7 〇 4, 7 〇 5 and 706 are contact plugs. φ The semiconductor memory device according to the fourth embodiment of the present invention may include the energy storage capacitor of FIG. 5 in each of the capacitor groups. Each of the large-capacity capacitors in each group has the same structure as that of the unit capacitor. As described above, the energy storage capacitor and the semiconductor having the same according to embodiments of the present invention can be applied to, for example, dynamics A semiconductor integrated circuit of a random access memory (dram) and a storage capacitor in other semiconductor devices use all of the conditions of the power supply scheme. The energy storage capacitor according to an embodiment of the present invention has a cell power formed on a bit line. The 137510.doc -12·200947672 dram is very useful. In particular, the energy storage capacitor according to an embodiment of the present invention can be advantageously formed in all peripheral circuits without metal contact points because of the early element capacitor It is not used in the peripheral circuit area. Since the power terminal can be placed on the transistor and there is no restriction to prevent the formation of the energy storage capacitor of the present invention, it is possible to add capacitance without increasing the area. The capacitor can be formed in any of the peripheral circuits.
❷ 雖然已關於特定實施例描述本發明，但熟習此項技術者 將顯而易見的是，在不背離如以下申請專利範圍中所界定 之本發明之精神及範疇的情況下可進行各種改變及修改。 本發明之實施例係關於具有儲能電容器之積體電路。本 實施例之儲能電容器使用一大容量電容器以移除低頻雜 訊。該大容量電容器具有當施加高電壓時洩漏增加的問 題。為了克服該問題，可串聯連接至少兩個大容量電容 器。 雖然在PF範圍内之電容可用以移除低頻雜訊，但M〇s 容器之電容可在#範圍内。為了在不增加面積的情況下 得在MF範圍内之電容，可在單位面積中之每—者中使用 M〇S電容器之電容大數百倍的電容。因為記憶體裝置之 元電容II在大小上比MOS電容器大約扇倍至伽倍，所 有可能使大體上具有與單元電容器之布局及材料相同的 局及材料之大容量電容器作為儲能電容器。 又，該大容量電容器可為具有大ESR之電容器。雖缺 藉由大容量電容器可能無法移除高頻雜訊，但则電容 I375I0.doc 200947672 可與大容量電容器組合使用以移除該高頻雜訊。 根據本發明之實施例的儲能電容器可減小約100 mV至 200 mV，至多500 mv的電力雜訊。又，根據本發明之實 施例的儲能電容器可穩定化諸如感測雜訊之低頻雜訊。 根據本發明之一例示性實施例，可在不增加晶片之大小 的情況下增加儲能電容器之電容。 使用單元電容器形成之儲能電容器可用以穩定化諸如用 於半導體裝置（諸如DRAM)中之内部電源及外部電源的電 源。特定言之，根據本發明之儲能電容器可用以穩定化具 有低電壓位準之供電電壓。根據本發明之儲能電容器亦可 用以在具有小電壓差之電源之間形成用於短路ac或/及開 路DC之連接。 【圖式簡單說明】 圖1為說明根據本發明之第一實施例之儲能電容器的圖 式。 圖2為根據本發明之第二實施例之儲能電容器的電路 圖。 圖3為圖2中所展示之儲能電容器的布局圖。 圖4為圖3中之儲能電容器沿線A_B所截之橫截面圖。 圖5為具有儲能電容器之MOS電容器及大容量電容器之 基板的橫截面圖。 圖6為說明DRAM之電路圖。 圖7為根據本發明之第三實施例之記憶體裝置的橫截面 圖0 137510.doc -14- 200947672 【主要元件符號說明】 120 第一電力供應單元 140 第二電力供應單元 160 大容量電容器 170 MOS電容器/MOS電晶體 180 大容量電容器 220 第一電力供應單元/第一電力供應群組 240 第二電力供應單元/第二電力供應群組 〇 260 第一電容器群組 270 MOS電容器 280 第二電容器群組 310 基板 320 第一電力線 340 第二電；6線 363A 第一電容器群組中之大容量電容器的第一電極 363B 第一電容器群組中之大容量電容器的第一電極 w 363C 第一電容器群組中之大容量電容器的第一電極 363D 第一電容器群組中之大容量電容器的第一電極 364 介電質 . 365 第二電極（板） 383A 第二電容器群組中之大容量電容器的第一電極 383B 第二電容器群組中之大容量電容器的第一電極 383C 第二電容器群組中之大容量電容器的第一電極 383D 第二電容器群組中之大容量電容器的第一電極 137510.doc -15- 200947672 510 大容量電容器 530 MOS電容器 702 參考數字 703 參考數字 704 參考數字 705 參考數字 706 參考數字 710A 位元線 ❹ 710B 第一電力線 710C 第二電力線 720A 單元電容器 720B 第一大容量電容器 720C 第二大容量電容器 722A 儲存節點 722B 第一電極 722C 第一電極 ❿ 724A 介電質 724B 介電質 « 724C 介電質 - 726A 板狀電極 726B 第二電極 726C 第二電極 Cap 單元電容器 D 汲極 137510.doc -16- 200947672 G 閘極 S 源極 Si-sub 矽基板 Tr 存取電晶體 VDD 第一電力線 vss 第二電力線 ❹Although the present invention has been described with respect to the specific embodiments thereof, it is apparent that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. Embodiments of the present invention relate to an integrated circuit having a storage capacitor. The energy storage capacitor of this embodiment uses a large capacity capacitor to remove low frequency noise. This large-capacity capacitor has a problem that leakage increases when a high voltage is applied. To overcome this problem, at least two bulk capacitors can be connected in series. Although the capacitance in the PF range can be used to remove low frequency noise, the capacitance of the M〇s container can be in the range #. In order to obtain a capacitance in the MF range without increasing the area, a capacitance hundreds of times larger than the capacitance of the M〇S capacitor can be used in each of the unit areas. Since the element capacitance II of the memory device is approximately doubled to gamma-fold larger than the MOS capacitor, it is possible to use a large-capacity capacitor having substantially the same layout and material as that of the unit capacitor as the storage capacitor. Also, the bulk capacitor can be a capacitor having a large ESR. Although high-frequency noise may not be removed by large-capacity capacitors, the capacitor I375I0.doc 200947672 can be used in combination with a large-capacity capacitor to remove the high-frequency noise. The energy storage capacitor according to an embodiment of the present invention can reduce power noise of about 100 mV to 200 mV up to 500 mV. Further, the energy storage capacitor according to the embodiment of the present invention can stabilize low frequency noise such as sensing noise. According to an exemplary embodiment of the present invention, the capacitance of the storage capacitor can be increased without increasing the size of the wafer. A storage capacitor formed using a unit capacitor can be used to stabilize a power source such as an internal power source and an external power source used in a semiconductor device such as a DRAM. In particular, an energy storage capacitor in accordance with the present invention can be used to stabilize a supply voltage having a low voltage level. The energy storage capacitor according to the present invention can also be used to form a connection for shorting ac or/and open circuit DC between power supplies having a small voltage difference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a storage capacitor according to a first embodiment of the present invention. Fig. 2 is a circuit diagram of a storage capacitor in accordance with a second embodiment of the present invention. 3 is a layout view of the energy storage capacitor shown in FIG. 2. 4 is a cross-sectional view of the energy storage capacitor of FIG. 3 taken along line A_B. Fig. 5 is a cross-sectional view showing a substrate of a MOS capacitor having a storage capacitor and a bulk capacitor. Figure 6 is a circuit diagram illustrating a DRAM. Figure 7 is a cross-sectional view of a memory device in accordance with a third embodiment of the present invention. 0 137510.doc -14- 200947672 [Main element symbol description] 120 First power supply unit 140 Second power supply unit 160 Large-capacity capacitor 170 MOS capacitor / MOS transistor 180 bulk capacitor 220 first power supply unit / first power supply group 240 second power supply unit / second power supply group 260 260 first capacitor group 270 MOS capacitor 280 second capacitor Group 310 substrate 320 first power line 340 second power; 6 line 363A first electrode 363B of bulk capacitor in first capacitor group first electrode w 363C first capacitor of bulk capacitor in first capacitor group The first electrode 363D of the bulk capacitor in the group is the first electrode 364 of the bulk capacitor in the first capacitor group. 365 Second electrode (plate) 383A The bulk capacitor of the second capacitor group The first electrode 383B is the first electrode 383C of the bulk capacitor in the second capacitor group First electrode 383D of the capacitor First electrode of the large capacity capacitor in the second capacitor group 137510.doc -15- 200947672 510 Large capacity capacitor 530 MOS capacitor 702 Reference numeral 703 Reference numeral 704 Reference numeral 705 Reference numeral 706 Reference numeral 710A Bit line ❹ 710B First power line 710C Second power line 720A Unit capacitor 720B First bulk capacitor 720C Second bulk capacitor 722A Storage node 722B First electrode 722C First electrode 724 724A Dielectric 724B Dielectric « 724C Dielectric - 726A plate electrode 726B second electrode 726C second electrode Cap unit capacitor D drain 137510.doc -16- 200947672 G gate S source Si-sub 矽 substrate Tr access transistor VDD first power line vss Second power line
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