KR100647384B1 - Appratus for controlling Reservoir Capacitance in Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a leisure capacitance adjusting device of a semiconductor memory device, in order to solve the problem that it is difficult to prepare for stable voltage supply and noise generation due to the leisure capacitance fixed to a specific value, one adjustment A capacitance control circuit including a capacitor is provided to adjust the leisure capacitance according to the magnitude of the voltage supplied to the semiconductor memory device, thereby implementing the leisure capacitor control device that provides the memory device flexibly, and provides a stable voltage supply and noise. In addition to the effect of prevention, the effect of providing various capacitances in a limited area and maximizing the capacitor capacity per area is obtained.

Description

Apparatus for controlling Reservoir Capacitance in Semiconductor Memory Device

1 is a circuit diagram showing a conventional leisure-time capacitance adjusting device.

Figure 2 is a block diagram showing an apparatus for adjusting leisure capacitance, which is an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a first embodiment of a capacitance controller in the leisure capacitance adjusting device of the present invention shown in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of a capacitance controller in the leisure capacitance adjusting device of the present invention shown in FIG.

FIG. 5 is a circuit diagram of a third embodiment of a capacitance control unit in the leisure capacity capacitance adjusting apparatus of the present invention shown in FIG. 2;

6 is an operation timing diagram of the leisure capacity capacitance adjusting device of the present invention shown in FIG.

<Description of Symbols for Main Parts of Drawings>

  1, 2: Reservoir capacitor 10: Adjustable capacitor

  20: control signal generator 30: capacitance control unit

The present invention relates to a leisure capacitance adjusting device, and in particular, having a capacitance control circuit including one regulating capacitor, in supplying two or more power supply voltages, the leisure capacitance is determined according to the supply voltage magnitude supplied. The present invention relates to a leisure capacitance adjusting device that adjusts and flexibly provides a memory device.

In semiconductor memory devices, the capacitor is composed of MOS transistors. By supplying the ground voltage to the source and drain of the MOS transistor and supplying a specific voltage to the gate, the capacitor is implemented. The capacitance of the leisure capacitor is implemented according to the voltage applied to the gate of the MOS transistor. Is determined.

As shown in FIG. 1, in the related art, leisure capacitors 1 and 2 are disposed in a predetermined space according to two or more power supply voltages Vext and Vdd provided to a semiconductor memory device, respectively. The capacitance of is fixed to a predetermined value by the voltages applied to the gates of the MOSFETs NM1 and NM2 constituting the respective leisure capacitors, and according to the magnitude of the power supply voltage supplied to the memory element, sufficient capacitance is required. Since it cannot be provided in a flexible manner, it is difficult to prepare noise, and there is a problem in providing a stable voltage.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and includes a capacitance control circuit including one regulating capacitor to adjust the capacitance according to the magnitude of the voltage supplied to the memory device. It is an object of the present invention to provide a leisure capacitance regulating device which is flexibly provided to a memory device.

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Recreational capacitance device of the present invention for achieving the above object, a plurality of power supply voltage; And a plurality of leisure capacitors connected between each of a plurality of power supply voltages and a ground, the leisure capacitor adjusting apparatus of a semiconductor memory device comprising: an adjustment capacitor; A control signal generator which receives a mode control signal and a burst control signal and outputs a voltage control signal for selecting one power supply voltage to be applied to a control capacitor among a plurality of power supply voltages; And a capacitance controller for applying one of the plurality of power voltages to the regulating capacitor according to the voltage control signal.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Figure 2 shows a leisure capacitance adjusting device according to an embodiment of the present invention. Referring to the drawings, the leisure device capacitance adjusting apparatus of the present invention

An external power supply voltage Vext and an internal power supply voltage Vdd, two leisure capacitors 1 and 2 connected to the ground from each of the external power supply voltage Vext and the internal power supply voltage Vdd, and a regulating capacitor 10 And a control signal generator 20 for generating a voltage control signal SEL for selecting one of the external power supply voltage Vext and the internal power supply voltage Vdd as a voltage to be applied to the regulating capacitor 10. And a capacitance controller 30 for adjusting the leisure capacitance by applying a voltage selected according to the voltage control signal SEL from the control signal generator 20 to the regulating capacitor 10.

The two leisure capacitors 1 and 2 and the regulating capacitor 10 each consist of one NMOS transistor NM1, NM2 and NM4.

The control signal generator 20 is connected in series between the internal power supply voltage Vdd and ground, and the gate of the control signal generator 20 is a signal in which the precharge signal is inverted by the inverter IV1 and the read enable signal READ, respectively. An input PMOS transistor PM1 and an NMOS transistor NM3,

A latch 21 composed of two inverters IV2 and IV3 which invertes and latches an output signal from a common connected drain of the PMOS transistor PM1 and the NMOS transistor NM3,

The NAND gate receives the inverted latched signal AAA and the inverted signal of the burst control signal BST_CNTL by the inverter IV4 through the latch 21, and NANDs the NAND gate to output the voltage control signal SEL. (ND1).

3 shows a first embodiment of the capacitance control unit 30 of the present invention.

In the capacitance control unit 30 of the present invention according to the first embodiment, a source is connected to an external power supply voltage Vext and an internal power supply voltage Vdd, and the drain is an NMOS constituting the control capacitor 10. Commonly connected to the gate of the transistor NM4, the gate supplying signal of the power supply control signal SEL and the power supply control signal SEL from the control signal generator 10 is inverted by the inverter IV5, respectively. In response to the input, two PMOS transistors PM2 and PM3 apply one of the two voltages to the control capacitor 10.

4 shows a second embodiment of the capacitance control unit 30 of the present invention.

In the capacitance control unit 30 according to the second embodiment, a source is connected to an external power supply voltage Vext and an internal power supply voltage Vdd, and the drain of the NMOS transistor NM4 constituting the control capacitor 10 is connected. Commonly connected to the gate, the inverted signal of the power supply control signal SEL by the inverter IV6 and the power supply control signal SEL inverted signal by the inverter IV6 are again inverted by the inverter IV7. Each of them is composed of two NMOS transistors NM2 and NM3 that receive one input and thus apply one of the two voltages to the control capacitor 10.

5 shows a capacitance control unit 30 according to the third embodiment.

The capacitance controller 30 according to the third embodiment selectively applies two external input voltages Vext and the internal power supply voltage Vdd to the gates of the NMOS transistor NM4 constituting the control capacitance 10. Consists of transmission gates (TG1, TG2),

The transfer gate TG1 is controlled by the voltage control signal SEL and the inverted signal of the voltage control signal SEL by the inverter IV8, which are respectively input toward the p-channel and n-channel, and the transfer gate TG2 is p The inversion signal of the voltage control signal SEL by the inverter IV8 and the voltage control signal SEL, which are respectively inputted toward the channel and the n channel, are controlled by signals sequentially inverted by the inverters IV8 and IV9, thereby One of the power supply voltage Vext and the internal power supply voltage Vdd is selected and applied to the control capacitor 10.

Looking at the operation of the leisure capacity capacitance adjustment apparatus of the present invention configured as described above is as follows.

First, the operation of the capacitance control unit 30 according to each embodiment of the present invention is as follows.

In the capacitance control unit 30 according to the first embodiment shown in FIG.

First, when the "low" voltage control signal SEL is input to the capacitance control unit 30, the voltage control signal SEL of "low" and the gate of the PMOS transistor PM2 and the PMOS transistor PM3, respectively, and The inverted signal of the voltage control signal SEL by the inverter IV5 is input, the PMOS transistor PM2 is turned on and the PMOS transistor PM3 is turned off, so that the external power supply voltage Vext is adjusted. Applied to capacitor C10.

On the other hand, when the voltage control signal SEL of " high " is input to the capacitance controller 30, the PMOS transistor PM2 is turned off and the PMOS transistor PM3 is turned on, so that the internal power supply voltage Vdd is turned on. Is applied to the regulating capacitor 10.

In the capacitance control unit 30 according to the second embodiment of the present invention shown in FIG.

First, when the "low" voltage control signal SEL is input and the "high" signal and the "low" signal are respectively input to the gates of the NMOS transistor NM5 and the NMOS transistor NM6, the NMOS transistor ( NM5 is turned on and NMOS transistor NM6 is turned off, so that external power supply voltage Vext is applied to regulating capacitor 10.

On the other hand, when the voltage control signal SEL of "high" is input, the NMOS transistor NM5 is turned off and the NMOS transistor NM6 is turned on, so that the internal power supply voltage Vdd is adjusted. Is applied.

In the capacitance control unit 30 according to the third embodiment of the present invention of FIG.

First, when the "low" voltage control signal SEL is input, the "low" and "high" signals are input to the p-channel and the n-channel of the transfer gate TG1, respectively, and the p-channel of the transfer gate TG2. When the "high" and "low" signals are respectively input to the n channel, the transfer gate TG1 is 'open' and the transfer gate TG2 is 'closed', so that the external power supply voltage Vext is adjusted to the regulating capacitor 10. Is applied to.

On the other hand, when a signal of "high" is input, the transfer gate TG1 is "closed" and the transfer gate TG2 is "open" so that the internal power supply voltage Vdd is applied to the regulating capacitor 10.

Referring to the operation timing diagram shown in FIG. 6 and the operation of the capacitance controller 30, the operation of the leisure capacitance adjusting device according to the embodiment of the present invention shown in FIG. 2 will be described below.

First, when the read enable signal READ of the "high" pulse is input to the gate of the NMOS transistor NM3 of the control signal generator 20, the "low" signal is inverted and latched by the latch 21. Is input to the NAND gate ND1 with the latch signal AAA of "high". As another input of the NAND gate ND1, an inverted signal of the burst control signal BST_CNTL by the inverter IV4 is input. While the latch signal AAA maintains "high", the NAND gate ND1 outputs the voltage control signal SEL in accordance with the input burst control signal BST_CNTL, and the "high" burst control signal BST_CNTL. ) Is inputted to output the "low" voltage control signal SEL.

When the "low" voltage control signal SEL is input to the capacitance controller 30, the external power supply voltage Vext is applied to the regulating capacitor 10. In this case, the capacitance of the regulating capacitor 10 determined to be applied with the external power supply voltage Vext is added to the capacitance of the leisure capacitor 1 fixedly provided to the external power supply voltage Vext. Leisure Look Capacitance is provided.

The external power supply voltage Vext applied during a read operation requiring a large power is larger than the internal power supply voltage Vdd applied to the memory circuit in other operations, so that the internal power supply voltage Vdd is Much larger capacitance is provided by the adjusting capacitor 10 to the memory device than when applied.

After the read operation is completed, when the burst control signal BST_CNTL of "high" is switched to "low", the voltage control signal SEL is switched to "high" and input to the capacitance controller 30, and the internal power supply voltage ( Vdd) is applied to the regulating capacitor 10. At this time, in addition to the capacitance of the leisure capacitor 2 connected to the internal power supply voltage Vdd, the capacitance of the regulating capacitor 10 determined by the applied internal power supply voltage Vdd is further provided to the memory device, and the size thereof. Is reduced to match the internal power supply voltage Vdd which is less than the external input voltage Vext.

 After the voltage supplied to the memory device is changed to the internal power supply voltage Vdd, when the precharge signal PCG of the "high" pulse is input to the control signal generator 20, the latch signal AAA is set to "low". Is switched, the voltage control signal SEL remains " high "

According to the leisure capacitance adjusting apparatus of the present invention as described above, by providing the capacitance in accordance with the power supply voltage supplied to the memory element, there is an effect of stable supply of voltage and noise reduction, by using one regulating capacitor, Since the capacitance can be efficiently adjusted for various voltage supplies, there is an effect of reducing the capacitor area, and a large capacitance can be obtained by increasing the voltage applied to the regulating capacitor, thereby maximizing the capacity of the capacitor.

On the other hand, the present invention is not limited to the above-described embodiment, but can be modified and modified within the scope not departing from the gist of the present invention, such modifications and changes should be regarded as belonging to the following claims. will be.

Claims (7)

A plurality of power supply voltages; And In the leisure capacitance adjusting device of a semiconductor memory device comprising a plurality of leisure capacitors connected between each of the plurality of power supply voltages and ground, Regulating capacitor; A control signal generator which receives a mode control signal and a burst control signal and outputs a voltage control signal for selecting one of the plurality of power voltages to be applied to the control capacitor; And A capacitance control unit for applying one of the plurality of power supply voltages to the regulating capacitor according to the voltage control signal. Leisure capacity capacitance adjusting device of a semiconductor memory device comprising a. The method of claim 1, wherein the control signal generator A PMOS transistor and an NMOS transistor connected in series between an internal power supply voltage and a ground to receive an inverted signal and a read enable signal of a precharge signal, respectively, as a gate; A latch unit for inverting and latching an output signal from a common connected drain of the PMOS transistor and the NMOS transistor; And A NAND gate configured to receive a latch signal from the latch unit and an inverted signal of the burst control signal; Leisure look capacitance adjustment device comprising a. The method of claim 1, The capacitance control unit is connected between each of the plurality of power supply voltages and the control capacitor, and selects one of the plurality of power supply voltages according to a voltage control signal from the control signal generator and applies the voltage to the control capacitor. Residual capacitance adjusting device of a semiconductor memory device comprising a switching means. The method of claim 3, wherein And said switching means is a plurality of PMOS transistors. The method of claim 3, wherein And said switching means is a plurality of NMOS transistors. The method of claim 3, wherein And said switching means is a plurality of transfer gates. The method of claim 1, The regulating capacitor is a leisure capacitance adjusting device of the semiconductor memory device, characterized in that consisting of a MOS transistor.

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