KR101128982B1 - Reservoir capacitor and semiconductor memory device with the same - Google Patents

Abstract

Disclosed are a leisure bar capacitor and a semiconductor memory device having the same for reducing low frequency noise and leakage current. A semiconductor memory device for this purpose comprises a memory cell having a cell capacitor and a peripheral circuit having a leisure bar capacitor, wherein the leisure bar capacitor is connected in series between the first power supply means and the second power supply means. And at least two large capacity capacitors, wherein each of the large capacity capacitors has substantially the same capacitance as the cell capacitor.

Memory, Leisure Bar Capacitor, Low Frequency, High Frequency, Noise, Leakage Current

Description

Leisure Bar Capacitor and Semiconductor Memory Device Having the Same {RESERVOIR CAPACITOR AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having a reservoir capacitor, and more particularly to a memory device.

Increasingly, memories such as DRAMs require low voltage and high speed operation. In high-speed operation, the small inductance of the package / board interferes with supplying the required current, and when a low power supply voltage is used to reduce power consumption, noise of a small power supply voltage causes a circuit delay ( Delay is greatly changed, causing malfunction.

To overcome this phenomenon, the noise of the power supply voltage should be kept small. The impedance between the external power supply and the on-chip circuit is very small, or the circuit around the circuit provided in the chip The impedance of the capacitor should be increased by increasing the capacitance of the bar capacitor. Here, the leisure bar capacitor is used in the power supply to minimize the voltage drop caused by power consumption.

For high frequency noise, a small enough impedance can be achieved with a leisure bar capacitor with a small ESR (Equivalent Series Resistance), but for a low frequency noise a very large capacitance leisure bar capacitor is required.

The present invention has been proposed to solve the above problems of the prior art.

It is an object of the present invention to provide a leisure bar capacitor suitable for stabilizing low frequency noise without increasing the chip area.

In addition, another object of the present invention is to provide a leisure bar capacitor which solves the problem of a large leakage current when a high voltage is applied due to the use of a large capacity capacitor.

In addition, another object of the present invention is to provide a leisure bar capacitor that can be implemented to have a large capacitance without adding an additional area.

It is another object of the present invention to provide an integrated circuit having a leisure bar capacitor having the above characteristics.

Another object of the present invention is to provide a semiconductor memory device in which a cell capacitor is applied to a leisure bar capacitor of a peripheral circuit, but the leakage current increases when a high voltage is applied.

The leisure bar capacitor according to the first embodiment of the present invention, the first power supply means and the second power supply means; And at least two large capacity capacitors connected in series between the first power supply means and the second power supply means.

In addition, the leisure bar capacitor according to the second embodiment of the present invention, the first power supply means and the second power supply means; A first capacitor group having a plurality of large capacity capacitors connected in parallel; And a second capacitor group having a plurality of large capacity capacitors connected in parallel. The first capacitor group and the second capacitor group are connected in series between the first and second power supply means.

The leisure bar capacitor according to the first embodiment of the present invention may further include a MOS capacitor connected in parallel with the at least two large capacity capacitors between the first power supply means and the second power supply means. The leisure bar capacitor according to the second embodiment of the present invention may further include a MOS capacitor connected in parallel with the first and second capacitor groups between the first power supply means and the second power supply means. In this case, the large capacity capacitors may be disposed above the MOS capacitors on the substrate.

In the leisure bar capacitors according to the first and second embodiments of the present invention, the large capacity capacitor has a structure in which a lower electrode conductive layer, a dielectric layer, and an upper electrode conductive layer are sequentially stacked. The first power supply means includes a first power line to receive a first power, and the lower electrode conductive layer of the large capacity capacitor is in contact with the first power line. The second power supply means includes a second power line to receive a second power source, and the lower electrode conductive layer of the large capacity capacitor is in contact with the second power line.

The dielectric layer of the large capacity capacitor may be a high dielectric thin film or a ferroelectric thin film.

In addition, a semiconductor memory device according to a third embodiment of the present invention includes a memory cell having a cell capacitor and a peripheral circuit having a leisure bar capacitor, wherein the leisure bar capacitor has a first power supply means and a second power supply. At least two large capacity capacitors connected in series between the means, wherein each of the large capacity capacitors has the same capacitance as the cell capacitor.

In addition, a semiconductor memory device according to a fourth embodiment of the present invention includes a memory cell having a cell capacitor and a peripheral circuit having a leisure bar capacitor, wherein the leisure bar capacitor includes a plurality of large capacity capacitors connected in parallel. A first capacitor group and a second capacitor group having a plurality of large capacity capacitors connected in parallel, wherein the first capacitor group and the second capacitor group are connected in series between first and second power supply means, respectively The large capacity capacitor of has the same capacitance as the cell capacitor.

In the semiconductor memory device according to the third embodiment of the present invention, the leisure bar capacitor may further include a MOS capacitor connected in parallel with the at least two large capacity capacitors between the first power supply means and the second power supply means. have. In the semiconductor memory device according to the fourth embodiment of the present invention, the leisure bar capacitor also includes a MOS capacitor connected in parallel with the first and second capacitor groups between the first power supply means and the second power supply means. It may further include.

The memory device has a cell array area and a peripheral circuit area planarly in the chip. In the present invention, when the cell capacitor is patterned in the cell area, the large capacity capacitor is similarly patterned in the peripheral circuit area. In particular, in the memory devices according to the third and fourth embodiments of the present invention, the cell capacitor is a stack capacitor of a COB (capacotor on bitline) structure formed on the bit line on the substrate.

In the process of forming the cell capacitor of the stack structure, a large capacity capacitor may be patterned in the peripheral circuit region. A large capacity capacitor may be formed in the peripheral circuit area without the metal contact, and the large capacity capacitors may be disposed on the MOS capacitor.

In the memory devices according to the third and fourth embodiments of the present invention. The first power supply means may be any one selected from the group consisting of a power supply voltage Vdd line, a high voltage Vpp line, a core voltage Vcore line, and a bit line precharge voltage Vblp line. The second power supply means may be a ground voltage Vss line or a back bias voltage Vbb line.

The leisure bar capacitor of the present invention uses a large capacity capacitor to remove low frequency noise. And a large capacity capacitor has a problem that the leakage current increases when a high voltage is applied. To overcome this, a method of connecting at least two large capacitors in series is used.

To remove low frequency noise, uF capacitance is required, but the capacitance of MOS capacitors is only a few tens of nF. In order to obtain uF-class capacitance without increasing the area, it is necessary to have capacitance per unit area that is several hundred times that of MOS capacitor. Since the cell capacitor of the current memory device has a size of about 300 to 400 times that of the MOS capacitor, a large capacity capacitor formed of substantially the same layout and materials as the cell capacitor can be used as a leisure bar capacitor. When each of the large capacity capacitors constituting the leisure bar capacitor is formed of substantially the same layout and materials as the cell capacitors, the cell capacitors and the large capacity capacitors have substantially the same capacitance.

Large capacity capacitors are also capacitors with large ESR. Since this alone cannot remove high frequency noise, it is also possible to remove high frequency noise by using MOS capacitors together.

The present invention can reduce the power supply noise of 100mV ~ 200mV to 50mV or less. Low frequency noise such as sensing noise can be stabilized.

The present invention is a method that can greatly increase the capacitance of the leisure bar capacitor without increasing the chip area.

Reservoir capacitors made using cell capacitors can be used for the purpose of stabilizing all power supplies (internal / external power supplies) used in semiconductor devices such as DRAM. In particular, such a leisure bar capacitor can be used for stabilization of a low power supply voltage. And it can be used for the connection for the purpose of AC short circuit and / or DC open between power supply with small voltage difference.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is an equivalent circuit diagram of a leisure bar capacitor according to a first embodiment of the present invention.

Referring to FIG. 1, the leisure bar capacitor includes a first power supply 120 and a second power supply 140, and includes at least two large capacity capacitors 160 and 180 connected in series between the first power supply 120 and the second power supply 140. Include. In addition, between the first power supply 120 and the second power supply 140, it includes a MOS capacitor 170 connected in parallel with the large capacity capacitor. Morse capacitor 170 can be omitted. Morse capacitor 170 has a capacitance of several tens of nF class. The large capacity capacitors 160 and 180 have a capacitance of uF class. The large capacity capacitors 160 and 180 have a structure in which a lower electrode conductive layer, a dielectric layer, and an upper electrode conductive layer are sequentially stacked. The lower electrode and the upper electrode of each of the large capacity capacitors may be made of polysilicon, a metal thin film, and the like. And the use of ferroelectrics.

As described above, the leisure bar capacitor uses large capacity capacitors 160 and 180 to remove low frequency noise. In addition, since the large capacity capacitors 160 and 180 have a problem in that leakage current increases when a high voltage is applied, a method of connecting at least two series of large capacity capacitors is used.

In addition, the large capacity capacitors 160 and 180 are capacitors with large ESR. Since this alone cannot remove high frequency noise, it is also possible to remove high frequency noise by using a Morse capacitor 170 together.

2 is an equivalent circuit diagram of a leisure bar capacitor according to a second embodiment of the present invention.

Referring to FIG. 2, the leisure bar capacitor includes a first power supply unit 220 and a second power supply unit 240, and includes a first capacitor group 260 having a plurality of large capacity capacitors connected in parallel, and a plurality of large capacity capacitors connected in parallel. A second capacitor group 280.

Herein, the first capacitor group 260 and the second capacitor group 280 are connected in series between the first and second power supply units 220 and 240. In addition, the first power supply unit 220 and the second power supply unit 240 includes a MOS capacitor 270 connected in parallel with the first and second capacitor group. Morse capacitor 270 can be omitted.

Morse capacitor 270 has a capacitance of several tens of nF class. Each unit large capacity capacitor belonging to the first and second capacitor groups has a capacitance of uF class. In the present exemplary embodiment, two capacitor groups 260 and 280 are connected in series, but three or more capacitor groups connected in series may be used.

In addition, the capacitors belonging to each capacitor group have a structure in which lower electrodes, dielectrics, and upper electrodes are sequentially stacked as described in the embodiment of FIG. This can be used, and the dielectric can use high dielectric constant and ferroelectric.

FIG. 3 is a layout diagram of capacitor groups 260 and 280 shown in FIG. 2. When connected in series with a capacitor group as in the second embodiment, the upper electrode (plate) patterning of the large capacity capacitor becomes easy.

Referring to FIG. 3, a first power line 320 to which the first power is applied and a second power line 340 to which the second power is applied are provided. Lower electrodes (first electrodes) 363a, 363b, 363c, and 363d of each of the large capacitors in the first capacitor group 260 are contacted on the first power line 320, and the large capacity belonging to the second capacitor group 280 is connected to the second power line 340. Lower electrodes 383a, 383b, 383c, and 383d of the capacitors are contacted. The upper electrode (second electrode) of each of the large capacitors of the first capacitor group 260 and the upper electrode (fourth electrode) of each of the large capacitors of the second capacitor group 280 are formed as a common electrode by a single conductive layer pattern 365.

The leisure bar capacitor according to the first embodiment shown in FIG. 1 has only the number of lower electrodes (ie, lower electrodes of the large capacitor 160 and lower electrodes of the large capacitor 180) formed on the first power line and the second power line. Only different, the layout is the same as FIG.

4 is a cross-sectional view taken along the line A-B of FIG. 3.

Referring to FIG. 4, a first power line 320 and a second power line 340 are provided on the substrate. The first and second power lines 320 and 340 are patterned with a conductive layer such as metal or polysilicon. Lower electrodes 363a, 363b, 383a, and 383b of the large-capacity capacitors penetrate the insulating layer 310 to contact the first and second power lines 320 and 340. A dielectric 364 is formed on the entire substrate structure including the lower electrodes 363a, 363b, 383a, and 383b, and an upper electrode 365 is formed on the dielectric 364. The dielectric 364 and the upper electrode 365 are commonly formed by the same thin film without being separated for each of the large capacity capacitors, but may be separately formed.

5 is a cross-sectional view of a MOS capacitor formed on a substrate with a large capacity capacitor. The large capacity capacitor 150 is disposed above the MOS capacitor 530 on the substrate Si-sub.

The MOS capacitor 530 has a gate G, a source S, and a drain D formed on the silicon substrate Si-sub. The source S and the drain D are connected to the second power line VSS and the gate G is connected to the first power line VDD. In FIG. 5, the large capacity capacitor and the connection wiring are shown in an equivalent circuit.

6 shows a typical DRAM cell. Referring to FIG. 6, a memory cell includes an access transistor Tr. Connected to a word line and a bit line, and a cell capacitor Cap. For storing cell data. The leisure bar capacitor of the present embodiment described above can be applied to a memory device having the above cell capacitor.

7 illustrates a memory device according to a third embodiment of the present invention. In a semiconductor memory device having a memory cell having a cell capacitor and a peripheral circuit having a leisure bar capacitor, a memory cell and a leisure bar capacitor are shown.

Referring to FIG. 7, a memory cell including a cell capacitor 720A is formed in a cell region, and peripheral circuits including a leisure bar capacitor are formed in a peripheral circuit region.

The leisure bar capacitor includes first and second large capacity capacitors 720B and 720C connected in series between the first power line 710B and the second power line. Although only two large capacitors are shown in the figure, more than this can be configured. In addition, although not shown in FIG. 7, the leisure bar capacitor may be configured in various ways as shown in FIGS. 1, 2, and 5. In particular, as shown in FIG. 5, the first and second high capacity capacitors 720B and 720C may further include a Morse capacitor connected in parallel.

Importantly, the first and second large capacity capacitors 720B and 720C constituting the leisure bar capacitor have substantially the same capacitance as the cell capacitor 720A.

The cell capacitor 720A is a stack capacitor having a capacitor on bitline (COB) structure formed on the bit line 710A on the substrate. The cell capacitor 720A includes a storage node 722A, a dielectric 724A formed on the storage node 722A, and a plate electrode 726A formed on the dielectric 724A.

The first large capacity capacitor 720B is formed on the lower electrode 722B having the same material and surface area as the storage node 722A, the lower electrode 722A, the dielectric 724B formed of the same material as the dielectric 724A of the cell capacitor, and the dielectric 724B, and the plate electrode 726A. An upper electrode 726B formed of the same material is provided. Thus, the cell capacitor 720A and the first high capacity capacitor 720B have substantially the same capacitance. The first electrode 722C, the dielectric 724C, and the second electrode 726C of the second large capacity capacitor 720C are also formed in the same manner as those of the first large capacity capacitor 720B, respectively.

The lower electrode 722B of the first large capacity capacitor 720B is contacted and connected to the first power supply line 710B, and the lower electrode 722C of the second large capacity capacitor 720C is contacted and connected to the second power supply line 710C. The lower electrode 722B of the first large capacity capacitor 720B and the lower electrode 722C of the second large capacity capacitor 720C are formed by patterning the same conductive layer.

The upper electrode 726B of the first large capacity capacitor 720B and the upper electrode 726C of the second large capacity capacitor 720C are commonly configured by a single conductive layer pattern.

The first power line 710B and the second power line 710C are the same conductive layer as the bit line 170A in the cell region and are patterned and separated. The first power line 710B and the second power line 710C may use other conductive layers in addition to the bit line conductive layer.

The first power line 710B receives a voltage level corresponding to logic 'high' among various voltages used in internal circuits of the memory. That is, the first power line 710B may be any one selected from the group of a power supply voltage Vdd line, a high voltage Vpp line, a core voltage Vcore line, and a bit line precharge voltage Vblp line.

The second power supply line 710C receives a voltage level corresponding to a logic 'low' among various voltages used in internal circuits of the memory. That is, the second power line 710C may be a ground voltage Vss line or a back bias voltage Vbb line.

Each dielectric layer of the first and second high capacity capacitors 720B and 720C may be a high dielectric thin film or a ferroelectric thin film.

In FIG. 7, reference numeral 702 denotes a silicon substrate, 703 denotes a gate electrode of a cell transistor, and 704, 705, and 706 denote contact plugs.

As a semiconductor memory device according to a fourth embodiment of the present invention, an embodiment in which a leisure bar capacitor is configured for each capacitor group is possible as shown in FIGS. 3 and 5, wherein each large-capacity capacitor belonging to each group is configured to be the same as a cell capacitor. do.

As described above, the present invention can be applied to a case where a power supply scheme using a leisure bar capacitor is used in a semiconductor integrated circuit such as a DRAM. It can be applied to semiconductor devices other than memory. In addition, the present invention is very useful in a structure in which a cell capacitor is implemented on the bit line among DRAMs. In particular, since the cell capacitor is not used in the peripheral circuit region, there is an advantage that it can be formed in all peripheral circuit regions without metal contact. In the conventional DRAM, the power terminal is provided on the MOS capacitor, and since the leisure bar capacitor of the present invention is not limited, it is possible to increase the capacitance without increasing the area. In addition, high-capacity capacitors can be made anywhere in the peripheral circuit area without metal contacts.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is an equivalent circuit diagram of a leisure bar capacitor according to a first embodiment of the present invention.

2 is an equivalent circuit diagram of a leisure bar capacitor according to a first embodiment of the present invention.

3 is a layout plan view of the leisure bar capacitor shown in FIG. 2;

4 is a cross-sectional view taken along the line A-B of FIG.

5 is a cross-sectional view formed on a substrate with a MOS capacitor and a large capacity capacitor constituting the leisure bar capacitor.

6 is a typical DRAM cell circuit diagram.

7 is a sectional view of a memory device according to a third embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

120: first power supply unit 140: second power supply unit

160, 180: large capacity capacitor 170; MOS capacitor

Claims (52)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete A semiconductor memory device comprising a memory cell having a cell capacitor and a peripheral circuit having a leisure bar capacitor. The leisure bar capacitor includes at least two large capacity capacitors connected in series between the first power supply means and the second power supply means, Each of the large capacity capacitors has substantially the same capacitance as the cell capacitors. Semiconductor memory device. 24. The method of claim 23, The leisure bar capacitor further includes a MOS capacitor connected in parallel with the at least two large capacity capacitors between the first power supply means and the second power supply means. Semiconductor memory device. The method of claim 23 or 24, The cell capacitor is formed above the bit line on the substrate. Semiconductor memory device. The method of claim 23 or 24, The cell capacitor includes a storage node, a first dielectric formed on the storage node, and a plate electrode formed on the first dielectric, The high capacity capacitor may include a first electrode having the same material and surface area as the storage node, a second dielectric formed on the first electrode and the same material as the first dielectric, and formed on the second dielectric and the plate electrode. A second electrode formed of the same material as Semiconductor memory device. The method of claim 23 or 24, The at least two large capacity capacitors, A first large capacity capacitor formed by stacking a lower electrode, a dielectric, and an upper electrode connected to the first power supply means; And And a second large capacity capacitor formed by stacking a lower electrode, a dielectric, and an upper electrode connected to the second power supply means. Semiconductor memory device. 28. The method of claim 27, The lower electrode of the first large capacity capacitor and the lower electrode of the second large capacity capacitor are separated by patterning the same conductive layer deposited on the substrate. Semiconductor memory device. 28. The method of claim 27, The upper electrode of the first large capacity capacitor and the upper electrode of the second large capacity capacitor are commonly configured by a single conductive layer pattern. Semiconductor memory device. 28. The method of claim 27, The first power supply means includes a first power line to receive a first power, the lower electrode of the first large capacity capacitor is configured to contact the first power line, The second power supply means includes a second power line to receive a second power source, the lower electrode of the second large capacity capacitor is configured to contact the second power line Semiconductor memory device. 31. The method of claim 30, The first power line and the second power line are separated by patterning a conductive layer for bit lines. Semiconductor memory device. The method of claim 31, wherein The first power line is any one selected from the group of a power supply voltage Vdd line, a high voltage Vpp line, a core voltage Vcore line, and a bit line precharge voltage Vblp line. Semiconductor memory device. The method of claim 31, wherein The second power supply line is a ground voltage (Vss) line or a back bias voltage (Vbb) line. Semiconductor memory device. The method of claim 26, The first and second dielectric layers are high dielectric thin films or ferroelectric thin films. Semiconductor memory device. The method of claim 23 or 24, The large capacity capacitor has a class capacitance Semiconductor memory device. The method of claim 24, The MOS capacitor has a class capacitance Semiconductor memory device. The method of claim 24, The MOS capacitor has a gate, a source, and a drain formed on a substrate, wherein the source and the drain are connected to the second power supply means, and the gate is connected to the first power supply means. Semiconductor memory device. A semiconductor memory device comprising a memory cell having a cell capacitor and a peripheral circuit having a leisure bar capacitor. The leisure bar capacitor, A first capacitor group having a plurality of large capacity capacitors connected in parallel; A second capacitor group having a plurality of large capacity capacitors connected in parallel; The first group of capacitors and the second group of capacitors are connected in series between first and second power supply means, wherein each of the large capacity capacitors has substantially the same capacitance as the cell capacitors. Semiconductor memory device. 39. The method of claim 38, The leisure bar capacitor, Between the first power supply means and the second power supply means, further comprising a Morse capacitor connected in parallel with the first and the second capacitor group Semiconductor memory device. The method of claim 38 or 39, The cell capacitor is formed above the bit line on the substrate. Semiconductor memory device. 40. The method of claim 39, The high capacity capacitor is disposed above the MOS capacitor on a substrate. Semiconductor memory device. The method of claim 38 or 39, The cell capacitor includes a storage node, a first dielectric formed on the storage node, and a plate electrode formed on the first dielectric, The high capacity capacitor may include a first electrode having the same material and surface area as the storage node, a second dielectric formed on the first electrode and the same material as the first dielectric, and formed on the second dielectric and the plate electrode. A second electrode formed of the same material as Semiconductor memory device. The method of claim 38 or 39, Each of the large capacitors of the first group of capacitors, A first electrode connected to said first power supply means, a first dielectric formed on said first electrode, and a second electrode formed on said first dielectric, Each of the large capacitors of the second group of capacitors, And a third electrode connected to the second power supply means, a second dielectric formed on the third electrode, and a fourth electrode formed on the second dielectric. Semiconductor memory device. The method of claim 43, The first power supply means includes a first power line to receive a first power, the first electrode is configured to contact the first power line, The second power supply means includes a second power line to receive a second power, and the third electrode is configured to be in contact with the second power line. Semiconductor memory device. The method of claim 44, The first power line and the second power line are separated by patterning a conductive layer for bit lines. Semiconductor memory device. The method of claim 43, The second electrode and the fourth electrode are commonly configured by a single conductive layer pattern Semiconductor memory device. The method of claim 45, The first power line is any one selected from the group of a power supply voltage Vdd line, a high voltage Vpp line, a core voltage Vcore line, and a bit line precharge voltage Vblp line. Semiconductor memory device. 49. The method of claim 47, The second power supply line is a ground voltage (Vss) line or a back bias voltage (Vbb) line. Semiconductor memory device. The method of claim 43, The first and second dielectric layers are high dielectric thin films or ferroelectric thin films. Semiconductor memory device. The method of claim 38 or 39, The large capacity capacitor has a class capacitance Semiconductor memory device. 40. The method of claim 39, The MOS capacitor has a class capacitance Semiconductor memory device. 40. The method of claim 39, The MOS capacitor has a gate, a source, and a drain formed on a substrate, wherein the source and the drain are connected to the second power supply means, and the gate is connected to the first power supply means. Semiconductor memory device.

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