200942118 九、發明說明： 【發明所屬之技術領域】 本發明與印刷電路板有關，特別是指用於高頻探針卡 之一種多層電路板。 5【先前技術】 - 用於晶圓級測試之探針卡中，探針卡電路板以具有適 當抗壓性及絕緣性的多層電路板所構成。電路板周圍上方 & 的銲墊係供測試機台的測試頭點觸，使各銲墊所對應連接 之傳輸線路傳送測試機台的測試訊號至電路板下方近中心 1〇處所密集設置之探針上。因此，當各探針對應點觸的晶圓 電子元件接收測試訊號後，則透過探針卡回傳所對應的電 氣特性至測試機台以供分析，如此在整個晶圓級測試過程 中，探針卡電路板的傳輸線路設計對電子元件的測試結果 佔有很重要的影響，尤其隨著電子科技越趨複雜且高速之 is運作，測試過程需涵蓋晶圓上大量的電路元件且操作於實 p 際對應的高速運作條件，故不但探針卡之電路空間利用需 為高密集度的設置，傳輸線路之製作更需符合高速訊號的 操作條件。 針對高速_的傳輸環麟，已有如錢公告專利第 2〇 6034533號所提供之『低漏電雌針卡』㈣，係於探針卡 訊號傳輸線路周圍設置接地環境，以改善傳輸線路之間的 漏電流、串音現象以及介質吸收等影響測試訊號的傳輸品 質及反應速度問題。由於此種傳輸線路為訊號傳輸於電路 板表面再與巾〜所;I：接接☆之探針相導通，其電路空間利 4 200942Π8 % 10 15 鵪 20 少量高頻測試需求的電路板結構，儘管其餘不 導^^件的訊魏路可佈設於電路㈣部或用一般 而當整個待測晶圓電路為更大量甚至皆為高 並=二=組成時，光單一電路板表面的高頻傳輪 ‘、=涵盍财電子魏元件的高_試需求。 外高頻傳輸線路佈設於電路板内部時，線路需由 著重於至下的延伸穿設層疊之印刷電路板，不但須二==;=特性，電路板所縱向穿設的導通 國公主裒ϋθ间頻傳輸特性的重大因素。縱使已有如美 專利第63_6號所提供之『具電路遮罩與控制阻 孔、纟。構』，係於_傳輸貫關_定間距設置接地 及維持==多Γ路板傳遞時所面臨漏電流效應 專輸斤需之特性阻抗，至於若電路板表面欲與 須與對靡2件相接设’當然訊號貫孔及鄰近之接地貫孔仍高頻值路元件㈣電性連接，才能有效於整個 地貫孔j =自轉其特性阻抗。朗訊號貫孔與周圍接 之特村=計有微小㈣定間㈣轉高頻訊號傳輸尚須考孔面欲與其他電路元件相接設 :Γ二=孔間距與電路元件間距無法實際對應的情 要達到有效電性連接的作用，甚至發生不必 要的漏電流以及電性短路現象。 d:rr用之一探針卡1為例，即為將高頻傳 線路佈权於-多層電路板10内部的結構電路板10於 5 200942118 二下面Γ、102分別近外圍及近中心處設有多數個銲 ，、12，電路板10内饰設有多數個訊號線路13 路Η以及導孔ls ,苴中， 按 A ^ Ψ上表面1〇1之鲜墊11為與測試 5 ❻ 15 ❹ 機口（圖中未示）之測試頭2間的電性連接介面，且透過 電路板ίο外圍之導孔⑸、152與各訊號線路13及接地線 路14分別電性連接’下表面啦之銲塾12為與探針17之 間的電性連接介面，且透過電路板1〇近中心之導孔Μ〕、 154與各訊號線路13及接地線路14分別電性連接，各接地 線路14為佈設於鄰近訊號線路13之上、下電路層，以達 到高頻測試訊號於各訊號線路13傳輸時所需之特性阻抗。 當高頻測試訊號自測試機台之測試頭2送出以至探針 Ρ之傳輸路徑上，除了藉由訊號線路13傳輸外，同時需經 由導孔151、153傳導於電路板10之上、下表面1〇卜1〇2 之間，其中上表面101各銲墊η之寬度及相距間隔係設計 為可供測試機台之各測試頭2對應點觸，同時考量測試頭 γ之對準誤差條件，故銲墊u之間距決定於測試機台之測 試頭2間距，進而決定了電路板10外圍導孔151、152之 間距。然以高頻訊號傳輸所需具備之特性阻抗條件，各測 試頭2之間距甚至其截面半徑皆大於訊號線路13與相鄰接 地線路14所需維持之距離，故使相鄰導孔151、152之設 置距離無法縮減至如相鄰訊號線路13與接地線路14之距 離，造成高頻訊號於各導孔151傳輪時無法維持如同於訊 號線路13中傳輸之特性阻抗。類似問題亦發生於電路板 近中心之導孔153、154 ’由於下表面1〇2各銲墊12之寬度 6 20 200942118 及相距間隔係設計為可供各探針17對應銲接，同時考量接 合強度所需銲錫量及避免鮮接過程中錫流或錫漏發生所需 之間隔誤差’故銲塾12之間距往_大於訊觀路13與 相鄰接地線路14所需維持之距離，使相鄰導孔153、 5之間距無法縮減至如相鄰訊號線路13與接地線路14之距 - 離，同樣造成高頻訊號於各導孔153傳輸時無法維接如回 於訊號線路13中傳輸之特性阻抗，因而探針卡丨於電測過 ® 程中高頻訊號傳輸於導孔151、153及訊號線路13之特性 阻抗不匹配，致使高頻减嚴重衰減而降低有效傳輸頻 10段’無法達到實際高頻電測之功效。 【發明内容】 因此，本發明之主要目的乃在於提供一種多層電路 板，使用以高頻測試之探針卡可維持有高頻訊號傳輸的阻 4 15抗匹配特性，並具有最佳的電性測試品質。 9 為達成前揭目的，本發明所提供一種多層電路板包含 有相互疊置之至少一轉接層及多數個高頻電路層，該轉接 層具有一表面與該高頻電路層相接合，以及貫穿有多數個 具導電性之第一訊號貫孔及第一接地貫孔，該些高頻電路 20層水平佈設多數個訊號導線、接地導線，以及貫穿有多數 個第二訊號貫孔及第二接地貫孔；其中，該第一接地貫孔 與該第一訊说貝孔之相鄰距離大於該第二接地貫孔與該第 二訊號貫孔之相鄰距離，該表面佈設有一接地金屬，位於 各該第一訊號貫孔周圍且電性連接該些第一及第二接地貫 7 200942118 L :亥些第-接地貫孔為電性導通至接地電位，該接地金 _與5亥第-訊號貫孔之相鄰距離相當於該接地金屬盘該第 二訊號貫孔之相鄰距離，亦相當於該第二接地貫孔&該第 一=號貫孔之相鄰距離。因此，當高頻訊號穿入電路板後， 可藉轉接層之接地金屬賴地訊料通至純訊號維持特 性阻抗所需之特定間距，用以維持高頻訊號貫穿該電路板 的縱向傳輸過程具有阻抗匹配的特性。 【實施方式】 以下，茲配合圖示列舉若干較佳實施例，用以對本發 明之結構與功效作詳細說明，其中所用圖示之簡要說明如 下： 第三圖為本發明第一較佳實施例之頂視圖； 第四圖為本發明第一較佳實施例之底視圖； 第五圖為第三圖中5-5剖線之剖視圖； 第六圖為本發明第一較佳實施例所提供之上轉接層的 底視圖； 第七圖為本發明第一較佳實施例所提供之下轉接層的 頂視圖； 第八圖為本發明第一較佳實施例所提供之高頻傳輸訊 號之特性曲線圖； ° 第九圖為本發明第二較佳實施例之電路板的結構示意 圖； 第十圖為本發明第三較佳實施例之電路板的結構示意 8 200942118 圖； 第十一圖為本發明第四較佳實施例之電路板的結構示 意圖；以及 第十一圖為本發明第五較佳實施例之電路板的結構示 5意圖。 請參閱如第三至第五圖所示，為本發明所提供第一較 佳實施例之探針卡3，包含有一電路板30、多數個訊號電 路36、多數個接地電路37,以及多數個探針4〇，可供一測 試機台（圖中未示）之測試頭2點觸，使電路板3〇可透過 1〇該些探針40點觸一積體電路晶圓（圖中未示）以做高頻電 性測試。 電路板30具有上、下相對之一上表面3〇1、一下表面 302以及分佈於内、外圍之一探針區3〇3及一測試區3〇4 電路板30之上、下表面分別設有多數個銲墊31、32，其中 15銲墊31位於測試區3〇4供測試機台電性連接，相鄰之各銲 塾31之間距為第一間距D1，第一間距D1係考量測試機台 之測試頭2對應接觸時之對準條件而設置，故各銲整31之 寬度相當於各測試頭2之截面寬度，且各銲墊31之相鄰第 —間距D1相當於相鄰各測試頭2之間距；該些銲墊31區 2〇分有用以接收高頻測試訊號之訊號銲墊311，以及伴隨高頻 机號傳遞之接地訊號所需對應接設之接地銲墊312;而銲塾 32位於探針區303供該些探針40電性連接，相鄰各之銲墊 32之間距為第二間距D2,第二間距D2係考量與各探針4〇 1 于接之條件而設置，包括考量接合強度所需銲錫量及避免 9 200942118 銲接過程中錫流或錫漏發生所需之間隔誤差，該些銲塾32 區分有對應輸出局頻測試訊號及接地訊號之訊號銲墊321 及接地銲墊322。 電路板30於上、下表面301、3〇2之間具有一上轉接 5層33、多數個相互疊置之高頻電路層34、一下轉接層35、 . 多數個自該上轉接層33延伸至下轉接層35之訊號電路36 及接地電路37，请配合第五圖參照。上、下轉接層33、35 ❹ 分別為形成電路板30上、下表面301、302之印刷電路層， 使上、下轉接層33、35之一第一表面分別形成電路板 10之上表面301與下表面302，而上、下轉接層33、35之一 第二表面330、350分別接合該些高頻電路層34。 各訊號電路36區分有穿設上、下轉接層33、35之第 一訊號貫孔361、穿設該些高頻電路層34之第二訊號貫孔 362，以及水平向佈設於各高頻電路層34之訊號導線363。 ‘ 15該些第一訊號貫孔361於上、下表面3〇1、3〇2分別電性連 ❹ 接該些訊號銲墊311、321 ;該些第二訊號貫孔362鄰接該 二第二表面330、350並與第一訊號貫孔361電性連接，該 些第二訊號貫孔362為沿訊號傳遞路徑縱向貫穿該些高頻 電路層34至所需對應電性連接之訊號導線363即戴止；各 2〇訊號導線363為自測試區3〇4水平延伸分佈至探針區， 於測試d 304 t性連接上層高頻電路層34之第二訊號貫孔 362，於探針區303電性連接下層高頻電路層34之第二訊 號貫孔362 ’使各訊號電路36為單一連續的訊號傳輸迴 路，避免高頻訊號於縱向傳遞轉至橫向傳遞之轉折介面 200942118 時’高頻電磁波於不連續的傳輸路徑發生介面反射現象而 造成訊號耗損。 各接地電路37區分有穿設上、下轉接層33、35之第 一接地貫孔371、水平佈設於各第二表面33〇、35〇之接地 5金屬372、373、穿設該些高頻電路層34之第二接地貫孔 374，以及水平向佈設於各高頻電路層34之接地導線375。 各第一接地貫孔371於上、下表面301、302分別電性連接 β 各接地銲墊312、322，該些第一接地貫孔371相鄰對應各 第一訊號貫孔36卜相鄰間距即受限於所對應該些銲墊3卜 1〇 32之第一及第二間距D1、D2;各接地金屬372、373位於 各第一訊號貫孔361周圍，請配合第六及第七圖參照，用 以將所對應該些第二表面330、350中之第一接地貫孔371 電性導通至相鄰各兩頻電路層34之第二接地貫孔374，提 供該些第一接地貫孔371及第二接地貫孔374之共接地平 • 15面。接地金屬與各第一訊號貫孔361之相鄰距離相當於該 ❹ 接地金屬與各第一訊说貫孔362之相鄰距離且相當於各第 二接地貫孔374與各第二訊號貫孔362之相鄰距離，各第 一接地貫孔374對應各第二訊號貫孔362相鄰設置有一第 三間距D3，相鄰距離相當於各高頻電路層34之厚度，為 2〇維持高頻測試訊號特性阻抗之最佳訊號傳輸結構，該些接 地導線375自測試區304水平延伸分佈至探針區3〇3,用以 電性連接第二接地貫孔374並與該些訊號導線363緊鄰佈 設於左右相鄰第三間距D3處或上下相鄰之高頻電路層34。 11 200942118 該^探針40為一般懸臂式探針結構’為了對應於晶圓 電路上局頻測试元件之接地迴路結構，相鄰二探針4〇需對 應點觸測試元件之高頻訊號接點及接地訊號接點，因此， 電路板30之相鄰各訊號電路36與接地電路37即分別透過 5訊號銲墊321及接地銲墊322對應電性連接相鄰各探針 40。該些探針4〇之結構、大小以及與電路板3〇之接設方 式為決定該些銲墊32之第二間距D2條件。 〇 當測試機台之測試頭2電性連接上表面301之訊號銲 墊311及接地銲墊312後，各訊號銲墊311所接收之高頻 10測試訊號即透過上轉接層33之第一訊號貫孔361、高頻電 路層34之第二訊號貫孔362與訊號導線363，以及下轉接 層35之第一訊號貫孔361傳輸至下表面3〇2之訊號銲墊 321，鄰近各高頻測試訊號之傳輸路徑皆對應有接地訊號自 上表面301之接地銲墊312接收後，導通至上轉接層33之 .15第一接地貫孔371、第二表面330之接地金屬373、高頻電 © 路層34之第二接地貫孔374與接地導線375、第二表面350 之接地金屬373、下轉接層35之第一接地貫孔371以至該 下表面302之接地銲墊322,使各訊號電路36自上表面301 延伸至下表面302之路徑上，除了分別與二表面3〇1、302 2〇鄰接之單一電路層（上、下轉接層33、35)中，第一訊號 貫孔361與對應相鄰的第一接地貫孔371有間隔較遠之第 一及第二間距Dl、D2外，藉由各接地金屬372、373用以 將所對應第二表面330、350中之第一接地貫孔371電性連 接相鄰該些高頻電路層34之第二接地貫孔374，使其餘第 12 200942118 二訊號貫孔362及訊號導線363皆可依照高頻訊號傳輸所 ，維持特性阻抗之需求’沿其路徑於鄰近第三間距D 3處佈 设有第二接地貫孔374及接地導線375。 因此，無淪因測試機台之測試頭對準間距與對準誤差 5條件二或者因探針銲接過程中避免錫流或錫漏發生所需之 _誤差條件，需使上、下表面則、3G2之訊麟塾3u、 _ 321 ,、接地銲塾312、322設置間距遠大於高頻電路層34 ❹ 巾訊號導線363與接地導線375之間距，亦即第一訊號貫 孔=1與對應相鄰的第一接地貫孔3?1設置間距遠大於維 1〇持高頻特性阻抗需求之特性，僅限於單層印刷電路板結構 之上、下轉接層33、35中，其餘高頻訊號傳輸於該些高頻 電路層34中皆可維持所需之特性阻抗，使高頻訊號穿入電 路板30後及穿出電路板3〇前，皆可藉二第二表面33〇、 之接地金屬372、373將接地訊號導通至高頻訊號維持特性 • 15阻抗所需之第三間距D3處，因此，維持高頻訊號貫穿該電 ® 路板30的縱向傳輸過程具有阻抗匹配的特性。 請參閱如第二及第八圖所示，分別為習用探針卡j及 本發明所提供探針卡3之高頻量測頻率特性圖，相較兩囷 之反射耗損（return loss)曲線Sll、S11，可知，本發明所 2〇提供之探針卡3的反射耗損曲線S11’有較低的反射率，顯 示於整個尚頻頻寬範圍有極佳的阻抗匹配特性，另相較兩 圖之插入耗損（insertion loss)曲線S21、S21，更顯示習用 探針卡1於-3dB增益之通帶（passband)限制頻率僅約有 2.56 GHz’遠小於本發明所提供之探針卡3可高於i〇GHz， 200942118 顯禾探針卡3具有較習用之 傳輸品質。 作為更良好的高頻訊號 號輸施供之電路板3G主要使高頻測試訊 跪輸出或輸入上、下表面則、3()2之鲜墊3 與=接，相鄰間距自表面單層轉接板33、“ 及第一間距D卜D2調整為内部高頻 = D3,因此並不偈限應用於該些探針40二 ^之探針結構可將對應_於晶㈣路頻 路36,且鄰近高頻訊號測測點 接地電路37，各_及高雜抗㈣特性之懸臂 直式探針結構或微機電探針結構皆可實施應 ::= 月Γ提供該電路板30。甚至當任-探針結構與電 =板輝墊相接合之焊接模社程可精密至相鄰銲塾間距相 15 二=述高頻電路層34之第三間距D2，則本發明所提供 探針卡電路板可省去如上述下轉接層35之結構。 如第九圊所示，為本發明第二較佳實施例所提供之用 =探針卡之多層電路板5G，多層電路板5G具有上轉接層 2及該些高頻電路層34，電路板50上表謂同樣對應 ^上轉接層33 ’下表面502則對應於底層之該高頻電路層 *並於下表面502對應各第二訊號貫孔362及各第二接 =貝孔374的位置設置有訊號銲墊51及接地銲墊&，該些 =塾51、52之相鄰間距即為相鄰各第二訊號貫孔362與各 了接地貝孔374之第三間距D3，可應用於以高精密度烊 接模組工程所接設之各種探針結構。 20 200942118 另外’為了再改善訊號電路在水平方向的傳輸路線過 長而產生過多的介電損耗，本發明之第三較佳實施例更提 供一種探針卡60 ’如第十圖所示，探針卡60在本實施例中 可區分為一測試區602、一探針區603與一位於測試區602 5與探針區603之間的跳線區604,其中測試區602的上表面 分別設有該些銲塾70’跳線區604的上表面與探針區的 上、下表面分別設有銲墊70’。探針卡60在本實施例中具 有多數個測試電路71，各測試電路71可區分為一第一段 72、一第二段73與一第三段74。 10 第一段72之訊號電路721區分有穿設測試區602之上 轉接層61的第一訊號貫孔722、穿設測試區602之高頻電 路層62之第二訊號貫孔723、由測試區602水平延伸分佈 至跳線區604之高頻電路層62的訊號導線724、穿設跳線 £ 604之尚頻電路層62的弟二訊號貫孔723，以及穿設跳 I5線區604之上轉接層61的第一訊號貫孔722,使測試區602 上表面的銲墊70與跳線區604之上表面的銲墊7〇,藉由測 試電路71的第一段72電性連接；第一段72之接地電路725 特徵與上述實施例相同，在此容不贅述。 第二段73之訊號電路731區分有穿設探針區6〇3之上 2〇轉接層61的第一訊號貫孔722、穿設探針區6〇3之高頻電 路層62的第二訊號貫孔723，以及穿設探針區6〇3下轉接 層63的第一訊號貫孔722，使探針區603上下表面之銲墊 70電性連接，第一段73之接地電路732特徵與上述實施例 相同，在此容不贅述。 15 200942118 八段74為—傳輸線，傳輸線之一軸心金屬742兩端 :別電性連接跳線區6G4上表面與探針區⑽上表面之一 5Κ说鲜塾702，’而僂給線之—ife. 4-Jr τ™ η λ Λ 得称踝之接地％ 744兩端則分別電性 連接探針區603上表面之一接地銲墊7〇4,。 冋樣地’請再參閱第十—圖與第十二圖，分別為本發 明第四與第五較佳實施例，本發明第四較佳實施例所提供200942118 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to printed circuit boards, and more particularly to a multilayer circuit board for a high frequency probe card. 5 [Prior Art] - In probe cards for wafer level testing, the probe card board is constructed of a multilayer circuit board with appropriate compression resistance and insulation. The solder pads on the top of the board are touched by the test heads of the test machine, so that the test lines connected to the pads transmit the test signals of the test machine to the densely arranged position near the center of the board. On the needle. Therefore, after the probe electronic components corresponding to the probes receive the test signal, the corresponding electrical characteristics are transmitted back to the test machine through the probe card for analysis, so that the whole wafer level test process is explored. The transmission line design of the pin card circuit board has a very important influence on the test results of the electronic components. Especially as the electronic technology becomes more complicated and the high speed is operating, the test process needs to cover a large number of circuit components on the wafer and operate on the real p. Corresponding to the high-speed operating conditions, not only the use of the circuit space of the probe card needs to be a high-density setting, but also the production of the transmission line needs to meet the operating conditions of the high-speed signal. For the high-speed transmission ring, there is a "low leakage female card" (4) provided by the No. 2, No. 6034533, which is provided with a grounding environment around the probe card signal transmission line to improve the transmission line. Leakage current, crosstalk, and dielectric absorption affect the transmission quality and response speed of test signals. Since the transmission line transmits the signal to the surface of the circuit board and then conducts with the probe of the towel~I: connected to the ☆ probe, the circuit space is 4200942Π8% 10 15 鹌20 A small number of circuit board structures required for high frequency testing, Although the remaining non-conductive components can be placed in the circuit (four) or in general, and when the entire wafer to be tested is larger or even higher and = two = composition, the high frequency transmission of the surface of the single circuit board The round _, = 盍 盍 电子 electronic components of the high _ test demand. When the external high-frequency transmission line is disposed inside the circuit board, the circuit needs to be stacked with the printed circuit board with a weight that extends to the lower end, and not only the second==;= characteristic, the conductive pendulum of the circuit board is longitudinally worn. A major factor in the inter-frequency transmission characteristics. Even though there is a circuit mask and control hole, 纟 provided by the US Patent No. 63_6. Structure, is based on _transmission clearance _ fixed spacing set grounding and maintenance == multi-turn circuit board transmission leakage current effect special characteristics of the required impedance, as for the surface of the board and the need and confrontation 2 pieces The connection of the 'optical signal through hole and the adjacent ground through hole is still electrically connected to the high frequency value circuit component (4), so as to be effective for the entire ground hole j = self-rotating its characteristic impedance. The Lucent No. hole and the surrounding special village = counted with a small (four) fixed (four) high-frequency signal transmission still need to test the hole surface to be connected with other circuit components: Γ two = hole spacing and circuit component spacing can not actually correspond In order to achieve an effective electrical connection, even unnecessary leakage current and electrical short circuit occur. d: rr uses one of the probe cards 1 as an example, that is, the high-frequency transmission line is distributed to the inside of the multi-layer circuit board 10, and the structural circuit board 10 is provided on the lower side and the near center of the bottom, 102, respectively. Most of the welding, 12, circuit board 10 interior has a number of signal lines 13 roads and guide holes ls, in the middle, press A ^ Ψ upper surface 1 〇 1 fresh pad 11 and test 5 ❻ 15 ❹ machine The electrical connection interface between the test heads 2 of the port (not shown) is electrically connected to the lower surface of the signal line ίο via the guide holes (5) and 152 of the circuit board, and the signal lines 13 and the ground line 14 respectively. 12 is an electrical connection interface with the probe 17, and is electrically connected to each of the signal lines 13 and the ground line 14 through the conductive holes 、, 154 of the circuit board 1 near the center, and the ground lines 14 are disposed on the ground line 14 The upper and lower circuit layers are adjacent to the signal line 13 to achieve the characteristic impedance required for the high frequency test signal to be transmitted to each of the signal lines 13. When the high-frequency test signal is sent from the test head 2 of the test machine to the transmission path of the probe ,, in addition to being transmitted by the signal line 13, it is also transmitted to the upper and lower surfaces of the circuit board 10 via the via holes 151, 153. Between 1 and 2, wherein the widths and spacings of the pads η of the upper surface 101 are designed to be suitable for each test head 2 of the test machine, and the alignment error condition of the test head γ is considered. Therefore, the distance between the pads u is determined by the distance between the test heads 2 of the test machine, and further determines the distance between the peripheral guide holes 151 and 152 of the circuit board 10. However, the characteristic impedance conditions required for high-frequency signal transmission, the distance between the test heads 2 and even the cross-sectional radius thereof are greater than the distance required for the signal line 13 and the adjacent ground line 14 to be maintained, so that the adjacent guide holes 151, 152 The set distance cannot be reduced to the distance between the adjacent signal line 13 and the ground line 14, so that the high frequency signal cannot maintain the characteristic impedance transmitted in the signal line 13 when the guide holes 151 pass. A similar problem also occurs in the near-center guiding holes 153, 154 ' of the circuit board. Since the width of the lower surface 1 〇 2 pads 12 6 200942118 and the spacing interval are designed for the corresponding welding of the probes 17, while considering the joint strength The required soldering amount and the interval error required to avoid tin flow or tin leakage during the soldering process. Therefore, the distance between the soldering pads 12 is greater than the distance required by the Xunguan Road 13 and the adjacent grounding line 14 to make the adjacent The distance between the guiding holes 153 and 5 cannot be reduced to the distance between the adjacent signal lines 13 and the grounding line 14, and the high frequency signals are not transmitted during the transmission of the guiding holes 153, such as the characteristics of the transmission in the signal line 13. Impedance, so the probe is stuck in the electrical measurement process, the high-frequency signal transmitted to the guiding holes 151, 153 and the signal line 13 characteristic impedance mismatch, causing the high frequency to reduce the severe attenuation and reduce the effective transmission frequency of 10 segments 'can not reach the actual The effect of high frequency electrical measurement. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a multilayer circuit board that uses a probe card that is tested at a high frequency to maintain a high frequency signal transmission resistance and has the best electrical properties. Test quality. In order to achieve the foregoing, the present invention provides a multilayer circuit board including at least one interposer layer and a plurality of high frequency circuit layers stacked on each other, the interposer having a surface bonded to the high frequency circuit layer. And a plurality of conductive first signal through holes and a first ground through hole, wherein the plurality of high frequency circuits 20 are horizontally arranged with a plurality of signal wires, ground wires, and a plurality of second signal through holes and a grounding through hole; wherein the first grounding through hole and the first sensing hole are adjacent to each other by an adjacent distance from the second grounding through hole and the second signal through hole, the surface is provided with a grounding metal Located around each of the first signal via holes and electrically connected to the first and second ground vias 7 200942118 L: the first-ground vias are electrically conductive to ground potential, the grounded gold _ and 5 hai The adjacent distance of the signal through hole is equivalent to the adjacent distance of the second signal through hole of the grounded metal plate, and is also equivalent to the adjacent distance of the second ground through hole & Therefore, when the high-frequency signal penetrates into the circuit board, the grounding metal ground material of the switching layer can be passed to a specific interval required for the pure signal to maintain the characteristic impedance, so as to maintain the longitudinal transmission process of the high-frequency signal through the circuit board. Has the characteristics of impedance matching. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In the following, a number of preferred embodiments are illustrated in the accompanying drawings to illustrate the structure and function of the present invention. The top view is a bottom view of the first preferred embodiment of the present invention; the fifth view is a cross-sectional view taken along line 5-5 of the third figure; and the sixth figure is provided in the first preferred embodiment of the present invention. The bottom view of the transfer layer is provided; the seventh view is a top view of the transfer layer provided by the first preferred embodiment of the present invention; and the eighth figure is the high frequency transfer provided by the first preferred embodiment of the present invention. The characteristic diagram of the signal; ° FIG. 9 is a schematic structural view of a circuit board according to a second preferred embodiment of the present invention; FIG. 10 is a schematic structural diagram of a circuit board according to a third preferred embodiment of the present invention; 1 is a schematic structural view of a circuit board according to a fourth preferred embodiment of the present invention; and FIG. 11 is a schematic view showing the structure of a circuit board according to a fifth preferred embodiment of the present invention. Referring to the third to fifth figures, the probe card 3 of the first preferred embodiment of the present invention includes a circuit board 30, a plurality of signal circuits 36, a plurality of ground circuits 37, and a plurality of The probe 4〇 can be used to touch the test head 2 of a test machine (not shown), so that the circuit board 3 can pass through the probes 40 to touch an integrated circuit wafer (not shown in the figure) Show) for high frequency electrical testing. The circuit board 30 has an upper and lower opposite upper surface 3〇1, a lower surface 302, and a probe area 3〇3 disposed on the inner and outer sides, and a test area 3〇4 on the circuit board 30 and the lower surface respectively. There are a plurality of pads 31, 32, wherein 15 pads 31 are located in the test area 3〇4 for electrical connection of the test machine, the distance between the adjacent pads 31 is the first spacing D1, and the first spacing D1 is a test machine. The test head 2 of the stage is set corresponding to the alignment condition at the time of contact, so the width of each solder 31 corresponds to the cross-sectional width of each test head 2, and the adjacent first-pitch D1 of each pad 31 corresponds to the adjacent test. The distance between the heads 2; the pads 31 of the pads 31 are used to receive the signal pads 311 for receiving the high frequency test signals, and the ground pads 312 corresponding to the ground signals transmitted by the high frequency signals; The 塾32 is located in the probe area 303 for electrically connecting the probes 40, and the distance between the adjacent pads 32 is a second spacing D2, and the second spacing D2 is considered to be in contact with each probe 4〇1. Setup, including the amount of solder required to consider joint strength and avoid the need for tin flow or tin leakage during the welding process Interval error, the plurality of solder 32 Sook distinguish between a corresponding output signal frequency of the test signal Board and a ground pad 321 of signal pads 322 and the ground. The circuit board 30 has an upper transfer 5 layer 33, a plurality of mutually overlapping high frequency circuit layers 34, and a lower transfer layer 35 between the upper and lower surfaces 301, 3〇2. The layer 33 extends to the signal circuit 36 and the ground circuit 37 of the lower switching layer 35. Please refer to the fifth drawing. The upper and lower transfer layers 33, 35 分别 are respectively printed circuit layers forming the upper and lower surfaces 301 and 302 of the circuit board 30, so that the first surfaces of the upper and lower transfer layers 33, 35 are respectively formed on the circuit board 10. The surface 301 and the lower surface 302, and the second surfaces 330, 350 of the upper and lower transfer layers 33, 35 respectively engage the high frequency circuit layers 34. Each signal circuit 36 is divided into a first signal through hole 361 through which the upper and lower transfer layers 33 and 35 are disposed, a second signal through hole 362 through which the high frequency circuit layers 34 are disposed, and horizontally disposed at each high frequency. Signal conductor 363 of circuit layer 34. The first signal through holes 361 are electrically connected to the signal pads 311 and 321 respectively on the upper and lower surfaces 3〇1 and 3〇2, and the second signal through holes 362 are adjacent to the second and second electrodes 362. The surface of the second signal through hole 362 is electrically connected to the first signal through hole 361, and the second signal through hole 362 is longitudinally penetrated through the high frequency circuit layer 34 along the signal transmission path to the signal conductor 363 corresponding to the corresponding electrical connection. Each of the two signal wires 363 is horizontally distributed from the test area 3〇4 to the probe area, and is connected to the second signal through hole 362 of the upper high frequency circuit layer 34 in the test d 304 t, in the probe area 303. The second signal through hole 362 ′ of the lower layer high frequency circuit layer 34 is electrically connected to each signal circuit 36 to avoid a high frequency electromagnetic wave when the high frequency signal is transmitted in the longitudinal direction to the lateral transmission turning interface 200942118. Signal leakage occurs due to interface reflection in a discontinuous transmission path. Each of the grounding circuits 37 is divided into a first grounding through hole 371 through which the upper and lower switching layers 33 and 35 are disposed, and a grounding 5 metal 372 and 373 horizontally disposed on each of the second surfaces 33 and 35, and is disposed to be high. The second ground via 374 of the frequency circuit layer 34 and the ground conductor 375 disposed horizontally on each of the high frequency circuit layers 34. Each of the first grounding through holes 371 is electrically connected to the respective grounding pads 312 and 322 on the upper and lower surfaces 301 and 302, and the first grounding through holes 371 are adjacent to each of the first signal through holes 36. It is limited to the first and second pitches D1 and D2 of the corresponding pads 3b and 32; the grounding metals 372 and 373 are located around the first signal through holes 361, please refer to the sixth and seventh figures. The first ground vias 371 are electrically connected to the first ground vias 371 of the adjacent second surfaces 330, 350 to the second ground vias 374 of the adjacent two-frequency circuit layers 34, and the first ground vias 371 are provided. And the common grounding hole 374 of the second grounding through hole 374 is 15 faces. The adjacent distance between the grounding metal and each of the first signal through holes 361 is equivalent to the adjacent distance between the grounding metal and each of the first sensing through holes 362 and corresponds to each of the second grounding through holes 374 and each of the second signal through holes. Each of the first grounding through holes 374 is adjacent to each of the second signal through holes 362 and has a third spacing D3 adjacent to each other. The adjacent distance corresponds to the thickness of each high frequency circuit layer 34, and the height is maintained at 2 〇. The best signal transmission structure of the test signal characteristic impedance, the grounding wires 375 are horizontally extended from the test area 304 to the probe area 3〇3 for electrically connecting the second grounding through holes 374 and adjacent to the signal wires 363. The high frequency circuit layer 34 is disposed adjacent to the left and right adjacent third pitch D3 or adjacent to the upper and lower sides. 11 200942118 The probe 40 is a general cantilever probe structure. In order to correspond to the ground loop structure of the local frequency test component on the wafer circuit, the adjacent two probes 4 need to correspond to the high frequency signal of the touch test component. The adjacent signal circuits 36 and the grounding circuit 37 are electrically connected to the adjacent probes 40 through the 5 signal pads 321 and the ground pads 322, respectively. The structure and size of the probes 4 and the connection with the circuit board 3 are the conditions for determining the second pitch D2 of the pads 32. After the test head 2 of the test machine is electrically connected to the signal pad 311 and the ground pad 312 of the upper surface 301, the high frequency 10 test signal received by each signal pad 311 is transmitted through the first layer of the upper transfer layer 33. The signal through hole 361, the second signal through hole 362 of the high frequency circuit layer 34 and the signal wire 363, and the first signal through hole 361 of the lower transfer layer 35 are transmitted to the signal pad 321 of the lower surface 3〇2, adjacent to each The transmission path of the high frequency test signal is corresponding to the grounding signal received from the ground pad 312 of the upper surface 301, and is connected to the grounding metal 373 of the first grounding through hole 371 and the second surface 330 of the upper switching layer 33. The second ground via 374 of the circuit layer 34 and the grounding conductor 375, the grounding metal 373 of the second surface 350, the first grounding via 371 of the lower switching layer 35, and the ground pad 322 of the lower surface 302, The signal circuit 36 is extended from the upper surface 301 to the lower surface 302, except for a single circuit layer (upper and lower transfer layers 33, 35) adjacent to the two surfaces 3?1, 3022, respectively. The signal through hole 361 is spaced apart from the corresponding first ground through hole 371 by the first and the third The grounding holes 371 and 373 are used to electrically connect the first grounding vias 371 of the corresponding second surfaces 330 and 350 to the second ground of the adjacent high frequency circuit layers 34. The through hole 374 enables the remaining 12th 200942118 two-signal through-hole 362 and the signal conductor 363 to follow the high-frequency signal transmission to maintain the characteristic impedance. A second ground is disposed along the path adjacent to the third spacing D 3 Through hole 374 and grounding wire 375. Therefore, it is necessary to make the upper and lower surfaces of the test head alignment pitch and alignment error 5 or the error conditions required to avoid tin flow or tin leakage during the probe soldering process. The spacing between the 3G2 塾 塾 3u, _ 321 , and the grounding 塾 312, 322 is much larger than the distance between the high frequency circuit layer 34 ❹ signal line 363 and the grounding wire 375, that is, the first signal through hole =1 and the corresponding phase The adjacent first grounding through hole 3?1 is disposed at a distance far greater than the dimension 1 holding high frequency characteristic impedance requirement, and is limited to the single layer printed circuit board structure and the lower switching layer 33, 35, and the remaining high frequency signals The high-frequency circuit layer 34 can be transmitted to maintain the required characteristic impedance. After the high-frequency signal is penetrated into the circuit board 30 and before the circuit board 3 is passed, the second surface 33 can be grounded. The metal 372, 373 conducts the ground signal to the third pitch D3 required for the high frequency signal sustaining characteristic 15 impedance. Therefore, the longitudinal transmission process for maintaining the high frequency signal throughout the electric circuit board 30 has impedance matching characteristics. Please refer to the high-frequency measurement frequency characteristic diagrams of the conventional probe card j and the probe card 3 provided by the present invention as shown in the second and eighth figures, respectively, compared with the return loss curve Sll of the two turns. S11, it can be seen that the reflection loss curve S11' of the probe card 3 provided by the present invention has a low reflectance, and has excellent impedance matching characteristics in the entire frequency range, and is compared with the two figures. The insertion loss curves S21 and S21 further show that the passband limit frequency of the conventional probe card 1 at -3 dB gain is only about 2.56 GHz' which is much smaller than the probe card 3 provided by the present invention. I〇GHz, 200942118 The display probe card 3 has a higher transmission quality. As a better high-frequency signal number, the circuit board 3G mainly makes the high-frequency test signal output or input to the upper and lower surfaces, and the 3()2 fresh pad 3 and = are connected, and the adjacent spacing is from the surface single layer. The adapter plate 33, "and the first pitch Db D2 are adjusted to the internal high frequency = D3, so the probe structure applied to the probes 40 is not limited to the corresponding _ crystal (four) way frequency path 36. And adjacent to the high-frequency signal measuring point grounding circuit 37, each of the _ and high-hybrid (four) characteristics of the cantilever straight probe structure or the micro-electromechanical probe structure can be implemented::= The moon provides the circuit board 30. Even The probe provided by the present invention can be precisely welded to the adjacent solder fill pitch phase 15 when the bonding structure of the probe-electrode structure is bonded to the adjacent solder fillet pitch. The card circuit board can omit the structure of the lower transfer layer 35 as described above. As shown in the ninth aspect, the multi-layer circuit board 5G using the probe card provided by the second preferred embodiment of the present invention, the multilayer circuit board 5G Having the upper switching layer 2 and the high frequency circuit layers 34, the circuit board 50 is said to correspond to the upper switching layer 33', and the lower surface 502 corresponds to the bottom layer. The high-frequency circuit layer* is provided with a signal pad 51 and a ground pad & at the position of the lower surface 502 corresponding to each of the second signal through holes 362 and each of the second connection holes 374, which are 塾51, 52 The adjacent spacing is the third spacing D3 between the adjacent second signal through holes 362 and each of the grounding holes 374, and can be applied to various probe structures connected by high precision splicing module engineering. 20 200942118 In addition, in order to further improve the transmission path of the signal circuit in the horizontal direction to generate excessive dielectric loss, the third preferred embodiment of the present invention further provides a probe card 60' as shown in the tenth figure, the probe card In this embodiment, the test area 602, a probe area 603, and a jumper area 604 between the test area 602 5 and the probe area 603 can be divided, wherein the upper surface of the test area 602 is respectively provided. The upper surface of the solder bump 70' jumper region 604 and the upper and lower surfaces of the probe region are respectively provided with solder pads 70'. The probe card 60 has a plurality of test circuits 71 in this embodiment, and each test circuit 71 can be It is divided into a first segment 72, a second segment 73 and a third segment 74. 10 signal circuit 721 of the first segment 72 The first signal through hole 722 passing through the transfer layer 61 on the test area 602, the second signal through hole 723 passing through the high frequency circuit layer 62 of the test area 602, and extending horizontally from the test area 602 to the jumper The signal conductor 724 of the high frequency circuit layer 62 of the area 604, the second signal via 723 of the frequency circuit layer 62 of the jumper 604, and the first layer of the transition layer 61 above the jump line I5. The signal through hole 722 is such that the pad 70 on the upper surface of the test area 602 and the pad 7 on the upper surface of the jumper area 604 are electrically connected by the first segment 72 of the test circuit 71; the ground circuit of the first segment 72 The features of the 725 are the same as those of the above embodiment, and are not described here. The signal circuit 731 of the second segment 73 is divided into a first signal through hole 722 that penetrates the second transfer layer 61 on the probe region 6〇3, and a high frequency circuit layer 62 that penetrates the probe region 6〇3. The second signal through hole 723, and the first signal through hole 722 of the transfer layer 63 under the probe region 6〇3, electrically connect the pads 70 on the upper and lower surfaces of the probe region 603, and the ground circuit of the first segment 73 The features of the 732 are the same as those of the above embodiment, and are not described here. 15 200942118 Eight segments 74 are - transmission line, one of the transmission line axis 742 ends: other electrical connection jumper area 6G4 upper surface and one of the upper surface of the probe area (10) 5 Κ 塾 702, 'And 偻 to the line —ife. 4-Jr τTM η λ Λ The grounding % of the 744 is electrically connected to one of the ground pads 7〇4 of the upper surface of the probe area 603. Please refer to the tenth-figure and the twelfth drawings, respectively, which are the fourth and fifth preferred embodiments of the present invention, which are provided by the fourth preferred embodiment of the present invention.
之探針卡8G於探針區82設有—貫穿上下表面之穿孔似， 傳輸線84 —端電性連接跳線區86上表面的銲墊88，另一 端由上而下穿過穿孔822而與探針區82之探針87電性連 接。 本發明第五較佳實施例所提供之探針卡9〇則於跳線區 902下表面設有銲塾91’，測試區904上表面之銲墊91與跳 線區902下表面之銲墊9Γ利用測試電路92之第一段93電 性連接，第一段93之接地電路932在此容不贅述，而第一 I5段93之訊號電路931區分為穿設測試區904之上轉接層95 的第一訊號貫孔933、穿設測試區904之高頻電路層96的 第二訊號貫孔934、由測試區904水平延伸分佈至跳線區 902之高頻電路層96的訊號導線936、穿設跳線區902之 高頻電路層96的第二訊號貫孔934，以及穿設跳線區902 2〇之下轉接層97的第一訊號貫孔933。跳線區902下表面的 銲墊91’是利用測試電路92之第二段94，亦即傳輸線電性 連接設於探針區906之探針98。 藉此，上述三實施例皆是利用傳輸線來取代訊號電路 於高頻電路層内的水平向傳輸路線，可有效減少傳輸路線 200942118The probe card 8G is provided in the probe region 82 with a through hole penetrating through the upper and lower surfaces. The transmission line 84 is electrically connected to the pad 88 on the upper surface of the jumper region 86, and the other end is passed through the through hole 822 from the top to the bottom. The probe 87 of the probe region 82 is electrically connected. The probe card 9 provided in the fifth preferred embodiment of the present invention is provided with a soldering spot 91' on the lower surface of the jumper region 902, a solder pad 91 on the upper surface of the test area 904 and a solder pad on the lower surface of the jumper region 902. The first stage 93 of the test circuit 92 is electrically connected. The ground circuit 932 of the first stage 93 is not described here, and the signal circuit 931 of the first I5 stage 93 is divided into the transfer layer above the test area 904. The first signal through hole 933 of the 95, the second signal through hole 934 of the high frequency circuit layer 96 of the test area 904, and the signal wire 936 extending horizontally from the test area 904 to the high frequency circuit layer 96 of the jumper area 902 The second signal through hole 934 of the high frequency circuit layer 96 of the jumper area 902 is disposed, and the first signal through hole 933 of the transfer layer 97 is disposed through the jumper area 902 2 . The pad 91' on the lower surface of the jumper region 902 is the second segment 94 of the test circuit 92, that is, the transmission line is electrically connected to the probe 98 disposed in the probe region 906. Therefore, the above three embodiments all use the transmission line to replace the horizontal transmission path of the signal circuit in the high frequency circuit layer, which can effectively reduce the transmission route.
過長而產生過多的介電損耗。 唯，以上所述者，僅為本發明之較佳可行實施例而已， 故舉凡應用本發明說明書及申請專利範圍所為之等效結構 變化，理應包含在本發明之專利範圍内。 17 200942118 【圖式簡單說明】 第一圖為習用探針卡之結構示意圖。 第二圖為上述習用探針卡之高頻傳輸訊號之特性曲線 圖。 5 第三圖為本發明第一較佳實施例之頂視圖。 . 第四圖為本發明第一較佳實施例之底視圖。 第五圖為第三圖中5-5剖線之剖視圖。 〇 第六圖為本發明第一較佳實施例所提供之上轉接層的 底視圖。 10 第七圖為本發明第一較佳實施例所提供之下轉接層的 頂視圖。 第八圖為本發明第一較佳實施例所提供之高頻傳輸訊 號之特性曲線圖。 第九圖為本發明第二較佳實施例之電路板的結構示意 15 圖。 ❿ 第十圖為本發明第三較佳實施例之電路板的結構示意 圖。 第十一圖為本發明第四較佳實施例之電路板的結構示 意圖。 20 第十二圖為本發明第五較佳實施例之電路板的結構示 意圖。 18 200942118Too long to produce excessive dielectric loss. It is to be understood that the above-described embodiments are merely preferred embodiments of the present invention, and the equivalent structural changes of the present invention and the scope of the claims are intended to be included in the scope of the present invention. 17 200942118 [Simple description of the diagram] The first diagram is a schematic diagram of the structure of the conventional probe card. The second figure is a characteristic diagram of the high frequency transmission signal of the above conventional probe card. 5 is a top view of a first preferred embodiment of the present invention. The fourth figure is a bottom view of a first preferred embodiment of the present invention. The fifth figure is a cross-sectional view taken along line 5-5 of the third figure.第六 Figure 6 is a bottom plan view of the upper transfer layer provided in the first preferred embodiment of the present invention. 10 is a top plan view of the transfer layer provided by the first preferred embodiment of the present invention. Figure 8 is a graph showing the characteristics of the high frequency transmission signal provided by the first preferred embodiment of the present invention. Figure 9 is a schematic view showing the structure of a circuit board according to a second preferred embodiment of the present invention.第十 Tenth is a schematic structural view of a circuit board according to a third preferred embodiment of the present invention. Fig. 11 is a view showing the construction of a circuit board according to a fourth preferred embodiment of the present invention. Fig. 12 is a view showing the configuration of a circuit board according to a fifth preferred embodiment of the present invention. 18 200942118
10 1510 15
【主要元件符號說明】 2測試頭 30、50電路板 302、502下表面 304測試區 311、32卜51訊號銲墊 33上轉接層 34高頻電路層 350第二轉接面 361第一訊號貫孔 363訊號導線 371第一接地貫孔 374第二接地貫孔 40探針 D2第二間距 S11、S11’反射耗損曲線 60探針卡 603探針區 61上轉接層 63下轉接層 702’訊號銲墊 71測試電路 721訊號電路 723第二訊號貫孔 3探針卡 3(M、501上表面 303探針區 31、32銲墊 312、322、52接地銲墊 330第一轉接面 35下轉接層 36訊號電路 362第二訊號貫孔 37接地電路 372、373接地金屬 375接地導線 D1第一間距 D3第三間距 S21、S21’插入耗損曲線 602測試區 604跳線區 62高頻電路層 70、70’銲墊 704’接地銲墊 72第一段 722第一訊號貫孔 724訊號導線 20 200942118[Main component symbol description] 2 test head 30, 50 circuit board 302, 502 lower surface 304 test area 311, 32, 51 signal pad 33, transfer layer 34 high frequency circuit layer 350 second transfer surface 361 first signal Through hole 363 signal wire 371 first ground through hole 374 second ground through hole 40 probe D2 second interval S11, S11' reflection loss curve 60 probe card 603 probe area 61 upper transfer layer 63 lower transfer layer 702 'Signal pad 71 test circuit 721 signal circuit 723 second signal through hole 3 probe card 3 (M, 501 upper surface 303 probe area 31, 32 pads 312, 322, 52 ground pad 330 first transfer surface 35 lower transfer layer 36 signal circuit 362 second signal through hole 37 ground circuit 372, 373 ground metal 375 ground wire D1 first pitch D3 third pitch S21, S21' insertion loss curve 602 test area 604 jumper area 62 high frequency Circuit layer 70, 70' pad 704' ground pad 72 first segment 722 first signal through hole 724 signal wire 20 200942118
1010
15 φ I 725接地電路 74傳輸線 744接地環 80探針卡 822穿孔 8 6跳線區 88銲墊 90探針卡 902跳線區 906探針區 92測試電路 931訊號電路 933第一訊號貫孔 936訊號導線 95上轉接層 97下轉接層 73第二段 742袖心金屬 82探針區 84傳輸線 87探針 904測試區 91、91’銲墊 93第一段 932接地電路 934第二訊號貫孔 94第二段 96高頻電路層 98探針 2015 φ I 725 ground circuit 74 transmission line 744 grounding ring 80 probe card 822 perforation 8 6 jumper area 88 solder pad 90 probe card 902 jumper area 906 probe area 92 test circuit 931 signal circuit 933 first signal through hole 936 Signal conductor 95 upper transfer layer 97 lower transfer layer 73 second stage 742 sleeve metal 82 probe area 84 transmission line 87 probe 904 test area 91, 91 'pad 93 first section 932 ground circuit 934 second signal Hole 94 second segment 96 high frequency circuit layer 98 probe 20